M66256FP [RENESAS]
5120 × 8-Bit Line Memory (FIFO); 5120 × 8位线存储器（ FIFO）
| 型号： | M66256FP |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 5120 × 8-Bit Line Memory (FIFO) |
| 文件： | 总14页 (文件大小：171K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M66256FP
5120 × 8-Bit Line Memory (FIFO)
REJ03F0250-0200
Rev.2.00
Sep 14, 2007
Description
The M66256FP is a high-speed line memory with a FIFO (First In First Out) structure of 5120-word × 8-bit
configuration which uses high-performance silicon gate CMOS process technology.
It has separate clock, enable and reset signals for write and read, and is most suitable as a buffer memory between
devices with different data processing throughput.
Features
•
•
•
•
•
•
•
Memory configuration:
High-speed cycle:
High-speed access:
Output hold:
Fully independent, asynchronous write and read operations
Variable length delay bit
5120 words × 8 bits (dynamic memory)
25 ns (Min)
18 ns (Max)
3 ns (Min)
Output:
3 states
Application
Digital photocopiers, high-speed facsimile, laser beam printers.
Block Diagram
Data input
D0 to D7
Data output
Q0 to Q7
13 14 15 16 21 22 23 24
1 2 3 4 9 10 11 12
Input buffer
Output buffer
RE
20
19
5
6
WE
Read
Write
enable input
enable input
Memory array of
RRES
WRES
Write
reset input
5120-word × 8-bit
configuration
Read
reset input
17
18
8
7
WCK
Write
clock input
RCK
Read
clock input
GND
VCC
REJ03F0250-0200 Rev.2.00 Sep 14, 2007
Page 1 of 13
M66256FP
Pin Arrangement
M66256FP
1
2
24
23
22
21
20
19
18
17
16
15
14
13
Q0
Q1
D0
D1
Data output
Data input
3
Q2
D2
4
Q3
D3
5
Read enable input
Read reset input
Write enable input
Write reset input
RE
WE
WRES
VCC
WCK
D4
6
RRES
GND
RCK
Q4
7
8
Read clock input
Data output
Write clock input
Data input
9
10
11
12
Q5
D5
Q6
D6
Q7
D7
(Top view)
Outline: 24P2U-A
REJ03F0250-0200 Rev.2.00 Sep 14, 2007
Page 2 of 13
M66256FP
Absolute Maximum Ratings
(Ta = 0 to 70°C, unless otherwise noted)
Item
Symbol
Ratings
−0.5 to +7.0
−0.5 to VCC + 0.5
−0.5 to VCC + 0.5
440
Unit
V
Conditions
Supply voltage
Input voltage
VCC
VI
A value based on
GND pin
V
Output voltage
VO
V
Power dissipation
Storage temperature
Pd
mW
°C
Ta = 25°C
Tstg
−65 to 150
Recommended Operating Conditions
Item
Symbol
VCC
Min
Typ
5
Max
5.5
Unit
V
Supply voltage
Supply voltage
4.5
0
GND
0
V
Operating ambient temperature
Topr
70
°C
Electrical Characteristics
(Ta = 0 to 70°C, VCC = 5 V ± 10%, GND = 0 V)
Item
"H" input voltage
"L" input voltage
"H" output voltage
"L" output voltage
"H" input current
Symbol
VIH
Min
Typ
Max
Unit
V
Test Conditions
2.0
VIL
0.8
V
VOH
VOL
V
CC − 0.8
V
IOH = −4 mA
0.55
1.0
V
IOL = 4 mA
VI = VCC
IIH
µA
WE, WRES, WCK,
RE, RRES, RCK,
D0 to D7
"L" input current
IIL
−1.0
µA
VI = GND WE, WRES, WCK,
RE, RRES, RCK,
D0 to D7
Off state "H" output current
Off state "L" output current
IOZH
IOZL
ICC
5.0
−5.0
80
µA
µA
VO = VCC
VO = GND
Operating mean current dissipation
mA
VI = VCC, GND, Output open
t
WCK, tRCK = 25 ns
Input capacitance
CI
10
15
pF
pF
f = 1 MHz
f = 1 MHz
Off state output capacitance
CO
Function
When write enable input WE is "L", the contents of data inputs D0 to D7 are written into memory in synchronization
with rise edge of write clock input WCK. At this time, the write address counter is also incremented simultaneously.
The write function given below are also performed in synchronization with rise edge of WCK.
When WE is "H", a write operation to memory is inhibited and the write address counter is stopped.
When write reset input WRES is "L", the write address counter is initialized.
When read enable input RE is "L", the contents of memory are output to data outputs Q0 to Q7 in synchronization with
rise edge of read clock input RCK. At this time, the read address counter is also incremented simultaneously.
The read functions given below are also performed in synchronization with rise edge of RCK.
When RE is "H", a read operation from memory is inhibited and the read address counter is stopped. The outputs are in
the high impedance state.
When read reset input RRES is "L", the read address counter is initialized.
REJ03F0250-0200 Rev.2.00 Sep 14, 2007
Page 3 of 13
M66256FP
Switching Characteristics
(Ta = 0 to 70°C, VCC = 5 V ± 10%, GND = 0 V)
Item
Access time
Symbol
tAC
Min
3
Typ
Max
18
Unit
ns
Output hold time
tOH
ns
Output enable time
Output disable time
tOEN
tODIS
3
18
ns
3
18
ns
Timing Conditions
(Ta = 0 to 70°C, VCC = 5 V ± 10%, GND = 0 V, unless otherwise noted)
Item
Symbol
tWCK
Min
25
11
11
25
11
11
7
Typ
Max
20
20
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
Write clock (WCK) cycle
Write clock (WCK) "H" pulse width
Write clock (WCK) "L" pulse width
Read clock (RCK) cycle
tWCKH
tWCKL
tRCK
Read clock (RCK) "H" pulse width
Read clock (RCK) "L" pulse width
Input data setup time to WCK
Input data hold time to WCK
Reset setup time to WCK or RCK
Reset hold time to WCK or RCK
tRCKH
tRCKL
tDS
tDH
3
tRESS
tRESH
7
3
Reset nonselect setup time to WCK or RCK tNRESS
7
Reset nonselect hold time to WCK or RCK
tNRESH
tWES
tWEH
tNWES
tNWEH
tRES
3
WE setup time to WCK
WE hold time to WCK
WE nonselect setup time to WCK
WE nonselect hold time to WCK
RE setup time to RCK
7
3
7
3
7
RE hold time to RCK
tREH
3
RE nonselect setup time to RCK
RE nonselect hold time to RCK
Input pulse rise/fall time
tNRES
tNREH
tr, tf
7
3
Data hold time*
tH
Notes: Perform reset operation after turning on power supply.
For 1-line access, the following should be satisfied:
*
WE "H" level period ≤ 20 ms − 5120 tWCK − WRES "L" level period
RE "H" level period ≤ 20 ms − 5120 tRCK − RRES "L" level period
REJ03F0250-0200 Rev.2.00 Sep 14, 2007
Page 4 of 13
M66256FP
Test Circuit
VCC
RL = 1 kΩ
Qn
SW1
CL = 30 pF: tAC, tOH
Qn
SW2
CL = 5 pF: tOEN, tODIS
RL = 1 kΩ
Input pulse level:
0 to 3V
Input pulse rise/fall time: 3 ns
Decision voltage input: 1.3 V
Decision voltage output: 1.3 V (However, tODIS (LZ) is 10% of output amplitude and tODIS (HZ) is 90% of that for
decision)
The load capacitance CL includes the floating capacitance of connection and the input capacitance of probe.
Parameter
SW1
Closed
Open
SW2
Open
tODIS (LZ)
tODIS (HZ)
tOEN (ZL)
tOEN (ZH)
Closed
Open
Closed
Open
Closed
tODIS/tOEN Test Condition
3 V
RCK
1.3 V
1.3 V
GND
3 V
RE
GND
tODIS (HZ)
tOEN (ZH)
VOH
90%
1.3 V
Qn
Qn
tODIS (LZ)
tOEN (ZL)
1.3 V
VOL
10%
REJ03F0250-0200 Rev.2.00 Sep 14, 2007
Page 5 of 13
M66256FP
Operating Timing
Write Cycle
Cycle n
Cycle n + 1 Cycle n + 2
Disable cycle
Cycle n + 3 Cycle n + 4
WCK
tWCK
tWCKH tWCKL tWEH tNWES
tNWEH tWES
WE
tDS tDH
tDS tDH
(n)
(n + 1)
(n + 2)
(n + 3)
(n + 4)
Dn
WRES = "H"
Write Reset Cycle
Cycle n − 1
Cycle n
Reset cycle
Cycle 0
Cycle 1
Cycle 2
WCK
tWCK
tNRESH tRESS
tRESH tNRESS
WRES
tDS tDH
tDS tDH
(n − 1)
(n)
(0)
(1)
(2)
Dn
WE = "L"
REJ03F0250-0200 Rev.2.00 Sep 14, 2007
Page 6 of 13
M66256FP
Matters that Needs Attention when WCK Stops
n cycle
n + 1 cycle
n cycle
Disable cycle
WCK
tWCK
tNWES
WE
tDS tDH
tDS tDH
Dn
(n)
(n)
Period for writing data (n)
into memory
Period for writing data (n)
into memory
WRES = "H"
Input data of n cycle is read at the rising edge after WCK of n cycle and writing operation starts in the WCK low-level
period of n + 1 cycle. The writing operation is complete at the falling edge after n + 1 cycle.
To stop reading write data at n cycle, enter WCK before the rising edge after n + 1 cycle.
When the cycle next to n cycle is a disable cycle, WCK for a cycle requires to be entered after the disable cycle as well.
REJ03F0250-0200 Rev.2.00 Sep 14, 2007
Page 7 of 13
M66256FP
Read Cycle
Cycle n
Cycle n + 1 Cycle n + 2
Disable cycle
Cycle n + 3 Cycle n + 4
RCK
tRCK
tRCKH tRCKL tREH tNRES
tNREH tRES
tAC
RE
tODIS
Reset cycle
(0)
tOEN
HIGH-Z
(n)
(n + 1)
(n + 2)
(n + 3)
tOH
(n + 4)
Qn
RRES = "H"
Read Reset Cycle
Cycle n − 1
Cycle n
Cycle 0
Cycle 1
Cycle 2
RCK
tRCK
tNRESH tRESS
tRESH tNRESS
RRES
tAC
(n − 1)
(n)
(0)
(0)
tOH
(1)
(2)
Qn
RE = "L"
REJ03F0250-0200 Rev.2.00 Sep 14, 2007
Page 8 of 13
M66256FP
Variable Length Delay Bits
1-line (5120 Bits) Delay
A write input data is written into memory at the second rise edge of WCK in the cycle, and a read output data is output
from memory at the first rise edge of RCK in the cycle, so that 1-line delay can be made easily.
Cycle 5120 Cycle 5121 Cycle 5122
Cycle 0
Cycle 1
Cycle 2
Cycle 5118 Cycle 5119
(0')
(1')
(2')
WCK
RCK
tRESS tRESH
WRES
RRES
tDS tDH
tDS tDH
(0)
(1)
(2)
(5117)
(5118)
(5119)
(0')
(1')
(1)
(2')
(2)
(3')
(3)
Dn
Qn
tAC
tOH
5120 cycles
(0)
WE, RE = "L"
N-bit Delay Bit
(Making a reset at a cycle corresponding to delay length)
Cycle n Cycle n + 1 Cycle n + 2 Cycle n + 3
(0') (1') (2') (3')
Cycle 0
Cycle 1
Cycle 2
Cycle n − 2 Cycle n − 1
WCK
RCK
tRESS tRESH
tRESS tRESH
WRES
RRES
tDS tDH
tDS tDH
(0)
(1)
(2)
(n − 3)
(n − 2)
(n − 1)
(0')
(1')
(1)
(2')
(2)
(3')
(3)
Dn
Qn
tAC
tOH
m cycles
(0)
WE, RE = "L"
m ≥ 3
REJ03F0250-0200 Rev.2.00 Sep 14, 2007
Page 9 of 13
M66256FP
N-bit Delay 2
(Sliding WRES and RRES at a cycle corresponding to delay length)
Cycle 0
Cycle 1
Cycle 2 Cycle n − 2 Cycle n − 1 Cycle n Cycle n + 1 Cycle n + 2 Cycle n + 3
WCK
RCK
tRESS tRESH
WRES
RRES
tRESS tRESH
tDS tDH
tDS tDH
(0)
(1)
(2)
(n − 2)
(n − 1)
(n)
(n + 1)
(n + 2)
(n + 3)
Dn
Qn
tAC
tOH
m cycles
(0)
(1)
(2)
(3)
WE, RE = "L"
m ≥ 3
N-bit Delay 3
(Disabling RE at a cycle corresponding to delay length)
Cycle 0
Cycle 1
Cycle 2
Cycle n − 1 Cycle n Cycle n + 1 Cycle n + 2 Cycle n + 3
WCK
RCK
tRESS tRESH
WRES
RRES
tNREH tRES
RE
tDS tDH
tDS tDH
(0)
(1)
(2)
(n − 2)
(n − 1)
(n)
(n + 1)
(n + 2)
(n + 3)
Dn
tAC
tOH
m cycles
HIGH-Z
(0)
(1)
(2)
(3)
Qn
WE = "L"
m ≥ 3
REJ03F0250-0200 Rev.2.00 Sep 14, 2007
Page 10 of 13
M66256FP
Shortest Read of Data "n" Written in Cycle n
(Cycle n − 1 on read side should be started after end of cycle n + 1 on write side)
When the start of cycle n − 1 on read side is earlier than the end of cycle n + 1 on write side, output Qn of cycle n
becomes invalid.
In the figure shown below, the read of cycle n − 1 is invalid.
Cycle n
Cycle n + 1
Cycle n + 2
Cycle n + 3
WCK
Dn
(n)
(n + 1)
(n + 2)
(n + 3)
Cycle n − 2
Cycle n − 1
Cycle n
RCK
Qn
Invalid
(n)
Longest Read of Data "n" Written in Cycle n: 1-line Delay
(Cycle n <1>* on read side should be started when cycle n <2>* on write is started)
Output Qn of n cycle <1>* can be read until the start of reading side n cycle <1>* and the start of writing side n cycle
<2>* overlap each other.
Cycle n <1>*
Cycle 0 <2>*
Cycle n <2>*
WCK
Dn
(n) <1>*
(00) <2>*
(n − 1) <2>*
(n) <2>*
(n − 1) <1>*
Cycle n <0>*
Cycle 0 <1>*
Cycle n <1>*
RCK
Qn
(n − 1) <0>*
(n) <0>*
(0) <1>*
(n − 1) <1>*
(n) <1>*
Note: <0>*, <1>* and <2>* indicates a line value.
REJ03F0250-0200 Rev.2.00 Sep 14, 2007
Page 11 of 13
M66256FP
Application Example
Laplacian Filter Circuit for Correction of Resolution in the Secondary Scanning Direction
N
M66256
Line n image data
D0 Q0
to
to
B
D7 Q7
Line (n + 1)
image data
Corrected
× 2
image data
1-line
delay
× K
M66256
D0 Q0
A
Line (n − 1)
image data
to
to
D7 Q7
1-line
delay
Primary scanning
direction
A
N
B
Line (n − 1)
Line n
N' = N + K { (N − A) + (N − B) }
= N + K {2N − (A + B)}
Line (n + 1)
K: Laplacian coefficient
REJ03F0250-0200 Rev.2.00 Sep 14, 2007
Page 12 of 13
M66256FP
Package Dimensions
24P2U-A
Plastic 24pin 375mil SSOP
EIAJ Package Code
SSOP24-P-375-0.80
JEDEC Code
—
Weight(g)
0.4
Lead Material
Cu Alloy
e
b2
24
13
F
Recommended Mount Pad
Dimension in Millimeters
Symbol
1
12
Min
—
0.1
—
0.3
0.23
10.2
7.4
—
10.0
0.5
—
—
—
—
0°
—
—
1.27
Nom
—
Max
2.65
0.3
—
0.45
0.3
10.4
7.6
—
A
A
A
A
1
2
0.2
2.3
0.35
0.25
10.3
7.5
0.8
10.3
0.7
1.4
0.75
—
—
—
0.5
9.53
—
D
G
b
c
D
E
e
A2
A1
e
b
y
HE
10.6
0.9
—
L
L1
z
—
Z1
0.9
0.1
8°
—
—
y
c
z
b2
Z1
Detail G
Detail F
e1
I
2
—
REJ03F0250-0200 Rev.2.00 Sep 14, 2007
Page 13 of 13
Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Notes:
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but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples.
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and regulations, and procedures required by such laws and regulations.
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© 2007. Renesas Technology Corp., All rights reserved. Printed in Japan.
Colophon .7.0
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