M66257FP [MITSUBISHI]
5120 x 8-BIT x 2 LINE MEMORY (FIFO); 5120 ×8位× 2行存储器（ FIFO ）
| 型号： | M66257FP |
| 厂家： | 
Mitsubishi Group |
| 描述： | 5120 x 8-BIT x 2 LINE MEMORY (FIFO) |
| 文件： | 总10页 (文件大小：124K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MITSUBISHI DIGITALASSP
M66257FP
)
5120 × 8-BIT × 2 LINE MEMORY (FIFO)
DESCRIPTION
PIN CONFIGURATION (TOP VIEW)
The M66257FP is a high-speed line memory with a FIFO
(First In First Out) structure of 5120-word × 8-bit double con-
figuration which uses high-performance silicon gate CMOS
process technology.
It allows simultaneous output of 1-line delay data and 2-line
delay data, and is most suitable for data correction over mul-
tiple lines.
It has separate clock, enable and reset signals for write and
read, and is most suitable as a buffer memory between de-
vices with different data processing throughput.
GND
1
2
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
VCC
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
READ ENABLE INPUT
READ RESET INPUT
READ CLOCK INPUT
WRITE ENABLE INPUT
WRITE RESET INPUT
WRITE CLOCK INPUT
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
00
01
02
03
04
05
06
07
10
11
12
13
14
15
16
17
RE
3
RRES
RCK
WE
4
5
6
WRES
WCK
GND
7
8
FEATURES
9
V
D
D
D
D
D
D
D
D
CC
DATA OUTPUT
• Memory configuration of 5120 words × 8 bits × 2 (dynamic
memory)
←
←
←
←
←
←
←
←
10
11
12
13
14
15
16
17
18
0
1
• High-speed cycle ............................................. 25ns (Min.)
• High-speed access ......................................... 18ns (Max.)
• Output hold ........................................................ 3ns (Min.)
• Fully independent, asynchronous write and read operations
• Output ....................................................................3 states
• Q00 to Q07 ........................................................ 1-line delay
• Q10 to Q17 ........................................................ 2-line delay
2
3
DATA INPUT
4
5
6
7
V
CC
GND
APPLICATION
Digital photocopiers, high-speed facsimile, laser beam print-
ers.
Outline 36P2R-A
BLOCK DIAGRAM
DATA INPUT
DATA OUTPUT
DATA OUTPUT
~
~
~
D0 D7
Q00 Q07
Q10 Q17
27 26 25 24 23 22 21 20
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
INPUT BUFFER
OUTPUT BUFFER
WRITE
ENABLE INPUT
READ
ENABLE INPUT
WE 32
WRES 31
WCK 30
35 RE
MEMORY ARRAY OF
WRITE
RESET INPUT
5120-WORD × 8-BIT × 2 CONFIGURATION
1-LINE DELAY DATA ONLY MEMORY/
2-LINE DELAY DATA ONLY MEMORY
READ
RESET INPUT
34 RRES
33 RCK
WRITE
CLOCK INPUT
READ
CLOCK INPUT
VCC 18
VCC 28
VCC 36
1 GND
19 GND
29 GND
1
MITSUBISHI DIGITAL ASSP
M66257FP
5120 × 8-BIT × 2 LINE MEMORY (FIFO)
FUNCTION
Moreover, data of Q00 to Q07 are written into 2-line delay data
only memory in synchronization with rise edge of RCK. At
this time, the write address of 2-line delay data only memory
is incremented.
The read functions given below are also performed in syn-
chronization with rise edge of RCK.
When write enable input WE is “L”, the contents of data inputs
D0 to D7 are written into 1-line delay data only memory in syn-
chronization with rise edge of write clock input WCK. At this
time, the write address counter of 1-line delay data only
memory is also incremented simultaneously.
The write functions given below are also performed in syn-
chronization with rise edge of WCK.
When WE is “H”, a write operation to 1-line delay data only
memory is inhibited and the write address counter of 1-line
delay data only memory is stopped.
When RE is “H”, a read operation from both of 1-line delay
data only memory and 2-line delay data only memory is inhib-
ited and the read address counter of each memory is
stopped. The outputs of Q00 to Q07 and Q10 to Q17 are in the
high impedance state.
When write reset input WRES is “L”, the write address counter
of 1-line delay data only memory is initialized.
Moreover, a write operation to 2-line delay data only memory
is inhibited and the write address counter of 2-line delay data
only memory is stopped.
When read reset input RRES is “L”, the read address counter
of 1-line delay data only memory, and the write address
counter and read address counter of 2-line delay data only
memory are initialized.
When read enable input RE is “L”, the contents of 1-line delay
data only memory are output to data outputs Q00 to Q07 and
those of 2-line delay data only memory to data outputs Q10 to
Q17 in synchronization with the rise of read clock input RCK.
At this time, the read address counters of 1-line and 2-line
delay data only memories is also incremented simulta-
neously.
2
MITSUBISHI DIGITAL ASSP
M66257FP
5120 × 8-BIT × 2 LINE MEMORY (FIFO)
ABSOLUTE MAXIMUM RATINGS (Ta = 0 ~ 70°C, unless otherwise noted)
Symbol Parameter
Conditions
A value based on GND pin
Ta = 25°C
Ratings
–0.5 ~ +7.0
–0.5 ~ VCC + 0.5
–0.5 ~ VCC + 0.5
660
Unit
V
VCC
Supply voltage
Input voltage
Output voltage
VI
V
VO
Pd
Tstg
V
Maximum power dissipation
Storage temperature
mW
°C
–65 ~ 150
RECOMMENDED OPERATING CONDITIONS
Limits
Symbol
Parameter
Unit
Min.
4.5
Typ.
5
Max.
5.5
VCC
Supply voltage
Supply voltage
V
V
GND
Topr
0
Operating ambient temperature
0
70
°C
ELECTRICAL CHARACTERISTICS (Ta = 0 ~ 70°C, VCC = 5V ± 10%, GND = 0V, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Test conditions
Unit
Min.
2.0
Max.
0.8
VIH
VIL
“H” input voltage
V
V
V
V
“L” input voltage
“H” output voltage
“L” output voltage
VOH
VOL
IOH = –4mA
IOL = 4mA
VCC–0.8
0.55
1.0
WE, WRES, WCK, RE,
RRES, RCK,
D0 ~ D7
IIH
IIL
“H” input current
“L” input current
VI = VCC
mA
mA
WE, WRES, WCK, RE,
RRES, RCK,
D0 ~ D7
VI = GND
–1.0
IOZH
IOZL
Off state “H” output current
Off state “L” output current
VO = VCC
VO = GND
5.0
mA
mA
–5.0
Operating mean current dissipa-
tion
VI = VCC, GND, Output open
tWCK, tRCK = 25ns
ICC
120
mA
CI
Input capacitance
f = 1MHz
f = 1MHz
10
15
pF
pF
CO
Off state output capacitance
3
MITSUBISHI DIGITAL ASSP
M66257FP
5120 × 8-BIT × 2 LINE MEMORY (FIFO)
SWITCHING CHARACTERISTICS (Ta = 0 ~ 70°C, VCC = 5V ± 10%, GND = 0V, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Unit
Min.
Max.
18
tAC
tOH
Access time
ns
ns
ns
ns
Output hold time
Output enable time
Output disable time
3
3
3
tOEN
18
18
tODIS
TIMING CONDITIONS (Ta = 0 ~ 70°C, VCC = 5V ± 10%, GND = 0V, unless otherwise noted)
Symbol Parameter
Limits
Typ.
Unit
Min.
25
11
11
25
11
11
7
Max.
tWCK
Write clock (WCK) cycle
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
tWCKH
tWCKL
tRCK
Write clock (WCK) “H” pulse width
Write clock (WCK) “L” pulse width
Read clock (RCK) cycle
tRCKH
tRCKL
tDS
Read clock (RCK) “H” pulse width
Read clock (RCK) “L” pulse width
Input data setup time to WCK
Input data hold time to WCK
Reset setup time to WCK or RCK
Reset hold time to WCK or RCK
tDH
3
tRESS
tRESH
tNRESS
tNRESH
tWES
tWEH
tNWES
tNWEH
tRES
7
3
Reset nonselect setup time to WCK or RCK
Reset nonselect hold time to WCK or RCK
WE setup time to WCK
7
3
7
WE hold time to WCK
3
WE nonselect setup time to WCK
WE nonselect hold time to WCK
RE setup time to RCK
7
3
7
tREH
RE hold time to RCK
3
tNRES
tNREH
tr, tf
RE nonselect setup time to RCK
RE nonselect hold time to RCK
Input pulse rise/fall time
7
3
20
20
tH
Data hold time (Note 1)
Note 1: For 1-line access, the following should be satisfied:
WE “H” level period < 20ms – 5120 tWCK – WRES “L” level period
RE “H” level period < 20ms – 5120 tRCK – RRES “L” level period
2: Reset the IC after power is turned on.
4
MITSUBISHI DIGITAL ASSP
M66257FP
5120 × 8-BIT × 2 LINE MEMORY (FIFO)
TEST CIRCUIT
V
CC
RL=1kΩ
Q
n
SW1
SW2
CL=30pF : tAC, tOH
Qn
CL=5pF : tOEN, tODIS
RL=1kΩ
Input pulse level
Input pulse rise/fall time : 3ns
Decision voltage input : 1.3V
: 0 ~ 3V
Parameter
SW1
SW2
tODIS(LZ)
tODIS(HZ)
tOEN(ZL)
tOEN(ZH)
Closed
Open
Open
Closed
Open
Decision voltage output : 1.3V (However, tODIS(LZ) is 10% of output amplitude and tODIS(HZ) is 90% of
that for decision).
Closed
Open
The load capacitance CL includes the floating capacitance of connection and the input capacitance of
probe.
Closed
tODIS/tOEN TEST CONDITION
3V
1.3V
1.3V
RCK
GND
3V
RE
GND
tODIS(HZ)
tOEN(ZH)
VOH
90%
Q0n
Q1n
1.3V
1.3V
tODIS(LZ)
tOEN(ZL)
Q0n
Q1n
10%
VOL
5
MITSUBISHI DIGITAL ASSP
M66257FP
5120 × 8-BIT × 2 LINE MEMORY (FIFO)
OPERATING TIMING
• Write cycle
Cycle n
Cycle n+1
Cycle n+2
Disable cycle
Cycle n+3
Cycle n+4
WCK
t
WCK
t
WCKH
t
WCKL
t
WEH
t
NWES
t
NWEH
tWES
WE
t
DS
t
DH
t
DS
tDH
(n)
( n+1)
(n+2)
(n+3)
(n+4)
Dn
WRES = “H”
• Write reset cycle
Cycle n–1
Cycle n
Reset cycle
Cycle 0
Cycle 1
Cycle 2
WCK
t
WCK
t
NRESH
t
RESS
t
RESH
tNRESS
WRES
t
DS
t
DH
t
DS
tDH
(n–1)
(n)
(0)
(1)
(2)
D
n
WE = “L”
6
MITSUBISHI DIGITAL ASSP
M66257FP
5120 × 8-BIT × 2 LINE MEMORY (FIFO)
• Read cycle
Cycle n
Cycle n+1
Cycle n+2
Disable cycle
Cycle n+3
Cycle n+4
RCK
t
RCK
t
RCKH
t
RCKL
t
REH
t
NRES
t
NREH
tRES
t
AC
RE
t
ODIS
tOEN
Q
Q
0n
1n
HIGH-Z
(n)
(n+1)
(n+2)
(n+3)
(n+4)
t
OH
RRES = “H”
• Read reset cycle
Cycle n–1
Cycle n
Reset cycle
Cycle 0
Cycle 1
Cycle 2
RCK
t
RCK
t
NRESH
t
RESS
tRESH tNRESS
RRES
t
AC
Q
Q
0n
1n
(n–1)
(n)
(0)
(0)
(0)
t
(1)
(2)
t
ON
t
ON
ON
RE = “L”
7
MITSUBISHI DIGITAL ASSP
M66257FP
5120 × 8-BIT × 2 LINE MEMORY (FIFO)
• Note at WCK stop
n cycle
tWCK
n+1 cycle
n cycle
Disable cycle
WCK
WE
tNWES
tDS tDH
tDS tDH
(n)
(n)
Dn
Period of writing data (n)
into memory
Period of writing data (n)
into memory
WRES = “H”
Input data Dn of n cycle is read at the rising edge after WCK of n cycle. Writing operation starts in the “L” period of WCK of n+1
cycle and ends at the rising edge after n+1 cycle.
To stop reading write data at n cycle, input WCK for up to the rising edge of n+1 cycle.
When the cycle next to n cycle is a disable cycle, input of WCK for a cycle is required after a disable cycle as well.
8
MITSUBISHI DIGITAL ASSP
M66257FP
5120 × 8-BIT × 2 LINE MEMORY (FIFO)
• Shortest read of data “n” written in cycle n
Cycle n–1 on read side should be started after end of cycle n+1 on write side
When the start of cycle n–1 on read side is earlier than the end of cycle n+1 on write side, output Qn of cycle n becomes invalid.
In the figure shown below, the read of cycle n–1 is invalid.
Cycle n
Cycle n+1
Cycle n+2
Cycle n+3
WCK
(n)
(n+1)
(n+2)
(n+3)
Dn
Cycle n–2
Cycle n–1
Cycle n
RCK
Q
n
invalid
(n)
• Longest read of data “n” written in cycle n: 1-line delay
Cycle n <1>* on read side should be started when cycle n <2>* on write is started
Output Qn of n cycle <1>* can be read until the start of reading side n cycle <1> and the start of writing side n cycle <2>* over-
lap each other.
Cycle n <1>*
Cycle 0 <2>*
Cycle n <2>*
WCK
(n–1)<1>*
(n)<1>*
(0) <2>*
(n–1)<2>*
(n)<2>*
Dn
Cycle n <0>*
Cycle 0 <1>*
Cycle n <1>*
RCK
(0)<1>*
(n–1)<1>*
(n)<1>*
(n–1)<0>*
(n)<0>*
Qn
<0>*, <1>* and <2>* indicates a line value.
9
MITSUBISHI DIGITAL ASSP
M66257FP
5120 × 8-BIT × 2 LINE MEMORY (FIFO)
APPLICATION EXAMPLE
Laplacian Filter Circuit for Correction of Resolution in the Secondary Scanning Direction.
N
Line n image data
M66257
D0
D7
Q00
Q07
B
Corrected
image data
Line (n+1)
image data
×2
1-line
delay
×K
A
Line (n–1)
image data
Q10
Q17
2-line
delay
Primary scanning
direction
Line (n–1)
Line n
A
N
B
N' = N+K {(N–A)+(N–B)}
= N+K { 2N–(A+B)}
K : Laplacean coefficient
Line (n+1)
10
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