NL17SH126P5T5G [ONSEMI]
Noninverting 3-State Buffer; 同相三态缓冲器
| 型号： | NL17SH126P5T5G |
| 厂家： | 
ONSEMI |
| 描述： | Noninverting 3-State Buffer |
| 文件： | 总5页 (文件大小：110K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NL17SH126
Noninverting 3-State Buffer
The NL17SH126 is an advanced high speed CMOS noninverting
3−state buffer fabricated with silicon gate CMOS technology. It
achieves high speed operation similar to equivalent Bipolar Schottky
TTL while maintaining CMOS low power dissipation.
The internal circuit is composed of three stages, including a buffered
3−state output which provides high noise immunity and stable output.
The NL17SH126 input structure provides protection when voltages
up to 7 V are applied, regardless of the supply voltage. This allows the
NL17SH126 to be used to interface 5 V circuits to 3 V circuits.
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MARKING
DIAGRAM
Features
SOT−953
CASE 527AE
JM
• High Speed: t = 3.5 ns (Typ) at V = 5 V
1
PD
CC
• Low Power Dissipation: I = 1 mA (Max) at T = 25°C
CC
A
J
M
= Specific Device Code
= Month Code
• Power Down Protection Provided on Inputs
• Balanced Propagation Delays
• Pin and Function Compatible with Other Standard Logic Families
• These are Pb−Free Devices
PIN ASSIGNMENT
1
2
3
4
5
IN A
GND
OE
5
IN A
GND
OE
1
2
3
V
CC
OUT Y
V
CC
FUNCTION TABLE
OE Input
4
OUT Y
A Input
Y Output
L
H
X
H
H
L
L
H
Z
Figure 1. Pinout (Top View)
OE
IN A
EN
OUT Y
ORDERING INFORMATION
See detailed ordering and shipping information in the
package dimensions section on page 4 of this data sheet.
Figure 2. Logic Symbol
© Semiconductor Components Industries, LLC, 2011
1
Publication Order Number:
August, 2011 − Rev. 1
NL17SH126/D
NL17SH126
MAXIMUM RATINGS
Symbol
Characteristics
Value
Unit
V
V
CC
DC Supply Voltage
DC Input Voltage
DC Output Voltage
−0.5 to +7.0
−0.5 to +7.0
−0.5 to 7.0
V
IN
V
V
OUT
V
= 0
CC
V
High or Low State
−0.5 to V + 0.5
CC
I
Input Diode Current
−20
20
mA
mA
mA
mA
mW
°C
IK
I
Output Diode Current
DC Output Current, per Pin
V
< GND; V
> V
OK
OUT
OUT CC
I
25
OUT
I
DC Supply Current, V and GND
50
CC
CC
P
Power dissipation in still air
50
D
T
Lead temperature, 1 mm from case for 10 secs
Junction temperature under bias
Storage temperature
260
L
T
+150
−65 to +150
100
°C
J
T
stg
°C
I
Latchup Performance
Above V and Below GND at 125°C (Note 1)
mA
Latchup
CC
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol
Characteristics
Min
2.0
0.0
0.0
−55
Max
5.5
Unit
V
V
CC
DC Supply Voltage
V
IN
DC Input Voltage
5.5
V
V
OUT
DC Output Voltage
V
CC
V
T
A
Operating Temperature Range
Input Rise and Fall Time
+125
°C
ns/V
t , t
V
CC
V
CC
= 3.3 V 0.3 V
= 5.0 V 0.5 V
0
0
100
20
r
f
Device Junction Temperature versus
Time to 0.1% Bond Failures
Junction
Temperature °C
FAILURE RATE OF PLASTIC = CERAMIC
UNTIL INTERMETALLICS OCCUR
Time, Hours
Time, Years
117.8
47.9
80
1,032,200
419,300
178,700
79,600
37,000
17,800
8,900
90
100
110
120
130
140
20.4
1
9.4
4.2
1
10
100
1000
2.0
TIME, YEARS
1.0
Figure 3. Failure Rate vs. Time Junction Temperature
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2
NL17SH126
DC ELECTRICAL CHARACTERISTICS
T
A
= 25°C
T
A
≤ 85°C
−55 ≤ T ≤ 125°C
A
V
CC
Min
Typ
Max
Min
Max
Min
Max
(V)
Symbol
Parameter
Test Conditions
Unit
V
IH
Minimum High−Level
Input Voltage
2.0
3.0
4.5
5.5
1.5
2.1
3.15
3.85
1.5
2.1
3.15
3.85
1.5
2.1
3.15
3.85
V
V
IL
Maximum Low−Level
Input Voltage
2.0
3.0
4.5
5.5
0.5
0.9
1.35
1.65
0.5
0.9
1.35
1.65
0.5
0.9
1.35
1.65
V
V
Minimum High−Level
V
OH
= V or V
2.0
3.0
4.5
1.9
2.9
4.4
2.0
3.0
4.5
1.9
2.9
4.4
1.9
2.9
4.4
V
V
V
V
OH
IN
IH
IL
IL
IL
IL
IL
Output Voltage
I
= −50 mA
V
IN
= V or V
IH IL
V
= V or V
IN
OH
OH
IH
I
I
= −4 mA
= −8 mA
3.0
4.5
2.58
3.94
2.48
3.80
2.34
3.66
V
Maximum Low−Level
V
OL
= V or V
2.0
3.0
4.5
0.0
0.0
0.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
OL
IN
IH
Output Voltage
I
= 50 mA
V
IN
= V or V
IH IL
V
= V or V
IN
OL
OL
IH
I
I
= 4 mA
= 8 mA
3.0
4.5
0.36
0.36
0.44
0.44
0.52
0.52
I
Maximum 3−State
Leakage Current
V
V
= V or V
5.5
0.2
5
2.5
1.0
20
2.5
1.0
40
mA
mA
mA
OZ
IN
OUT
IH
= V or GND
CC
I
Maximum Input
Leakage Current
V
= 5.5 V or GND
0 to
5.5
0.1
IN
IN
IN
I
Maximum Quiescent
Supply Current
V
= V or GND
5.5
1.0
CC
CC
AC ELECTRICAL CHARACTERISTICS C
= 50 pF, Input t = t = 3.0 ns
r f
load
T
A
= 25°C
T
A
≤ 85°C
−55 ≤ T ≤ 125°C
A
Min
Typ
Max
Min
Max
Min
Max
Symbol
Parameter
Test Conditions
Unit
t
,
Maximum Propagation
Delay, Input A to Y
(Figures 3. and 5.)
V
V
V
= 3.3 0.3 V C = 15 pF
4.5
6.4
8.0
9.5
12.0
16.0
ns
PLH
CC
CC
CC
L
t
C = 50 pF
11.5
13.0
PHL
L
= 5.0 0.5 V C = 15 pF
3.5
4.5
5.5
7.5
6.5
8.5
8.5
10.5
L
C = 50 pF
L
t
,
Maximum Output Enable
Time, Input OE to Y
(Figures 4. and 5.)
= 3.3 0.3 V C = 15 pF
4.5
6.4
8.0
11.5
9.5
13.0
11.5
15.0
ns
ns
PZL
L
L
t
R = 1000 W
C = 50 pF
PZH
L
V
CC
= 5.0 0.5 V C = 15 pF
3.5
4.5
5.1
7.1
6.0
8.0
8.5
10.5
L
R = 1000 W
C = 50 pF
L
L
t
,
Maximum Output Disable
Time, Input OE to Y
(Figures 4. and 5.)
V
CC
= 3.3 0.3 V C = 15 pF
6.5
8.0
9.7
13.2
11.5
15.0
14.5
18.0
PLZ
L
t
R = 1000 W
C = 50 pF
PHZ
L
L
V
CC
= 5.0 0.5 V C = 15 pF
4.8
7.0
6.8
8.8
8.0
10.0
10.0
12.0
L
R = 1000 W
C = 50 pF
L
L
C
Maximum Input
Capacitance
4.0
10
10
10
pF
pF
IN
C
Maximum 3−State Output
Capacitance (Output in
High Impedance State)
6.0
OUT
Typical @ 25°C, V = 5.0 V
CC
8.0
C
Power Dissipation Capacitance (Note 2)
pF
PD
2. C is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
PD
Average operating current can be obtained by the equation: I
) = C ꢀ V ꢀ f + I . C is used to determine the no−load dynamic
CC(OPR
PD CC in CC PD
2
power consumption; P = C ꢀ V
ꢀ f + I ꢀ V
.
D
PD
CC
in
CC
CC
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3
NL17SH126
SWITCHING WAVEFORMS
V
CC
OE
50%
GND
t
t
PZL
PLZ
HIGH
V
CC
IMPEDANCE
50%
50% V
Y
Y
CC
A
Y
V
+ 0.3V
OL
GND
t
t
PZH
PHZ
t
PHL
t
PLH
V
OH
- 0.3V
50% V
CC
50% V
CC
HIGH
IMPEDANCE
Figure 4. Switching Waveforms
Figure 5.
TEST POINT
1 kW
TEST POINT
OUTPUT
CONNECT TO V WHEN
CC
TESTING t AND t
PLZ
OUTPUT
PZL.
DEVICE
UNDER
TEST
CONNECT TO GND WHEN
TESTING t AND t
DEVICE
UNDER
TEST
PHZ
PZH.
C *
L
C *
L
*Includes all probe and jig capacitance
*Includes all probe and jig capacitance
Figure 6. Test Circuit
Figure 7. Test Circuit
INPUT
Figure 8. Input Equivalent Circuit
Package
ORDERING INFORMATION
†
Device
Shipping
8000 Units / Tape & Reel
NL17SH126P5T5G
SOT−953
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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4
NL17SH126
PACKAGE DIMENSIONS
SOT−953
CASE 527AE
ISSUE E
NOTES:
X
Y
D
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
A
2. CONTROLLING DIMENSION: MILLIMETERS
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD
FINISH. MINIMUM LEAD THICKNESS IS THE
MINIMUM THICKNESS OF THE BASE MATERIAL.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR GATE BURRS.
5
4
3
PIN ONE
H
E
INDICATOR
E
1
2
MILLIMETERS
DIM MIN
NOM
0.37
0.15
0.12
1.00
MAX
0.40
0.20
0.17
1.05
0.85
A
b
0.34
0.10
0.07
0.95
0.75
C
TOP VIEW
e
C
D
SIDE VIEW
E
e
0.80
0.35 BSC
HE
L
0.95
1.00
0.175 REF
1.05
5X
L
L2
L3
0.05
−−−
0.10
−−−
0.15
0.15
5X
5X
L3
L2
SOLDERING FOOTPRINT*
5X
0.35
5X
0.20
5X
b
PACKAGE
OUTLINE
0.08 X
Y
BOTTOM VIEW
1.20
1
0.35
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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NL17SH126/D
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