NL17SHT00P5T5G [ONSEMI]
Single 2-Input NAND Gate CMOS Logic Level Shifter;型号: | NL17SHT00P5T5G |
厂家: | ONSEMI |
描述: | Single 2-Input NAND Gate CMOS Logic Level Shifter 栅 光电二极管 逻辑集成电路 触发器 |
文件: | 总5页 (文件大小:103K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
NL17SHT00
Single 2-Input NAND Gate/
CMOS Logic Level Shifter
LSTTL−Compatible Inputs
The NL17SHT00 is a single gate 2−input NAND fabricated with
silicon gate CMOS technology.
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MARKING
The internal circuit is composed of multiple stages, including a
buffer output which provides high noise immunity and stable output.
The device input is compatible with TTL−type input thresholds and
the output has a full 5 V CMOS level output swing. The input
protection circuitry on this device allows overvoltage tolerance on the
input, allowing the device to be used as a logic−level translator from
3 V CMOS logic to 5 V CMOS Logic or from 1.8 V CMOS logic to
3 V CMOS Logic while operating at the high voltage power supply.
The NL17SHT00 input structure provides protection when voltages
up to 7 V are applied, regardless of the supply voltage. This allows the
NL17SHT00 to be used to interface 5 V circuits to 3 V circuits. The
DIAGRAM
SOT−953
CASE 527AE
KM
1
K
M
= Specific Device Code
= Month Code
output structures also provide protection when V = 0 V. These
CC
PIN ASSIGNMENT
input and output structures help prevent device destruction caused by
supply voltage − input/output voltage mismatch, battery backup, hot
insertion, etc.
1
2
3
4
5
IN A
GND
IN B
Features
OUT Y
• High Speed: t = 3.1 ns (Typ) at V = 5 V
PD
CC
V
CC
• Low Power Dissipation: I = 1 mA (Max) at T = 25°C
CC
A
• TTL−Compatible Inputs: V = 0.8 V; V = 2 V
IL
IH
FUNCTION TABLE
• CMOS−Compatible Outputs: V > 0.8 V ; V < 0.1 V @Load
OH
CC
OL
CC
Inputs
Output
Y
• Power Down Protection Provided on Inputs and Outputs
• Balanced Propagation Delays
• Pin and Function Compatible with Other Standard Logic Families
• These are Pb−Free Devices
A
B
L
L
L
H
L
H
H
H
L
H
H
H
5
1
2
3
V
CC
IN A
GND
IN B
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
4
OUT Y
Figure 1. Pinout
IN A
IN B
&
OUT Y
Figure 2. Logic Symbol
© Semiconductor Components Industries, LLC, 2011
1
Publication Order Number:
August, 2011 − Rev. 0
NL17SHT00/D
NL17SHT00
MAXIMUM RATINGS
Symbol
Characteristics
Value
Unit
V
V
CC
DC Supply Voltage
DC Input Voltage
DC Output Voltage
−0.5 to +7.0
−0.5 to +7.0
−0.5 to 7.0
V
IN
V
V
OUT
V
= 0
CC
V
High or Low State
−0.5 to V + 0.5
CC
I
Input Diode Current
Output Diode Current
DC Output Current
−20
mA
mA
mA
mA
_C
IK
I
V
< GND; V
> V
CC
20
OK
OUT
OUT
I
25
OUT
I
DC Supply Current, V and GND
50
CC
CC
T
Storage Temperature Range
*65 to )150
STG
T
Lead Temperature, 1 mm from Case for 10 Seconds
Junction Temperature Under Bias
Power Dissipation in Still Air at 85_C
Moisture Sensitivity
260
_C
L
T
)150
_C
J
P
50
Level 1
mW
D
MSL
F
Flammability Rating
Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
100
R
I
Latchup Performance
Above V and Below GND at 125_C (Note 1)
mA
LATCHUP
CC
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol
Characteristics
Min
3.0
0.0
Max
5.5
5.5
5.5
Unit
V
V
CC
DC Supply Voltage
DC Input Voltage
DC Output Voltage
V
IN
V
V
OUT
V
= 0
CC
0.0
0.0
V
High or Low State
V
CC
T
Operating Temperature Range
Input Rise and Fall Time
−55
+125
°C
A
t , t
r
V
CC
V
CC
= 3.3 V 0.3 V
= 5.0 V 0.5 V
0
0
100
20
ns/V
f
Device Junction Temperature versus
Time to 0.1% Bond Failures
FAILURE RATE OF PLASTIC = CERAMIC
UNTIL INTERMETALLICS OCCUR
Junction
Temperature °C
Time, Hours
1,032,200
419,300
178,700
79,600
Time, Years
117.8
47.9
80
90
100
110
120
130
140
20.4
1
9.4
37,000
4.2
1
10
100
1000
17,800
2.0
TIME, YEARS
8,900
1.0
Figure 3. Failure Rate vs. Time Junction Temperature
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2
NL17SHT00
DC ELECTRICAL CHARACTERISTICS
T
A
= 25°C
T
A
≤ 85°C
−55 ≤ T ≤ 125°C
A
V
CC
Min
Typ
Max
Min
Max
Min
Max
(V)
Symbol
Parameter
Test Conditions
Unit
V
IH
Minimum High−Level
Input Voltage
3.0
4.5
5.5
1.4
2.0
2.0
1.4
2.0
2.0
1.4
2.0
2.0
V
V
IL
Maximum Low−Level
Input Voltage
3.0
4.5
5.5
0.53
0.8
0.8
0.53
0.8
0.8
0.53
0.8
0.8
V
V
OH
Minimum High−Level
V
OH
= V or V
3.0
4.5
2.9
4.4
3.0
4.5
2.9
4.4
2.9
4.4
V
V
IN
IH
IL
Output Voltage
I
= −50 mA
V
IN
= V or V
IH IL
V
= V or V
IN
OH
OH
IH
IL
I
I
= −4 mA
= −8 mA
3.0
4.5
2.58
3.94
2.48
3.80
2.34
3.66
V
OL
Maximum Low−Level
V
OL
= V or V
3.0
4.5
0.0
0.0
0.1
0.1
0.1
0.1
0.1
0.1
V
V
IN
IH
IL
Output Voltage
I
= 50 mA
V
IN
= V or V
IH IL
V
= V or V
IN
OL
OL
IH
IL
I
I
= 4 mA
= 8 mA
3.0
4.5
0.36
0.36
0.44
0.44
0.52
0.52
I
Maximum Input
Leakage Current
V
= 5.5 V or GND
0 to
5.5
0.1
1.0
1.0
mA
mA
mA
mA
IN
IN
I
Maximum Quiescent
Supply Current
V
IN
= V or GND
5.5
5.5
0.0
1.0
20
40
CC
CC
I
Quiescent Supply
Current
Input: V = 3.4 V
1.35
0.5
1.50
5.0
1.65
10
CCT
IN
I
Power Off Output
Leakage Current
V
OUT
= 5.5 V
OFF
AC ELECTRICAL CHARACTERISTICS Input t = t = 3.0 ns
r
f
T
A
= 25°C
T
A
≤ 85°C
−55 ≤ T ≤ 125°C
A
Min
Typ
Max
Min
Max
Min
Max
Symbol
Parameter
Test Conditions
Unit
t
,
Maximum Propagation
Delay, Input A or B to Y
V
V
= 3.3 0.3 V C = 15 pF
4.1
5.5
10.0
13.5
11.0
15.0
13.0
17.5
ns
PLH
CC
L
t
C = 50 pF
PHL
L
= 5.0 0.5 V C = 15 pF
3.1
3.6
6.9
7.9
8.0
9.0
9.5
10.5
CC
L
C = 50 pF
L
C
Maximum Input
Capacitance
5.5
10
10
10
pF
pF
IN
Typical @ 25°C, V = 5.0 V
CC
11
C
Power Dissipation Capacitance (Note 2)
PD
2. C is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
PD
Average operating current can be obtained by the equation: I
) = C ꢀ V ꢀ f + I . C is used to determine the no−load dynamic
CC(OPR
PD CC in CC PD
2
power consumption; P = C ꢀ V
ꢀ f + I ꢀ V
.
D
PD
CC
in
CC
CC
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3
NL17SHT00
3.0 V
GND
A or B
50%
t
t
PHL
PLH
V
V
OH
Y
50% V
CC
OL
Figure 4. Switching Waveforms
V
CC
OUTPUT
INPUT
C
L*
*Includes all probe and jig capacitance.
A 1−MHz square input wave is recommended for propagation delay tests.
Figure 5. Test Circuit
ORDERING INFORMATION
†
Device
Package
Shipping
8000 / Tape & Reel
NL17SHT00P5T5G
SOT−953
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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4
NL17SHT00
PACKAGE DIMENSIONS
SOT−953
CASE 527AE
ISSUE E
NOTES:
X
Y
D
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
A
2. CONTROLLING DIMENSION: MILLIMETERS
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD
FINISH. MINIMUM LEAD THICKNESS IS THE
MINIMUM THICKNESS OF THE BASE MATERIAL.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR GATE BURRS.
5
4
3
PIN ONE
H
E
INDICATOR
E
1
2
MILLIMETERS
DIM MIN
NOM
0.37
0.15
0.12
1.00
MAX
0.40
0.20
0.17
1.05
0.85
A
b
0.34
0.10
0.07
0.95
0.75
C
TOP VIEW
e
C
D
SIDE VIEW
E
e
0.80
0.35 BSC
HE
L
L2
L3
0.95
1.00
0.175 REF
0.10
1.05
5X
L
0.05
−−−
0.15
0.15
−−−
5X
5X
L3
L2
SOLDERING FOOTPRINT*
5X
0.35
5X
0.20
5X
b
PACKAGE
OUTLINE
0.08 X
Y
BOTTOM VIEW
1.20
1
0.35
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
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“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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NL17SHT00/D
相关型号:
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