NL17SHT04 [ONSEMI]
Inverting Buffer CMOS Logic Level Shifter;
| 型号： | NL17SHT04 |
| 厂家： | 
ONSEMI |
| 描述： | Inverting Buffer CMOS Logic Level Shifter |
| 文件： | 总5页 (文件大小：103K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NL17SHT04
Inverting Buffer /
CMOS Logic Level Shifter
LSTTL−Compatible Inputs
The NL17SHT04 is a single gate inverting buffer fabricated with
silicon gate CMOS technology. It achieves high speed operation
similar to equivalent Bipolar Schottky TTL while maintaining CMOS
low power dissipation.
http://onsemi.com
MARKING
DIAGRAM
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output.
The device input is compatible with TTL−type input thresholds and
the output has a full 5 V CMOS level output swing. The input protection
circuitry on this device allows overvoltage tolerance on the input,
allowing the device to be used as a logic−level translator from 3 V
CMOS logic to 5 V CMOS Logic or from 1.8 V CMOS logic to 3 V
CMOS Logic while operating at the high−voltage power supply.
The NL17SHT04 input structure provides protection when voltages
up to 7.0 V are applied, regardless of the supply voltage. This allows
the NL17SHT04 to be used to interface 5 V circuits to 3 V circuits.
SOT−953
CASE 527AE
LM
1
L
M
= Specific Device Code
= Month Code
PIN ASSIGNMENT
1
2
3
4
5
IN A
GND
NC
The output structures also provide protection when V = 0 V. These
CC
input and output structures help prevent device destruction caused by
supply voltage − input/output voltage mismatch, battery backup, hot
insertion, etc.
OUT Y
Features
V
CC
• High Speed: t = 3.8 ns (Typ) at V = 5 V
PD
CC
• Low Power Dissipation: I = 1 mA (Max) at T = 25°C
CC
A
FUNCTION TABLE
• TTL−Compatible Inputs: V = 0.8 V; V = 2 V
IL
IH
• CMOS−Compatible Outputs: V > 0.8 V ; V < 0.1 V @ Load
A Input
Y Output
OH
CC OL
CC
• Power Down Protection Provided on Inputs and Outputs
• Balanced Propagation Delays
L
H
L
H
• Pin and Function Compatible with Other Standard Logic Families
• These are Pb−Free Devices
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
1
2
3
5
IN A
GND
NC
V
CC
4
OUT Y
Figure 1. Pinout (Top View)
1
IN A
OUT Y
Figure 2. Logic Symbol
© Semiconductor Components Industries, LLC, 2011
1
Publication Order Number:
August, 2011 − Rev. 0
NL17SHT04/D
NL17SHT04
MAXIMUM RATINGS
Symbol
Characteristics
Value
Unit
V
V
CC
DC Supply Voltage
DC Input Voltage
DC Output Voltage
−0.5 to +7.0
−0.5 to +7.0
−0.5 to 7.0
V
IN
V
V
OUT
V
= 0
CC
V
High or Low State
−0.5 to V + 0.5
CC
I
Input Diode Current
Output Diode Current
DC Output Current
−20
20
mA
mA
mA
mA
mW
°C
IK
I
V
< GND; V
> V
OK
OUT
OUT CC
I
25
OUT
I
DC Supply Current, V and GND
50
CC
CC
P
Power dissipation in still air
50
D
T
Lead temperature, 1 mm from case for 10 s
Junction temperature under bias
Storage temperature
260
L
T
+150
−65 to +150
100
°C
J
T
stg
°C
I
Latchup Performance
Above V and Below GND at 125°C (Note 1)
mA
Latchup
CC
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Tested to EIA/JESD78
RECOMMENDED OPERATING CONDITIONS
Symbol
Characteristics
Min
3.0
0.0
Max
5.5
5.5
5.5
Unit
V
V
CC
DC Supply Voltage
DC Input Voltage
DC Output Voltage
V
IN
V
V
OUT
V
= 0
CC
0.0
0.0
V
High or Low State
V
CC
T
Operating Temperature Range
Input Rise and Fall Time
−55
+125
°C
A
t , t
r
V
CC
V
CC
= 3.3 V 0.3 V
= 5.0 V 0.5 V
0
0
100
20
ns/V
f
DEVICE JUNCTION TEMPERATURE VERSUS
TIME TO 0.1% BOND FAILURES
FAILURE RATE OF PLASTIC = CERAMIC
UNTIL INTERMETALLICS OCCUR
Junction
Temperature °C
Time, Hours
1,032,200
419,300
178,700
79,600
Time, Years
117.8
47.9
80
90
100
110
120
130
140
20.4
1
9.4
37,000
4.2
1
10
100
1000
17,800
2.0
TIME, YEARS
8,900
1.0
Figure 3. Failure Rate vs. Time Junction Temperature
http://onsemi.com
2
NL17SHT04
DC ELECTRICAL CHARACTERISTICS
T
A
= 25°C
T
A
≤ 85°C
−55 ≤ T ≤ 125°C
A
V
CC
Min
Typ
Max
Min
Max
Min
Max
(V)
Symbol
Parameter
Test Conditions
Unit
V
IH
Minimum High−Level
Input Voltage
3.0
4.5
5.5
1.4
2.0
2.0
1.4
2.0
2.0
1.4
2.0
2.0
V
V
IL
Maximum Low−Level
Input Voltage
3.0
4.5
5.5
0.53
0.8
0.8
0.53
0.8
0.8
0.53
0.8
0.8
V
V
OH
= V or V
3.0
4.5
2.9
4.4
3.0
4.5
2.9
4.4
2.9
4.4
V
V
V
OH
Minimum High−Level
IN
IH
IL
Output Voltage
I
= −50 mA
V
IN
= V or V
IH IL
V
= V or V
IN
OH
OH
IH
IL
I
I
= −4 mA
= −8 mA
3.0
4.5
2.58
3.94
2.48
3.80
2.34
3.66
V
OL
= V or V
3.0
4.5
0.0
0.0
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
OL
Maximum Low−Level
IN
IH
IL
Output Voltage
I
= 50 mA
V
IN
= V or V
IH IL
V
= V or V
IN
OL
OL
IH
IL
I
I
= 4.0 mA
= 8.0 mA
3.0
4.5
0.36
0.36
0.44
0.44
0.52
0.52
I
Maximum Input
Leakage Current
V
= 5.5 V or GND
0 to
5.5
0.1
1.0
1.0
mA
mA
mA
mA
IN
IN
I
Maximum Quiescent
Supply Current
V
IN
= V or GND
5.5
5.5
0.0
1.0
20
40
CC
CC
I
Quiescent Supply
Current
Input: V = 3.4 V
1.35
0.5
1.50
5.0
1.65
10
CCT
IN
I
Output Leakage
Current
V
OUT
= 5.5 V
OPD
AC ELECTRICAL CHARACTERISTICS C
= 50 pF, Input t = t = 3.0 ns
r f
load
T
A
= 25°C
T
A
≤ 85°C
−55 ≤ T ≤ 125°C
A
Min
Typ
Max
Min
Max
Min
Max
Symbol
Parameter
Test Conditions
Unit
V
V
= 3.3 0.3 V C = 15 pF
5.0
6.2
10.0
13.5
11.0
15.0
13.0
17.5
t
,
Maximum Propagation
Delay, Input A to Y
ns
CC
L
PLH
C = 50 pF
t
L
PHL
= 5.0 0.5 V C = 15 pF
3.8
4.2
6.7
7.7
7.5
8.5
8.5
9.5
CC
L
C = 50 pF
L
C
Maximum Input
Capacitance
5.0
10
10
10
pF
pF
IN
Typical @ 25°C, V = 5.0 V
CC
10
C
Power Dissipation Capacitance (Note 2)
PD
2. C is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
PD
Average operating current can be obtained by the equation: I
) = C ꢀ V ꢀ f + I . C is used to determine the no−load dynamic
CC(OPR
PD CC in CC PD
2
power consumption; P = C ꢀ V
ꢀ f + I ꢀ V
.
D
PD
CC
in
CC
CC
http://onsemi.com
3
NL17SHT04
3.0 V
GND
A
Y
50%
t
t
PHL
PLH
V
V
OH
50% V
CC
OL
Figure 4. Switching Waveforms
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
C *
L
*Includes all probe and jig capacitance
Figure 5. Test Circuit
ORDERING INFORMATION
†
Device
Package Type
Package
4000 / Tape & Reel
NL17SHT04P5T5G
SOT−953
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
http://onsemi.com
4
NL17SHT04
PACKAGE DIMENSIONS
SOT−953
CASE 527AE
ISSUE E
NOTES:
X
Y
D
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
A
2. CONTROLLING DIMENSION: MILLIMETERS
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD
FINISH. MINIMUM LEAD THICKNESS IS THE
MINIMUM THICKNESS OF THE BASE MATERIAL.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR GATE BURRS.
5
4
3
PIN ONE
H
E
INDICATOR
E
1
2
MILLIMETERS
DIM MIN
NOM
0.37
0.15
0.12
1.00
MAX
0.40
0.20
0.17
1.05
0.85
A
b
0.34
0.10
0.07
0.95
0.75
C
TOP VIEW
e
C
D
SIDE VIEW
E
e
0.80
0.35 BSC
HE
L
0.95
1.00
0.175 REF
1.05
5X
L
L2
L3
0.05
−−−
0.10
−−−
0.15
0.15
5X
5X
L3
L2
SOLDERING FOOTPRINT*
5X
0.35
5X
0.20
5X
b
PACKAGE
OUTLINE
0.08 X
Y
BOTTOM VIEW
1.20
1
0.35
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5773−3850
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
For additional information, please contact your local
Sales Representative
NL17SHT04/D
相关型号：
©2020 ICPDF网 联系我们和版权申明