NL17SH17P5T5G [ONSEMI]
Single Schmitt-Trigger Inverter;
| 型号： | NL17SH17P5T5G |
| 厂家： | 
ONSEMI |
| 描述： | Single Schmitt-Trigger Inverter 栅 光电二极管 逻辑集成电路 触发器 |
| 文件： | 总5页 (文件大小：102K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NL17SH17
Single Schmitt-Trigger
Buffer
The NL17SH17 is a single gate CMOS Schmitt−trigger
non−inverting buffer fabricated with silicon gate CMOS technology.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output. The
NL17SH17 input structure provides protection when voltages up to 7
V are applied, regardless of the supply voltage. This allows the
NL17SH17 to be used to interface 5 V circuits to 3 V circuits.
The NL17SH17 can be used to enhance noise immunity or to square
up slowly changing waveforms.
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MARKING
DIAGRAM
M
SOT−953
CASE 527AE
1
Features
• High Speed: t = 4.0 ns (Typ) at V = 5.0 V
Y
= Specific Device Code
(Rotated 90°)
= Month Code
PD
CC
• Low Power Dissipation: I = 1.0 mA (Max) at T = 25°C
CC
A
M
• Power Down Protection Provided on Inputs
• Balanced Propagation Delays
• Pin and Function Compatible with Other Standard Logic Families
• Chip Complexity: FETs = 101
PIN ASSIGNMENT
1
2
3
4
5
IN A
GND
NC
• These Devices are Pb−Free and are RoHS Compliant
OUT Y
V
CC
V
IN A
GND
NC
1
2
3
5
4
CC
FUNCTION TABLE
Input A
Output Y
OUT Y
L
L
H
H
Figure 1. Pinout
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
IN A
1
OUT Y
Figure 2. Logic Symbol
© Semiconductor Components Industries, LLC, 2012
1
Publication Order Number:
September, 2012 − Rev. 0
NL17SH17/D
NL17SH17
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
V
CC
DC Supply Voltage
−0.5 to +7.0
−0.5 to +7.0
V
IN
DC Input Voltage
V
V
OUT
DC Output Voltage
−0.5 to V + 0.5
V
CC
I
DC Input Diode Current
V
< GND
IN
−20
mA
mA
mA
mA
mA
°C
IK
I
DC Output Diode Current
DC Output Source/Sink Current
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature Range
Lead Temperature, 1 mm from Case for 10 Seconds
Junction Temperature Under Bias
Moisture Sensitivity
V
< GND, V
> V
CC
20
OK
OUT
OUT
I
12.5
OUT
I
25
CC
I
25
−65 to +150
260
GND
T
STG
T
°C
L
T
+150
°C
J
MSL
Level 1
F
R
Flammability Rating
Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
V
ESD
ESD Withstand Voltage
Human Body Model (Note 2)
Machine Model (Note 3)
Charged Device Model (Note 4)
>3000
>200
N/A
V
I
Latchup Performance
Above V and Below GND at 125°C (Note 5)
100
mA
LATCHUP
CC
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Measured with minimum pad spacing on an FR4 board, using 10 mm−by−1 inch, 2−ounce copper trace with no air flow.
2. Tested to EIA/JESD22−A114−A.
3. Tested to EIA/JESD22−A115−A.
4. Tested to JESD22−C101−A.
5. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol
Characteristics
Min
1.65
0.0
Max
5.5
Unit
V
V
CC
Positive DC Supply Voltage
Digital Input Voltage
V
IN
5.5
V
V
OUT
Output Voltage
0.0
V
CC
V
T
Operating Temperature Range
Input Transition Rise or Fail Rate
−55
+125
°C
ns/V
A
Dt / DV
V
CC
V
CC
= 3.3 V 0.3 V
= 5.0 V 0.5 V
0
0
No Limit
No Limit
DEVICE JUNCTION TEMPERATURE VERSUS
TIME TO 0.1% BOND FAILURES
FAILURE RATE OF PLASTIC = CERAMIC
UNTIL INTERMETALLICS OCCUR
Junction
Temperature °C
Time, Hours
1,032,200
419,300
178,700
79,600
Time, Years
117.8
47.9
80
90
100
110
120
130
140
20.4
1
9.4
37,000
4.2
1
10
100
1000
17,800
2.0
TIME, YEARS
8,900
1.0
Figure 3. Failure Rate vs. Time Junction Temperature
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2
NL17SH17
DC ELECTRICAL CHARACTERISTICS
T
A
= 255C
Typ
T
v 855C
*555C to 1255C
A
V
CC
Min
Max
Min
Max
Min
Max
(V)
Symbol
Parameter
Test Conditions
Unit
V
T+
Positive Threshold
Voltage
3.0
4.5
5.5
2.0
3.0
3.6
2.2
3.15
3.85
2.2
3.15
3.85
2.2
3.15
3.85
V
V
Negative Threshold
Voltage
3.0
4.5
5.5
0.9
1.35
1.65
1.5
2.3
2.9
0.9
1.35
1.65
0.9
1.35
1.65
V
V
V
T−
V
Hysteresis Voltage
3.0
4.5
5.5
0.3
0.4
0.5
0.57
0.67
0.74
1.2
1.4
1.6
0.3
0.4
0.5
1.2
1.4
1.6
0.3
0.4
0.5
1.2
1.4
1.6
H
V
OH
High−Level
Output Voltage
V
IN
V
IN
V
IN
V
IN
≥ V
≥ V
≤ V
≤ V
2.0
3.0
4.5
1.9
2.9
4.4
2.0
3.0
4.5
1.9
2.9
4.4
1.9
2.9
4.4
Tmin
OH
I
= −50 mA
Tmin
I
= −4 mA
= −8 mA
3.0
4.5
2.58
3.94
2.48
3.80
2.34
3.66
OH
I
OH
V
OL
Low−Level
Output Voltage
2.0
3.0
4.5
0.0
0.0
0.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
Tmax
I
= 50 mA
OL
Tmax
I
I
= 4 mA
= 8 mA
3.0
4.5
0.36
0.36
0.44
0.44
0.52
0.52
OL
OL
I
Input Leakage Current
V
V
= 5.5 V or GND
0 to
5.5
$0.1
$1.0
$1.0
mA
mA
IN
IN
I
Quiescent Supply
Current
= V or GND
5.5
1.0
20
40
CC
IN
CC
AC ELECTRICAL CHARACTERISTICS (Input t = t = 3.0 ns)
r
f
T
A
= 255C
Typ
T
v 855C
*555C to 1255C
A
V
(V)
Test
Conditions
CC
Min
Max
Min
Max
Min
Max
Symbol
Parameter
Unit
t
,
Propagation Delay,
A to Y
3.0 to 3.6
C = 15 pF
L
7.0
8.5
12.8
16.3
1.0
1.0
15.0
18.5
1.0
1.0
17.0
20.5
ns
PLH
L
t
C = 50 pF
PHL
4.5 to 5.5
C = 15 pF
L
4.0
5.5
8.6
10.6
1.0
1.0
10.0
12.0
1.0
1.0
11.5
13.5
L
C = 50 pF
C
Input Capacitance
5.0
10
10
10
pF
pF
IN
Typical @ 25°C, V = 5.0 V
CC
7.0
C
Power Dissipation Capacitance (Note 6)
PD
6. C is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
PD
Average operating current can be obtained by the equation: I
) = C ꢀ V ꢀ f + I . C is used to determine the no−load dynamic
CC(OPR
PD CC in CC PD
2
power consumption; P = C ꢀ V
ꢀ f + I ꢀ V
.
D
PD
CC
in
CC
CC
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3
NL17SH17
TEST POINT
OUTPUT
V
CC
A or B
50%
GND
DEVICE
UNDER
TEST
t
t
PLH
PHL
C *
L
Y
50% V
CC
*Includes all probe and jig capacitance.
Figure 4. Switching Waveform
Figure 5. Test Circuit
ORDERING INFORMATION
Device
†
Package
Shipping
NL17SH17P5T5G
SOT−953
(Pb−Free)
8000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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4
NL17SH17
PACKAGE DIMENSIONS
SOT−953
CASE 527AE
ISSUE E
NOTES:
X
Y
D
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
A
2. CONTROLLING DIMENSION: MILLIMETERS
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD
FINISH. MINIMUM LEAD THICKNESS IS THE
MINIMUM THICKNESS OF THE BASE MATERIAL.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR GATE BURRS.
5
4
3
PIN ONE
H
E
INDICATOR
E
1
2
MILLIMETERS
DIM MIN
NOM
0.37
0.15
0.12
1.00
MAX
0.40
0.20
0.17
1.05
0.85
A
b
0.34
0.10
0.07
0.95
0.75
C
TOP VIEW
e
C
D
SIDE VIEW
E
e
0.80
0.35 BSC
HE
L
0.95
1.00
0.175 REF
1.05
5X
L
L2
L3
0.05
−−−
0.10
−−−
0.15
0.15
5X
5X
L3
L2
SOLDERING FOOTPRINT*
5X
0.35
5X
0.20
5X
b
PACKAGE
OUTLINE
0.08 X
Y
BOTTOM VIEW
1.20
1
0.35
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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NL17SH17/D
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