ML7033GA [OKI]
Dual-Channel Line Card CODEC; 双通道线路卡CODEC
| 型号： | ML7033GA |
| 厂家： | 
OKI ELECTRONIC COMPONETS |
| 描述： | Dual-Channel Line Card CODEC |
| 文件： | 总51页 (文件大小：442K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FEDL7033-02
This version:
Dec. 2001
1
Previous version: Jul. 2001
Semiconductor
ML7033
Dual-Channel Line Card CODEC
GENERAL DESCRIPTION
The ML7033 is a 2-channel PCM CODEC CMOS IC designed for Central Office (CO) and Customer Premise
Equipment (CPE) environments. The ML7033 device contains 2-channel analog-to-digital (A/D) and digital-to-
analog (D/A) converters with multiplexed PCM input and output. The ML7033 is designed for single-rail, low
power applications. The high integration of the ML7033 reduces the number of external components and overall
board size. The ML7033 is best suited for line card applications and provides an easy interface to subscriber line
interface circuits (SLIC’s), in particular the Intersil RSLICTM series.
FEATURES
•
•
•
•
•
•
Seamlessly interfaces with Intersil RSLICTM series devices
Single 5 volt power supply (4.75 V to 5.25 V)
∆-Σ ADC and DAC
PCM format: µ-law/A-law (ITU-T G.711 compliant), 14-bit linear (2’s complement)
Optional wideband filter for V.90 data modem applications
Low power consumption
- 2-channel operating mode: 115 mW (typical) 180 mW (max)
- 1-channel operating mode: 80 mW (typical)
115 mW (max)
- Power-down mode:
Power-on reset
0.1 mW (typical)
0.25 mW (max); PDN pin = logic “0”
•
•
Dual programmable tone generators (300 Hz to 3400 Hz; 10 Hz intervals; 0.1 dB intervals)
- Call progress tone, DTMF tone
•
•
•
•
•
•
•
•
•
•
•
•
Ringing tone generator (15 Hz to 50 Hz; 1Hz intervals; 0.1 dB intervals)
Pulse metering tone generator (12 kHz, 16 kHz; gain level selectable)
Call ID tone generator (ITU-T V.23, Bell 202)
Analog and digital loop back test modes
Time-slot assignment
Serial MCU interface
Master clock: 2.048 MHz/4.096 MHz selectable
Serial PCM transmission data rate: 256 kbps to 4096 kbps
Adjustable transmit/receive gain (1 dB intervals)
Built-in reference voltage generator
Differential or single-ended analog output selectable
Package: 64-pin plastic QFP (QFP64-P-1414-0.80-BK) (Ordering Part number: ML7033GA)
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Semiconductor
BLOCK DIAGRAM
PDN
RESET
MCK
TEST
CIDATA1
CIDATA2
DIO
DEN
EXCK
INT
F2_1
F1_1
F0_1
E0_1
SWC1
BSEL1
DET1
ALM1
F2_2
F1_2
F0_2
E0_2
SWC2
BSEL2
DET2
ALM2
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Semiconductor
PIN CONFIGURATION (TOP VIEW)
1
2
3
4
5
6
7
8
N.C
AIN1N
GSX1
AOUT1P
AOUT1N
TOUT1
AG
N.C
48
47 RESET
RSYNC
XSYNC
PCMOUT
46
45
44
43
42
41
PCMOSY
PCMIN
DG
SG
SGC
AG
9
40 BCLK
39 MCK
38 VDDD
37 DIO
10
11
12
13
14
15
16
TOUT2
AOUT2N
AOUT2P
GSX2
AIN2N
N.C
36
35
34
33
DEN
EXCK
INT
N.C
64-Pin Plastic QFP
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PIN DESCRIPTIONS
Pin
1
2
3
4
5
6
7
8
Symbol
N.C
Type
—
I
Description
(Leave unconnected)
AIN1N
GSX1
AOUT1P
AOUT1N
TOUT1
AG
SG
SGC
AG
TOUT2
AOUT2N
AOUT2P
GSX2
AIN2N
N.C
N.C
AIN2P
VDDA
CH1 Transmit Op-amp Input Negative
CH1 Transmit Op-amp Output
CH1 Receive Output Positive
CH1 Receive Output Negative
CH1 Tone Output
O
O
O
O
—
O
O
—
O
O
O
O
I
—
—
I
—
—
O
I
Analog Ground
Signal Ground for External Circuit
Signal Ground for Internal Circuit
Analog Ground
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
CH2 Tone Output
CH2 Receive Output Negative
CH2 Receive Output Positive
CH2 Transmit Op-amp Output
CH2 Transmit Op-amp Input Negative
(Leave unconnected)
(Leave unconnected)
CH2 Transmit Op-amp Input Positive
Power Supply for Internal Analog Circuit
Power Supply for Internal Digital Circuit
Output for SLIC2 Battery Select
Input from SLIC2 Thermal Shut Down Alarm Detector
Input from SLIC2 Switch Hook, Ground Key or Ring Trip Detector
Output for SLIC2 Detector Mode Selection
Mode Control Output to SLIC2 F0
Mode Control Output to SLIC2 F1
Mode Control Output to SLIC2 F2
Output for SLIC2 Uncommitted Switch Control
Digital Ground
VDDD
BSEL2
ALM2
DET2
E0_2
F0_2
I
O
O
O
O
O
—
I
F1_2
F2_2
SWC2
DG
CIDATA1
CIDATA2
N.C
N.C
INT
EXCK
DEN
Call ID Data Input for CH1
Call ID Data Input for CH2
(Leave unconnected)
(Leave unconnected)
I
—
—
O
I
Interrupt Output (from SLIC status)
MCU Interface Data Clock Input
MCU Interface Data Enable Input
MCU Interface Control Data Input/Output
I
DIO
I/O
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Pin
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
Symbol
VDDD
MCK
BCLK
DG
PCMIN
PCMOSY
PCMOUT
XSYNC
RSYNC
RESET
N.C
N.C
PDN
TEST
DG
BSEL1
ALM1
DET1
E0_1
F0_1
F1_1
F2_1
SWC1
VDDD
Type
—
I
I
—
I
O
O
I
I
I
Description
Power Supply for Internal Digital Circuit
Master Clock (2.048/4.096 MHz)
PCM Data Shift Clock
Digital Ground
PCM Data Input
PCM Data Output Indicator for Time-Slot Assignment
PCM Data Output
Transmit Synchronizing Clock Input
Receive Synchronizing Clock Input
Reset for Control Register
(Leave unconnected)
(Leave unconnected)
Power-down Control
LSI Manufacturer’s Test Input (keep logic “0”)
Digital Ground
Output for SLIC1 Battery Select
Input from SLIC1 Thermal Shut Down Alarm Detector
Input from SLIC1 Switch Hook, Ground Key or Ring Trip Detector
Output for SLIC1 Detector Mode Selection
Mode Control Output to SLIC1 F0
—
—
I
I
—
O
I
I
O
O
O
O
O
—
—
I
Mode Control Output to SLIC1 F1
Mode Control Output to SLIC1 F2
Output for SLIC1 Uncommitted Switch Control
Power Supply for Internal Digital Circuit
Power Supply for Internal Analog Circuit
CH1 Transmit Op-amp Input Positive
(Leave unconnected)
VDDA
AIN1P
N.C
—
Note: In this datasheet, “1” and “2” in names for pins which respectively exist for CH1 and CH2 are often
substituted by “n” (in a small letter).
Ex) GSX1, GSX2
AOUT1N, AOUT2N
DET1, DET2
→ GSXn
→ AOUTnN
→ DETn
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Semiconductor
Control Register Assignment
Address
Register
Data
R/W
B0
A4 A3 A2 A1 A0
B7
B6
B5
B4
B3
B2
B1
Filter2
SEL
CH2TG CH1TG
ON
Filter1
SEL
MCK
SEL
CR0
CR1
0
0
0
0
0
0
0
0
0
1
R/W
R/W
SHORT
LIN
ALAW MODE1 MODE0
CID
CID
CID
ON
FMT
CH2ON CH1ON
PMG2
FRQ
TSAE
DET2
TIM3
PMG2
LV1
TSAC
DET2
TIM2
PMG2
LV0
TSA5
DET2
TIM1
PMG2
PMG1
FRQ
TSA3
DET1
TIM3
PMG1
LV1
TSA2
DET1
TIM2
PMG1
LV0
TSA1
DET1
TIM1
PMG1
R/W
W
CR2
CR3
CR4
0
0
0
0
0
0
0
0
1
1
1
0
0
1
0
TOUT2
TOUT1
TSA4
DET2
TIM0
TSA0
DET1
TIM0
R/W
CR5
CR6
0
0
0
0
1
1
0
1
1
0
LV1R3 LV1R2 LV1R1 LV1R0 LV1X3 LV1X2 LV1X1 LV1X0 R/W
F2_1
F1_1
F0_1
SWC1 BSEL1
E0_1
DET1* ALM1*
R/W
AOUT1 CH1TG2
CH1TG2 CH1TG2 CH1TG2 CH1TG2 CH1TG2
CH1TG2
TOUT1
CR7
CR8
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
1
0
0
1
1
1
0
1
0
1
R/W
SEL
TX
LV3
LV2
LV1
LV0
_8
CH1TG2 CH1TG2 CH1TG2 CH1TG2 CH1TG2 CH1TG2 CH1TG2 CH1TG2
R/W
R/W
R/W
R/W
_7
CH1TG1 CH1TG1 CH1TG1 CH1TG1 CH1TG1 CH1TG1 CH1TG1 CH1TG1
LV6 LV5 LV4 LV3 LV2 LV1 LV0 _8
CH1TG1 CH1TG1 CH1TG1 CH1TG1 CH1TG1 CH1TG1 CH1TG1 CH1TG1
_7 _6 _5 _4 _3 _2 _1 _0
CH2 CH2TG1 CH2TG1 CH2TG1 CH1 CH1TG1 CH1TG1 CH1TG1
RING TRP2 TRP1 TRP0 RI NG TRP2 TRP1 TRP0
_6
_5
_4
_3
_2
_1
_0
CR9
CR10
CR11
CR12
CR13
0
0
1
1
1
1
0
0
0
1
LV2R3 LV2R2 LV2R1 LV2R0 LV2X3 LV2X2 LV2X1 LV2X0 R/W
F2_2
AOUT2 CH2TG CH2TG CH2TG2 CH2TG2 CH2TG2 CH2TG2 CH2TG2
SEL TX TOUT2 LV3 LV2 LV1 LV0 _8
CH2TG2 CH2TG2 CH2TG2 CH2TG2 CH2TG2 CH2TG2 CH2TG2 CH2TG2
F1_2
F0_2
SWC2 BSEL2
E0_2
DET2* ALM2*
R/W
CR14
CR15
CR16
CR17
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
0
1
0
1
R/W
R/W
R/W
R/W
_7
CH2TG1 CH2TG1 CH2TG1 CH2TG1 CH2TG1 CH2TG1 CH2TG1 CH2TG1
LV6 LV5 LV4 LV3 LV2 LV1 LV0 _8
_6
_5
_4
_3
_2
_1
_0
CH2TG1 CH2TG1 CH2TG1 CH2TG1 CH2TG1 CH2TG1 CH2TG1 CH2TG1
_7
_6
_5
_4
_3
_2
_1
_0
CH2
CH2
CH1
CH1
CR18
CR19
1
1
0
0
0
0
1
1
0
1
TEST3 TEST2 TEST1 TEST0 R/W
LOOP1 LOOP0 LOOP1 LOOP0
TEST11 TEST10 TEST9 TEST8 TEST7 TEST6 TEST5 TEST4 R/W
*: Read only bit
Note: In this datasheet, numbers in names for control register bits are often substituted by “n” (in a small letter). In
the case, the “n” does not always refer to a channel number.
Ex) MODE0, MODE1
→ MODEn
CH1TG2_7, CH1TG2_6 → CH1TG2_n
PMG2FRQ, PMG1FRQ → PMGnFRQ
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ABSOLUTE MAXIMUM RATINGS
Parameter
Power Supply Voltage
Analog Input Voltage
Digital Input Voltage
Storage Temperature
Symbol
VDD
VAIN
VDIN
TSTG
Condition
VDDD, VDDA
Rating
–0.3 to +7.0
–0.3 to VDD+0.3
–0.3 to VDD+0.3
–55 to +150
Unit
V
V
V
°C
—
—
—
RECOMMENDED OPERATING CONDITIONS
Parameter
Power Supply Voltage
Operating Temperature
High Level Input Voltage
Low Level Input Voltage
Symbol
VDD
TOP
VIH
VIL
Condition
Voltage to be fixed; VDDD, VDDA
—
Min.
Typ.
5.0
—
—
—
Max.
Unit
V
°C
V
4.75
–40
2.2
0
5.25
+85
VDD
0.8
All digital input pins
V
MCK = 2.048 MHz
–0.01% 2048 +0.01% kHz
–0.01% 4096 +0.01% kHz
MCKSEL (CR0-B5) bit = “0”
MCK Frequency
FMCK
MCK = 4.096 MHz
MCKSEL (CR0-B5) bit = “1”
BCLK Frequency
Sync Pulse Frequency
Clock Duty Ratio
Digital Input Rise Time
Digital Input Fall Time
MCK to BCLK Phase Difference
FBCLK
FSYNC
DCLK
tIR
tIF
tMB
tXS
tSX
tRS
tSR
BCLK
XSYNC, RSYNC
MCK,BCLK
256
–0.01%
40
—
8
4096
+0.01% kHz
kHz
50
—
—
—
—
—
—
—
60
50
50
50
—
—
—
—
%
ns
ns
ns
ns
ns
ns
ns
—
—
—
50
50
50
50
All digital input pins
MCK, BCLK
BCLK to XSYNC
XSYNC to BCLK
BCLK to RSYNC
RSYNC to BCLK
Transmit Sync Pulse Setting Time
Receive Sync Pulse Setting Time
XSYNC, RSYNC
125 µs –
1 BCLK
210
—
—
µs
SHORT (CR0-B4) bit = “0”
1BCLK
Sync Pulse Width
tWS
XSYNC, RSYNC
SHORT (CR0-B4) bit = “0”
1BCLK
ns
PCMOUT Set-up Time
PCMOUT Hold Time
tDS
tDH
RDL
CDL1
CDL2
CSG
PCMOUT
PCMOUT
Pull-up Resistor, PCMOUT
PCMOUT
50
50
0.5
—
—
0.1
—
—
—
—
—
—
—
—
—
50
50
—
ns
ns
kΩ
pF
pF
µF
Digital Output Load
Other output pins
SGC to AG
Bypass Capacitor for SGC
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ELECTRICAL CHARACTERISTICS
DC and Digital Interface Characteristics
(VDD = 4.75 to 5.25 V, Ta = –40 to +85°C)
Parameter
Symbol
IDD1
IDD2
Condition
2CH Operating Mode, No Signal
1CH Operating Mode, No Signal
Min.
—
—
Typ.
23.0
16.0
Max.
35.0
22.0
Unit
mA
mA
Power Supply Current
Power-down Mode
PDN pin = logic “0”
All Digital Input Pins
VI = VDD
All Digital Input Pins
VI = 0 V
IDD4
IIH
—
—
25.0
0.1
50.0
5.0
—
µA
µA
µA
High Level Input Leakage Current
Low Level Input Leakage Current
Digital Output Low Voltage
IIL
–5.0
–0.1
VOL1
VOL2
VOH
IO
PCMOUT, Pull-up = 0.5 kΩ
Other output pins, IOL = –0.4 mA
IOH = 0.4 mA
PCMOUT High Impedance State
—
0
0
2.5
—
—
0.2
0.2
—
—
5
0.4
0.4
—
10
—
V
V
V
µA
pF
Digital Output High Voltage
Digital Output Leakage Current
Input Capacitance
CIN
Analog Interface Characteristics
(VDD = 4.75 to 5.25 V, Ta = –40 to +85°C)
Parameter
SG, SGC Output Voltage
Symbol
VSG
Condition
SGC to AG 0.1 µF
SGC to AG 0.1 µF
Rise time to 90% of max. level
SG
Min.
—
Typ.
2.4
Max.
—
Unit
V
SG, SGC Rise Time
tSGC
—
—
—
10
—
ms
SG Output Load Resistance
RLSG
10
kΩ
Transmit Analog Interface Characteristics
(VDD = 4.75 to 5.25 V, Ta = –40 to +85°C)
Parameter
Input Resistance
Output Load Resistance
Output Load Capacitance
Output Amplitude
Symbol
RINX
RLGX
CLGX
VOGX
Condition
AINnN, AINnP
GSXn
Min.
—
20
—
—
Typ.
10
—
—
—
Max.
—
—
Unit
MΩ
kΩ
(to SGC)
*1
30
pF
2.226 Vpp
Offset Voltage
VOSGX
Gain = 1
–50
—
50
mV
*1 –3.0 dBm (600Ω) = 0 dBm0
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Semiconductor
Receive Analog Interface Characteristics
(VDD = 4.75 to 5.25 V, Ta = –40 to +85°C)
Parameter
Symbol
RLAO
Condition
AOUTnN, AOUTnP
(to SGC)
Min.
Typ. Max. Unit
20
—
—
kΩ
Output Load Resistance
TOUTn
(to SGC)
AOUTnN, AOUTnP, TOUTn
AOUTnN, AOUTnP, TOUTn
RLAO = 20 kΩ (to SGC)
RLTO
CLAO
VOAO
10
—
—
—
—
—
—
kΩ
Output Load Capacitance
Output Amplitude
50
pF
3.4* Vpp
AOUTnN, AOUTnP, TOUTn
Offset Voltage
VOSAO
–100
—
100
mV
R
LAO = 20 kΩ (to SGC)
*
0.658 dBm (600Ω) = 0 dBm0
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Semiconductor
AC Characteristics
(VDD = 4.75 to 5.25 V, Ta = –40 to +85°C)
Condition
Level
(dBm0)
Parameter
Symbol
Min.
Typ.
Max. Unit
Freq.
(Hz)
Loss T1
Loss T2
Loss T3
Loss T4
Loss T5
Loss T6
Loss R1
Loss R2
Loss R3
Loss R4
Loss R5
SDT1
SDT2
SDT3
SDT4
SDT5
SDR1
SDR2
SDR3
SDR4
60
300
25
–0.15
45
0.15
Reference
0.02
0.1
—
0.20
GSXn to
1020
3000
3300
3400
100
1020
3000
3300
3400
Transmit
Frequency Response
PCMOUT
0
0
dB
–0.15
–0.15
0
0.20
(Attenuation)
0.80
0.80
0.2
0.6
–0.15
0.04
Reference
0.07
0.2
PCMIN to
AOUTn
(Attenuation)
Receive
Frequency Response
–0.15
–0.15
0
36
36
36
30
25
36
36
36
30
25
0.2
0.8
0.8
—
—
—
—
—
—
—
dB
dB
dB
dB
dB
0.6
43
40
38
32
29
42
39
3
0
–30
–40
–45
3
Transmit
Signal to Distortion
Ratio
GSXn to
PCMOUT
1020
1020
1020
1020
*1
0
Receive
Signal to Distortion
Ratio
PCMIN to
AOUTn
–30
–40
–45
3
–10
–40
–50
–55
3
–10
–40
–50
–55
39
33
30
—
—
—
0.2
*1
SDR5
GTT1
GTT2
GTT3
GTT4
GTT5
GTR1
GTR2
–0.2
0.02
Reference
0.06
0.4
0.4
0
Reference
–0.02
–0.1
–0.2
Transmit
Gain Tracking
GSXn to
PCMOUT
–0.2
–0.6
–1.2
–0.2
0.2
0.6
1.2
0.2
Receive
Gain Tracking
PCMIN to
AOUTn
GTR3
GTR4
GTR5
–0.2
–0.6
–1.2
0.2
0.6
1.2
*1 C-message filter used
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Semiconductor
AC Characteristics (Continued)
(VDD = 4.75 to 5.25 V, Ta = –40 to +85°C)
Condition
Parameter
Symbol
NIDLET
Min.
—
Typ.
9
Max. Unit
Freq.
(Hz)
Level
(dBm0)
—
Analog input = SGC*1
—
15
AINn to PCMOUT
Gain = 1 (µ-law)
Idle Channel Noise
dBm0
10
PCMIN = ‘FF’h (µ-law)
PCMIN = ‘D5’h (A-law)
PCMIN = all ‘0’ (linear)*1
NIDLER
—
—
0
—
4
PCMIN to AOUTn
GSXn to PCMOUT
0.511 0.548 0.587
0.806 0.835 0.864
VDD = 5 V, Ta = 25°C
Absolute Level
(Initial Difference)
AVT/AVR
Vrms
PCMIN to AOUTn
(Single-ended)
1020
1020
VDD = 5 V, Ta = 25°C
Absolute Level
AVTT
AVRT
–0.3
–0.3
—
—
0.3
0.3
VDD = 4.75 to 5.25 V
Ta = –40 to 85°C
(Deviation of
dB
ms
Temperature and Power)
A to A Mode
Absolute Delay
TD
0
0
—
0.58
0.6
BCLK = 2048 kHz
TGD T1
TGD T2
TGD T3
TGD T4
TGD T5
TGD R1
TGD R2
TGD R3
TGD R4
TGD R5
CRT
500
600
1000
2600
2800
500
—
—
—
—
—
—
—
—
—
—
75
75
75
0.26
0.16
0.02
0.05
0.07
0.00
0.00
0.00
0.09
0.12
83
0.75
0.35
0.125
0.125
0.75
0.75
0.35
0.125
0.125
0.75
—
Transmit Group Delay
*2
ms
600
Receive Group Delay
1000
2600
2800
0
0
*2
ms
dB
Trans to Receive
Receive to Trans
Channel to Channel
Cross Talk
Attenuation
CRR
CRCH
1020
80
78
—
—
4.6 to
72k
Discrimination
DIS
0
0
0
0 to 4 kHz
4.6 to 1000 kHz
0 to 4 kHz
30
32
—
dB
dB
300 to
Out of Band Spurious
OBS
—
–37.5
–35
3.4K
SFDT
SFDR
IMDT
IMDR
—
—
—
—
40
50
40
50
–50
–48
–50
–54
44
55
45
56
–40
–40
–40
–40
—
—
—
—
Signal Frequency
Distortion
1020
dBm0
fa = 470
fb = 320
PSRT1 0 to 4k
PSRT2 4 to 50k
PSRR1 0 to 4k
PSRR2 4 to 50k
Intermodulation Distortion
–4
2 fa – fb
*3
dBm0
dB
Power Supply Noise
Rejection Ratio
100
mVrms
*1 C-message filter used
*2 Minimum value of the group delay distortion
*3 Under idle channel noise
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AC Characteristics (Continued)
(VDD = 4.75 to 5.25 V, Ta = –40 to +85°C)
Parameter
Symbol
tSD
tXD1
tXD2
tXD3
tXD4
Condition
PCMOUT
Pull-up resister = 0.5 kΩ
CL = 50 pF and 1 LSTTL
Min.
—
—
—
—
Typ.
—
—
—
—
Max.
100
100
100
100
100
Unit
ns
Digital Output Delay Time
PCMOSY, CL = 50 pF
ns
ms
ms
—
—
PCMOUT Operation Delay
Time
AOUTn/TOUTn Signal Output
Delay Time
Time to operation
after Power-down release
Time to baseband signal output
after power-on
tDDO
—
4
—
tDAO
—
4
—
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
fEXCK
t20
t21
t22
t23
t24
50
50
50
50
100
50
50
—
50
50
—
0.5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
20
—
—
—
—
—
—
—
—
—
—
50
—
—
50
10
200
—
200
200
225
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
ns
µs
ns
ns
ms
Serial Port I/O Setting Time
CLOAD = 50 pF
EXCK Clock Frequency
EXCK
—
—
—
—
SLIC Interface Delay Time
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TIMING DIAGRAM
Transmit Timing - 8-bit PCM Mode with LIN (CR0-B3) bit = “0”
Long Frame Sync Mode with SHORT (CR0-B4) bit = “0”
MCK
tMB
3
BCLK
1
2
4
5
6
7
8
tXS
tSX
XSYNC
PCMOUT
PCMOSY
tWS
tXD2
D4
tXD1
tXD3
tSD
MSD
D2
D3
D5
D6
D7
D8
tXD4
Short Frame Sync Mode with SHORT (CR0-B4) bit = “1”
MCK
tMB
3
BCLK
1
2
4
5
6
7
8
tSX
tXS
XSYNC
PCMOUT
PCMOSY
tXD2
D3
tWS
tXD3
tXD1
MSD
D2
D4
D5
D6
D7
D8
tXD4
Figure 1 Transmit Side Timing Diagram
Receive Timing - 8-bit PCM Mode with LIN (CR0-B3) bit = “0”
Long Frame Sync Mode with SHORT (CR0-B4) bit = “0”
MCK
tMB
1
2
3
4
5
6
7
8
BCLK
tRS
tSR
RSYNC
PCMIN
tW S
tDS
tDH
MSD
D2
D3
D4
D5
D6
D7
D8
Short Frame Sync Mode with SHORT (CR0-B4) bit = “1”
MCK
tMB
1
2
3
4
5
6
7
8
BCLK
tSR
tRS
RSYNC
PCMIN
tW S
tDS
tDH
MSD
D2
D3
D4
D5
D6
D7
Figure 2 Receive Side Timing Diagram
Note: The above timings are also valid in 14-bit linear PCM Mode with the LIN (CR0-B3) bit = “1”,
except that the number of data bits on the PCMIN and PCMOUT signals changes from 8 to 14.
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PCM Interface Bit Configuration
8-bit PCM Mode with LIN (CR0-B3) bit =”0” & Long Frame Sync Mode with SHORT (CR0-B4) bit = “0”
1
9
17
25
1
BCLK
RSYNC
PCMIN
PCMOUT
CH1 PCM DATA
CH2 PCM DATA
PCMOSY
14-bit Linear PCM Mode with LIN (CR0-B3) bit = ”1” & Long Frame Sync Mode with SHORT (CR0-B4) bit = “0”
1
9
17
25
1
BCLK
RSYNC
PCMIN
PCMOUT
CH1 Linear DATA
CH2 Linear DATA
PCMOSY
8-bit PCM Mode with LIN (CR0-B3) bit = “0” & Short Frame Sync Mode with SHORT (CR0-B4) bit = “1”
1
9
17
25
1
BCLK
RSYNC
PCMIN
PCMOUT
CH1 PCM DATA
CH2 PCM DATA
PCMOSY
14-bit Linear PCM Mode with LIN (CR0-B3) bit = “1” & Short Frame Sync Mode with SHORT (CR0-B4) bit = “1”
1
9
17
25
1
BCLK
RSYNC
PCMIN
PCMOUT
CH1 Linear DATA
CH2 Linear DATA
PCMOSY
Figure 3 PCM Interface Bit Configuration
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SGC, PCMOUT, and AOUT Output Timing
Figure 4 SGC, PCMOUT, and AOUT Output Timing
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MCU Serial Interface
DEN
t2
t5
t10
15
EXCK
1
2
3
4
5
6
13
14
t9
t6
t7
t1
t3
t4
DIO
W
A4
A4
A3
A3
A2
A2
A1
t8
A0
A0
B1
B1
B0
B0
(Write)
t11
DIO
R
A1
(Read)
Figure 5 MCU Serial Interface
SLIC Interface
DEN
15
t20
16
13
14
EXCK
SLIC_I/F *5
E0_n
t21
*5 SLIC_I/F = F2_n pin, F1_n pin, F0_n, SWCn pin, BSELn pin
Figure 6 SLIC Interface 1 (to SLIC)
ALMn
DETn
pin,or
Either
pin or
ALMn, DETn
DEN pin (CR6 and CR13)
t23
t23
t22
INT
INT
ALMn
)
(from
(from
DETn
)
t24
Figure 7 SLIC Interface 2 (from SLIC)
* The INT pin driven to a logic “1” in either of the following cases;
(1) (PDN pin = logic “1”) Any of the ALMn or DETn pins (maximum 4 pins concerned) in a logic “0”
state go to logic “1”.
(2) (PDN pin = logic “0”) All of the ALMn or DETn pins (maximum 4 pins concerned) in a logic “0” state
go to logic “1”.
(3) Both SLIC 1 control (CR6) and SLIC 2 control (CR13) are read by the MCU.
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FUNCTIONAL DESCRIPTION
Pin Functional Description
AIN1N, AIN1P, AIN2N, AIN2P, GSX1, GSX2
The AINnN and AINnP pins are the transmit path analog inputs for Channel-n, where n equals channel 1 or
channel 2. The AINnN pin is the inverting input, and the AINnP pin is the non-inverting input for the op-amp.
The GSXn pin functions as the transmit path level adjustment for Channel-n and is connected to the output of the
op-amp. It is used to adjust the output level as shown in Figure 8 below.
When the AINnN or AINInP pins are not in use, connect the AINnN pin to the GSXn pin and the AINnP pin to
the SGC pin. During power-down mode, the GSXn output is in a high impedance state.
In the case of the analog input 2.226 Vpp at the GSXn pin, the digital output will be +3.00 dBm0.
GSX1
CH1 Gain
Gain = R2/R1 ≤ 10
R1: Variable
R2
AIN1N
AIN1P
CH1
Analog
Input
R2 > 20 kΩ
C1 R1
C1 > 1/(2 × 3.14 × 30 × R1)
SGC
CH2 Gain
Gain = R4/R3 ≤ 10
R3: Variable
GSX2
R4
AIN2N
AIN1P
R4 > 20 kΩ
CH2
C2 > 1/(2 × 3.14 × 30 × R3)
Analog
Input
C2 R3
SGC
Figure 8 Example of Analog Input Setting Schematic
AOUT1P, AOUT1N, AOUT2P, AOUT2N
The AOUTnN and AOUTnP pins are the receive path analog outputs from Channel-n, where n equals channel 1
or channel 2. These pins can drive a load of 20 kΩ or more. When the AOUTnSEL register bit (CR7-B7/CR14-
B7) is cleared (0), the AOUTnP pin is a single-ended output from Channel-n and the AOUTnN pin is at high
impedance. When the AOUTnSEL bit is set (1), the AOUTnN and AOUTnP pins are differentials outputs from
the corresponding channel.
The output signal from each of these pins has an amplitude of 3.4 Vpp above and below the signal ground
voltage (SG). Hence, when the maximum PCM code (+3.00 dBm0) is input to the PCMIN pin, the maximum
amplitude between the AOUTnN pin and the AOUTnP pin will be 6.8 Vpp.
While the device is in power-down mode, or the corresponding channel (1 or 2) is in power saving mode, the
related outputs are high impedance. Refer to Table 5 for more information.
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TOUT1, TOUT2
TOUTn is the tone analog output for the corresponding channel. The output signal has an amplitude of 2.5 Vpp
above and below the signal ground voltage (SG). While the device is in power-down mode, or the corresponding
channel is in power-save mode, the related outputs are high impedance.
VDDA, VDDD
+5 V power supply for analog and digital circuits. The VDDA pin is the power pin for the analog circuits. The
V
DDD pin is the power pin for the digital circuits. If these signals are connected together externally, The VDDA pin
must be connected to the VDDD pin in the shortest distance on the printed circuit board. Internal to the ML7033,
the VDDA plane is separate from the VDDD plane.
To minimize power supply noise, a 0.1 µF bypass capacitor (with excellent high frequency characteristics) and a
10 µF electrolytic capacitor should be connected between the VDDA pin and the AG pin. In addition, the same
capacitive network should also be connected between the VDDD pin and the DG pin. If the AG and DG pins are
connected together externally, only one capacitive network is required.
AG, DG
The AG pin is a ground for the analog circuits. The DG pin is a ground for the digital circuits.
The analog ground and the digital ground are separated internally within the device. The AG pin and DG pins
must be connected in the shortest distance on the printed circuit board, and then to system ground with a low
impedance.
SGC
The SGC pin used is to internally generate the signal ground voltage level by connecting a bypass capacitor. The
output impedance is approximately 50 kΩ. Connect a 0.1 µF bypass capacitor with excellent high frequency
characteristics between the SGC pin and the AG pin. During power-down mode, the SGC output is at the voltage
level of the AG pin.
SG
The SG pin is the signal ground level output for the system circuits. The output voltage is 2.4 V, the as same as
the SGC pin in a normal operating state. During power-down mode, this output is high impedance.
MCK
Master clock input. Input either 2.048 or 4.096 MHz clock. After turning on the power, the appropriate value
must be written into the MCKSEL bit (CR0-B5) depending upon the desired master clock frequency.
If the supplied master clock frequency and the value of the MCKSEL bit (CR0-B5) do not match, the power-
down control circuit and the MCU interface circuit will continue to operate properly. Access to the control
registers can also occur. However, other circuits may not operate properly.
As for the power-on sequence, please refer to “Power-On Sequence” in the later page.
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BCLK
Shift clock signal input for the PCMIN and the PCMOUT signals. The clock frequency, equal to the data rate, is
256 kHz to 4096 kHz. This signal must be generated from the same clock source as the master clock and
synchronized in phase with the master clock. Please refer to Figures 1 and 2 for more information about the
phase difference between MCK and BCLK.
RSYNC
Receive synchronizing clock input. The PCMIN signals are received in synchronization with this clock. The 8
kHz input clock is generated from the identical clock source as MCK and must be synchronized in phase with
the master clock.
XSYNC
Transmit synchronizing clock input. The PCMOUT signals are transmitted in synchronization with this clock.
The 8 kHz input clock is generated from the identical clock source as MCK and must be synchronized in phase
with the master clock.
PCMIN
Serial PCM data input. The serial PCM data input on the PCMIN pin is converted to analog signals and output
from the AOUTnP pin (or from the AOUTnN pin and the AOUTnP pin) in synchronization with the RSYNC
clock and the BCLK clock.
When in Long Frame Sync Mode (CR0-B4 = “0”), the first bit of the serial PCM data (MSD of channel 1) is
identified at the rising edge of the RSYNC clock.
When in Short Frame Sync Mode (CR0-B4 = “1”), the first bit of the serial PCM data (MSD of channel 1) is
identified at the falling edge of the RSYNC clock.
PCMOUT
Serial PCM data output. Channel 1 data is output in sequential order, from most significant data (MSD) to least
significant data (LSD). Data is synchronized with the rising edge of BCLK.
When in Long Frame Sync Mode (CR0-B4 = “0”), the first bit of PCM data may be output at the rising edge of
the XSYNC signal, depending on the timing between BCLK and XSYNC.
When in Short Frame Sync Mode (CR0-B4 = “1”), the first bit of PCM data may be output at the falling edge of
the XSYNC signal, depending on the timing between BCLK and XSYNC.
This pin is in a high impedance state during power-down. A pull-up resistor must be connected to this pin since
it is an open drain output.
PCMOSY
PCMOSY is asserted to a logic 0 when PCM data is valid on the PCMOUT pin. This includes both normal mode
and power-save mode.
When PCM data is not being output from the PCMOUT pin (including during power-down mode), this pin goes
a logic “1”.
This signal is used to control the TRI-STATE Enable of a backplane line-driver.
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Table 1 PCM Codes in 8-bit PCM Mode with the LIN (CR0-B3) bit = “0”
PCMIN/PCMOUT
ALAW (CR0-B2) bit = “0” (µ-law ) ALAW (CR0-B2) bit = “1” (A-law )
MSD D2 D3 D4 D5 D6 D7 D8 MSD D2 D3 D4 D5 D6 D7 D8
INPUT/OUTPUT
Level
+Full scale
+0
1
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
1
0
0
0
1
1
0
1
0
0
1
0
1
1
0
1
0
0
1
0
1
1
0
1
0
0
1
0
1
1
0
–0
–Full scale
Table 2 PCM Codes in 14-bit Linear PCM Mode with the LIN (CR0-B3) bit = “1”
PCMIN/PCMOUT
MSD D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14
INPUT/OUTPUT
Level
+Full scale
0
0
0
1
1
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
1
0
1
0
+1
0
–1
–Full scale
PDN
Power-down control signal. When PDN is a asserted (logic “0”), both the channel 1 and channel 2 circuits enter
the power-down state. However, even in power-down mode, the state of the control registers is maintained.
Reads and writes to the registers are also possible, and the state of the INT pin also changes in accordance with
inputs from the SLIC devices. This pin is deasserted (logic “1”) by external logic during normal operation.
This power-down function is available even in power saving mode by the MODEn (CR0-B1/CR0-B0) bit.
RESET
An input to reset control registers. By asserting the RESET pin (applying a logic “0”), all control registers are
initialized. During a normal operation mode, set this pin logic “1”.
Table 3 State of PCMOUT in 8-bit PCM Mode with LIN (CR0-B3) bit = “0”
PDN pin
MODE1 bit
0/1
MODE0 bit
0/1
ALAW bit
CH2 PCM Data
Hi-Z *1
CH1 PCM Data
Hi-Z *1
1 1 1 1 1 1 1 1
1 1 0 1 0 1 0 1
Operate
0
0/1
0
1
0
1
0
1
0
1
1 1 1 1 1 1 1 1
1 1 0 1 0 1 0 1
1 1 1 1 1 1 1 1
1 1 0 1 0 1 0 1
Operate
1
1
1
1
0
0
1
1
0
1
0
1
Operate
1 1 1 1 1 1 1 1
1 1 0 1 0 1 0 1
Operate
Operate
Operate
Operate
Operate
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Table 4 State of PCMOUT in 14-bit Linear PCM Mode with LIN (CR0-B3) bit = “1”
PDN pin
MODE1 bit
MODE0 bit
ALAW bit
CH2 PCM Data
Hi-Z *1
CH1 PCM Data
Hi-Z *1
0
1
1
1
1
0/1
0
0
1
1
0/1
0
1
0
1
ALL “0”
ALL “0”
Operate
Operate
ALL “0”
Operate
ALL “0”
0/1
Operate
Table 5 State of Analog Output Pins
PDN MODE1 MODE0 GSX1
GSX2
pin
Hi-Z
AOUT1
pin
Hi-Z
AOUT2
pin
Hi-Z
SG
pin
Hi-Z
SGC
pin
MCU
pin
0
bit
0/1
0
bit
0/1
0
pin
Hi-Z
Interface
AG level *2 Operate
AG level *2 Operate
1
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
1
1
1
0
1
1
1
0
1
Operate
Hi-Z
Hi-Z
Operate
Operate
Hi-Z
Hi-Z
Operate
Operate
Operate
Operate
Operate
Operate
Operate
Operate Operate
Operate Operate Operate Operate Operate
*1 The data will be ‘H’ by an external pull-up resistor.
*2 Output impedance = about 50 kΩ
F2_1, F1_1, F0_1, F2_2, F1_2, F0_2
The F2_n, F1_n and F0_n pins are data outputs used when the SLIC connected to the corresponding channel is
an Intersil RSLICTM series device. The output levels from the F2_n, the F1_n and F0_n pins are determined by
the F2_n, F1_n, and F0_n register bits (CR6-B7 to B5 and CR13-B7 to B5). By inputting these outputs directly
into the corresponding input pin of the SLIC device, the SLIC operating mode selection is possible.
Even in the power-down state with the PDN pin is asserted, these pins remain functional.
E0_1, E0_2
The E0_n pins are the detector mode selection data outputs. These pins are used when the SLIC connected to the
corresponding channel is an Intersil RSLICTM series device. Though the output level from the E0_n pin is
determined by the E0_n bit (CR6-B2/CR13-B2), the output level changes in 20 µs (= hold timer) in the power-
on mode with the PDN pin = logic “1” and in 200 ns in the power-down mode with the PDN pin = logic “0”
after the change of E0_n bit (CR6-B2 /CR13-B2). Refer to Figure 6 for information.
What event is actually detected by the SLIC is determined by the combination of the F2_n, F1_n, F0_n and E0_n
pins. Refer to Table 6 for more information. By connecting the output directly into the corresponding input pin
of the SLIC device, detector mode selection in the SLIC is possible. Even in the power-down state with the PDN
pin = logic “0”, this pin remains functional. However, the hold timer is ignored in this state.
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Table 6 SLIC Device Operation Mode and Detector Mode
Operating Mode
Low Power Standby
Forward Active
Unbalanced Ringing
Reverse Active
Ringing
Forward Loop Back
Tip Open
Power Denial
F2_n F1_n F0_n E0_n = 1
E0_n = 0
GKD
GKD
RTD
GKD
RTD
GKD
GKD
n/a
Description
Standby mode
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
SHD
SHD
RTD
SHD
RTD
SHD
SHD
n/a
Forward battery loop feed
Unbalanced ringing mode
Reverse battery loop feed
Balanced ringing mode
Test mode
For PBX type application
Device shutdown
SHD: Switch Hook Detection RTD: Ring Trip Detection GKD:Ground Key Detection
BSEL1, BSEL2
The BSELn pin is the battery mode selection data output. This pin is used when the SLIC connected to the
corresponding channel is an Intersil RSLICTM series SLIC device. A logic “0” on this pin selects the low battery
mode, and the logic “1” selects the high battery mode within the SLIC device. The output levels from the BSELn
pins are determined by the BSELn register bits (CR6-B3/CR13-B3).
By connecting these outputs directly to the corresponding SLIC device input pins, battery mode selection of the
SLIC is possible. This pin remains functional even in power-down mode.
SWC1, SWC2
The SWCn pin is the uncommitted switch control data output. This pin is used when the SLIC connected to the
corresponding channel is an Intersil RSLICTM series SLIC device. By connecting this pin directly to the
corresponding input pin of the SLIC device, the uncommitted switch control can be made. The uncommitted
switch is located between the SW+ pin and the SW- pin. A logic “0” on this pin enables the SLIC internal switch
on, and a logic “1” disables the switch.
The output levels from the SWC1 and SWC2 pins are determined by the SWCn register bits (CR6-B4/CR13-
B4). This pin remains functional even in power-down mode with the PDN pin is a logic “0”.
DET1, DET2
The DETn pins are the SLIC’s detection signal (switch hook, ring trip or ground key detection) inputs. These
pins are used when the SLIC connected to the corresponding channel is an Intersil RSLICTM series device. A
logic “0” on this pin clears the corresponding DETn register bit (CR6-B1/CR13-B1). A logic ‘1’ on this pin
input sets the register bit.
The Intersil RSLICTM series SLIC device is equipped with a function to switch the output on its DET pin from a
logic “1” state to a logic “0” state when it detects an assigned event of either off-hook, ring trip or ground key.
Therefore, by connecting these pins to the corresponding pins on the SLIC device and reading the DETn register
bit (CR6-B1/CR13-B1), the occurrence of an assigned event can be detected.
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The event detected by the SLIC is determined by the F2_n, F1_n, and F0_n register bits (CR6-B7 to B5/CR13-
B7 to B5), and the E0_n register bits (CR6-B2 /CR13-B2). To avoid the unintended detection of these conditions
due to glitches on the DETn signal of the SLIC, the ML7033 is equipped with a debounce timer to hold the DET
register bit (CR6-B1/CR13-B1) and the output of the INT pin for a set period, even when an input to the DETn
pin changes from a logic “1” to a logic “0”. For more information on the debounce timer, refer to the
DETnTIM3 through DETnTIM0 register bit descriptions (CR4-B7 to B0).
This pin remains functional in power-down mode (PDN pin low). However, while in the power-down state, the
debounce timer is disabled.
When this pin is not used, it should be tied to VDDD
.
ALM1, ALM2
The ALMn pins are the thermal shut down alarm signals. These pins are used when the SLIC connected to the
corresponding channel is an Intersil RSLICTM series device. A logic “0” on the ALMn input pin clears the
corresponding ALM register bit (CR6-B0/CR13-B0). A logic “1” on this pin sets the bit.
The Intersil RSLICTM series device is equipped with a function that allows it to automatically enter power-down
mode and toggle its ALMn pin from a logic “1” to a logic “0” state when the SLIC die temperature exceeds a
safe operating temperature. Hence, by connecting the corresponding pin of the SLIC device to the ALM1 and
ALM2 pins and reading the ALM register bit (CR6-B0/CR13-B0), it is possible to know whether the concerned
SLIC device is operating normally, or is in a thermal shutdown state.
This pin remains functional in power-down mode. However, while in the power-down state, the debounce timer
is disabled.
When this pin is not used, it should be tied to VDDD
.
INT
The ML7033 asserts the INT interrupt pin when either the DETn pin or the ALMn pin are asserted by the SLIC
device when the device is an Intersil RSLICTM series SLIC device. The Intersil RSLICTM series device is
equipped with detector and thermal shut down alarm functions to notify a change of SLIC state by driving a
logic 0 onto the output pins connected to DETn and ALMn. Refer to the DETn and ALMn pin descriptions
above. By monitoring the state of the INT pin and reading the DETn (CR6-B0/CR13-B0) and ALMn (CR6-
B0/CR13-B0) register bits, it is possible to know that a change of a state occurred within the SLIC device.
The INT pin transitions from a logic “1” to a logic “0” in the following cases;
(1) (PDN pin = logic “0”) Any of the ALMn or DETn pins in the logic “1” state transition to the logic “0”
state.
(2) (PDN pin = logic “1”) Any of the ALMn or DETn pins transition from the logic “1” state to the logic “0”
state when all the four pins (ALM1, ALM2, DET1, and DET2) have been in the logic “1” state.
Note that the debounce timer with the DETn pin is not valid while in power-down mode (PDN pin = logic “0”).
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The INT pin is released to the logic “1” state in either of the following cases;
(1) (PDN pin = logic “1”) Any one of the ALMn or DETn pins in the logic “0” state transition to the logic “1”
state.
(2) (PDN pin = logic “0”) All of the ALMn or DETn pins in the logic “0” state transition to the logic “1”
state.
(3) Both SLIC 1 control (CR6 register) and SLIC 2 control (CR13 register) are read by the MCU.
Note that the debounce timer, which works when the DETn pin changes from a logic “1” state to a to logic “0”
state, does not work when the pin changes from logic “0” to logic “1”.
DEN, EXCK, DIO
Serial control ports for the MCU interface. These pins are used by an external MCU to access the internal control
registers of the ML7033. The DEN pin is the data enable input. The EXCK pin is the data shift clock input. The
DIO pin is the address and data input/output. Figure 9 shows the MCU interface input/output timing diagram.
Note that EXCK must be a continuous clock of at least 15 pulses or more.
DEN
EXCK
DIO (I)
W
R
A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0
Write timing
DEN
EXCK
Output
Input
DIO (O)
A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0
Read timing
Figure 9 MCU Interface Timing Diagram
CIDATA1, CIDATA2
The CIDATA1 and CDATA2 data inputs are used for Caller ID generation. While in a Caller ID tone generation
mode with the CIDCHnON register bit set, (CR1-B1/CR1-B0), signals on the CIDATAn pins are modulated in
either the ITU-T V.23 or Bell 202 schemes. The scheme is determined by the CIDFMT register bit (CR1-B2),
and output from the analog output pin(s).
The analog output pins for modulated Caller ID data can be selected by the CHnTG2TX (CR7-B6/CR14-B6),
the CHnTGTOUTn (CR7-B5/CR14-B5), and the AOUTnSEL (CR7-B7/CR14-B7) register bits.
The output level for the modulated Caller ID data can be tuned by the CHnTG1LVn (CR9-B7 to B1/CR16-B7 to
B1) register bits.
TEST
The TEST input is used for testing purposes only during the manufacturing process and has no function once the
testing process is completed. This pin is not used during normal operation of the device and should be kept at a
logic “0” state.
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Power-On Sequence
While in the power-on state, the following chart is recommended.
<NOTE>
POWER OFF
As the ML7033 is equipped with a power-on
reset function, initialization of the control
registers automatically occurs as the power is
turned on, even with the RESET pin = logic “1”.
However, if any of input pins are not in a high
impedance state, the power-on reset may not
function properly.
Power supply on
<Recommendation>
PDN pin = logic “0”, RESET pin= “0”
Keep the input to the RESET pin in the logic “0”
state for 100ns or longer before changing to a
logic “1”.
RESET pin = “0” to “1”
(or Power-on Reset Function)
Control Register Setting
(CH1/CH2)
Even during power-down mode with the PDN
pin = logic “0”, the SLIC interface registers
(CR6, CR13) and the INT pin are working. Data
set in other registers becomes valid after the
PDN pin is driven to a logic “1” state.
PDN pin = “1”
Normal Operation
Figure 10 Power-on Sequence Flow Chart
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Control Registers Functional Description
CR0 (Basic operating mode)
B7
B6
B5
B4
B3
LIN
0
B2
ALAW
0
B1
MODE1
0
B0
MODE0
0
CR0
FILTER1SEL FILTER2SEL MCKSEL SHORT
default
0
0
0
0
B7
… Transmit and receive filter select for CH1
0 : ITU-T G.714 filter 1 : wideband filter for V.90 data modem application
B6
… Transmit and receive filter select for CH2
0 : ITU-T G.714 filter
1 : wideband filter for V.90 data modem application
B5
B4
… MCK frequency select
0 : 2.048 MHz 1 : 4.096 MHz
… Frame synchronizing scheme select 0 : Long frame SYNC 1 : Short frame SYNC
Refer to Figure 3.
B3
… PCM companding law select
0 : 8-bit PCM mode
1 : 14-bit linear PCM (2’s complement) mode
“1” is selected, a setting with the ALAW (CR0-B2) bit is ignored.
B2
… PCM companding law select 0 : µ-law 1 : A-law
When the LIN (CR0-B3) is “1”, a setting with this bit is ignored.
… Power saving control
B1, B0
0 : Power saving mode 1 : Normal operation
The MODE1 (CR0-B1) bit is for channel 2, and the MODE0 (CR0-B0) bit is for channel 1.
In power saving mode, power for the corresponding channel is turned off except for the last
output stage of the PCMOUT pin. The power saving mode differs from the power-down
mode controlled by the PDN pin in the following aspects;
-
-
Possible to control a state for an individual channel independently
The last stage of the PCMOUT pin is operational, and outputs ‘positive zero’ PCM code
in the 8-bit PCM mode or ‘zero’ PCM code in the 14-bit Linear PCM mode during the
assigned time slot.
-
Debounce timer and hold timer are valid.
As in power-down mode, the power saving mode does not initialize control registers and
read and write of control registers are possible in the power saving mode. The power-down
mode setting by the PDN pin takes precedence over the power saving mode.
Table 7 Mode Settings for CH1 and CH2
Power of Channel
MODE1 MODE0
PDN
RESET
Register
bit
0*1
0*1
0/1
0
bit
0*1
0*1
0/1
0
pin
pin
CH2
OFF
OFF*2
OFF
OFF*2
OFF*2
ON
CH1
OFF
OFF*2
OFF
OFF*2
ON
0
1
0
1
1
1
1
0
0
1
1
1
1
1
Initialized to default
Initialized to default
Read/Write possible
Read/Write possible
Read/Write possible
Read/Write possible
Read/Write possible
0
1
1
0
OFF*2
ON
1
1
ON
*1 forced to be default by the RESET pin = logic “0”.
*2 The last output stage is powered.
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CR1 (Tone generator and Call ID tone control)
B7
B6
B5
B4
0
B3
0
B2
CIDFMT
0
B1
CID
CH2ON
B0
CID
CH1ON
CH2TG
ON
CH1TG
ON
CR1
default
0
0
0
0
0
B7
B6
… State control for a tone generator on CHl
… State control for a tone generator on CH2
0 : disabled
0 : disabled
1 : enabled
1 : enabled
B5, B4, B3
… Reserved (The default alternation is prohibited.)
When a write action is executed for CR1, set these bits to “0”.
B2
… Caller ID generator modulation scheme select
0 : ITU-T V.23 scheme (1: 1300 Hz, 0: 2100 Hz)
1 : Bell 202 format (1: 1200 Hz, 0: 2200 Hz)
B1
B0
… State control for Caller ID generator on CH2
0 : OFF
1 : ON
Regardless of how the CH2TGON bit (CR1-B7) is set, signals input into the CIDATA2 pin
are modulated and output as Caller ID tones. When this bit is set, the level setting by the
CH2TG1LVn (CR16-B7 to B1) bits is valid, but the CH2TG1_n (CR16-B0/CR17-B7 to
B0) bits, CH2RING (CR11-B7) bit, and CH2TG1TRPn (CR11-B6 to B4) bits are invalid.
… State control for Caller ID generator on CH1
0 : OFF
1 : ON
Regardless of how the CH1TGON bit (CR1-B6) is set, signals input into the CIDATA1 pin
are modulated and output as Caller ID tones. When this bit is set, the level set by the
CH1TG1LVn (CR9-B7 to B1) bits is valid, but the CH1TG1_n (CR9-B0/CR11-B7 to B0)
bits, the CH1RING (CR11-B3) bit, and the CH1TG1TRPn (CR11-B2 to B0) bits are
invalid.
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CR2 (Pulse metering tone generator control)
B7
B6
B5
B4
B3
B2
B1
B0
PMG2
FRQ
PMG2
LV1
PMG2
LV0
PMG2
TOUT2
PMG1
FRQ
PMG1
LV1
PMG1
LV0
PMG1
TOUT1
CR2
default
0
0
0
0
0
0
0
0
B7
B6, B5
… Pulse metering tone frequency select for CH2
0 : 12 kHz
1 : 16 kHz
… Pulse metering tone level setting for CH2
(B6, B5) (0, 0) = OFF
(0, 1) = 0.5 Vpp
(1, 0) = 1.0 Vpp
(1, 1) = 1.5 Vpp
The level of the pulse metering tone, as shown in Figure 11, reaches the assigned level in
10 ms and gradually fades out over 10 ms.
The ramp-up and ramp-down times also apply when a tone is cancelled by writing (0,0)
into these register bits. Once the register bits are set, the tone begins to fade out and
completely fades out after 10 ms. In addition, subsequent writes to these bits are prohibited
for 10 ms.
Ramp down time=10ms
Ramp up time=10ms
Figure 11 Pulse Metering Tone Waveform
B4
… Pulse metering tone output pin select for CH2
0 : AOUT2 pin (added to voice signals)
1 : TOUT2 pin
B3
… Pulse metering tone frequency select for CH2
0 : 12 kHz
1 : 16 kHz
B2, B1
… Pulse metering tone level setting for CH1
(B2, B1) (0,0) = OFF
(0, 1) = 0.5 Vpp
(1, 0) = 1.0 Vpp
(1, 1) = 1.5 Vpp
The level of the pulse metering tone, as shown in Figure 11, reaches the assigned level in
10 ms and gradually fades over 10 ms.
The ramp-up and ramp-down times also apply when a tone is cancelled by writing (0,0)
into these register bits. In this case the tone fades out after 10 ms. In addition, subsequent
writes to these bits are prohibited for 10 ms.
B0
… Pulse metering tone frequency select for CH1
0 : 12 kHz
1 : 16 kHz
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CR3 (Time slot assignment control)
B7
TSAE
0
B6
TSAC
0
B5
TSA5
0
B4
TSA4
0
B3
TSA3
0
B2
TSA2
0
B1
TSA1
0
B0
TSA0
0
CR3
default
* CR3 is a write only register.
B7
… Time slot assignment customization enable
0 : Default time slot assignment 1 : Customized time slot assignment
The default time slot assignment is CH1 for Slot 0 and CH2 for Slot 2.
B6
… Time slot assignment channel select 0 : CH1 1 : CH2
This bit is used to specify the channel for which the accompanied TSAn
(CR3-B5 to B0) bits are going to assign a time slot. Hence, when a customized time slot
assignment is enabled, CR3 should be written twice; once for CH1 and another for CH2.
B5 to B0
… Assigned time slot select
Each time slot consists of 8 BCLK cycles. The number of time slots available for time slot
assignment depends upon the applied BCLK frequency, and can be calculated in the
following equations;
Number of time slots available for time slot assignment
= (BCLK frequency)/(SYNC frequency)/8
= (BCLK frequency)/64k
For instance, when the BCLK frequency is 4096 kHz, time slots that can be assigned are
from 0 (000000) to 63 (111111). The specification of a time slot beyond 63 is prohibited.
Note that in 14-bit linear PCM (2’s complement) mode, specified when the LIN bit (CR0-
B3) is set, only even numbered time slots (0, 2, 4, … 62) can be assigned.
In any mode, the assigned time slot for a channel is common both for transmit and receive,
and different time slots cannot be assigned for transmit and receive. When the TSAE bit
(CR3-B7) is cleared, the time slot assignment specified by these bits is ignored, and the
default time slots are assigned (CH1 for Time Slot 0 and CH2 for Time Slot 2). Figure 12
shows an example of how CH1 is assigned for Time Slot 0 (000000) and CH2 is assigned
for Time Slot 3 (000011) in 8-bit PCM mode.
1
9
17
25
33
BCLK
XSYNC
PCMOUT/
PCMIN
CH1 PCM DATA
CH2 PCM DATA
PCMOSY
Slot 0
Slot 1
Slot 2
Slot 3
Figure 12 Example of Time Slot Assignment: CH1 = Slot 0, CH2 = Slot 3
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CR4 (Debounced timer setting)
B7
B6
B5
B4
B3
B2
B1
B0
DET2
TIM3
DET2
TIM2
DET2
TIM1
DET2
TIM0
DET1
TIM3
DET1
TIM2
DET1
TIM1
DET1
TIM0
CR4
default
0
0
0
0
0
0
0
0
B7 to B4
B3 to B0
… Debounce timer setting for CH2
… Debounce timer setting for CH1
To avoid the unintended detection of glitches on the DETn signal, the ML7033 is equipped with
a debounce timer to hold the DETn (CR6-B1/CR13-B1) bit and the INT output state for a set
period, even when the state of the DETn pin changes from logic “1” to logic “0”. Bits B7 to B4
determine the debounce timer setting for CH2. Bits B3 to B0 determine the debounce timer
setting CH1.
The debounce timer is operational only in the power-on state when the PDN pin = logic “1”,
and remains operational in the power-saving mode with the MODEn (CR0-B1, B0) bits = “0” as
long as the device is in the power-on state.
The debounce timer holding time ranges from 0 ms to 225 ms at 15 ms intervals for each
individual channel. The values written into B7 to B4 (channel 2) or B3 to B0 (channel 1)
determine the holding time for each channel.
The timer value is calculated by the equation of [Decimal(B7,B6,B5,B4) * 15] or
[Decimal(B3,B2,B1,B0) * 15]. Refer to Table 8.
Table 8 Debounce Timer Setting
B7/B3
B6/B2
B5/B1
B4/B0
Timer (ms)
0
0
0
0
0
:
0
0
0
0
1
:
0
0
1
1
0
:
0
1
0
1
0
:
0
15
30
45
60
:
0
1
1
:
1
0
0
:
1
0
0
:
1
0
1
:
105
120
135
:
1
1
1
1
225
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CR5 (CH1 transmit/receive level control)
B7
LV1R3
0
B6
LV1R2
0
B5
LV1R1
0
B4
LV1R0
0
B3
LV1X3
0
B2
LV1X2
0
B1
LV1X1
0
B0
LV1X0
0
CR5
default
B7 to B4
B3 to B0
… Level setting for CH1 on its receive side
The LV1R3 to LV1R0 bits determine the level for the CH1 receive side as shown in Table
9.
… Level setting for CH1 on its transmit side
The LV1X3 to LV1X0 bits determine the level for the CH1 transmit side as shown in Table
9.
Table 9 Receive and Transmit Level Setting
LV1R3/LV1X3
LV1R2/ LV1X2 LV1R1/LV1X1 LV1R0/LV1X0
Level (dBm0)
0.0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
–1.0
–2.0
–3.0
–4.0
–5.0
–6.0
–7.0
–8.0
–9.0
–10.0
–11.0
–12.0
–13.0
–14.0
OFF
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CR6 (SLIC 1 control)
B7
B6
F1_1
0
B5
F0_1
0
B4
SWC1
0
B3
BSEL1
0
B2
E0_1
0
B1
DET1
—
B0
ALM1
—
CR6
default
F2_1
0
* CR6-B1 and B0 are read-only bits. Though either of “0” or “1” will do for these registers when a byte-wide write action is
made, the written values are ignored.
* The INT pin which stays at logic “0” will be released to logic “1” when both of this control register (CR6) and SLIC 2
control register (CR13) are read.
B7 to B5
… Operation mode setting for SLIC1
The F2_1 to F0_1 bits determine the output level for the Fn_1 pins. For more details, refer
to Table 6. When each bit is cleared (“0”), the corresponding Fn_1 pin outputs a logic “0”.
When each bit is set (“1”), the corresponding Fn_1 pin outputs a logic “1”.
B4
… Uncommitted switch control for SLIC1
0 : switch on
1 : switch off
This bit determines the output level for the SWC1 pin. When this bit is cleared, the SWC1
pin outputs a logic “0”. When this bit is set, the pin outputs a logic “1”.
When the SLIC connected to CH1 is the Intersil RSLICTM series, the SLIC’s internal
uncommitted switch, located between the SW+ pin and the SW- pin, can be controlled by
inputting the output from the SWC1 pin directly into the corresponding input pin of the
SLIC device.
B3
B2
… Battery mode select for SLIC1
0 : low battery mode
1 : high battery mode
This bit determines the output level for the BSEL1 pin. When this bit is cleared, the BSEL1
pin outputs a logic “0”. When this bit is set, the pin outputs a logic “1”.
When the SLIC connected to CH1 is from the Intersil RSLICTM series, the SLIC’s battery
mode selection is possible by inputting the output from the BSEL1 pin directly into the
corresponding input pin of the SLIC device.
… Detector mode selection for SLIC1
This bit determines the output level for the E0_1 pin. When this bit is cleared, the E0_1 pin
outputs a logic “0”. When this bit is set, the pin outputs a logic “1”.
When a SLIC connected to CH1 is Intersil RSLICTM series, the SLIC’s detector mode
selection is possible by connecting the E0_1 pin directly to the corresponding input pin of
the SLIC device. The event detected by the SLIC is determined by the combination of the
F2_1, the F1_1, the F0_1 and the E0_1 pins as shown in Table 6.
The output level of the E0_1 pin changes 20µs later (hold timer) in the power-on mode with
the PDN pin = logic “1”, and 200ns later in the power-down mode with the PDN pin =
logic “0” than a change of this bit value. Refer to Figure 6.
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B1
… Event detection indicator for SLIC1 (Read-only bit)
0 : detected 1 : not detected
By reading the state of this bit, the input level to the DET1 pin can be known. If this bit is
cleared it indicates that the DET1 pin is in the logic “0” state. If this bit is set it indicates
that the DET1 pin is in the logic “1” state.
When the SLIC connected to channel 1 is from the Intersil RSLICTM series, the DET1 pin
can be connected directly to the corresponding output pin of the SLIC device. This allows
an assigned event such as off-hook, ring trip, or ground key to be detected. The event
detected by the SLIC detects is determined by the F2_1, F1_1, F0_1 (CR6-B7 to B5), and
E0_1 (CR6-B2) bits.
When the debounce timer is enabled by setting the DET1TIM3 through DET1TIM0 bits
(CR4-B3 to B0), the DET1 (CR6-B1) bit is held unchanged for a set period, even when the
DET1 input pin changes from logic “1” to logic “0”.
B0
… Thermal Shutdown Alarm indicator for SLIC1 (Read-only bit) 0 : detect
1 : not
detect
By reading this bit, the input level to the ALM1 pin can be known. When this bit is cleared,
the ALM1 pin is a logic “0”. When this bit is set, the pin is a logic “1”.
When the SLIC connected to channel 1 is from the Intersil RSLICTM series, the ALM1 pin
can be connected directly to the corresponding output pin of the SLIC device. This allows
the user to know whether the SLIC1 is in the normal operating state, or in the thermal
shutdown state.
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CR7 (CH1 Tone generator 2 control 1)
B7
AOUT1 SEL
0
B6
B5
B4
CH1TG2
LV3
B3
CH1TG2
LV2
B2
CH1TG2
LV1
B1
CH1TG2
LV0
B0
CH1TG2 _8
0
CH1TG 2
TX
CH1TG 2
TOUT1
CR7
default
0
0
0
0
0
0
CR8 (CH1 Tone generator 2 control 2)
B7 B6 B5
B4
B3
B2
B1
B0
CR8
CH1TG2 _7 CH1TG2 _6 CH1TG2 _5 CH1TG2 _4 CH1TG2 _3 CH1TG2 _2 CH1TG2 _1 CH1TG2 _0
CR7-B7
… AOUT1P, AOUT1N output select
0 : Single-ended output with the AOUT1P pin with the AOUT1N pin at high impedance
1 : Differential output with the AOUT1P and the AOUT1N pins
B6
… CH1 tone generator output select
0 : to Rx side
1 : to Tx side
B5
… CH1 tone generator Rx side output pin select
0 : AOUT1 pin
1 : TOUT1 pin
B4 to B1
… CH1 Tone Generator 2 (TG2) output level setting
This 4-bit field defines the output level for TG2 on CH1 as shown in Table 10.
Table 10 TG2 Level Setting
B4
(TG2LV3)
B3
(TG2LV2)
B2
(TG2LV1)
B1
(TG2LV0)
Level
(dBm0)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
OFF
–12.0
–11.0
–10.0
–9.0
–8.0
–7.0
–6.0
–5.0
–4.0
–3.0
–2.0
–1.0
0.0
+1.0
+2.0
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CR7-B0, CR8-B7 to B0
…
CH1 Tone Generator 2 (TG2) Frequency Select
These bits define the output frequency from TG2 on CH1. The frequency is between 300
and 3400Hz at 10Hz intervals. The values written to these bits determine the frequency as
shown in the following equation. Refer to Table 11.
Binary data for CR7-B0, CR8-B7 to B0
= (Output Frequency [Hz])/10
Below is an example of how these bits are programmed when the intended frequency is
1500Hz;
Ex) (Output Frequency [Hz])/10 = 1500/10 = 150d = 10010110b
Bits to set in CR7-B0, CR8-B7 to B0 = (0,1,0,0,1,0,1,1,0)
Note that the operations are not guaranteed when these bits define a frequency out of a band
between 300 and 3400 Hz.
Table 11 Tone Generator Frequency Setting
CR7
CR8
Frequency
(Hz)
decimal
hex
B0
0
0
0
:
B7
0
0
0
:
B6
0
0
0
:
B5
0
0
1
:
B4
1
1
0
:
B3
1
1
0
:
B2
1
1
0
:
B1
1
1
0
:
B0
0
1
0
:
300
310
320
:
30
31
32
:
01Eh
01Fh
020h
:
400
410
:
40
41
:
028h
029h
:
0
0
:
0
0
:
0
0
:
1
1
:
0
0
:
1
1
:
0
0
:
0
0
:
0
1
:
1000
1010
:
100
101
:
064h
065h
:
0
0
:
0
0
:
1
1
:
1
1
:
0
0
:
0
0
:
1
1
:
0
0
:
0
1
:
2000
:
200
:
0C8h
:
0
:
1
:
1
:
0
:
0
:
1
:
0
:
0
:
0
:
3000
:
300
:
12Ch
:
1
:
0
:
0
:
1
:
0
:
1
:
1
:
0
:
0
:
3390
3400
339
340
153h
154h
1
1
0
0
1
1
0
0
1
1
0
0
0
1
1
0
1
0
35/51
FEDL7033-02
ML7033
1
Semiconductor
CR9 (CH1 tone generator 1 control1)
B7
B6
B5
B4
CH1TG1
LV3
B3
CH1TG1
LV2
B2
CH1TG1
LV1
B1
CH1TG1
LV0
B0
CH1TG1 _8
0
CH1TG1
LV6
CH1TG1
LV5
CH1TG1
LV4
CR9
default
0
0
0
0
0
0
0
CR10 (CH1 tone generator 1 control2)
B7 B6 B5
B4
B3
B2
B1
B0
CR10
CH1TG1 _7 CH1TG1 _6 CH1TG1 _5 CH1TG1 _4 CH1TG1 _3 CH1TG1 _2 CH1TG1 _1 CH1TG1 _0
default
0
0
0
0
0
0
0
0
CR9-B7 to B1 … CH1 Tone Generator 1 (TG1) Output Level Setting
This 7-bit field defines the output level of TG1 on CH1. The output level can be turned
OFF or ON. When turned on, the level is between –12.1 dBm0 and +0.5 dBm0 at 0.1 dBm0
intervals as shown in Table 12.
The value written to this field is calculated based on the desired output level as shown in
the following equation.
Binary data for CR9- B7 to B1
= [(Output Level [dBm0]) + 12.2]*10
The following is an example of how to program this field when the intended output level is
–5.8 dBm0;
Ex) [(Output Level [dBm0]) + 12.2]*10 = (-5.8 + 12.2)*10 = 64d = 1000000b
Bits to set in CR9-B7 to B1 = (1,0,0,0,0,0,0)
Table 12 Tone Generator 1 Level Setting
B7
TG1LV6
B6
TG1LV5
B5
TG1LV4
B4
TG1LV3
B3
TG1LV2
B2
TG1LV1
B1
TG1LV0
Level
(dBm0)
0
0
0
0
0
:
0
0
0
0
0
:
0
0
0
0
0
:
0
0
0
0
0
:
0
0
0
0
1
:
0
0
1
1
0
:
0
1
0
1
0
:
OFF
–12.1
–12.0
–11.9
–11.8
:
0
1
1
:
1
0
0
:
1
0
0
:
1
0
0
:
1
0
0
:
1
0
0
:
1
0
1
:
–5.9
–5.8
–5.7
:
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
0
0
1
0
1
0
1
0
0.0
0.1
0.2
0.3
0.4
0.5
(= 1.25 Vop)
1
1
1
1
1
1
1
36/51
FEDL7033-02
ML7033
1
Semiconductor
CR9-B0, CR10-B7 to B0 …CH1 Tone Generator 1 Output Frequency Select
When the CH1RING (CR11-B3) bit is cleared (“0”), these 9 bits determine the output
frequency of tone generator 1 on channel 1 to a value between 300 and 3400 Hz at 10Hz
intervals. A sample list of frequencies is shown in Table 13. The value programmed into
this field is calculated based on the desired frequency using the following equation.
Binary data for CR9-B0, CR10-B7 to B0
= (Output Frequency [Hz])/10
The following is an example of how to program this field when the intended frequency is
1500 Hz;
Ex) (Output Frequency [Hz])/10 = 1500/10 = 150d = 10010110b
Bits to set in CR9-B0, CR10-B7 to B0 = (0,1,0,0,1,0,1,1,0)
Note that the operations are not guaranteed when these bits define a frequency out of a band
between 300 and 3400 Hz.
Table 13 Tone Generator Frequency Setting (CH1RING bit = “0”)
CR9
CR10
B4
1
1
0
:
Frequency
(Hz)
decimal
hex
B0
0
0
0
:
B7
0
0
0
:
B6
0
0
0
:
B5
0
0
1
:
B3
1
1
0
:
B2
1
1
0
:
B1
1
1
0
:
B0
0
1
0
:
300
310
320
:
30
31
32
:
01Eh
01Fh
020h
:
400
410
:
40
41
:
028h
029h
:
0
0
:
0
0
:
0
0
:
1
1
:
0
0
:
1
1
:
0
0
:
0
0
:
0
1
:
1000
1010
:
100
101
:
064h
065h
:
0
0
:
0
0
:
1
1
:
1
1
:
0
0
:
0
0
:
1
1
:
0
0
:
0
1
:
2000
:
200
:
0C8h
:
0
:
1
:
1
:
0
:
0
:
1
:
0
:
0
:
0
:
3000
:
300
:
12Ch
:
1
:
0
:
0
:
1
:
0
:
1
:
1
:
0
:
0
:
3390
3400
339
340
153h
154h
1
1
0
0
1
1
0
0
1
1
0
0
0
1
1
0
1
0
37/51
FEDL7033-02
ML7033
1
Semiconductor
When the CH1RING (CR11-B3) bit is set (“1”), the CH1TG1_8 (CR9-B0) bit and the
CH1TG1_7 to CH1TG1_6 (CR10-B7 to B6) bits are ignored and the CH1TG1_5 to
CH1TG1_0 (CR10-B5 to B0) bits are used to define the ringing tone frequency.
When the CH1RING (CR11-B3) bit is set, the frequency can be set to a value between 15
Hz and 50 Hz at 1 Hz intervals. The value programmed into this field is calculated based on
the desired frequency using the following equation. A partial list of frequencies is shown in
Table 14.
Binary data for CR10-B5 to B0
= (Output Frequency [Hz])
The following is an example of how to program this field when the intended frequency is
20Hz;
Ex) Output Frequency [Hz] = 20d = 010100b
Bits to set in CR10-B5 to B0 = (0,1,0,1,0,0)
Note that the operations are not guaranteed when these bits define a frequency out of a band
between 15 and 50Hz.
Table 14 Tone Generator Frequency Setting (CH1RING bit = “1”)
CR9
B0
—
—
—
—
—
—
:
CR10
B4
Frequency
(Hz)
decimal
hex
B7
—
—
—
—
—
—
:
B6
—
—
—
—
—
—
:
B5
0
0
0
0
0
0
:
B3
1
0
0
0
0
0
:
B2
1
0
0
0
0
1
:
B1
1
0
0
1
1
0
:
B0
1
0
1
0
1
0
:
15
16
17
18
19
20
:
15
16
17
18
19
20
:
0Fh
10h
11h
12h
13h
14h
:
0
1
1
1
1
1
:
48
49
50
48
49
50
30h
31h
32h
—
—
—
—
—
—
—
—
—
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
0
1
0
38/51
FEDL7033-02
ML7033
1
Semiconductor
CR11 (Ringing_ON and Trapezoid crest factors control)
B7
B6
B5
B4
B3
B2
B1
B0
CH2
RING
CH2TG1
TRP2
CH2TG1
TRP1
CH2TG1
TRP0
CH1
RING
CH1TG1
TRP2
CH1TG1
TRP1
CH1TG1
TRP0
CR11
default
0
0
0
0
0
0
0
0
B7
… CH2 Tone Generator 1 (TG1) function select
0 : CH2TG1 works as a non-ringing tone generator (300 to 3400 Hz)
1 : CH2TG1 works as a ringing tone generator (15 to 50 Hz)
The frequency and level of CH2TG1 are set by CR16 to CR17.
B6 to B4
… CH2 ringing tone waveform setting
This 3-bit field determines the type of ringing tone waveform for TG1 on CH2. A
sinusoidal waveform, or a trapezoidal waveform with a crest factor between 1.225 V and
1.375 V at 0.025 V intervals, can be selected as shown in Table 15. For a definition of
‘crest factor’, refer to Figure 13. These bits are valid when the CH2RING (CR11-B7) bit is
set.
B3
… CH1 TG1 function select
0 : CH1TG1 works as a non-ringing tone generator (300 to 3400 Hz)
1 : CH1TG1 works as a ringing tone generator (15 to 50 Hz)
The frequency and level of CH1TG1 are set by CR9 to CR10.
B2 to B0
… CH1 ringing tone waveform setting
This 3-bit field determines the type of ringing tone waveform for TG1 on CH1. A
sinusoidal waveform, or a trapezoidal waveform with a crest factor between 1.225 V and
1.375 V at 0.025 V intervals, can be selected as shown in Table 15. For a definition of
‘crest factor’, refer to Figure 13. These bits are valid when the CH1RING (CR11-B3) bit is
set.
Vp
a
a
CrestFactor =1/ 1− 4a /3
1
Figure 13 Ringing Tone Waveform
Table 15 Crest Factor Setting
B6/B2
TG1 TRP2
B5/B1
TG1 TRP1
B4/B0
TG1 TRP0
Crest Factor
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
OFF
1.225
1.250
1.275
1.300
1.325
1.350
1.375
39/51
FEDL7033-02
ML7033
1
Semiconductor
CR12 (CH2 transmit/receive level control)
B7
LV2R3
0
B6
LV2R2
0
B5
LV2R1
0
B4
LV2R0
0
B3
LV2X3
0
B2
LV2X2
0
B1
LV2X1
0
B0
LV2X0
0
CR12
default
B7 to B4
B3 to B0
… Level setting for CH2 on its receive side
This 4-bit field determines the level setting for the CH2 receive side. The settings range
from 0 to –14 dBm0 as shown in Table 16.
… Level setting for CH2 on its transmit side
This 4-bit field determines the level setting for the CH2 transmit side. The settings range
from 0 to –14 dBm0 as shown in Table 16.
Table 16 Receive and Transmit Level Setting
LV2R3/ LV2X3 LV2R2/ LV2X2 LV2R1/ LV2X1 LV2R0/ LV2X0
Level (dBm0)
0.0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
–1.0
–2.0
–3.0
–4.0
–5.0
–6.0
–7.0
–8.0
–9.0
–10.0
–11.0
–12.0
–13.0
–14.0
OFF
40/51
FEDL7033-02
ML7033
1
Semiconductor
CR13 (SLIC 2 control)
B7
B6
F1_2
0
B5
F0_2
0
B4
SWC2
0
B3
BSEL2
0
B2
E0_2
0
B1
DET2
-
B0
ALM2
-
CR13
default
F2_2
0
* CR13-B1 and B0 are read-only bits. Though either of “0” or “1” will do for these registers when a byte-wide write action is
made, the written values are ignored.
* The INT pin which stays at logic “0” will be released to logic “1” when both of this control register (CR13) and SLIC 1
control register (CR6) are read.
B7 to B5
… Operation mode setting for SLIC2
This 3-bit field determines the output level of the Fn_2 pins. For more detail, refer to Table
6. When any of these bits are cleared, the corresponding Fn_2 pin outputs a logic “0”.
When any of these bits are set, the corresponding Fn_2 pin outputs a logic “1”.
B4
… Uncommitted switch control for SLIC2
0 : switch on
1 : switch off
This bit determines the output level of the SWC2 pin. When this bit is cleared, the SWC2
pin outputs a logic “0”. When this bit is set, the SWC2 pin outputs a logic “1”.
When the SLIC connected to channel 2 is an Intersil RSLICTM series device, the internal
uncommitted switch of the SLIC, located between the SW+ and the SW- pins, can be
controlled by connecting the SWC2 pin directly to the corresponding input pin of the SLIC
device.
B3
B2
… Battery mode select for SLIC2
0 : low battery mode
1 : high battery mode
This bit determines the output level for the BSEL2 pin. When this bit is cleared, the BSEL2
pin outputs a logic “0”. When this bit is set, the BSEL2 pin outputs a logic “1”.
When the SLIC connected to CH2 is an Intersil RSLICTM series device, the battery mode
selection of the SLIC is possible by connecting the BSEL2 pin directly to the corresponding
input pin of the SLIC device.
… Detector mode selection for SLIC2
This bit determines the output level of the E0_2 pin. When this bit is cleared, the E0_2 pin
outputs a logic “0”. When this bit is set, the E0_2 pin outputs a logic “1”.
When the SLIC connected to channel 2 is an Intersil RSLICTM series device, the detector
mode selection of the SLIC is possible by connecting the E0_2 pin directly to the
corresponding input pin of the SLIC device. The event detected by the SLIC is determined
by the F2_2, F1_2, F0_2 and E0_2 output pins as shown in Table 6.
The output level from the E0_2 pin changes 20 µs later (hold timer) in the power-on mode
with the PDN pin = logic “1”, and 200 ns later in the power-down mode with the PDN pin
= logic “0” than a change of this bit value. Refer to Figure 6 for more information.
41/51
FEDL7033-02
ML7033
1
Semiconductor
B1
… Event detection indicator for SLIC2 (Read-only bit)
0 : detected 1 : not detected
By reading the state of this bit, the input level to the DET2 pin can be determined.
If this bit is cleared, the DET2 pin is a logic “0”. If this bit is set, the DET2 pin is a logic
“1”.
When the SLIC connected to channel 2 is an Intersil RSLICTM series device, an assigned
event of off-hook, ring trip or ground key can be detected by connecting the DET2 pin of
the ML7033 directly to the corresponding output pin of the SLIC device.
The event detected by the the SLIC is determined by the F2_2, F1_2, F0_2 (CR13-B7 to
B5), and E0_2 (CR13-B2) bits.
When a debounce timer is enabled by a setting with the DET2TIM3 through DET2TIM0
bits (CR4-B7 to B4), the DET2 (CR13-B1) bit is held unchanged for a set period, even
when the DET2 pin changes from a logic “1” to a logic “0”.
B0
… Thermal Shutdown Alarm indicator for SLIC2 (Read-only bit) 0 : detect
By reading the state of this bit, the input level to the ALM2 pin can be determined.
1 : not
detect
If this bit is cleared, the ALM2 pin is a logic “0”. If this bit is set, the ALM2 pin is a logic
“1”.
When the SLIC connected to channel 2 is an Intersil RSLICTM series device, connecting the
ALM2 pin directly to the corresponding output pin of the SLIC device allows the ML7033
to know whether the SLIC is in the normal operating mode, or in a thermal shutdown state.
42/51
FEDL7033-02
ML7033
1
Semiconductor
CR14 (CH2 tone generator 2 control1)
B7
B6
B5
B4
CH2TG2
LV3
B3
CH2TG2
LV2
B2
CH2TG2
LV1
B1
CH2TG2
LV0
B0
CH2TG2 _8
0
CH2TG2
TOUT2
CR14
AOUT2 SEL CH2TG2 TX
default
0
0
0
0
0
0
0
CR15 (CH2 tone generator 2 control2)
B7 B6 B5
B4
B3
B2
B1
B0
CR15
CH2TG2 _7 CH2TG2 _6 CH2TG2 _5 CH2TG2 _4 CH2TG2 _3 CH2TG2 _2 CH2TG2 _1 CH2TG2 _0
default
0
0
0
0
0
0
0
0
CR14-B7
… AOUT2P, AOUT2N output select
0 : Single-ended output with the AOUT2P pin with the AOUT2N pin at high impedance.
1 : Differential output with the AOUT2P and the AOUT2N pins.
B6
… CH2 tone generator output select
… CH2 tone generator Rx side output pin select
… CH2 TG2 output level setting
0 : to Rx side
1 : to Tx side
B5
0 : AOUT2 pin
1 : TOUT2 pin
B4 to B1
This 4-bit field determines the output level of TG2 on CH2. The output level ranges from –
12 to +2 dBmO as shown in Table 17.
Table 17 Tone Generator 2 Level Setting
B4
TG2LV3
B3
TG2LV2
B2
TG2LV1
B1
TG2LV0
Level
(dBm0)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
OFF
–12.0
–11.0
–10.0
–9.0
–8.0
–7.0
–6.0
–5.0
–4.0
–3.0
–2.0
–1.0
0.0
+1.0
+2.0
43/51
FEDL7033-02
ML7033
1
Semiconductor
CR14-B0, CR15-B7 to B0… CH2 TG2 frequency select
These 9 bits define the output frequency for TG2 on CH2. The frequency range is between
300 and 3400 Hz in 10 Hz intervals as shown in Table 18.
The output frequency is calculated using the following formula:
Binary data for CR14-B0, CR15-B7 to B0
= (Output Frequency [Hz])/10
The following example shows how to program the output frequency when the intended
frequency is 1500 Hz;
Ex) (Output Frequency [Hz]) / 10 = 1500/10 = 150d = 10010110b
Bits to set in CR14-B0, CR15-B7 to B0 = (0,1,0,0,1,0,1,1,0)
Note that the operations are not guaranteed when these bits define a frequency out of a band
between 300 and 3400 Hz.
Table 18 Tone Generator Frequency Setting
CR14
CR15
B4
1
1
0
:
Frequency
(Hz)
decimal
hex
B0
0
0
0
:
B7
0
0
0
:
B6
0
0
0
:
B5
0
0
1
:
B3
1
1
0
:
B2
1
1
0
:
B1
1
1
0
:
B0
0
1
0
:
300
310
320
:
30
31
32
:
01Eh
01Fh
020h
:
400
410
:
40
41
:
028h
029h
:
0
0
:
0
0
:
0
0
:
1
1
:
0
0
:
1
1
:
0
0
:
0
0
:
0
1
:
1000
1010
:
100
101
:
064h
065h
:
0
0
:
0
0
:
1
1
:
1
1
:
0
0
:
0
0
:
1
1
:
0
0
:
0
1
:
2000
:
200
:
0C8h
:
0
:
1
:
1
:
0
:
0
:
1
:
0
:
0
:
0
:
3000
:
300
:
12Ch
:
1
:
0
:
0
:
1
:
0
:
1
:
1
:
0
:
0
:
3390
3400
339
340
153h
154h
1
1
0
0
1
1
0
0
1
1
0
0
0
1
1
0
1
0
44/51
FEDL7033-02
ML7033
1
Semiconductor
CR16 (CH2 tone generator 1 control1)
B7
B6
B5
B4
CH2TG1
LV3
B3
CH2TG1
LV2
B2
CH2TG1
LV1
B1
CH2TG1
LV0
B0
CH2TG1 _8
0
CH2TG1
LV6
CH2TG1
LV5
CH2TG1
LV4
CR16
default
0
0
0
0
0
0
0
CR17 (CH2 tone generator 1 control2)
B7 B6 B5
B4
B3
B2
B1
B0
CR17
CH2TG1 _7 CH2TG1 _6 CH2TG1 _5 CH2TG1 _4 CH2TG1 _3 CH2TG1 _2 CH2TG1 _1 CH2TG1 _0
default
0
0
0
0
0
0
0
0
CR16-B7 to B1 … CH2 TG1 output level setting
This 7-bit field defines the output level of tone generator 1 on channel 2. The output level
ranges from –12.1 to +0.5 dBm0 in 0.1 dBm0 intervals as shown in Table 19. A value of 0
in this field disables the tone generator.
The output level is calculated using the following formula.
Binary data for CR16- B7 to B1
= [(Output Level [dBm0]) + 12.2]*10
The following example shows how to program this field when the intended output level is –
5.8 dBm0;
Ex) [(Output Level [dBm0]) + 12.2]*10 = (–5.8 + 12.2)*10 = 64d = 1000000b
Bits to set in CR9-B7 to B1 = (1,0,0,0,0,0,0)
Table 19 Tone Generator 1 Level Setting
B7
B6
B5
TG1LV4
B4
TG1LV3
B3
TG1LV2
B2
TG1LV1
B1
TG1LV0
Level
(dBm0)
TG1LV6 TG1LV5
0
0
0
0
0
:
0
0
0
0
0
:
0
0
0
0
0
:
0
0
0
0
0
:
0
0
0
0
1
:
0
0
1
1
0
:
0
1
0
1
0
:
OFF
–12.1
–12.0
–11.9
–11.8
:
0
1
1
:
1
0
0
:
1
0
0
:
1
0
0
:
1
0
0
:
1
0
0
:
1
0
1
:
–5.9
–5.8
–5.7
:
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
0
0
1
0
1
0
1
0
0.0
0.1
0.2
0.3
0.4
0.5
(= 1.25 Vop)
1
1
1
1
1
1
1
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CR16-B0, CR17-B7 to B0 … CH2 TG1 frequency select
When the CH2RING (CR11-B7) bit is cleared, this 9-bit field is valid and determines the
output frequency from tone generator 1 on channel 2. The frequency range is between 300
and 3400 Hz at 10 Hz intervals as shown in Table 20.
The output level is calculated using the following formula.
Binary data for CR16-B0, CR17-B7 to B0
= (Output Frequency [Hz])/10
The following is an example of how to program this register field when the intended
frequency is 1500 Hz;
Ex) (Output Frequency [Hz]) / 10 = 1500/10 = 150d = 10010110b
Bits to set in CR16-B0, CR17-B7 to B0 = (0,1,0,0,1,0,1,1,0)
Note that the operations are not guaranteed when these bits define a frequency out of a band
between 300 and 3400 Hz.
Table 20 Tone Generator Frequency Setting (CH2RING bit = “0”)
CR16
CR17
B4
1
1
0
:
Frequency
(Hz)
decimal
hex
B0
0
0
0
:
B7
0
0
0
:
B6
0
0
0
:
B5
0
0
1
:
B3
1
1
0
:
B2
1
1
0
:
B1
1
1
0
:
B0
0
1
0
:
300
310
320
:
30
31
32
:
01Eh
01Fh
020h
:
400
410
:
40
41
:
028h
029h
:
0
0
:
0
0
:
0
0
:
1
1
:
0
0
:
1
1
:
0
0
:
0
0
:
0
1
:
1000
1010
:
100
101
:
064h
065h
:
0
0
:
0
0
:
1
1
:
1
1
:
0
0
:
0
0
:
1
1
:
0
0
:
0
1
:
2000
:
200
:
0C8h
:
0
:
1
:
1
:
0
:
0
:
1
:
0
:
0
:
0
:
3000
:
300
:
12Ch
:
1
:
0
:
0
:
1
:
0
:
1
:
1
:
0
:
0
:
3390
3400
339
340
153h
154h
1
1
0
0
1
1
0
0
1
1
0
0
0
1
1
0
1
0
When the CH2RING (CR11-B7) bit is set, the setting of the CH2TG1_8 (CR16-B0) bit and
the CH2TG1_7 to CH2TG1_6 (CR16-B7 to B6) bits are ignored, and the CH2TG1_5 to
CH2TG1_0 (CR16-B5 to B0) field defines the ringing tone frequency.
When the CH2RING (CR11-B7) bit is set, the frequency range is between 15 and 50 at 1
Hz intervals as shown in Table 21.
The output frequency is calculated using the following formula.
Binary data for CR17-B5 to B0
= (Output Frequency [Hz])
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The following example shows how to program this register field when the intended
frequency is 20 Hz;
Ex) Output Frequency [Hz] = 20d = 010100b
Bits to set in CR17-B5 to B0 = (0,1,0,1,0,0)
Note that the operations are not guaranteed when these bits define a frequency out of a band
between 15 and 50 Hz.
Table 21 Tone Generator Frequency Setting (CH2RING bit = “1”)
CR16
B0
—
—
—
—
—
—
:
CR17
B4
Frequency
(Hz)
decimal
hex
B7
—
—
—
—
—
—
:
B6
—
—
—
—
—
—
:
B5
0
0
0
0
0
0
:
B3
1
0
0
0
0
0
:
B2
1
0
0
0
0
1
:
B1
1
0
0
1
1
0
:
B0
1
0
1
0
1
0
:
15
16
17
18
19
20
:
15
16
17
18
19
20
:
0Fh
10h
11h
12h
13h
14h
:
0
1
1
1
1
1
:
48
49
50
48
49
50
30h
31h
32h
—
—
—
—
—
—
—
—
—
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
0
1
0
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CR18 (Test control)
B7
B6
CH2
LOOP0
B5
CH1
LOOP1
B4
CH1
LOOP0
B3
TEST3
0
B2
TEST2
0
B1
TEST1
0
B0
TEST0
0
CH2
LOOP1
CR18
default
B7, B6
0
0
0
0
… CH2 loop-back test mode select
(B7, B6):
(0, 0) = Loop-back OFF
(0, 1) = Loop-back OFF
(1, 0) = Channel 2 digital loop-back test. PCM data output on the PCMOUT pin during
normal operation is internally looped back through the Receive path via the
PCMIN pin. In digital loop-back test mode, input data on PCMIN pin is ignored,
but PCM data continues to be output on the PCMOUT pin.
(1, 1) = Channel 2 analog loop-back test. Analog signals output on the AOUT2P pin (or the
AOUT2P and AOUT2N pins) are internally looped back to the transmit path
behind a built-in feedback amplifier located after the AIN2P, AIN2N and GSX2
pins. In this mode, the AIN2P and AIN2N input pins are ignored. However, analog
signals continue to be output on the AOUT2P pin (or the AOUT2P and the
AOUT2N pins).
A loop-back test is functional only if XSYNC and RSYNC are from the same clock source.
B5, B4
… CH1 loop-back test mode select
(B5, B4):
(0, 0) = Loop-back OFF
(0, 1) = Loop-back OFF
(1, 0) = Channel 1 digital loop-back test. PCM data is output on the PCMOUT pin in
normal operation is internally looped back through the Receive path via the
PCMIN pin. In loop-back test mode, input data on PCMIN pin is ignored. However,
PCM data can be output on the PCMOUT pin.
(1, 1) = Channel 1 analog loop-back test. Analog signals output on the AOUT1P pin (or
from the AOUT1P and the AOUT1N pins) are internally looped back to the
transmit path via a built-in feedback amplifier located after the AIN1P, AIN1N and
GSX1 pins. In this mode, the AIN1P and AIN1N input pins are ignored. However,
analog signals can be output from the AOUT1P pin (or from the AOUT1P and the
AOUT1N pins).
A loop-back test is functional if XSYNC and RSYNC are from the same clock source.
B3 to B0
… LSI test registers for an LSI manufacturer
The default alternation is prohibited. When a write action is executed for CR18, set all of
these bits to “0”.
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CR19 (LSI manufacturer’s test control)
B7
TEST11
0
B6
TEST10
0
B5
TEST9
0
B4
TEST8
0
B3
TEST7
0
B2
TEST6
0
B1
TEST5
0
B0
TEST4
0
CR19
default
B7 to B0
… LSI test registers for an LSI manufacturer
For manufacturing use only. Both reads and writes to this register are prohibited.
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PACKAGE DIMENSIONS
(Unit: mm)
QFP64-P-1414-0.80-BK
Mirror finish
Package material
Lead frame material
Pin treatment
Package weight (g)
Rev. No./Last Revised
Epoxy resin
42 alloy
Solder plating (J5µm)
0.87 TYP.
6/Feb. 23, 2001
5
Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow mounting and humidity
absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product
name, package name, pin number, package code and desired mounting conditions (reflow method,
temperature and times).
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NOTICE
1. The information contained herein can change without notice owing to product and/or technical
improvements. Before using the product, please make sure that the information being referred to is up-to-
date.
2. The outline of action and examples for application circuits described herein have been chosen as an
explanation for the standard action and performance of the product. When planning to use the product,
please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs.
3. When designing your product, please use our product below the specified maximum ratings and within the
specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating
temperature.
4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation
resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or
unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the
specified maximum ratings or operation outside the specified operating range.
5. Neither indemnity against nor license of a third party’s industrial and intellectual property right, etc. is
granted by us in connection with the use of the product and/or the information and drawings contained
herein. No responsibility is assumed by us for any infringement of a third party’s right which may result
from the use thereof.
6. The products listed in this document are intended for use in general electronics equipment for commercial
applications (e.g., office automation, communication equipment, measurement equipment, consumer
electronics, etc.). These products are not authorized for use in any system or application that requires
special or enhanced quality and reliability characteristics nor in any system or application where the failure
of such system or application may result in the loss or damage of property, or death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety devices,
aerospace equipment, nuclear power control, medical equipment, and life-support systems.
7. Certain products in this document may need government approval before they can be exported to particular
countries. The purchaser assumes the responsibility of determining the legality of export of these products
and will take appropriate and necessary steps at their own expense for these.
8. No part of the contents contained herein may be reprinted or reproduced without our prior permission.
Copyright 2001 Oki Electric Industry Co., Ltd.
51/51
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