ML7050LA [OKI]
Bluetooth RF Transceiver IC; 蓝牙RF收发器IC
| 型号： | ML7050LA |
| 厂家： | 
OKI ELECTRONIC COMPONETS |
| 描述： | Bluetooth RF Transceiver IC |
| 文件： | 总16页 (文件大小：134K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FEDL7050LA-02
This version: June 2001
Previousꢀversion: Sep. 2000
1
Semiconductor
ML7050LA
Bluetooth RF Transceiver IC
GENERAL DESCRIPTION
The Oki ML7050LA is a highly integrated BluetoothTM radio transceiver designed to operate in the global 2.4 GHz
Industrial, Scientific, and Medical (ISM) band. The ML7050LA architecture incorporates vital intermediate frequency
(IF) and radio frequency (RF) circuits on a low cost, integration-friendly bulk CMOS process.
Bluetooth technology directly supports short range, wireless voice and data communications with 1 Mbps throughput
performance in the public ISM band across many applications, employing rapid frequency hopping (1.6K hops/s)
spread spectrum (FHSS) approach. The ML7050LA highly integrated CMOS Bluetooth RF transceiver LSI will
establish a 2.4 to 2.5 GHz communication link compliant with Bluetooth Specification Version 1.1 and is packaged in
the Oki 48-pin ball grid array (BGA) package requires only 7 mm x 7 mm of the systems critical board space.
Oki’s Bluetooth LSI family includes baseband LSI (ML70511LA), System Development Kit (BT-SDK), firmware and
software (BTS Pack1/2/3). Together, the RF LSI (ML7050LA) and baseband (ML70511LA) devices form a complete
hardware solution optimized for low system cost, small form factor, and reduced power consumption Bluetooth
applications.
FEATURES
• Circuit design based on the Bluetooth Specification Version 1.1.
• CMOS process technology lowers system cost and simplifies future baseband integration
• Fully integrated CMOS RF LSI: TX/RX switch, power amplifier, LNA, image rejection mixer, VCO, PLL, gm-
C IF filter, modulator, and demodulator.
• Low IF circuitry eliminates off-chip SAW filter reducing bill-of-material (BOM)
• Class 2 power operation compliant covering a wide range of applications
• Seamless interface with Oki’s ML70511LA Bluetooth baseband controller LSI
• Power supply voltage: 2.7 to 3.3 V
• Package: 48-pin BGA (7 mm x 7 mm x 1.41mm)
BLUETOOTH is a trademark owned by Bluetooth SIG, Inc. and licensed to Oki Electric Industry.
The information contained herein can change without notice owing to the product being under development.
1/16
FEDL7050LA-02
1
Oki Semiconductor
ML7050LA
BLOCK DIAGRAM
LIM_C1
LPF_C
DEMOD
LIM_C2
Tune_C
IF BPF
Limiting
AMP
LNA
IRM
RXD
Gm-C
Tuning
(SW Control)
TX_POW
RX_POW
PLL_POW
SW
PA
RF_Ant
PLL
Loop Filter
PLL_CLK
PLL_DATA
PLL_LE
PLL_OFF
Vdd_PA
Vdd_VCO
Vdd_PLL
Vdd_IF
Gaussian
Filter
VCO
AMP
SW
TXD
Vdd_IRM_LO
Vdd_IRM
GND_D Vdd_D
PLL_LF2 PLL_LF1
MCLK
GND Vdd_LNA
ABSOLUTE MAXIMUM RATINGS
Parameter
Power supply voltage
Input voltage
Allowable power dissipation
Storage temperature
Input RF Power
Symbol
VDD
VI
PD
TSTG
Conditions
Ta = 25°C
Rating
–0.3 to 4.5
–0.3 to VDD +0.3
0.5
–55 to +150
TBD
Unit
V
V
W
°C
-
-
In-Band
Out-of-Band
dBm
dBm
-
TBD
RECOMMENDED OPERATING CONDITIONS
Parameter
Power supply voltage
Full specification range
Operating temperature range
Symbol
VDD
Ta
Conditions
Min.
2.7
0
Typ.
3.0
-
-
Max.
3.3
55
Unit
V
-
-
-
Ta
–20
+85
°C
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FEDL7050LA-02
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Oki Semiconductor
ML7050LA
ELECTRICAL CHARACTERISTICS
(VDD = 3.0V, Ta = 0 to +55°C)
Symbol
Description
Conditions
Min.
Typ.
Max.
Unit
Digital Inputs
Vih
Vil
Digital input high
Digital input low
2.4
-0.3
VDD+0.3
0.4
V
V
Digital Outputs
Voh
Vol
Digital output high
Digital output low
Ioh=-2mA
Iol=2mA
2.2
0
3.6
0.8
V
V
Clock
MCLK
Master clock frequency
-
12.13,
16
-
MHz
Current Consumption Ta=25°C
IDDO
Receive Mode
Transmit Mode
PLL Mode
-
-
-
-
55
34
22
10
-
-
-
-
mA
mA
mA
uA
TX and RX disabled
VDD applied and power
control pins disabled
IDDS
Standby Mode
Receiver
FRF
RF Frequency
Reception sensitivity
2.4
2.5
GHz
dBm
RIN
Includes ANT BPF loss,
Note 1
–75
–20
-
-
Maximum Received Signal
Spurious level
dBm
dBm
dBm
30 MHz to 1 GHz
1 GHz to 12.75 GHz
–57
–47
-
-
ZIN
Input VSWR
RF Input impedance
-
2:1
50
SW in
Ω
Transmitter
fRF
PO
—
fstab1
fstab2
fstab3
RF Frequency
RF Output power
Carrier frequency tolerance initial accuracy (static)
Frequency drift(1 slot packet)
Frequency drift(3 slot packet)
Frequency drift(5 slot packet)
Maximum frequency drift
rate
2.4
0
-75
-25
-40
-40
2.5
4
GHz
dBm
KHz
KHz
KHz
KHz
Hz/µs
fRF = 2.4 to 2.5 GHz,
2
75
25
40
40
400
—
—
Power stability
Modulation index
over temp
TBD
0.35
–20
–20
–40
dBm
-
dBm
dBm
dBm
0.28
±500 kHz
Offset = 2 MHz
Offset > 3 MHz
—
In-band spurious level
3/16
FEDL7050LA-02
1
Oki Semiconductor
ML7050LA
30 MHz to 1 GHz
–36
dBm
dBm
dBm
dBm
1 GHz to 12.75 GHz
1.8 GHz to 1.9 GHz
5.15 GHz to 5.3 GHz
–30
–47
–47
-
—
Out-of-band spurious level
—
Output VSWR
-
-
2:1
50
ZOUT
RF Output impedance
SW out
Ω
PLL
@550 kHz
@2 MHz
–103
–120
-
dBc/Hz
dBc/Hz
µs
—
—
Phase noise
PLL lock-up time
150
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FEDL7050LA-02
1
Oki Semiconductor
ML7050LA
PIN LAYOUT (TOP VIEW)
A1 ball
corner
1
2
3
4
5
6
7
8
Vdd_
LNA
Vdd_
IRM
Vdd_
PLL_
POW
Gnd
Test3
Test4
TXD
IRM_LO
A
B
C
D
E
F
RF_Ant
Gnd
Gnd
Gnd
RX_POW Gnd
Gnd TX_POW
Test1
Test2
Lim_C1 Lim_C2
Vdd_PA
Test7
Test8
Gnd
Tune_C
Test6
Vdd_
VCO
Vdd_IF
Test5
Gnd
Gnd
Gnd
LPF_C
PLL_
LF1
PLL_
PLL_
OFF
MCLK
GND
RXD
Test9
Gnd_D
Vdd_IF
CLK
G
H
PLL_
LF2
Vdd_
PLL
PLL_
PLL_LE
Test10
Vdd_D
DATA
TOP VIEW
5/16
FEDL7050LA-02
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Oki Semiconductor
ML7050LA
PIN DESCRIPTION
Pins for RF Function
No.
Pin Name
I/O
Description
B1
RF_Ant
I/O
RF connection to external BPF (antenna filter)
Gm-C tuning components - Connect capacitors and resister between D8
and GND
D8
Tune_C
I
C7
C8
F8
Lim_C1
Lim_C2
LPF_C
I
I
Limiting amplifier capacitors - Connect capacitors between pins and GND
Low pass filter (LPF) capacitor - Connect capacitor between F8 and GND
External components for loop filter tuning:
PLL_LF1 - Connect to VCO
PLL_LF2 - Connect to PLL
G1
H1
PLL_LF1
PLL_LF2
—
Pins for TEST Interface, etc.
G4
B7
B8
A5
A6
F1
E8
MCLK
Test1
Test2
Test3
Test4
Test5
Test6
I
I/O
I/O
I
I
O
O
Master clock (12MHz, 13MHz or 16MHz) - CMOS level
Test pins - Connect to GND
No connect - Open
No connect - Open
D2
E2
Test7
Test8
O
Test pins - Connect to GND
G6
H8
Test9
Test10
O
I/O
No connect - Open
No connect - Open
Pins for Power Supply and Ground
H6
G7
D1
E1
A2
H2
A3
Vdd_D
GND_D
—
—
Power supply (VDD)- Digital; 3.0V+/-0.3V (from regulated voltage source)
Common Ground - Digital
Vdd_PA
Vdd_VCO
Vdd_LNA
Vdd_PLL
Vdd_IRM
Power supply (VDD) - Analog; 3.0V+/-0.3V
(from regulated voltage source)
—
—
A4
Vdd_IRM_LO
E7, H7 Vdd_IF
A1/B2
B4/B5
C1/C2
GND
Common ground (GND) - Analog
D7/F2
F7/G2
G5
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FEDL7050LA-02
1
Oki Semiconductor
ML7050LA
Pins for the Interface Between the RF LSI and the Baseband LSI
No.
A8
H5
H3
G3
Pin Name
I/O
Description
TXD
RXD
PLL_DATA
PLL_CLK
I
O
I
Transmit (TX) data - CMOS level
Receive (RX) data - CMOS level
PLL setup data: 6 Mbps <= PLL DATA <= 10 Mbps
PLL clock setup: 6 MHz <= PLL CLK <= 10 MHz
PLL load enable setup:
I
H4
G8
A7
B6
B3
PLL_LE
I
I
I
I
I
Data latched : ‘High’
100 nsec <= PLL LE
PLL Open-loop/Closed-loop mode control:
Closed loop mode (receive): ‘High’
Open loop mode (transmit) : ‘Low’
PLL power supply control switch:
PLL Power ON : ‘Low’
PLL_OFF
PLL_POW
TX_POW
RX_POW
PLL Power OFF :’ High’
Transmitter (TX) power supply control switch:
TX ON (transmit) : ‘Low ‘
TX OFF(receive) : ‘High’
Receiver (RX) power supply control switch:
RX ON (receive) : ‘Low’
RX OFF (transmit) : ‘High’
Modes of Operation
By setting or transitioning control pins, the device will enter into various modes of operation including receive,
transmit, and standby.
Mode
PLL_POW
TX_POW
RX_POW
Receive
Transmit
PLL
Standby
0
1
0
0
0
1
0
1
1
1
1
1
7/16
FEDL7050LA-02
1
Oki Semiconductor
ML7050LA
PIN CONNECTION DIAGRAM
Tune_C
10 nF
Lim_C1 Lim_C2
33 nF
1 nF
3 kΩ
LPF_C
0.1 µF
33 nF
33 nF
Limiting
AMP
IF BPF
LNA
IRM
DEMOD
RXD
Gm-C
Tuning
TX_POW
RX_POW
PLL_POW
BPF
RF_Ant
SW
(for Ant)
PLL
PLL_CLK
PLL_DATA
PLL_LE
GND
Loop Filter
VCO
PLL_OFF
0.1 µF
for
Gaussian
Filter
AMP
PA
SW
(for Local)
each
TXD
Vdd_PA
Vdd_VCO
Vdd_PLL
MCLK
0.1µF
0.1 µF
100 pF
Vdd_LNA
Vdd_IRM_LO
Vdd_IRM
66kΩ
33kΩ
470pF
PLL_LF2
12MHz,
13MHz
100 pF
~
47pF
NM
or 16MHz
Vdd_D
PLL_LF1
GND_D
GND
Vdd_IF
The externally connected components shown are tentative (April 2001).
* The circuit is subject to change according to the specific board design.
Please contact Oki Electric Industry Co., Ltd. for detailed information.
The ML7050LA provides a low bill-of-material (BOM) Bluetooth solution by minimizing external components. The
design incorporates numerous internal tuning circuits using Gm-C and other leading-edge technologies to reliably
control phase lock loop (PLL), VCO, amplifiers, modulator, and demodulator circuits. The TX-POW, RX_POW,
PLL_POW, PLL-CLK, PLL_DATA, PLL_LE, PLL_OFF, RXD, and TXD connect directly to the complementary
Bluetooth baseband (ML70511LA) device.
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FEDL7050LA-02
1
Oki Semiconductor
ML7050LA
DESCRIPTION OF INTERNAL BLOCKS
• Transmit filter (Gaussian filter):
The input data is converted into a frequency modulation signal by a filter with Gaussian characteristics and is sent
to the VCO.
• Frequency control section (VCO, PLL, Loop Filter, AMP and SW):
Generates a frequency in the 2.4 GHz to 2.5 GHz band (ISM band). During transmission, the VCO oscillator
frequency is modulated by the modulation signal output by the Gaussian filter. The PLL frequency is controlled
by the signals PLL_DATA, PLL_CLK, and PLL_LE. The switch SW (for Local) distributes the oscillator output
to the transmitter circuit and the receiver circuit depending on the control signal (TX_POW/RX_POW).
• Power amplifier (PA):
This is the power amplifier for the transmitter.
• Transmit/Receive selection switch (SW for Ant)
Depending on the control signal (TX_POW/RX_POW), this switch feeds the output of the power amplifier to the
antenna during transmission. During reception, the received signal of the antenna is fed to the LNA.
• Reception amplifier (LNA):
This amplifies the weak RF received signal from the antenna.
• Image Rejection Mixer (IRM):
Converts the output signal from the LNA (2.4 to 2.5 GHz) into an intermediate frequency and also eliminates the
image frequency component.
• IF Band pass filter (IF BPF):
Removes the signal of the nearby bands.
• Limiting amplifier:
Amplifies the signal converted into the intermediate frequency up to a specific amplitude.
• Demodulator (DEMOD):
The received signal is demodulated using the delay detector circuit.
• Filter tuning (Gm-C Tuning):
The reference clock is compared with the oscillator frequency inside the tuning circuit, and the frequency
characteristics of the Gm-C filter is adjusted automatically.
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FEDL7050LA-02
1
Oki Semiconductor
ML7050LA
PLL METHODOLOGY
Reference
crystal
To
oscillator
Mixer
Charge
pump
And
Phase
Frequency
Detector
To
Programmable
Divider
LC
PA
Switch
Buffer
Tank
VCO
Loop
Filter
Programmable
Counter
Pre-
scaler
Data
Clock
LE
Swallow
Counter
10/16
FEDL7050LA-02
1
Oki Semiconductor
ML7050LA
PLL Computation Method
Fvco
Fosc
R
(0 <= A<=31)
MxN+A
(M × N + A denotes (M - A) × 32 + A × 33)
R: Reference counter set value
N: Programmable counter set value
A: Swallow counter set value
PLL Reference Counter
Freq
(MHz) (Dec)
R
R(Bin)
R2
R4
R3
R1
R0
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Programmable Counter and Swallow Counter
F.step
M
1 MHz
32 div
(RX PLL Frequency) = (TX PLL Frequency) – 2MHz
* In receive mode, PLL generates local frequency for IRM. Intermediate frequency is 2MHz.
Freq.
N
A
N(Bin)
A(Bin)
(MHz)
(Dec)
(Dec)
N6 N5 N4 N3 N2 N1 N0 A4 A3 A2 A1 A0
2397
74
74
74
75
75
29
30
31
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
0
0
0
1
1
1
1
1
0
0
1
1
1
0
0
1
1
1
0
0
0
1
1
0
0
1
0
1
0
1
2398
2399
2400
2401
1
11/16
FEDL7050LA-02
1
Oki Semiconductor
ML7050LA
2402
:
:
75
:
:
2
1
:
:
0
:
:
0
:
:
1
:
:
0
:
:
1
:
:
1
:
:
0
:
:
0
:
:
0
:
:
1
:
:
0
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
2496
2497
2498
2499
2500
78
78
78
78
78
0
1
2
3
4
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
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FEDL7050LA-02
1
Oki Semiconductor
ML7050LA
PLL Set-up Time Chart
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
CLK
DATA
CTL R4 R3 R2 R1 R0
MSB
CTL N6 N5 N4 N3 N2 N1 N0 A4 A3 A2 A1 A0
LSB
LE
Reference counter setting duration
Programmable counter and swallow counter setting duration
R4 to R0: Binary 5-bit reference counter (5-20)
N6 to N0: Programmable counter (7 bits)
See "PLL Setting method”.
A4 to A0: Swallow counter (0-31) (5 bits)
See "PLL Setting method”.
CTL:
When CTL is "H", the input data is handed over to the reference counter register.
When CTL is "L", the input data is handed over to the programmable and swallow counter register.
Note: Start data input from the MSB.
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FEDL7050LA-02
1
Oki Semiconductor
ML7050LA
SYSTEM OVERVIEW
VDD
ML7050LA
GND
VDD
Antenna
2.4 to 2.5 GHz
Host
Control
Signal
System
~
~
~
ML70511LA
Band-pass
Filter
USB
USB
or
UART
TXD
RXD
or
UART
GND
OSC
Together, RF (ML7050LA) and baseband (ML70511LA) devices form a complete hardware solution optimized for
low system cost, small form factor, and reduced power consumption wireless applications. The ML70511LA
baseband IC controls the ML7050LA frequency selection, tuning characteristics, and control functions through writing
to internal registers. ML7050LA can then read-back the register information to ML70511LA insuring proper modes of
operation. The communication between the devices occurs on Oki’s proprietary, low pin count serial interface. The
connection between a host controller or processor and the baseband device is implemented via USB (version 1.1) or
UART.
Power Supply
The analog power supply (VDD) voltage is connected to pins serving each analog functional blocks (Vdd_PA,
Vdd_LNA, Vdd_VCO, Vdd_PLL, Vdd_IF, Vdd_IRM and Vdd_IRM_LO). A separate digital power supply voltage is
required by the digital section. Each of the analog power supply voltage should be supplied from regulated voltage
source and should be low-frequency de-coupled by external blocking capacitors.
Ground
In order to minimize electrical noise and other interference, the ground plane should be distributed with low impedance
characteristics including underneath the ML7050LA. Connect all GND pins to the ground plane.
14/16
FEDL7050LA-02
1
Oki Semiconductor
ML7050LA
PACKAGE DIMENSIONS (48-PIN BGA)
(Unit: mm)
0.70 REF
0.80 NON ACUMULATIVE
7.0
Index Mark
0.50 TYP
0.70 REF
7.0
1.41 TYP
0.40 REF
15/16
FEDL7050LA-02
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Oki Semiconductor
ML7050LA
NOTICE
1. The information contained herein can change without notice owing to product and/or technical improvements.
Before using the product, please make sure that the information being referred to is up-to-date.
2. The outline of action and examples for application circuits described herein have been chosen as an explanation
for the standard action and performance of the product. When planning to use the product, please ensure that the
external conditions are reflected in the actual circuit, assembly, and program designs.
3. When designing your product, please use our product below the specified maximum ratings and within the
specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating
temperature.
4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting
from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical
or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or
operation outside the specified operating range.
5. Neither indemnity against nor license of a third party’s industrial and intellectual property right, etc. is granted by
us in connection with the use of the product and/or the information and drawings contained herein. No
responsibility is assumed by us for any infringement of a third party’s right which may result from the use thereof.
6. The products listed in this document are intended for use in general electronics equipment for commercial
applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics,
etc.). These products are not authorized for use in any system or application that requires special or enhanced
quality and reliability characteristics nor in any system or application where the failure of such system or
application may result in the loss or damage of property, or death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace
equipment, nuclear power control, medical equipment, and life-support systems.
7. Certain products in this document may need government approval before they can be exported to particular
countries. The purchaser assumes the responsibility of determining the legality of export of these products and
will take appropriate and necessary steps at their own expense for these.
8. No part of the contents contained herein may be reprinted or reproduced without our prior permission.
Copyright 2001 Oki Electric Industry Co., Ltd.
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