ML7055 [OKI]
Bluetooth Baseband Controller IC; 蓝牙基带控制器IC
| 型号： | ML7055 |
| 厂家： | 
OKI ELECTRONIC COMPONETS |
| 描述： | Bluetooth Baseband Controller IC |
| 文件： | 总30页 (文件大小：342K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FEDL7055-02
Issue Date: Apr. 8, 2003
OKI Semiconductor
ML7055
Bluetooth Baseband Controller IC
GENERAL DESCRIPTION
The ML7055 is a CMOS digital IC for use in 2.4 GHz band Bluetooth™ systems. This IC incorporates the
ARM7TDMI as the CPU core, features a highly expandable architecture, and supports the interfaces for a variety
of applications. Since the ML7055 has Oki’s Bluetooth protocol stack software installed, when the IC is used in
conjunction with the Bluetooth RF transceiver IC, data/voice communications are possible while maintaining
interconnectivity with other Bluetooth systems.
FEATURES
•
•
Conforms to Bluetooth Specification (Ver1.1)
Designed for connection with the RF-LSI interface, such as the OKI RF-LSI interface (ML7050), the
SKYWORKS RF-LSI interface (CX72303), or the BROADCOM RF-LSI interface (BCM2002X) that
functions as the Bluetooth RF-LSI interface
The high-speed, low-power ARM7TDMITM is installed as the CPU core
•
•
•
•
PCM-CVSD transcoder that provides high quality voice using the noise filter is installed
Low power consumption in flexible power management modes according to operating modes of Bluetooth
DETACH signal provides control of change to power-saving mode (STOP) and return request to normal
mode.
•
•
•
UART interface corresponding to baud rates up to 921.6 kbps
I2C bus interface provides accesses to EEPROM or PCM-Codec
Selactable 12 MHz or 13 MHz for the system clock
•
•
•
Selectable 32 kHz or 32.768 kHz for the LPO clock
Built-in programmed ROM eliminates external ROM/FLASH
The packages are available in three types:
63-pin WCSP for ML7055HB
64-pin BGA for ML7055LA
84-pin BGA for ML7055LP
ARM, ARM7TDMI and Thumb are registered trademarks of ARM Ltd., UK.
BLUETOOTH is a trademark owned by Bluetooth SIG, Inc. and licensed to Oki Electric Industry.
The information contained herein can change without notice owing to the product being under development.
1/30
FEDL7055-02
OKI Semiconductor
ML7055
SPECIFICATIONS
Process
Package
0.16 µm CMOS (5-layer metal wire)
63-pin WCSP (P-VFLGA63-4.90×4.72-0.50-W)
(Dimensions: 4.90 mm × 4.72 mm × 0.48 mm; pin pitch: 0.50 mm)
64-pin BGA (P-TFBGA64-0707-0.65)
(Dimensions: 7 mm × 7 mm × 1.2 mm; pin pitch: 0.65 mm)
84-pin BGA (P-LFBGA84-0909-0.80)
(Dimensions: 9 mm × 9 mm × 1.5 mm; pin pitch: 0.80 mm)
22 mA (24 MHz operation)
Supply current
Operating voltage ranges
2.70 to 3.6 V for input-output, 1.65 to 1.95 V for internal circuits
24 MHz
Operating frequency
Built-in ROM size
Built-in RAM size
Input clocks
176 KB (for ARM program)
24 KB
12 MHz or 13 MHz (system clock)
32 kHz or 32.768 kHz (LPO clock)
RF-LSI interface
OKI RF-LSI interface (ML7050)
SKYWORKS RF-LSI interface (CX72303)
BROADCOM RF-LSI interface (BCM2002X)
UART interface (up to 921.6 Kbps)
Installed interfaces
General-purpose I/O interface (used as a pin for I2C bus interface
depending on software installed)
PCM interface (PCM Linear/A-law/µ-law can be selected)
DETACH interface
Timers
16-bit auto reload timer (1ch)
18-bit auto reload timer (1ch)
Interrupt controller
Clock control circuit
11 causes
Crystal oscillator circuit (12 MHz or 13 MHz, 32 kHz or 32.768 kHz)
Internal PLL
2/30
FEDL7055-02
OKI Semiconductor
ML7055
PIN PLACEMENT
ML7055HB: 63-pin WCSP (P-VFLGA63-4.90 × 4.72-0.50-W)
RSSI_
GND
VDD
GND
Core
GND
GND
VDD
GND
LVDD
TX_POW
CLK
8
7
PLL
_POW
PLL_
DATA
PLL
_PS
SOUT VDD
GND
PLL
RX_
PLL
PCM
OUT
Core
VDD
GND
GND
TXD
POW _OFF _CLK
6
5
4
Core
VDD
PCM PCM
SYNC CLK
RSSI
PLL_LE
RXD
GND
SFRQ
SEL
PLL
LOCK
SCL
SDA
VDD
SIN RFSEL1
PCMIN
SCLK
SEL
XC32KN
XC32KP
RESET AGND0 RFSEL0
CLKOUT VDD
CTS
3
2
Core
AVDD1
AVDD0
RTS
Core
GND
AGND1
GND
VDD
VDD DETACH
GND
A
SCLKN SCLKP
GND VDD RFSEL2
1
C
D
E
H
B
F
G
TOP VIEW
3/30
FEDL7055-02
OKI Semiconductor
ML7055
ML055LA: 64-pin BGA (P-TFBGA64-0707-0.65)
Core
VDD
Core
VDD
SCLKN
GND
RFSEL2
AGND0
GND AGND1
RFSEL1
RESET
10
9
XC32KP
GND SCLKP
AVDD1 AVDD0
VDD
CTS
GND
SCL
RFSEL0 RTS
CLKOUT
DETACH
XC32KN VDD
8
7
SCLK
SEL
SFRQ
SEL
SDA
VDD
Core
VDD
PLL
LOCK
Core
VDD
6
5
4
PCMIN
RSSI
GND
RXD
TXD
GND
PCM
SYNC
PCM
CLK
Core
VDD
PLL_PS PLL_LE
PCMOUT
3
2
PLL_
DATA
RX_
TX_
LVDD
GND
VDD
GND
SIN
GND
GND
VDD
GND
POW POW
Core
VDD
PLL_
GND
CLK
PLL_ RSSI_
PLL_
POW
SOUT
GND
OFF
CLK
1
B
C
D
E
F
G
H
J
K
A
TOP VIEW
4/30
FEDL7055-02
OKI Semiconductor
ML7055
ML7055LP: 84-pin BGA (P-LFBGA84-0909-0.80)
Core
VDD
GND AVDD1
RFSEL2
RTS
AGND1
SCLKN
RFSEL0
NC
AVDD0 AGND0
RESET
10
9
XC32KP
AVDD1
AGND1 AGND0 GND
Core
GND
CTS
VDD
NC AVDD0
VDD
VDD XC32KN
SFRQ SCLK
SCLKP
GND CLKOUT
DETACH RFSEL1
8
7
NC
NC
SCL
NC
NC
SDA
VDD
SEL
SEL
Core
VDD
NC
NC
6
5
4
Core
VDD
PLL
PCMIN GND
PCM
RSSI
RXD
TXD
LOCK
PCM
SYNC
PCMCLK
GND
NC
OUT
Core
VDD
GND
NC
NC
GND
SIN
VDD
SOUT
NC
NC
GND
PLL_LE PLL_PS NC
3
2
PLL_
CLK
RX_ RSSI_
POW CLK
TX_
POW
GND
GND
VDD
GND
NC
PLL_
DATA
Core
VDD
PLL_ PLL_
POW OFF
LVDD
D
GND
GND
1
C
E
H
J
K
B
F
G
A
TOP VIEW
5/30
FEDL7055-02
OKI Semiconductor
ML7055
PIN DESCRIPTIONS
RF I/F
Internal
Pin Placement
Direc-
tion
[*0]
Pull Up/ Initial
Down, Value
Schmitt
Pin Name
Description
ML7055 ML7055 ML7055
HB
LA
LP
L
L
L
ML7050: Transmit data output
CX72303: Transmit data output
BCM2002X: Transmit data output
ML7050: Receive data input
CX72303: Receive data input
BCM2002X: Receive data input
ML7050: Serial write data
CX72303: Serial write data
BCM2002X: Transmit enable
ML7050: Serial clock
TXD
RXD
O
I
—
—
—
—
B4
B6
A4
—
—
—
X
H
L
L
L
L
B5
C2
D1
C5
C7
E6
A5
C1
D2
PLL_DATA
PLL_CLK
O
O
CX72303: Serial clock
BCM2002X: Serial clock
ML7050: Serial road enable
0: Negate, 1: Assert
CX72303: Serial enable
0: Assert, 1: Negate
L
H
L
PLL_LE
O
—
B3
D5
A3
BCM2002X: RF-LSI synthesizer on
0: Negate, 1: Assert
ML7050: Receive field strength data
input
CX72303: Serial read data
BCM2002X: Serial read data
ML7050: Receive field strength data
clock
CX72303: RF-LSI receiving
characteristic control
BCM2002X: System clock request
—
—
—
Pull
down
RSSI
I
A5
C1
B5
B8
C5
C2
L
L
RSSI_CLK
O
—
—
X
H
ML7050: Local PLL power control
0: Assert, 1: Negate
CX72303: PA Power control
0: Negate, 1: Assert
L
PLL_POW
O
A1
B7
A1
BCM2002X: Select serial transmit
mode
H
H
ML7050: Transmit enable
0: Assert, 1: Negate
TX_POW
RX_POW
O
O
—
—
B2
A2
CX72303: Transmit enable
0: Negate, 1: Assert
BCM2002X: Serial write data
A8
C6
A2
B2
L
L
ML7050: Receive enable
0: Assert, 1: Negate
CX72303: Receive enable
0: Negate, 1: Assert
H
L
L
L
BCM2002X: Receive enable
ML7050: ”L”
CX72303: Power on reset
0: Assert (reset) 1: Negate
X
PLL_PS
O
—
A7
A3
B3
BCM2002X: RF-LSI receiving
characteristic control
L
[*0] “I” = Input, “O” = Output, “I/O” = Input/Output
6/30
FEDL7055-02
OKI Semiconductor
ML7055
RF I/F
Internal
Pull Up/
Down,
Direc-
tion
[*0]
Pin Placement
Initial
Value
Description
Pin Name
ML7055 ML7055 ML7055
HB
LA
LP
Schmitt
—
—
—
ML7050: —
Pull
down
PLLLOCK
I
B4
B6
B5
CX72303: —
BCM2002X: 1MHz clock
ML7050: PLL loop control
0: Open loop 1: Closed loop
CX72303: Diversity output
BCM2002X: PA Power control
H
—
L
O
—
D6
B1
B1
PLL_OFF
PCM I/F
Internal
Pull Up/
Down,
Pin Placement
Direc-
tion
Initial
Value
Description
Pin Name
ML7055 ML7055 ML7055
Schmitt
HB
LA
LP
PCMOUT
PCMIN
O
I
—
L
G6
J3
J4
PCM data output
Pull up
—
H4
F5
J5
J4
H5
K4
PCM data input
PCM sync signal (8 kHz),
Initial setting: input
(can be switched by an internal
register)
Pull
down
PCMSYNC
PCMCLK
I/O
I/O
—
—
PCM clock (64 kHz/128 kHz)
Initial setting: input
(can be switched by an internal
register)
Pull
down
G5
K4
H4
Note: The PCM sync signal (8 kHz) must be guaranteed at the accuracy of ±50 ppm if the
PCMSYNC pin is configured as an input.
UART I/F
Internal
Pull Up/
Down,
Pin Placement
Direc-
tion
Initial
Value
Pin Name
Description
ML7055 ML7055 ML7055
Schmitt
HB
LA
LP
SOUT
SIN
O
I
—
Schmitt
—
H
—
—
H
E7
F1
F2
ACE transmit serial data
ACE receive serial data
ACE transmit data ready
ACE transmit ready
D4
G2
F3
G1
J9
G2
K9
J9
RTS
CTS
O
I
—
K9
7/30
FEDL7055-02
OKI Semiconductor
ML7055
CLK and Configuration
Internal
Pull Up/
Down,
Pin Placement
Direc-
tion
Initial
Value
Pin Name
Description
ML7055 ML7055 ML7055
HB
E1
D1
A2
A3
LA
LP
Schmitt
SCLKP
SCLKN
XC32KP
XC32KN
I
—
—
—
—
—
E9
F8
System clock (12/13 MHz) pins
(Power level: CMOS level)
O
I
—
E10
A9
F10
A9
—
Subclock pins (for oscillator)
O
—
A8
B8
System clock frequency select pin
Pull
down
L: Select CLK divided by
internal PLL
H: Select subclock
System clock frequency select pin
L: 13 MHz
SCLKSEL
SFRQSEL
I
I
—
—
B3
C4
A7
B7
B7
A7
Pull
down
H: 12 MHz
RF-LSI select pins
RFSEL[2:0]
001:
010:
101:
ML7050 (OKI)
CX72303 (SKYWORKS)
BCM2002X
RFSEL0–
2
I
—
—
[*1]
[*2]
[*3]
(BROADCOM)
Others: Unused
RESET
DETACH
SCL
I
I
Schmitt
Schmitt
—
—
—
L
C3
F2
G4
F4
F10
G9
K7
J7
G10
G8
H7
Hardware reset pin (Reset = L)
Sleep pin (Sleep = L)
I2C serial clock
O
I/O
I2C serial data
SDA
—
H
K7
System clock (12/13 MHz) output
pins
CLKOUT
O
—
—
G3
J8
K8
[*1] RFSEL0: E3; RFSEL1: E4; RFSEL2: H1
[*2] RFSEL0: H9; RFSEL1: H10; RFSEL2: K10
[*3] RFSEL0: H10; RFSEL1: H8; RFSEL2: K10
8/30
FEDL7055-02
OKI Semiconductor
ML7055
NC
Internal
Pull Up/
Down,
Pin Placement
Direc-
Pin Name
Initial
Value
Description
tion
ML7055 ML7055 ML7055
HB
LA
LP
Schmitt
NC
—
—
[*4]
No connection
[*4] B6, C3, C4, C6, C7, C8, D3, E1, F1, H2, H3, H6, H9, J6, J7
Note: Do not wire under the NC pin.
Power, GND
Internal
Pull Up/
Down,
Pin Placement
Direc-
tion
Initial
Value
Pin Name
Description
ML7055 ML7055 ML7055
HB
LA
LP
Schmitt
VDD
—
—
—
—
—
[*5]
[*6]
[*7]
I/O power supply pin 2.70 to 3.6 V
Power supply pin for internal circuit
1.65 to 1.95 V
CoreVDD
—
—
[*8]
C8
[*9]
D2
[*10]
D1
RF-I/O power suply pin (Same
voltage to the VDD for RF-LSI)
LVDD
GND
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
[*11]
B1
[*12]
C9
[*13]
[*14]
[*15]
[*16]
[*17]
Digital block ground pin
AVDD
0
1
Analog block power supply pin
1.65 to 1.95 V
AVDD
B2
B9
AGND0
AGND1
D3
C10
B10
Analog block ground pin
C2
[*5]
[*6]
[*7]
[*8]
[*9]
VDD: A4, E2, E8, H3, H8
V
V
DD: B8, F2, K1, J6, F9
DD: A8, F3, K1, K6, F9
Core VDD: A5, D2, F7, G1, H6
Core VDD: A6, H1, K3, K6, J10, D10
[*10] Core VDD: A6, G1, K3, K5, J10, E8
[*11] GND: A1, A6, C1, D7, D8, F1, F6, F8, G7, G8, H2, H5, H7
[*12] GND: A4, A10, D9, E1, E2, G2, G10, H2, J1, J2, K2, K5, K8
[*13] GND: A10, B4, E2, E3, E9, G3, G9, H1, J1, J2, J3, J5, J8, K2
[*14] AVDD0: D8, D10
[*15] AVDD1: B9, B10
[*16] AGND0: E10, D9
[*17] AGND1: C9, C10
9/30
FEDL7055-02
OKI Semiconductor
ML7055
BLOCK DIAGRAM
ML7055
DETACH
UART I/F
GPIO I/F
SCL
SDA
Clock
10/30
FEDL7055-02
OKI Semiconductor
ML7055
DESCRIPTION OF INTERNAL BLOCKS
CLKGEN Block
•
•
Generates a clock that is supplied to each block through SCLKP (12/13 MHz)
STOP/HALT function
CTL/WDT Block
•
•
•
•
•
Control of the frequency division function of the internal main clock
Control of clock supplied to each peripheral
Control of reset of each peripheral
STOP/HALT control
Watchdog timer function (interrupt/reset)
Timer Block
•
•
•
•
1 channel
18-bit timer counter
Interrupt by compare function
One shot, interval, or free-run mode
Base band Core Block
RF LSI
Tx SCO Buffer
Tx ACL Buffer
TXD
CNT
Packet
Composer
Codec
I/F
Audio
RF
FHCNT
Security
Timing
CNT
ARM
I/F
APB
Rx SCO Buffer
Rx ACL Buffer
Packet
Decomposer
RXD
•
•
RF Controller
- RF power supply control (PLL, TX, RX)
- Local PLL frequency division ratio setting
- Receive clock regeneration function
- Synchronization detection (synchronizing within the permissable error limit of SyncWord)
- Receive clock re-timing function
FH Controller hopping
- Sequence control
- Frequency hopping selection function
- CRC computation's initial value selection function
11/30
FEDL7055-02
OKI Semiconductor
ML7055
•
Timing Generator
- Bluetooth clock generation
- Operation interrupts depend on mode (slot, scan, sniff, hold, park)
- Sync detection timing generation (sync window ±10 µs)
- PLL setting timing generation
- Transmit/Receive timing generation
- Multi-master timing management function
•
•
Packet Composer
- Access code generation (SyncWord generation, appending PR*TRAILER)
- Packet header generation (HEC generation, scrambling, FEC encoding)
- Payload generation (CRC generation, encryption, scrambling, FEC encoding)
- Packet synthesis
Packet Decomposer
- Packet decomposition (separating the packet header and the payload)
- Packet header processing (FEC decoding, descrambling, HEC error detection, header information
separation)
- Payload processing (FEC decoding, descrambling, encryption decoding, CRC judgement, payload
separation)
•
Security
- Various key generation functions (initialization, link key, encryption key)
- Certification function
- Encryption function
12/30
FEDL7055-02
OKI Semiconductor
ML7055
UART Block
•
•
•
•
•
•
•
•
•
•
Full-duplex buffering method
All status reporting function
Built-in 64-byte transmit/receive FIFO
Modem control based on CTS
Programmable serial interface
5-, 6-, 7-, 8-bit characters
Generation and verification of odd parity, even parity, or no parity
1, 1.5, or 2 stop bits
Programmable Baud Rate Generator (9600 bps to 921.6 kbps)
Error servicing for parity, overrun, and framing errors
•
Configuration of 1 Data Frame during Reception
5 data bits to
SIN
SAMPLE CLK
Start
Stop
Parity
8 data bits
•
Configuration of 1 Data Frame during Transmission
5 data bits to
SOUT
Start
Stop
Parity
8 data bits
13/30
FEDL7055-02
OKI Semiconductor
ML7055
PCM-CVSD Transcoder Block
•
•
•
Application side I/O:
- PCM Codec
Application-side format:
- PCM linear (8, 14, 16 bits/sample, 8 kHz sampling frequency)/A-law/µ-law
Bluetooth-side format:
- CVSD/A-law/µ-law
•
•
All combinations of the above conversions are supported
PCMSYNC/PCMCLK I/O can be switched (initial setting: input)
•
Timing in Short Mode and in PCMCLK and PCMSYNC Output Mode
(For PCM data of 14 bits/sample, lower 2 bits of 16 bits are invalid.)
8 bits or 16 bits
PCMCLK(O)
64k/128kHz
PCMOUT
LSB
LSB
MSB
Data is output on the rising edge of CLK.
MSB DATA DATA
DATA
DATA
DATA
DATA
LSB
LSB
MSB
MSB
DATA
DATA
PCMIN
Data is shifted in on the falling edge of CLK
PCMSYNC(O)
125µs (8kHz)
•
Timing in Short Mode and in PCMCLK and PCMSYNC Input Mode.
(For PCM data of 14 bits/sample, lower 2 bits of 16 bits are invalid.)
8 bits or 16 bits
PCMCLK(I)
64k/128kHz
PCMOUT
LSB
LSB
MSB
Data is output on the rising edge of CLK.
MSB DATA DATA
DATA
DATA
DATA
DATA
LSB
LSB
MSB
MSB
DATA
DATA
PCMIN
Data is shifted in on the falling edge of CLK
PCMSYNC(I)
125µs (8kHz)
14/30
FEDL7055-02
OKI Semiconductor
ML7055
•
Timing in Long Mode and in PCMCLK and PCMSYNC Output mode
(For PCM data of 14 bits/sample, lower 2 bits of 16 bits are invalid.)
8 bits or 16 bits
PCMCLK(O)
64k/128kHz
MSB
MSB
DATA
DATA
DATA
DATA
LSB
MSB
MSB
DATA
DATA
PCMOUT
Data is shifted in on the falling edge of CLK
Data is output on the rising edge of CLK
DATA
DATA
DATA
DATA
LSB
PCMIN
PCMSYNC(O)
PCMCLK period × 3
125µs (8kHz)
•
Timing in Long Mode and in PCMCLK and PCMSYNC Input Mode.
(For PCM data of 14 bits/sample, lower 2 bits of 16 bits are invalid.)
8 bits or 16 bits
PCMCLK(I)
64k/128kHz
MSB
Data is output on the rising edge of CLK.
MSB DATA DATA DATA
DATA
DATA
DATA
DATA
LSB
MSB
MSB
DATA
DATA
PCMOUT
Data is shifted in on the falling edge of CLK.
DATA
LSB
PCMIN
≥ PCMCLK period (Min.) or ≤ 62.5 µs (Max.)
125µs (8kHz)
DETACH Interface Block
•
Generation of the request for change to (from) the stop mode by detection of the rising (falling) edge of
the DETACH signal
15/30
FEDL7055-02
OKI Semiconductor
ML7055
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Conditions
—
Rating
Unit
V
I/O power supply voltage
VDD/LVDD
–0.3 to +4.5
Core power supply voltage
Input voltage
CoreVDD/AVDD
—
—
—
—
–0.3 to +2.5
–0.3 to +4.5
0.62
V
V
VI
Pd
Allowable power dissipation
Storage temperature
W
°C
Tstg
–55 to 150
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
VDD/LVDD
CoreVDD/AVDD
Vih
Conditions
Min. Typ. Max.
Unit
V
I/O power supply voltage
Core power supply voltage
“H” level input voltage
“L” level input voltage
Operating temperature
—
—
—
—
—
2.7
1.65
2.2
0
3.3
1.8
—
3.6
1.95
VDD
0.8
V
V
Vil
—
V
Ta
–40
—
85
°C
ELECTRICAL CHARACTERISTICS
DC Characteristics
(VDD = 2.7 to 3.6 V, CoreVDD = 1.65 to 1.95 V, Ta = –40 to +85°C)
Parameter
Symbol
Conditions
Min. Typ. Max. Unit
“H” level output voltage
Ioh =
–2 mA
3.0V≤Vdd≤3.6V
2.7V≤Vdd<3.0V
Iol = 2 mA
2.4
2.2
—
—
—
—
—
—
—
Voh
V
V
“L” level output voltage
Input leakage current
Vol
0.4
10
Vi = GND to 3.6 V
Vi = VDD
–10
10
66
200
Ii
µA
µA
50 kΩ Pull-down
Vi = GND
–200 –66
–10
10
50 kΩ Pull-up
Vo = GND to VDD
Vo = VDD
–10
10
—
Output leakage current
Io
66
200
50 kΩ Pull-down
Power supply current (during
operation)
During 24 MHz operation
CLK stopped
Iddo
Idds
0
22
10
32
mA
Power supply current (during
stand-by)
—
100
µA
16/30
FEDL7055-02
OKI Semiconductor
ML7055
Power Supply Current (IDDO) Characteristics by Power Saving Mode
(VDD = 2.7 V to 3.6V, CoreVDD = 1.65 V to 1.95V, Ta = -40 to 85°C)
Operating mode
Conditions
—
Min. Typ. Max.
Unit
STOP mode (DETACH = "L")
—
—
—
—
0.03
—
—
—
—
Interval:1.28sec
Window:11.25msec
Interval:40slot
Page Scan operating mode
Poll Interval operating mod
Sniff operating mode
2.5
3.5
Interval:2000slot
Attempt:4frame
Interval:4000slot
2.5
mA
Hold operating mode
—
—
0.05
22.0
—
—
DH1/DM1
RX:DH3/DM3
TX:DH1/DM1
RX:DH5/DM5
TX:DH1/DM1
—
—
22.0
22.0
—
—
ACL operating mode
AC Characteristics
~ System clock (SCLKP)
SCLKP
Tmc0 Tmc1
(VDD = 2.7 to 3.6V, CoreVDD = 1.65 to 1.95V, Ta = -40 to 85°C)
Description Min Typ Max Unit
Parameter
Tmc0
Tmc1
Duty in SCLKP “H” duration
Duty in SCLKP “L” duration
40
40
50
50
60
60
%
%
~ Sub-clock (XC32KP)
XC32KP
Tmp0
Tmp1
(VDD = 2.7 to 3.6V, CoreVDD = 1.65 to 1.95V, Ta = -40 to 85°C)
Description Min Typ Max Unit
Parameter
Tmp0
Tmp1
Duty in XC32KP “H” duration
Duty in XC32KP “L” duration
40
40
50
50
60
60
%
%
17/30
FEDL7055-02
OKI Semiconductor
ML7055
~ Reset
Power supply stable period
Vdd/LVdd
CoreVdd/AVdd
TRESW
RESET
(VDD = 2.7 to 3.6V, CoreVDD = 1.65 to 1.95V, Ta = -40 to 85°C)
Description Min Typ Max Unit
10
Parameter
TRESW
Reset pulse width
—
—
µs
Note : Apply "L" to the RESET pin for 10 µsec or more after the power supply has been settled.
18/30
FEDL7055-02
OKI Semiconductor
ML7055
~ PCM interface
PCMCLK(I)
PCMIN
Tpc0
Tpc1
PCMOUT
Tpc2
Tpc4
Tpc2
Tpc4
PCMSYNC(I)
Tpc3
Tpc3
PCMCLK(O)
PCMIN
Tpc6
Tpc5
PCMOUT
Tpc7
Tpc 7
Tpc 8
PCMSYNC(O)
(Vdd = 2.7 to 3.6V, CoreVdd = 1.65 to 1.95V, Ta = -40 to 85°C)
Description Min Typ Max Unit
Parameter
Tpc0
PCMIN setup time relative to PCMCLK (input) falling edge
PCMIN hold time relative to PCMCLK (input) falling edge
PCMOUT delay time relative to PCMCLK (input) rising edge
PCMSYNC (input) setup time relative to PCMCLK (input)
rising edge
100
100
—
ns
ns
ns
—
—
—
—
—
—
250
Tpc1
Tpc2
—
Tpc3
Tpc4
100
ns
ns
PCMSYNC (input) hold time relative to PCMCLK (input)
rising edge
—
—
100
Tpc5
Tpc6
PCMIN setup time relative to PCMCLK (output) falling edge 100
ns
ns
—
—
—
—
—
PCMIN hold time relative to PCMCLK (output) falling edge
100
PCMOUT delay time relative to PCMCLK (output) rising
edge
Tpc7
Tpc8
250
ns
ns
—
Delay time from PCMCLK (output) rising edge to PCMSYNC
(output)
150
—
—
~ AC Characteristic Measuring Points
VDD
0.8VDD
0.8VDD
0.2VDD
0.2VDD
0 V
19/30
FEDL7055-02
OKI Semiconductor
ML7055
REFERENCE FOR VOLTAGE SUPPLY CIRCUIT
ML7055
AVDD0
0.1µF
AGND0
AVDD1
0.1µF
AGND1
CoreVDD
CoreVDD
10 to 47µF
10 to 47µF
0.1µF
0.1µF
0.1µF
0.1µF
LVDD
VDD
GND
VDD
GND
10 to 47µF
0.1µF
0.1µF
Capacitors should locate close to LSI pins.
Feed lines should be separated
from LSI pins.
Example of ML7055 voltage supply circuit
• Insert appropriate bypass capacitors between the VDD and GND lines.
Note 1: Precautions to insert the bypass capacitors
- Use traces of VDD and GND lines wider than those of the other signal lines.
- Keep the length of traces between the bypass capacitors and the VDD line and between the bypass
capacitors and the GND line as short as possible.
- Keep the length of traces between the bypass capacitors and the VDD line and between the bypass
capacitors and the GND line as equal as possible.
The circuit is subject to change according to the specific LSI board design. Please contact Oki Electric Industry Co.,
Ltd. for detailed information.
20/30
FEDL7055-02
OKI Semiconductor
ML7055
REFERENCE FOR OSCILLATOR CIUCUIT
ML7055
R0
R2
R1
R3
C3
X’tal 1
X’tal 2
C1
C0
C2
Connect this oscillator circuit only when
connecting the OKI RF-LSI ML7050.
Example of oscillator circuit
Note 1: The values of C0 and C1, and R0 and R1 should be determined according to the specifications for the
external crystal X’tal 1 (32 or 32.768 kHz).
The values of C2 and C3, and R2 and R3 should be determined according to the specifications for the
external crystal X’tal 2 (13 or 12 MHz).
Note 2: The crystal oscillator circuit should be connected to pins SCLKP and SCLKN only when the OKI RF-LSI
(ML7050) is connected. In other cases, the system clock should be input from the RF-LSI to pin SCLKP.
Note 3: In the case of 13 MHz or 12 MHz system clock (SCLKP) input, make sure the crystal frequency tolerance
is ±20 ppm for temperature, supply voltage, and aging.
In the case of 32 kHz or 32.768 kHz sub-clock (XC32KP) input, make sure the crystal frequency tolerance
is ±250 ppm for temperature, supply voltage, and aging.
Note 4: Precautions to build a crystal oscillator circuit
- Keep length of wire traces as short as possible.
- Do not cross the crystal oscillator circuit wires over other signal line wires.
- Do not keep signal line wires through which high current flows close to the crystal oscillator circuit.
- Keep the grounding point of the capacitors in the oscillator circuit at the potential equal to GND. And do
not connect the capacitors to the GND or GND lines through which high current flows.
- Do not output signals from the oscillator circuit.
The circuit is subject to change according to the specific LSI board design. Please contact Oki Electric Industry Co.,
Ltd. for detailed information. It is recommended to determine the final circuit values including the capacitance of
the circuit board designed by the user.
21/30
FEDL7055-02
OKI Semiconductor
ML7055
APPLICATION NOTES
Clock Selection
•
The system clock frequency is selected according to external pin SFRQSEL.
SFRQSEL = 0 : A 13 MHz clock is input to external pins SCLKP.
SFRQSEL = 1 : A 12 MHz clock is input to external pins SCLKP.
•
The CPU clock supply source is selected according to external pin SCLKSEL.
SCLKSEL = 0 : Use the clock that was divided down from the internal PLL output of 192 MHz that
was generated from external pins SCLKP. (Dividing ratios are selectable in the
range of 1/6 to 1/16. Initial value is 1/8 (24 MHz).)
SCLKSEL = 1 : Use external pins XC32KP.
Note: The clock supply source can be set by the CLKCNTL register in the CTL/WDT block once the
LSI is powered up.
•
The frequency of CPU clock is selectable from the high speed (24 MHz) and low speed (16 MHz). This
can be performed by the Vendor Specific Command.
Setting the Reset
•
Apply a “L” level to the RESET pin for more than 10 µs after power voltage is stabilized. When the
system clock oscillator circuit is stable and the RESET pin is at a “H” level, the internal reset is released
and operation starts after the internal reset is held for 1.9 ms for the input clock of 13 MHz or 2.0 ms for
the input clock of 12 MHz.
Setting the UART Baud Rate
It is possible to set the UART baud rate using the Vendor Specific Commands.
•
Available baud rate settings:
9600/19.2k/38.4k/56k/57.6k/115.2k/230.4k/345.6k/460.8k/921.6k
(Initial value is 115.2 kbps.)
Setting the PCM-CVSD Transcoder
•
•
It is possible to set the PCM-CVSD transcoders using the Vendor Specific Commands.
For command details, contact Oki Electric Industry Co., Ltd.
It is possible to set the following parameters using the VCCTL command:
- PCMSYNC/PCMCLK mode (initial setting: input)
- Mute reception (initial setting: OFF)
- Mute transmission (initial setting: OFF)
- Air coding
CVSD (initial setting)/µ-law/A-law
- Interface coding
Linear (initial setting)/µ-law/A-law
- PCM format (data width of one PCM Linear sample)
8-bit (initial setting)/14-bit/16-bit
- Serial interface format
Short frame (initial setting)/long frame
22/30
FEDL7055-02
OKI Semiconductor
ML7055
- Application interface mode
PCM Codec I/F (initial setting)/APB I/F
XTAL Input Frequency of BCM2002X
•
If the system clock is supplied from BCM2002X, the XTAL input frequency of BCM2002X must be 13
MHz. 12, 19.2, 19.68, or 19.8 MHz should not be applied.
XTAL Input Frequency of CX72303
• If the system clock is supplied from CX72303, the XTAL input frequency of CX72303 must be 13 MHz.
10 MHz should not be applied.
Required processes when interface pins are unused
•
•
The following tables show the processes that should be performed when interface pins are not used.
The pins that are not included in the following table should be left open.
RF I/F
Pin Name
Process When Pin Not Used
GND
Comments
RXD
RSSI
Open or GND
PLLLOCK
Open or GND
UART I/F
Pin Name
SIN
Process When Pin Not Used
Comments
Comments
VDD
CTS
GND
PCM I/F
Pin Name
PCMIN
Process When Pin Not Used
Open or VDD
PCMSYNC
PCMCLK
Open or GND
Open or GND
Processes of Other Pins
TEST I/F etc.
Pin Name
Process When Pin Not Used
Pull up or VDD
Comments
DETACH
23/30
RFVDD
System Configuration Example
VDD
ML7055
ML7050
ANT
ML7055/ML7050
RESET
LVDD
VDD
VDD_D
0.1 µ
0.1 µ
47 µ
68kΩ
Poewr on reset
GND
RXD
PLL_LE
RXD
Hardware reset
PLL_LE
PLL_DATA
PLL_CLK
PLL_OFF
TXD
PLL_POW
RX_POW
TX_POW
PLL_DATA
PLL_CLK
PLL_OFF
TXD
PLL_POW
RX_POW
TX_POW
RSSI
PCMIN
PCMOUT
PCMIN
PCMSYNC
Microphone
PCMOUT
RSYNC
XSYNC
BCLK
Voice input/
output
peripherals
PCMCLK
Speaker
MSM7702-01
RSSI_CLK
PLL_PS
PLLLOCK
MCLK
CLKOUT
SCLKN
SCLKSEL
SFRQSEL
13MHz ± 20ppm
SCLKP
VDD
RFSEL2
RFSEL1
RFSEL0
VDD
GND
XC32KN
68kΩ
GND
XC32KP
32kHz or
DETACH
AVDD0
AGND0
AVDD1
AGND1
32.768kHz ± 250ppm
GND
UART
I/F
SOUT
RTS
SIN
TD
RTS
T1IN
T2IN
T3IN
R1OUT
R2OUT
T1OUT
T2OUT
0.1 µ
1
2
3
4
5
6
7
8
9
CTS
Separate, as far as
possible, the wiring
from the board pins.
RD
CTS
R1IN
R2IN
0.1
µ
DSUB9PIN
GND
MAX3245
CoreVDD
GND
VDD
CoreVDD
GND
VDD
VDD
47 µ
47 µ
0.1 µ
0.1 µ
0.1 µ
0.1 µ
47kΩ
Vcc
SDA
SCL
VDD
GND
NC
SDA
SCL
GND
AT24C02
The capacitors should be
as close to the LSI pins
as possible.
GND
GND
FEDL7055-02
OKI Semiconductor
ML7055
PACKAGE DIMENSIONS
ML7055HB - 63pinWCSP (P-VFLGA63-4.90 × 4.72-0.50-W)
(Unit: mm)
P-VFLGA63-4.90×4.72-0.50-W
Package material
Terminal material
Epoxy resin
Sn/Pb
5
Package weight (g)
Rev. No./Last Revised
0.03 TYP.
1/May 27, 2002
Note: A lead-free package is available. Please contact Oki Sales Office/Distributors for more
information.
25/30
FEDL7055-02
OKI Semiconductor
ML7055
ML7055LA - 64pinBGA (P-TFBGA64-0707-0.65)
(Unit: mm)
P-TFBGA64-0707-0.65
Package material
Ball material
Epoxy resin
Sn/Pb
5
Package weight (g)
Rev. No./Last Revised
0.10 TYP.
1/July 5, 2002
Note: A lead-free package is available. Please contact Oki Sales Office/Distributors for more
information.
26/30
FEDL7055-02
OKI Semiconductor
ML7055
ML7055LP - 84pinBGA (P-LFBGA84-0909-0.80)
(Unit: mm)
P-LFBGA84-0909-0.80
Package material
Ball material
Epoxy resin
Sn/Pb
Package weight (g)
Rev. No./Last Revised
0.20 TYP.
1/May 15, 2000
5
Note: A lead-free package is available. Please contact Oki Sales Office/Distributors for more
information.
Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow mounting and humidity
absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product
name, package name, pin number, package code and desired mounting conditions (reflow method,
temperature and times).
27/30
FEDL7055-02
OKI Semiconductor
ML7055
REVISION HISTORY
Page
Previous Current
Document
No.
Date
Description
Edition
Edition
PEDL7055-01
Aug.23, 2002
–-
–-
Preliminary edition 1
The contents of the “FEATURES” Section have
been fully changed.
1
1
2
–-
Added the “SPECIFICATIONS” Section.
The contents of the table in the “ABSOLUTE
MAXIMUM RATINGS” Section have been
partially changed.
2
3
The voltage values of “Core VDD” have been
added on the table in the “DC Characteristics”
Section.
The pin name has been changed from LPO_CLK
to TCK.
3
5
4
6
Eliminated the “LPO_CLK” row in the table of the
“RF/IF” Section.
Eliminated “Note” on the bottom side of the table
of the “RF/IF” Section.
The “Description” column of Pin name “TCK” in
the table of the “JTAG I/F” Section has been
partially changed.
PEDL7055-02
Nov. 25, 2002
6
8
7
Added “REFERENCE FOR OSCILLATOR
CIRCUIT” Section.
9
“DETACH signal” has been changed to
“DETECH signal” in the content of the “DETACH
Interface Block” Section.
11
12
–-
13
14
15
Eliminated the “RESET signal input” Section and
added the “Setting the Reset” Section.
The “XTAL Input Frequency of BCM2002X” and
“XTAL Input Frequency of CX72303” Sections
have been added.
Eliminated the “LPO_CLK” row of the “Pin name”
column in the table of the “RF/IF” Section..
13
15
14-16
16-18
Changed the System Configuration Examples.
Partially changed the contents of “FEATURES”
Section.
1
2
1
2
Changed the contents of “Package” row in the
table.
FEDL7055-01
Dec. 17, 2002
Partially added the contents of “UART Block”
Section.
13
13
13
14
Partially added the contents of “PCM-CVSD”
Section.
28/30
FEDL7055-02
OKI Semiconductor
ML7055
Page
Previous Current
Document
No.
Date
Description
Edition
Edition
Partially eliminated the contents of “DETACH
Interface Block” Section.
13
15
Added “Power Supply Current Characteristics by
Power Saving Mode” and “AC Characteristics”
Sections.
–-
17-19
Partially added the contents of “REFERENCE
FOR VOLTAGE SUPPLY CIRCUIT” Section.
9
19
20
22
24
FEDL7055-01
Dec. 17, 2002
Partially added the contents of “REFERENCE
FOR OSCILLATOR CIRCUIT” Section.
10
14
16
Partially added the contents of “Clock Selection”
Section.
Partially changed the contents of “System
Configuration Example” Section.
6
6
Partially added the contents of “RF I/F” Section.
Partially added the contents of “DC
Characteristics” Section.
16
18
23
16
18
23
FEDL7055-02
Apr. 8, 2003
Partially eliminated the contents of “Reset”
Section.
Eliminated the “RESET” row in the table of the
“TEST I/F ” Section.
29/30
FEDL7055-02
OKI Semiconductor
ML7055
NOTICE
1. The information contained herein can change without notice owing to product and/or technical improvements.
Before using the product, please make sure that the information being referred to is up-to-date.
2. The outline of action and examples for application circuits described herein have been chosen as an
explanation for the standard action and performance of the product. When planning to use the product, please
ensure that the external conditions are reflected in the actual circuit, assembly, and program designs.
3. When designing your product, please use our product below the specified maximum ratings and within the
specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating
temperature.
4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation
resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or
unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified
maximum ratings or operation outside the specified operating range.
5. Neither indemnity against nor license of a third party’s industrial and intellectual property right, etc. is granted
by us in connection with the use of the product and/or the information and drawings contained herein. No
responsibility is assumed by us for any infringement of a third party’s right which may result from the use
thereof.
6. The products listed in this document are intended for use in general electronics equipment for commercial
applications (e.g., office automation, communication equipment, measurement equipment, consumer
electronics, etc.). These products are not, unless specifically authorized by Oki, authorized for use in any
system or application that requires special or enhanced quality and reliability characteristics nor in any
system or application where the failure of such system or application may result in the loss or damage of
property, or death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace
equipment, nuclear power control, medical equipment, and life-support systems.
7. Certain products in this document may need government approval before they can be exported to particular
countries. The purchaser assumes the responsibility of determining the legality of export of these products and
will take appropriate and necessary steps at their own expense for these.
8. No part of the contents contained herein may be reprinted or reproduced without our prior permission.
Copyright 2003 Oki Electric Industry Co., Ltd.
30/30
相关型号：
©2020 ICPDF网 联系我们和版权申明