ML7074-001GA [OKI]
VoIP CODEC; 的VoIP编解码器
| 型号： | ML7074-001GA |
| 厂家： | 
OKI ELECTRONIC COMPONETS |
| 描述： | VoIP CODEC |
| 文件： | 总31页 (文件大小：327K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FEDL7074-001DIGEST-01
Issue Date: Oct. 15, 2002
OKI Semiconductor
ML7074-001 GA
VoIP CODEC
GENERAL DESCRIPTION
The ML7074-001GA is a speech CODEC for VoIP. This LSI allows selection of G.729.A, G.726, or G.711
standard as a speech CODEC. The LSI is optimum for adding VoIP functions to TAs, routers, etc., since it has the
functions of an echo canceller for 32 msec delay, DTMF detection, tone detection, tone generation, etc.
FEATURES
• Single 3.3 V power supply operation (DVDD0, 1, 2, AVDD: 3.0 to 3.6 V)
• Speech CODEC:
Selectable among G.729.A (8 kbps), G726 (32 kbps), G.711 (64 kbps) µ-law, and A-law
Mutual conversion function between G.729.A (8 kbps) and G.726 (32 kbps).
• Echo canceller for 32 ms delay
• DTMF detect function
• Tone detect function: 2 systems (1650 Hz, 2100 Hz: Detect frequency can be changed.)
• Tone generate function
• FSK generate function
• Dial pulse detect function
• Dial pulse transmit function
• Internal 1-channel 16-bit timer
• Built-in FIFO buffers (640 bytes) for transferring transmit and receive data
Frame/DMA (slave) interface selectable.
• Master clock frequency: 4.096 MHz (crystal oscillation or external input)
• Hardware or software power down operation possible.
• Analog input/output type:
Two built-in input amplifiers, 10 kΩ driving
Two built-in output amplifiers, 10 kΩ driving
• Package:
64-pin plastic QFP (QFP64-P-1414-0.80-BK)
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ML7074-001 GA
BLOCK DIAGRAM
G P O 1
G P O 0
G P I 1
G P I 0
T 3 T S
T 2 T S
T 1 T S
T 0 T S
P D N B
D D A V
A G N D
N D 2 D G
2
D V D D
N D 1 D G
N D 0 D G
D V D D
D V D D
0
1
X O
X I
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ML7074-001 GA
PIN ASSIGNMENT (TOP VIEW)
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
AVDD
AIN0P
AIN0N
GSX0
GSX1
AIN1N
AVREF
VFRO0
VFRO1
AGND
DGND2
XI
D15
D14
D13
D12
D11
D10
D9
D8
ML7074-001
D7
D6
D5
D4
D3
XO
DVDD2
TST3
D2
D1
TST2
D0
64-pin plastic QFP
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PIN DESCRIPTIONS
Pin
No.
Symbol
I/O PDNB = “0”
Description
1
2
3
4
TST1
TST0
PCMO
PCMI
I
I
O
I
“0”
“0”
“Hi-z”
I
Test control input 1: Normally input “0”.
Test control input 0: Normally input “0”.
PCM data output
PCM data input
CLKSEL = ”0”
PCM shift clock input
I
5
6
BCLK
SYNC
I/O
I/O
CLKSEL = ”1”
PCM shift clock output
CLKSEL = ”0”
PCM sync signal 8 kHz input
CLKSEL = ”1”
PCM sync signal 8 kHz output
Digital power supply
Transmit buffer DMA access acknowledge signal input
Receive buffer DMA access acknowledge signal input
FR0B: (CR11-B7 = ”0”)
“L”
I
“L”
7
8
9
DVDD0
ACK0B
ACK1B
I
I
I
I
FR0B
(DMARQ0B)
Transmit buffer frame signal output
DMARQ0B: (CR11-B7 = ”1”)
Transmit buffer DMA access request signal output
FR1B: (CR11-B7 = ”0”)
10
O
”H”
FR1B
(DMARQ1B)
Receive buffer frame signal output
DMARQ1B: (CR11-B7 = ”1”)
Receive buffer DMA access request signal output
Interrupt request output
“L” level is output for about 1.0 µsec when an interrupt is generated.
Chip select control input
Read control input
Write control input
Digital ground (0.0 V)
Data input/output
Data input/output
Data input/output
Data input/output
Data input/output
Data input/output
Data input/output
Data input/output
11
12
O
O
“H”
“H”
INTB
13
14
15
16
17
18
19
20
21
22
23
24
CSB
RDB
WRB
DGND0
D0
D1
D2
D3
D4
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
D5
D6
D7
Data input/output
Fix to input state when using in 8-bit bus access (CR11-B5 = “1”).
25
D8
I/O
I
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Data input/output
Fix to input state when using in 8-bit bus access (CR11-B5 = “1”).
Data input/output
Fix to input state when using in 8-bit bus access (CR11-B5 = “1”).
Data input/output
Fix to input state when using in 8-bit bus access (CR11-B5 = “1”).
Data input/output
Fix to input state when using in 8-bit bus access (CR11-B5 = “1”).
Data input/output
Fix to input state when using in 8-bit bus access (CR11-B5 = “1”).
26
27
28
29
30
31
32
D9
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
I
I
D10
D11
D12
D13
D14
D15
Data input/output
Fix to input state when using in 8-bit bus access (CR11-B5 = “1”).
Data input/output
Fix to input state when using in 8-bit bus access (CR11-B5 = “1”).
33
34
35
36
37
38
39
40
41
DVDD
A0
A1
A2
A3
A4
A5
A6
1
Digital power supply
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Address input
Address input
Address input
Address input
Address input
Address input
Address input
Address input
A7
Power down input
42
43
PDNB
I
I
“0”
I
“0”: Power down reset
“1”: Normal operation
SYNC and BCLK I/O control input
“0”: SYNC and BCLK become inputs
“1”: SYNC and BCLK become outputs
Digital ground (0.0 V)
General-purpose input pin 0 (5 V tolerant input)
/Secondary function: Dial pulse detect input pin
General-purpose input pin 1 (5 V tolerant input)
General-purpose output pin 0 (5 V tolerant output, can be pulled up
externally)
CLKSEL
44
45
46
DGND1
GPI0
I
I
I
I
GPI1
47
GPO0
O
“L”
/Secondary function: Dial pulse transmit pin
General-purpose output pin 1 (5 V tolerant output, can be pulled up
externally)
48
GPO1
O
“L”
49
50
51
52
53
54
55
AVDD
AIN0P
AIN0N
GSX0
GSX1
AIN1N
AVREF
Analog power supply
AMP0 non-inverted input
AMP0 inverted input
AMP0 output (10 kΩ driving)
AMP1 output (10 kΩ driving)
AMP1 inverted input
Analog signal ground (1.4 V)
I
I
O
O
I
I
I
“Hi-z”
“Hi-z”
I
O
“L”
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ML7074-001 GA
56
57
58
59
60
61
62
63
64
VFRO0
VFRO1
AGND
DGND2
XI
O
O
I
“Hi-z”
“Hi-z”
AMP2 Output (10 kΩ driving)
AMP3 Output (10 kΩ driving)
Analog ground (0.0 V)
Digital ground (0.0 V)
4.096 MHz crystal oscillator I/F, 4.096 MHz clock input
4.096 MHz crystal oscillator I/F
Digital power supply
Test control input 3: Normally input “0”.
Test control input 2: Normally input “0”.
I
XO
O
“H”
DVDD
2
I
I
TST3
TST2
“0”
“0”
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ML7074-001 GA
ABSOLUTE MAXIMUM RATINGS
Parameter
Analog power supply
voltage
Symbol
VDA
Conditions
Rating
Unit
V
−0.3 to 5.0
Digital power supply voltage
Analog input voltage
VDD
VAIN
VDIN1
VDIN2
Tstg
V
V
V
V
°C
−0.3 to 5.0
−0.3 to VDD + 0.3
−0.3 to VDD + 0.3
−0.3 to 6.0
Analog pins
Normal digital pins
5 V tolerant pins
Digital input voltage
Storage temperature range
−55 to +150
RECOMMENDED OPERATING CONDITIONS
(Unless otherwise specified, AVDD = 3.0 to 3.6 V, DVDD0, 1, 2 = 3.0 to 3.6 V, AGND = DGND0, 1, 2 = 0.0 V,
Ta = −20 to +60°C)
Parameter
Symbol
VDA
VDD
Conditions
Min.
3.0
3.0
Typ.
3.3
3.3
Max.
3.6
3.6
60
Unit
V
V
Analog power supply voltage
Digital power supply voltage
Operating temperature range
Ta
−20
°C
VDD
+
VIH1
Digital input pins
2.0
V
0.3
5.5
0.8
20
20
50
Digital high level input voltage
VIH2
VIL
tIR
tIF
CDL
GPI0 and GPI1 pins
Digital pins
2.0
−0.3
V
V
ns
ns
pF
2
2
Digital low level input voltage
Digital input rise time
Digital input fall time
Digital pins
Digital pins
Digital pins
Digital output load capacitance
Capacitance of bypass capacitor
for AVREF
Cvref Between AVREF and AGND 2.2+0.1
4.7+0.1
µF
Master clock frequency
PCM shift clock frequency
PCM sync signal frequency
Clock duty ratio
Fmck
Fbclk
Fsync
DRCLK
MCK
BCLK (at input)
SYNC (at input)
MCK, BCLK (at input)
BCLK to SYNC
(at input)
4.096 +0.01%
MHz
kHz
kHz
%
−0.01%
64
2048
60
8.0
50
40
tBS
100
ns
PCM sync timing
SYNC to BCLK
(at input)
SYNC (at input)
tSB
100
ns
PCM sync signal width
tWS
1BCLK
100
µs
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ELECTRICAL CHARACTERISTICS
DC Characteristics
(Unless otherwise specified, AVDD = 3.0 to 3.6 V, DVDD0, 1, 2 = 3.0 to 3.6 V, AGND = DGND0, 1, 2 = 0.0 V,
Ta = −20 to +60°C)
Parameter
Symbol
ISS
Conditions
Standby state
(PDNB = ”0”, VDD = 3.3 V, Ta = 25°C)
Min.
Typ.
5.0
Max.
20.0
Unit
µA
Operating state 1
In the PCM/IF mode
(SC_EN = “1”, PCMIF_EN = “1”,
AFE_EN = “1”, TRANS_EN = “1”)
Connect a 4.096 MHz crystal oscillator
between XI and XO.
IDD
1
45.0
50.0
55.0
65.0
mA
mA
Power supply current
Operating state 2
When operating the whole system
(SC_EN = “1”, PCMIF_EN = “0”,
TRANS_EN = “0”, AFE_EN = “0”)
Connect a 4.096 MHz crystal oscillator
between XI and XO.
IDD2
Digital input pin
input leakage current
IIH
IIL
IOZH
IOZL
Vin = DVDD
Vin = DGND
Vout = DVDD
Vout = DGND
0.01
−0.01
0.01
1.0
1.0
−1.0
µA
µA
µA
µA
Digital I/O pin
output leakage current
−1.0
−0.01
Digital output pins, I/O pins
IOH = 4.0 mA
IOH = 1.0 mA (XO pin)
Digital output pins, I/O pins
IOL = −4.0 mA
High level output
voltage
VOH
2.2
V
Low level output
voltage
VOL
CIN
0.4
12
V
IOL = −1.0 mA (XO pin)
Input pins
Input capacitance *1
8
pF
Note: *1 Guaranteed design value
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ML7074-001 GA
Analog Interface
(Unless otherwise specified, AVDD = 3.0 to 3.6 V, DVDD0, 1, 2 = 3.0 to 3.6 V, AGND = DGND0, 1, 2 = 0.0 V,
Ta = −20 to +60°C)
Parameter
Input resistance *1
Output load resistance
Output load capacitance
Offset voltage
Symbol
RIN
RL
CL
VOF
Conditions
AIN0N, AIN0P, AIN1N
GSX0, GSX1, VFRO0, VFRO1
Analog output pins
Min.
10
10
−40
Typ.
Max.
50
40
Unit
MΩ
kΩ
pF
mV
VFRO0, VFRO1
GSX0, GSX1, VFRO0, VFRO1
RL = 10 kΩ
Output voltage level *2
VO
1.3
Vpp
Notes:
*1 Guaranteed design value
*2 −7.7 dBm (600Ω) = 0 dBm0, +3.17 dBm0 = 1.3 Vpp
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AC Characteristics
CODEC (Speech CODEC in G.711 (µ-law) Mode)
(Unless otherwise specified, AVDD = 3.0 to 3.6 V, DVDD0, 1, 2 = 3.0 to 3.6 V, AGND = DGND0, 1, 2 = 0.0 V,
Ta = −20 to +60°C)
Conditions
Parameter
Symbol
Min.
Typ.
Max.
Unit
Frequency (Hz)
0 to 60
300 to 3000
1020
Level (dBm0)
25
−0.15
Reference value
−0.15
0
13
−0.15
Reference value
−0.15
0
13
35
35
35
28
23
35
35
dB
dB
dB
dB
dB
dB
dB
LT1
LT2
LT3
LT4
LT5
LT6
LR2
LR3
LR4
0.20
Transmit frequency
characteristics
0
3300
3400
0.80
0.80
3968.75
0 to 3000
1020
0.20
Receive frequency
characteristics
3300
3400
3968.75
0
0.80
0.80
dB
dB
LR5
LR6
0.2
3
0
−30
−40
−45
3
dBp
dBp
dBp
dBp
dBp
dBp
dBp
dBp
dBp
dBp
dB
dB
dB
dB
dB
dB
dB
SDT1
SDT2
SDT3
SDT4
SDT5
SDR1
SDR2
SDR3
SDR4
SDR5
GTT1
GTT2
GTT3
GTT4
GTT5
GTR1
GTR2
GTR3
GTR4
GTR5
Transmit signal to noise
ratio [*1]
1020
1020
1020
1020
0
Receive signal to noise
ratio [*1]
35
28
23
−0.2
−30
−40
−45
3
−10
−40
−50
−55
3
Reference value
Transmit inter-level
loss error
0.2
−0.2
−0.6
−1.2
−0.2
0.6
1.2
0.2
Reference value
−10
−40
−50
Receive inter-level loss
error
0.2
0.6
1.2
−0.2
−0.6
−1.2
dB
−55
Analog input =
AVREF
PCMI = ”1”
NIDLT
NIDLR
AVT
dBm0p
dBm0p
Vrms
Idle channel noise
[*1]
−68
−72
Transmit absolute level
[*2]
1020
0
0.285 0.320 0.359
Receive absolute level
[*2]
AVR
1020
0
0.285 0.320 0.359
30
Vrms
dB
Noise frequency
range: 0 to 50 kHz
Noise level: 50mVpp
PSRRT
PSRRR
Power supply noise
reject ratio
30
dB
Notes: *1 Using P-message filter
*2 0.320 Vrms = 0 dBm0 = −7.7 dBm (600Ω)
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Gain Setting (Speech CODEC in G.711 (µ-law) Mode)
(Unless otherwise specified, AVDD = 3.0 to 3.6 V, DVDD0, 1, 2 = 3.0 to 3.6 V, AGND = DGND0, 1, 2 = 0.0 V,
Ta = −20 to +60°C)
Parameter
Transmit and receive
gain setting accuracy
Symbol
GAC
Conditions
Min.
Typ.
Max.
1.0
Unit
dB
−1.0
Tone Output (Speech CODEC in G.711 (µ-law) Mode)
(Unless otherwise specified, AVDD = 3.0 to 3.6 V, DVDD0, 1, 2 = 3.0 to 3.6 V, AGND = DGND0, 1, 2 = 0.0 V,
Ta = −20 to +60°C)
Parameter
Frequency deviation
Output level
Symbol
fDFT
oLEV
Conditions
Relative to set frequency
Relative to set gain
Min.
−1.5
−2.0
Typ.
Max.
1.5
2.0
Unit
%
dB
DTMF Detector, Other Detectors (Speech CODEC in G.711 (µ-law) Mode)
(Unless otherwise specified, AVDD = 3.0 to 3.6 V, DVDD0, 1, 2 = 3.0 to 3.6 V, AGND = DGND0, 1, 2 = 0.0 V,
Ta = −20 to +60°C)
Parameter
Detect level accuracy
Symbol
dLAC
Conditions
Relative to set detect level
Min.
−2.5
Typ.
Max.
2.5
Unit
dB
Echo Canceller
(Unless otherwise specified, AVDD = 3.0 to 3.6 V, DVDD0, 1, 2 = 3.0 to 3.6 V, AGND = DGND0, 1, 2 = 0.0 V,
Ta = −20 to +60°C)
Parameter
Symbol
eRES
tECT
Conditions
In the analog I/F mode
In the PCM I/F (16-bit linear) mode
In the PCM I/F (G.711) mode
Min.
Typ.
35
Max.
Unit
dB
Echo attenuation
30
Erasable echo delay time
32
ms
Measurement method
Echo Canceller
ATT
E.R.L
Sin
Sout
Level Meter
(echo return loss)
LPF
5 kHz
Delay
Rout
Rin
Echo delay time
White noise generator
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ML7074-001 GA
PDNB, XO, AVREF Timings
(Unless otherwise specified, AVDD = 3.0 to 3.6 V, DVDD0, 1, 2 = 3.0 to 3.6 V, AGND = DGND0, 1, 2 = 0.0 V,
Ta = −20 to +60°C)
Parameter
Power down signal pulse
width
Symbol
tPDNB
txtal
Conditions
PDNB pin
Min.
1
Typ.
Max.
Unit
µs
Oscillation start-up time
100
ms
2+α
AVREF = 1.4 (90%)
C5 = 4.7 µF, C6 = 0.1 µF
(See Fig. 9.)
AVREF rise time
tAVREF
600
ms
s
Initialization mode start-up
time
tINIT
1
* α is a value that depends on the oscillation stabilizing time when using a crystal oscillator.
VDD
DVDD,
AVDD
0 V
VDD
PDNB
0 V
tPDNB
VDD
0 V
XO
txtal
About
1.4 V
AVREF
0 V
tAVREF
"1"
"0"
CR5-B7
Initialization mode
(READY)
tINIT
Fig. 1 PDNB, XO, and AVREF timings
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ML7074-001 GA
PCM I/F Mode
(Unless otherwise specified, AVDD = 3.0 to 3.6 V, DVDD0, 1, 2 = 3.0 to 3.6 V, AGND = DGND0, 1, 2 = 0.0 V,
Ta = −20 to +60°C)
Parameter
Bit clock frequency
Bit clock duty ratio
Symbol
fBCLK
dBCLK
fSYNC
Conditions
CDL = 20pF(at output)
CDL = 20pF(at output)
CDL = 20pF(at output)
CDL = 20pF(at output)
At 64 kHz output
CDL = 20pF(at output)
At 128 kHz output
BCLK to SYNC
(at output)
Min.
−0.1%
45
Typ.
64
50
8
Max.
+0.1%
55
Unit
kHz
%
+0.1%
kHz
Sync signal frequency
−0.1%
dSYNC1
dSYNC2
tBS
12.4
6.24
100
100
12.5
6.25
12.6
6.26
%
%
Sync signal duty ratio
ns
ns
Transmit/receive signal sync
timing
SYNC to BCLK
(at output)
tSB
Input setup time
Input hold time
tDS
tDH
tSDX
tXD1
tXD2
tXD3
100
100
—
—
100
100
100
100
ns
ns
ns
ns
ns
ns
Digital output delay time
Digital output hold time
PCMO pin
Pull-up, pull-down resistors
RDL = 1 kΩ, CDL = 50 pF
BCLK
0
1
2
3
4
5
6
7
8
-
16
tBS tSB
tWS
SYNC
PCMI
tDS tDH
MSB
LSB
G.726
LSB
G.711
LSB
16-bit
linear
Fig. 2 PCM I/F mode input timing (long frame)
BCLK
0
1
2
3
4
5
6
7
8
9
-
17
tBS tSB
tWS
SYNC
PCMI
tDS tDH
MSB
LSB
G.726
LSB
G.711
LSB
16-bit
linear
Fig. 3 PCM I/F mode input timing (short frame)
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BCLK
0
1
2
3
4
5
6
7
8
9
-
17
tBS tSB
tWS
SYNC
PCMO
tXD2
LSB
G.726
tXD3
tXD3
tSDX
tXD1
Hi-z
MSB
LSB
LSB
16-bit
linear
G.711
Fig. 4 PCM I/F mode output timing (long frame)
BCLK
0
1
2
3
4
5
6
7
8
9
10
-
18
tBS tSB
tWS
SYNC
PCMO
tXD2
tXD3
tXD3
tXD1
MSB
Hi-z
LSB
LSB
G.711
LSB
16-bit
linear
G.726
Fig. 5 PCM I/F mode output timing (short frame)
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Control Register Interface
(Unless otherwise specified, AVDD = 3.0 to 3.6 V, DVDD0, 1, 2 = 3.0 to 3.6 V, AGND = DGND0, 1, 2 = 0.0 V,
Ta = −20 to +60°C)
Parameter
Address setup time
Address hold time
Write data setup time
Write data hold time
CSB setup time
CSB hold time
WRB pulse width
Read data output delay time
Read data output hold time
RDB pulse width
Symbol
tAS
tAH
tWDS
tWDH
tCS
Conditions
Min.
10
10
10
10
10
10
10
Typ.
Max.
20
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCH
CL = 50 pF
tWW
tRDD
tRDH
tRW
3
25
10
CSB disable time
tCD
A7-A0
Input
A2
A1
tAS
tAH
tAS
tCS
tAH
D7-D0
I/O
D1
Input
D2
Output
tWDS
tCS
tWDH
tCH
tRDD
tRDH
CSB
Input
tCD
tCH
WRB
Input
tRW
tWW
RDB
Input
Write timing
Read timing
Fig. 6 Control register interface
15/31
FEDL7074-001DIGEST-01
OKI Semiconductor
ML7074-001 GA
Transmit and Receive Buffer Interface (in Frame Mode)
(Unless otherwise specified, AVDD = 3.0 to 3.6 V, DVDD0, 1, 2 = 3.0 to 3.6 V, AGND = DGND0, 1, 2 = 0.0 V,
Ta = −20 to +60°C)
Parameter
FR1B setup time
FR1B output delay time
Address setup time
Address hold time
Write data setup time
Write data hold time
CSB setup time
CSB hold time
WRB pulse width
FR0B setup time
FR0B output delay time
Read data output delay time
Read data output hold time
RDB pulse width
Symbol
tF1S
tF1D
tAS
Conditions
Min.
Typ.
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3
20
10
10
10
10
10
10
10
3
20
30
tAH
tWDS
tWDH
tCS
tCH
CL = 50 pF
tWW
tF0S
tF0D
tRDD
tRDH
tRW
3
35
10
CSB disable time
tCD
FR0B
Output
tF0S
tF0D
FR1B
Output
tF1S
tF1D
A7-A0
Input
A2
A1
tAS
tWDS
tCS
tAH
tAS
tCS
tAH
D15-D0
I/O
D1
Input
D2
Output
tWDH
tCH
tRDD
tRDH
CSB
Input
tCD
tCH
WRB
Input
tRW
tWW
RDB
Input
Write timing
Read timing
Fig. 7 Transmit and receive buffer interface (in frame mode)
16/31
FEDL7074-001DIGEST-01
OKI Semiconductor
ML7074-001 GA
Transmit and Receive Buffer Interface (in DMA Mode)
(Unless otherwise specified, AVDD = 3.0 to 3.6 V, DVDD0, 1, 2 = 3.0 to 3.6 V, AGND = DGND0, 1, 2 = 0.0 V,
Ta = −20 to +60°C)
Parameter
DMARQ1B setup time
Symbol
tDR1S
tDR1RD
tDR1FD
tAS
Conditions
Min.
3
Typ.
Max.
25
25
20
25
30
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
10
10
10
10
10
10
3
3
35
10
DMARQ1B output delay time
Address setup time
Address hold time
Write data setup time
Write data hold time
ACK setup time
ACK hold time
WRB pulse width
DMARQ0B setup time
tAH
tWDS
tWDH
tAKS
tAKH
tWW
tDR0S
tDR0RD
tDR0FD
tRDD
tRDH
tRW
CL = 50 pF
DMARQ0B output delay time
Read data output delay time
Read data output hold time
RDB pulse width
ACKB disable time
tAD
DMARQ0B
Output
tDR0S
tDR0FD
tDR0RD
DMARQ1B
Output
tDR1S
tDR1FD
tDR1RD
A7-A0
Input
A2
A1
tAS
tAH
tAS
tAH
D15-D0
I/O
D1
Input
D2
Output
tWDS
tWDH
tRDD
tRDH
ACK0B
Input
tAKS
tAKH
ACK1B
Input
tAKS
tAKH
tAD
WRB
Input
tRW
tWW
RDB
Input
Write timing
Read timing
Fig. 8 Transmit and receive buffer interface (in DMA mode)
17/31
FEDL7074-001DIGEST-01
OKI Semiconductor
ML7074-001 GA
PIN FUNCTION DESCRIPTIONS
AIN0N, AIN0P, GSX0, AIN1N, GSX1
These are the analog transmit input and transmit level adjust pins. Each of AIN0N and AIN1N is connected to each
of the inverting input pins of the built-in transmit amplifiers AMP0 and AMP1, and AIN0P is connected to the
non-inverting input pin of AMP0. In addition, GSX0 and GSX1 are connected to the output pins of AMP0 and
AMP1, respectively. The selection between AMP0 and AMP1 is made by CR10-B0. See Fig. 9 for the method of
making level adjustment. During the power down mode (when PDNB = “0” or CR0-B7 = “1”), the outputs of
GSX0 and GSX1 go to the high impedance state. If AMP0 is not used in the specific application of this LSI, short
GSX0 with AIN0N and connect AIN0P with AVREF. When AMP1 is not used, short GSX1 with AIN1N.
Notice:
It is recommended to select the amplifier to be used before the conversation starts, since a small amount of noise
will be generated if the amplifier selection is changed while conversation is in progress.
VFRO0, VFRO1
These are analog receive output pins and are connected to the output pins of the built-in receive amplifiers AMP2
and AMP3, respectively. The output signals of VFRO0 and VFRO1 can be selected using CR10-B1 and CR10-B2,
respectively. When selected (“1”), the received signal will be output, and when deselected (“0”), the AVREF
signal (about 1.4 V) will be output. In the power down mode, these pins will be in the high impedance state. It is
recommended to use these output signals via DC coupling capacitors.
Notice:
It is recommended to select the amplifier to be used before the conversation starts, since a small amount of noise is
generated if the output selection is changed while the conversation is in progress.
At the time of resetting or releasing from the reset state, it is recommended to select the AVREF as outputs of
VFRO0 and VFRO1.
GSX0
R2
10kΩ
Gain = R2/R1 <=
63(+36dB)
R1 : Variable
R2 : Max 500k
C1
R1
AIN0N
AIN0P
GSX1
AIN1N
AMP0
CR10-B0
A/D
R4
Gain = R4/R3 <=63(+36dB)
R1 : Variable
R2 : Max 500k
10κΩ
C2
R3
AMP1
CR10-B1
10kΩ
C3
VFRO0
VFRO1
D/A
Out : Max 1.3Vp-p
Out : Max 1.3Vp-p
AMP2
CR10-B2
10kΩ
C4
AMP3
AVREF
VREF
C5
+
2.2 to 4.7µF
C6 0.1µF
Fig. 9 Analog interface
18/31
FEDL7074-001DIGEST-01
OKI Semiconductor
ML7074-001 GA
AVREF
This is the output pin for the analog signal ground potential. The output potential at this pin will be about 1.4 V.
Connect a 2.2 to 4.7 µF (aluminum electrolytic type) capacitor and a 0.1 µF (ceramic type) capacitor in parallel
between this pin and the GND pin as bypass capacitors. The output at the AVREF pin goes to 0.0 V in the power
down mode. The voltage starts rising after the power down mode is released (PDNB = “1” and also CR0-B7 = “0”).
The rise time is about 0.6 sec.
XI, XO
These are the pins for either connecting the crystal oscillator for the master clock or for inputting an external master
clock signal.
The oscillations of the master clock oscillator will be stopped during a power down due to the PDNB signal or
during a software power down due to CR0-B7 (SPDN). The oscillations start when the power down condition is
released, and the internal clock supply of the LSI will be started after counting up the oscillation stabilization
period (of about 16 ms). Examples of crystal oscillator connection and external master clock input are shown in
Fig. 10.
CR0-B7
(SPDN)
CR0-B7
(SPDN)
To internal
circuits
To internal
circuits
PDNB
PDNB
XI
XO
XI
XO
Open
R
4.096 MHz
X'tal
C1
C2
X'tal(4.096 MHz)
C1
C2
R
Daishinku Co., Ltd.
AT-49
5pF
10pF
1MΩ
Fig. 10 Examples of oscillator circuit and clock input
PDNB
This is the power down control input pin. The power down mode is entered when this pin goes to “0”. In addition,
this pin also has the function of resetting the LSI. In order to prevent wrong operation of the LSI, carry out the
initial power-down reset after switching on the power using this PDNB pin. Also, keep the PDNB pin at “0” level
for 1 µs or more to initiate the power down state.
Further, it is possible to carry out a power down reset of the LSI when the power is being supplied by performing
control of CR0-B7 (SPDN) in the sequence “0” → “1” → “0”.
The READY signal (CR5-B7) goes to “1” about 1.0 second after the power down mode is released thereby entering
the mode of setting various functions (initialization mode). See Fig. 1 for the timings of PDNB and AVREF, XO,
and the initialization mode.
Notice: At the time of switching on the power, start from the power down mode using PDNB.
DVDD0, DVDD1, DVDD2, AVDD
These are power supply pins. DVDD0, 1, 2 are the power supply pins for the digital circuits while AVDD is the
power supply pin for the analog circuits of the LSI. Connect these pins together in the neighborhood of the LSI and
connect as bypass capacitors a 10 µF electrolytic capacitor and a 0.1 µF ceramic capacitor in parallel between the
DGND and AGND pins.
DGND0, DGND1, DGND2, AGND
These are ground pins. GDND0, 1, 2 are the ground pins for the digital circuits and AGND is the ground pin for the
analog circuits of the LSI. Connect these pins together in the neighborhood of the LSI.
19/31
FEDL7074-001DIGEST-01
OKI Semiconductor
ML7074-001 GA
TST0, TST1, TST2, TST3
These are input pins for testing purposes only. Keep the inputs to these pins at the “0” level during normal use
conditions.
INTB
This is the interrupt request output pin. An “L” level is output for a duration of about 1.0 µsec at this pin when
there is a change in state of an interrupt cause.
This output will be maintained at the “H” level when there is no change in state of any of the interrupt causes. The
actual interrupt cause generating the interrupt can be verified by reading CR3 and CR4. The different interrupt
causes are described below.
• Underflow error (CR3-B0)
An interrupt is generated when an internal read from the receive buffer occurs before the writing into the receive
buffer from the MCU has been completed.
An interrupt is generated when a normal writing is made in the receive buffer by the MCU and the underflow
error is released.
• Overrun error (CR3-B1)
An interrupt is generated when an internal write of the next data into the transmit buffer occurs before the
transmit buffer data read out from the MCU has been completed.
An interrupt is generated when a normal read out is made from the transmit buffer by the MCU and the overrun
error is released.
• When a dial pulse is detected (CR4-B6).
• When a DTMF signal is detected (CR4-B4).
• When DTMF_CODEC0, 1, 2, 3 are detected (CR4-B0, B1, B2, B3).
An interrupt is generated when a DTMF signal is detected.
An interrupt is generated when there is a change from the DTMF signal detected state to the no-detected state.
An interrupt is generated when there is a change in the detected code (CR4-B0, B1, B2, B3) in the condition in
which a DTMF signal is being detected.
• When TONE0 is detected (CR3-B3).
An interrupt is generated when a 1650 Hz tone signal is detected.
An interrupt is generated when there is a change to the non-detection condition in the tone signal detection
condition.
• When TONE1 is detected (CR3-B4).
An interrupt is generated when a 2100 Hz tone signal is detected.
An interrupt is generated when there is a change to the non-detection condition in the tone signal detection
condition.
• When FGEN_RQ is generated (CR3-B6).
An interrupt is generated when the FSK generator makes a request for the next data to be transmitted.
An interrupt is generated when there is a change from the condition in which the FSK generator is requesting for
transmission data to the condition in which there is no request for internal fetch of the data to be transmitted next.
• When DSP_ERR is detected (CR3-B7).
An interrupt is generated when any error occurs in the DSP inside the LSI.
20/31
FEDL7074-001DIGEST-01
OKI Semiconductor
ML7074-001 GA
A0 to A7
These are the address input pins for use during an access of the frame, DMA, or control registers. The different
addresses will be the following.
Transmit buffer (TX Buffer)
A7 to A0 = 10xxxxxxb (the lower 6 bits are not valid)
Receive buffer (RX Buffer)
A7 to A0 = 01xxxxxxb (the lower 6 bits are not valid)
Control register (CR)
A7 to A0 = 00xxxxxxb
D0 to D15
These are the data input/output pins for use during an access of the frame, DMA, or control registers. Connect
pull-up resistors to these pins since they are I/O pins. When the 8-bit bus access method is selected by CR11-B5,
only D0 to D7 become valid. Since the higher 8 bits D8 to D15 will always be in the input state when the 8-bit bus
access method is selected (CR11-B5 = “1”), tie them to “0” or “1” inputs.
CSB
This is the chip select input pin for use during a frame or control register access.
RDB
This is the read enable input pin for use during a frame, DMA, or control register access.
WRB
This is the write enable input pin for use during a frame, DMA, or control register access.
21/31
FEDL7074-001DIGEST-01
OKI Semiconductor
ML7074-001 GA
FR0B (DMARQ0B)
• FR0B (In frame mode, CR11-B7 = “0”)
This is the transmit frame output pin which outputs the signal when the transmit buffer is full during frame
access. This pin outputs an “L” level when the transmit buffer becomes full, and maintains that “L” level output
until a specific number of words are read out from the MCU.
• DMARQ0B (In DMA mode, CR11-B7 = “1”)
This is the DMA request output pin which outputs the signal when the transmit buffer is full during DMA access.
This output becomes “L” when the transmit buffer becomes full, and returns to the “H” level automatically on
the falling edge of the read enable signal (RDB = “1” → “0”) when there is an acknowledgement signal (ACK0B
= “0”) from the MCU. This relationship is repeated until a specific number of words are read out from the MCU.
FR1B (DMARQ1B)
• FR1B (In frame mode, CR11-B7 = “0”)
This is the receive frame output pin which outputs the signal when the receive buffer is empty during frame
access. This pin outputs an “L” level when the receive buffer becomes empty, and maintains that “L” level
output until a specific number of words are written from the MCU.
• DMARQ1B (In DMA mode, CR11-B7 = “1”)
This is the DMA request output pin which outputs the signal when the receive buffer is empty during DMA
access. This output becomes “L” when the receive buffer becomes empty, and returns to the “H” level
automatically on the falling edge of the write enable signal (WRB = “1” → “0”) when there is an
acknowledgement signal (ACK1B = “0”) from the MCU. This relationship is repeated until a specific number of
words are written from the MCU.
ACK0B
This is the DMA acknowledgement input pin for the DMARQ0B signal during DMA access of the transmit buffer
and becomes valid in the DMA mode (CR11-B7 = “1”).
Tie this pin to “1” when using this LSI in the frame access mode (CR11-B7 = “0”).
ACK1B
This is the DMA acknowledgement input pin for the DMARQ1B signal during DMA access of the receive buffer
and becomes valid in the DMA mode (CR11-B7 = “1”).
Tie this pin to “1” when using this LSI in the frame access mode (CR11-B7 = “0”).
GPI0, GPI1
These are general-purpose input pins. The state (“1” or “0”) of each of these GPI0 and GPI1 pins can be read out
respectively from CR16-B0 and CR16-B1. Further, GPI0 becomes the input pin for the dial pulse detector
(DPDET) in the secondary functions.
GPO0, GPO1
These are general-purpose output pins. The values set in CR17-B0 and CR17-B1 are output at these pins GPO0
and GPO1, respectively. Further, GPO0 becomes the output pin for the dial pulse generator (DPGEN) in the
secondary functions.
22/31
FEDL7074-001DIGEST-01
OKI Semiconductor
ML7074-001 GA
CLKSEL
This is the input/output control input pin of SYNC and BCLK. The pin becomes input at “0” level and output at
“1” level.
SYNC
This is the 8 kHz sync signal input/output pin of PCM signals. When CLKSEL is “0”, input continuously an 8 kHz
clock synchronous with BCLK. Further, when CLKSEL is “1”, this pin outputs an 8 kHz clock synchronous with
BCLK. Long frame synchronization is used when CR0-B1 (LONG/SHORT) is “0” and short frame
synchronization is used when it is “1”.
BCLK
This is the shift clock input/output pin for the PCM signal. When CLKSEL is “0”, it is necessary to input to this pin
a clock signal that is synchronous with SYNC. Input a 64 to 2048 kHz clock when the G.711 mode or the G.726
mode has been selected, and input a 128 to 2048 kHz clock when the 16-bit linear mode has been selected. When
CLKSEL is “1”, this pin outputs a clock that is synchronous with SYNC. This pin outputs a 64 kHz clock when the
G.711 mode or the G.726 mode has been selected, and outputs an 128 kHz clock when the 16-bit linear mode or
G.729.A mode has been selected.
Note: The input/output control and frequencies of the above SYNC and BLCK signals will be as shown in Table 1
below.
Table 1 Input/output control of SYNC and BCLK
CLKSEL
“0”
SYNC
BCLK
Remarks
Input a continuous clock after starting the power
supply.
Input
Input
Input a 64 to 2048 kHz clock when G.711 or G.726 is
(8 kHz)
(64 kHz to 2048 kHz) selected.
Input a 128 to 2048 kHz clock when 16-bit linear
mode is selected.
An “L” level is output during the power down mode.
A 64 kHz clock is output when G.711 or G.726 is
selected.
A 128 kHz clock is output when G.729.A or 16-bit
linear mode is selected.
Output
(8 kHz)
Output
(64 kHz or 128 kHz)
“1”
PCMO
This is the PCM signal output pin for the transmitting section. The PCM signal is output in synchronization with
the rising edges of SYNC and BCLK. The PCMO outputs the data only during the valid data segment in the
selected coding format and goes to the high impedance state during all other segments. The basic timing chart of
the PCM I/F mode is shown in Fig. 11. The PCMO output will be in the high impedance state when the mutual
conversion function is not used (CR11-B0 = “0”) or when the PCM I/F mode is not used (CR12-B0 = “0”).
PCMI
This is the PCM signal input pin for the receiving section. The data is entered starting from the MSB by shift on the
falling edge of BCLK.
The basic timing chart of the PCM I/F mode is shown in Fig. 11.
Fix input with “0” or “1” when the mutual conversion function is not used (CR11-B0 = “0”) or when the PCM I/F
mode (CR12-B0 = “0”) is not used.
23/31
FEDL7074-001DIGEST-01
OKI Semiconductor
ML7074-001 GA
16-Bit linear
Long frame synchronization mode (CR0-B1 = "0")
SYNC
(IN/OUT)
BCLK
(IN/OUT)
PCMI
Hi-z
PCMO
16-Bit linear
Short frame synchronization mode (CR0-B1 = "1")
SYNC
(IN/OUT)
BCLK
(IN/OUT)
PCMI
Hi-z
PCMO
G.711 (µ-law, A-law)
Long frame synchronization mode (CR0-B1 = "0")
SYNC
(IN/OUT)
BCLK
(IN/OUT)
PCMI
Hi-z
Hi-z
Hi-z
Hi-z
Hi-z
Hi-z
Hi-z
PCMO
G.711 (µ-law, A-law)
Short frame synchronization mode (CR0-B1 = "1")
SYNC
(IN/OUT)
BCLK
(IN/OUT)
PCMI
Hi-z
PCMO
G.726 (32 kbps)
Long frame synchronization mode (CR0-B1 = "0")
SYNC
(IN/OUT)
BCLK
(IN/OUT)
PCMI
Hi-z
PCMO
G.726 (32 kbps)
Short frame synchronization mode (CR0-B1 = "1")
SYNC
(IN/OUT)
BCLK
(IN/OUT)
PCMI
Hi-z
Hi-z
Hi-z
PCMO
Fig. 11 PCM I/F mode timing diagram
24/31
FEDL7074-001DIGEST-01
OKI Semiconductor
ML7074-001 GA
example of Configuration
Analog I/F mode
TONE_DET0
TONE_DET1
DTMF_REC
TONE0_DET
TONE1_DET
DTMF_DET
DTMF_CODE[3:0]
GSX0
Speech Codec
Bus Control Unit
10kΩ
Linear PCM Codec
Echo Canceller
AIN0N
AIN0P
GSX1
Encoder
G.729.A
TX
Buffer0
AMP0
TXGAIN
A/D
BPF
Sin
Sout
G.726
G.711
TX
Buffer1
LPAD
GPAD
Center
Clip
+
10kΩ
ATTs
-
AIN1N
G.729.A
AMP1
STGAIN
TONE_GEN
(TONEA/B)
AFF
Decoder
G.729.A
RX
Buffer0
10kΩ
10kΩ
Rout
ATTr
Rin
RXGAIN
D/A
LPF
VFRO0
VFRO1
G.726
G.711
RX
Buffer1
AMP2
AMP3
8b
G.729.A
FSK_GEN
A0-A7
16b
Codec
D0-D15
AVREF
PCMI
VREF
CSB
Frame/DMA
Controller
Decoder
G.711
RDB
WRB
FR0B
FR1B
ACK0B
ACK1B
S/P
TIMER
G.726
CR17-B0(GPO0)
DPGEN
DPDET
Control
Register
Encoder
G.711
CR16-B0(GPI0)
DP_DET
MCK
SYNC(8kHz)
P/S
PCMO
PLL
CKGN
DTMF_DET
DTMF_CODE[3:0]
TONE0_DET
TONE1_DET
DP_DET
G.726
SYNC
BCLK
INT
OSC
Power
INTB
CLKSEL
Serial I/F
Function stopped
Cannot be used
Example of settings in the initialization mode
⋅ CR15 = 40
⋅ CR11 = 00h (Frame/10 ms/16B/Speech CODEC = G.729.A)
⋅ Various settings
⋅ CR0 = 09h (OPE_STAT = “1”)
25/31
FEDL7074-001DIGEST-01
OKI Semiconductor
ML7074-001 GA
PCM I/F Mode
TONE_DET0
TONE_DET1
DTMF_REC
TONE0_DET
TONE1_DET
DTMF_DET
DTMF_CODE[3:0]
GSX0
Speech Codec
Bus Control Unit
10kΩ
Linear PCM Codec
Echo Canceller
AIN0N
Encoder
G.729.A
TX
Buffer0
AMP0
TXGAIN
AIN0P
A/D
BPF
Sin
Sout
G.726
G.711
TX
Buffer1
LPAD
GPAD
Center
Clip
GSX1
+
10kΩ
ATTs
-
AIN1N
G.729.A
AMP1
STGAIN
TONE_GEN
(TONEA/B)
AFF
Decoder
G.729.A
RX
Buffer0
10kΩ
Rout
ATTr
Rin
RXGAIN
D/A
LPF
VFRO0
G.726
G.711
RX
Buffer1
AMP2
10kΩ
8b
VFRO1
G.729.A
FSK_GEN
A0-A7
AMP3
16b
Codec
D0-D15
VRE
AVREF
F
CSB
Frame/DMA
Controller
Decoder
G.711
RDB
WRB
FR0B
FR1B
ACK0B
ACK1B
S/P
PCMI
TIMER
G.726
CR17-B0(GPO0)
DPGEN
DPDET
Control
Register
Encoder
G.711
CR16-B0(GPI0)
DP_DET
MCK
SYNC(8kHz)
P/S
PCMO
PLL
CKGN
DTMF_DET
DTMF_CODE[3:0]
TONE0_DET
TONE1_DET
DP_DET
G.726
SYNC
BCLK
INT
OSC
Power
INTB
CLKSEL
Serial I/F
Function stopped
Cannot be used
Examples of settings in the initialization mode
⋅ CR15 = 40
⋅ CR10 = 00h (VFRO1 = AVREF/VFRO0 = AVREF)
⋅ CR11 = 00h (Frame/10 ms/16B/PCMIF = 16-bit linear)
⋅ CR12 = 01h (Speech CODEC = G.729.A/PCMIF_EN = “1”)
⋅ Various settings
⋅ CR0 = 29h (AFE_EN = Power down/LONG/OPE_STAT = “1”)
26/31
FEDL7074-001DIGEST-01
OKI Semiconductor
ML7074-001 GA
G.729.A ↔ G.726 Mutual Conversion
TONE0_DET
TONE1_DET
TONE_DET0
TONE_DET1
DTMF_REC
DTMF_DET
DTMF_CODE[3:0]
GSX0
Speech Codec
Bus Control Unit
10kΩ
Linear PCM Codec
AIN0N
Echo Canceller
Encoder
G.729.A
TX
Buffer0
AMP0
TXGAIN
AIN0P
A/D
BPF
Sin
Sout
G.726
G.711
TX
Buffer1
LPAD
GPAD
Center
Clip
GSX1
+
10kΩ
ATTs
-
AIN1N
G.729.A
AMP1
TONE_GEN
(TONEA/B)
STGAIN
AFF
Decoder
G.729.A
RX
Buffer0
10kΩ
10kΩ
Rout
ATTr
Rin
RXGAIN
D/A
LPF
VFRO0
VFRO1
G.726
G.711
RX
Buffer1
AMP2
AMP3
8b
G.729.A
FSK_GEN
A0-A7
16b
Codec
D0-D15
AVREF
PCMI
VREF
CSB
Frame/DMA
Controller
Decoder
G.711
RDB
WRB
FR0B
FR1B
ACK0B
ACK1B
S/P
TIMER
G.726
CR17-B0(GPO0)
DPGEN
DPDET
Control
Register
Encoder
G.711
CR16-B0(GPI0)
DP_DET
MCK
SYNC(8kHz)
P/S
PCMO
PLL
CKGN
DTMF_DET
DTMF_CODE[3:0]
TONE0_DET
TONE1_DET
DP_DET
G.726
SYNC
BCLK
INT
OSC
Power
INTB
CLKSEL
Serial I/F
Function stopped
Cannot be used
Examples of settings in the initialization mode
⋅ CR15 = 40
⋅ CR11 = 05h (Frame/10 ms/16B/G.726/TRANS_EN= “1”)
⋅ CR10 = 00h (VFRO1 = AVREF/VFRO0 = AVREF)
⋅ Various settings
⋅ CR0 = 29h (AFE_EN = Power down/LONG/OPE_STAT = “1”)
27/31
FEDL7074-001DIGEST-01
OKI Semiconductor
ML7074-001 GA
EXAMPLE OF APPLICATION CIRCUIT
1.4V
50
41
40
39
38
37
36
35
34
A7
A6
A5
A4
A3
A2
A1
A0
AIN0P
51
AIN0N
52
53
Analog
input
GSX0
GSX1
54
55
AIN1N
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
D15
D14
D13
D12
D11
D10
D9
AVREF
56
57
VFRO0
VFRO1
Analog
output
D8
D7
General-
purpose
input pins
MCU
I/F
45
46
47
48
GPI0
D6
GPI1
D5
General-
purpose
output pins
GPO0
GPO1
D4
D3
D2
+3.3V
D1
ML7074-001
CLKSEL
D0
43
4
+3.3V
PCMI
8
9
3
PCM
I/F
ACK0B
ACK1B
open
PCMO
BCLK
5
open
open
6
SYNC
10
11
12
FR0B
FR1B
INTB
Power down control
42
PDNB
4.096 MHz
crystal
13
14
15
oscillator
60
61
CSB
RDB
WRB
XI
XO
+3.3V
7
DVDD0
DVDD1
DVDD2
AVDD
33
62
49
Conditions:
- When using analog
interface
- Frame mode
- SYNC and BCLK are
output (CLKSEL="1")
63
64
1
16
44
59
58
TST3
TST2
TST1
TST0
DGND0
DGND1
DGND2
AGND
2
28/31
FEDL7074-001DIGEST-01
OKI Semiconductor
ML7074-001 GA
PACKAGE DIMENSIONS
(Unit: mm)
QFP64-P-1414-0.80-BK
Mirror finish
Package material
Lead frame material
Pin treatment
Package weight (g)
Rev. No./Last Revised
Epoxy resin
42 alloy
Solder plating (J5µm)
0.87 TYP.
6/Feb. 23, 2001
5
Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow mounting and humidity
absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product
name, package name, pin number, package code and desired mounting conditions (reflow method,
temperature and times).
29/31
FEDL7074-001DIGEST-01
OKI Semiconductor
ML7074-001 GA
REVISION HISTORY
Page
Previous
Edition
Document
No.
Date
Oct. 15, 2002
Description
Current
Edition
FEDL7074-001-01
–
–
Final edition 1
30/31
FEDL7074-001DIGEST-01
OKI Semiconductor
ML7074-001 GA
NOTICE
1. The information contained herein can change without notice owing to product and/or technical improvements.
Before using the product, please make sure that the information being referred to is up-to-date.
2. The outline of action and examples for application circuits described herein have been chosen as an
explanation for the standard action and performance of the product. When planning to use the product, please
ensure that the external conditions are reflected in the actual circuit, assembly, and program designs.
3. When designing your product, please use our product below the specified maximum ratings and within the
specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating
temperature.
4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation
resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or
unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified
maximum ratings or operation outside the specified operating range.
5. Neither indemnity against nor license of a third party’s industrial and intellectual property right, etc. is
granted by us in connection with the use of the product and/or the information and drawings contained herein.
No responsibility is assumed by us for any infringement of a third party’s right which may result from the use
thereof.
6. The products listed in this document are intended for use in general electronics equipment for commercial
applications (e.g., office automation, communication equipment, measurement equipment, consumer
electronics, etc.). These products are not authorized for use in any system or application that requires special
or enhanced quality and reliability characteristics nor in any system or application where the failure of such
system or application may result in the loss or damage of property, or death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace
equipment, nuclear power control, medical equipment, and life-support systems.
7. Certain products in this document may need government approval before they can be exported to particular
countries. The purchaser assumes the responsibility of determining the legality of export of these products
and will take appropriate and necessary steps at their own expense for these.
8. No part of the contents contained herein may be reprinted or reproduced without our prior permission.
Copyright 2002 Oki Electric Industry Co., Ltd.
31/31
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