ML70512LA [OKI]
Bluetooth Baseband Controller IC; 蓝牙基带控制器IC![ML70512LA](http://pdffile.icpdf.com/pdf1/p00180/img/icpdf/ML705_1011919_icpdf.jpg)
型号: | ML70512LA |
厂家: | ![]() |
描述: | Bluetooth Baseband Controller IC |
文件: | 总29页 (文件大小:331K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
FEDL70512-04
Issue Date: Sep. 2, 2003
OKI Semiconductor
ML70512
Bluetooth Baseband Controller IC
GENERAL DESCRIPTION
The ML70512 is a CMOS digital IC for use in 2.4 GHz band Bluetooth™ systems. This IC incorporates the
ARM7TDMI as the CPU core, features a highly expandable architecture, and supports the interfaces for a variety
of applications. Since the ML70512 has Oki’s Bluetooth protocol stack software installed, when the IC is used in
conjunction with the Bluetooth RF transceiver IC, data/voice communications are possible while maintaining
interconnectivity with other Bluetooth systems.
FEATURES
• Conforms to Bluetooth Specification (Ver1.1)
• Designed for connection with the RF-LSI interface, such as the OKI RF-LSI interface (ML7050, ML70561), the
SKYWORKS RF-LSI interface (CX72303), or the BROADCOM RF-LSI interface (BCM2002X) that functions
as the Bluetooth RF-LSI interface
• The high-speed, low-power ARM7TDMITM is installed as the CPU core
• PCM-CVSD transcoder that provides high quality voice using the noise filter is installed
• Low power consumption in flexible power management modes according to operating modes of Bluetooth
• DETACH signal provides control of change to power-saving mode (STOP) and return request to normal mode.
• UART interface corresponding to baud rates up to 921.6 kbps
• I2C bus interface provides accesses to EEPROM or PCM-Codec
• Selactable 12 MHz, 13 MHz, or 16 MHz for the system clock
• Selectable 32 kHz or 32.768 kHz for the LPO clock
• Built-in programmed ROM eliminates external ROM/FLASH
• The packages are available in two types:
83-pin WCSP for ML70512HB
84-pin BGA for ML70512LA
ARM, ARM7TDMI and Thumb are registered trademarks of ARM Ltd., UK.
BLUETOOTH is a trademark owned by Bluetooth SIG, Inc. and licensed to Oki Electric Industry.
The information contained herein can change without notice owing to the product being under development.
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FEDL70512-04
OKI Semiconductor
ML70512
SPECIFICATIONS
Process
Package
0.16 µm CMOS (5-layer metal wire)
83-pin WCSP (P-VFLGA83-6.22×6.22-0.50-W)
(Dimensions: 6.22 mm × 6.22 mm × 0.48 mm; pin pitch: 0.50 mm)
84-pin BGA (P-LFBGA84-0909-0.80)
(Dimensions: 9 mm × 9 mm × 1.5 mm; pin pitch: 0.80 mm)
23.4 mA (24 MHz operation)
Supply current
Operating voltage ranges
2.70 to 3.6 V for input-output, 1.65 to 1.95 V for internal circuits
24 MHz
Operating frequency
Built-in ROM size
Built-in RAM size
Input clocks
384 KB (for ARM program)
72 KB
12 MHz, 13 MHz, or 16 MHz (system clock)
32 kHz or 32.768 kHz (LPO clock)
OKI RF-LSI interface (ML7050, ML70561)
SKYWORKS RF-LSI interface (CX72303)
BROADCOM RF-LSI interface (BCM2002X)
UART interface (up to 921.6 Kbps)
General-purpose I/O interface (Bits 0 and 1 are used as a pin for I2C bus
interface
RF-LSI interface
Installed interfaces
depending on software installed)
PCM interface (PCM Linear/A-law/µ-law can be selected)
DETACH interface
Timers
16-bit auto reload timer (1ch)
18-bit auto reload timer (3ch)
Interrupt controller
Clock control circuit
11 causes
Crystal oscillator circuit (12 MHz, 13 MHz, or 16 MHz, 32 kHz or 32.768
kHz)
Internal PLL
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ML70512
PIN PLACEMENT
ML70512HB: 83-pin WCSP (P-VFLGA83-6.22 × 6.22-0.50-W)
Core
VDD
Core
VDD
Core
VDD
PCM
GND
GND
CIO4
RTS
GND SCLKO
RFSEL2
GND
SYNC
10
9
CIO1
(SDA)
CIO0
(SCL)
PCM
OUT
PCM
CLK
RFSEL0
CIO5
GND
GND
CIO3
Core
VDD
PCMIN
RFSEL1
GND
VDD CIO2
GND
RESET
VDD
DETACH
SCLKN
AGND0
8
7
Core
VDD
GND
SIN
GND
CTS
SFRQ
SEL1
CIO6
VDD
SCLKP
6
5
4
Core
VDD
AGND0
AGND1
AVDD0
AVDD1
GND
VDD
LVDD
SOUT
PLL_
CLK
RSSI
_CLK
AVDD0
PLL_
PLL_
POW
Core
VDD
PLL
GND
RSSI
GND
GND
AVDD1 AGND1
Core
DATA
LOCK
3
2
SFRQ
SEL0
PLL_
OFF
RX_
POW
VDD
GND
RXD
GND
VDD
PLL_PS
TXD
GND
TX_
POW
SCLK
Core
VDD
VDD
PLL_LE
B
VDD XC32KN
XC32KP
SEL
1
C
D
E
F
G
H
J
K
A
TOP VIEW
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OKI Semiconductor
ML70512
ML0512LA: 84-pin BGA (P-TFBGA84-0909-0.80)
Core
VDD
GND AVDD1
AGND1 AVDD0
SCLKN
RFSEL0
CIO4
RFSEL2
RESET
AGND0
10
9
AGND1
SCLK
XC32KP
GND
GND
RTS
AGND0
AVDD0
CTS
VDD
AVDD1
Core
VDD
VDD XC32KN
SCLKP
GND
Core
CIO2
RFSEL1
CIO0
DETACH
SEL
8
7
SFRQ
SEL0
CIO1
(SDA)
GND
VDD
GND
(SCL) VDD
Core
VDD
CIO5
GND
VDD
VDD
6
5
4
PLL
Core
VDD
PCMIN
GND
PCM
RSSI
RXD
LOCK
PCM
OUT SYNC
PCMCLK
SCLKO
CIO3
GND
TXD
GND
Core
VDD
Core
NC
PLL_
DATA
PLL_LE
VDD
LVDD
GND
PLL_PS
CIO6
NC
VDD
3
2
RX_
POW
RSSI_
CLK
TX_
POW
SFRQ
SEL1
GND
GND
GND
GND
VDD
VDD
Core
VDD
PLL_
POW
PLL_
OFF
PLL_
CLK
SIN
F
GND
H
SOUT
E
1
C
D
J
K
B
G
A
TOP VIEW
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ML70512
PIN DESCRIPTIONS
RF I/F
Internal
Pull Up/
Down,
Pin Placement
Direc-
tion
[*0]
Initial
Value
Pin Name
Description
ML70512HB ML70512LA
Schmitt
L
L
L
ML7050: Transmit data output
CX72303: Transmit data output
BCM2002X: Transmit data output
ML70561: Transmit data output
ML7050: Receive data input
CX72303: Receive data input
BCM2002X: Receive data input
ML70561: Receive data input
ML7050: Serial write data
CX72303: Serial write data
BCM2002X: Transmit enable
ML70561: Transmit enable (Active H)
ML7050: Serial clock
TXD
O
I
—
—
—
—
C1
D1
A3
B4
A4
A5
C3
C1
L
—
—
—
—
X
H
L
RXD
PLL_DATA
PLL_CLK
O
O
L
L
L
L
CX72303: Serial clock
BCM2002X: Serial clock
L
ML70561: Serial clock
ML7050: Serial road enable
0: Negate, 1: Assert
CX72303: Serial enable
0: Assert, 1: Negate
BCM2002X: RF-LSI synthesizer on
0: Negate, 1: Assert
L
H
L
PLL_LE
O
—
B1
A3
L
ML70561: RF-LSI synthesizer on
0: Negate, 1: Assert
ML7050: Receive field strength data
input
—
—
—
—
RSSI
I
—
—
E2
C4
C5
C2
CX72303: Serial read data
BCM2002X: Serial read data
ML70561: Serial read data
ML7050: Receive field strength data
clock
H
L
CX72303: RF-LSI receiving
characteristic control
RSSI_CLK
O
H
H
H
BCM2002X: System clock request
ML70561: System clock request
ML7050: Local PLL power control
0: Assert, 1: Negate
L
CX72303: PA Power control
0: Negate, 1: Assert
PLL_POW
O
—
B3
A1
H
H
BCM2002X: Select serial transmit mode
ML70561: Select serial transmit mode
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FEDL70512-04
OKI Semiconductor
ML70512
Internal
Pull Up/
Down,
Pin Placement
Direc-
tion
[*0]
Initial
Value
Pin Name
TX_POW
Description
ML70512HB ML70512LA
Schmitt
H
L
ML7050: Transmit enable
0: Assert, 1: Negate
CX72303: Transmit enable
0: Negate, 1: Assert
BCM2002X: Serial write data
ML70561: Serial write data
ML7050: Receive enable
0: Assert, 1: Negate
CX72303: Receive enable
0: Negate, 1: Assert
O
O
—
—
A1
B2
A2
B2
L
L
H
L
RX_POW
L
L
BCM2002X: Receive enable
ML70561: Receive enable
[*0]
“I” = Input, “O” = Output, “I/O” = Input/Output
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FEDL70512-04
OKI Semiconductor
ML70512
RF I/F
Internal
Pull Up/
Down,
Pin Placement
ML70512H
Direc-
tion
[*0]
Initial
Value
Pin Name
Description
ML70512LA
B
Schmitt
L
L
ML7050: ”L”
CX72303: Power on reset
0: Assert (reset) 1: Negate
BCM2002X: RF-LSI receiving
characteristic control
PLL_PS
O
—
C2
B3
L
L
ML70561: SYNCWORD detection
ML7050: —
CX72303: —
BCM2002X: 1MHz clock
ML70561: Clock for 1 MHz transmit data
ML7050: PLL loop control
0: Open loop 1: Closed loop
CX72303: Diversity output
BCM2002X: PA Power control
ML70561: PA Power control
—
—
—
—
PLLLOCK
PLL_OFF
I
—
—
H3
A2
B5
B1
H
—
O
L
L
CLK and Configuration
Internal
Pin Placement
ML70512HB ML70512LA
Direc-
tion
Initial
Value
Pull Up/
Down,
Schmitt
—
Pin Name
Description
SCLKP
SCLKN
XC32KP
XC32KN
I
—
—
—
—
K6
J7
F8
F10
A9
System clock (12/13/16 MHz) pins
(Power level: CMOS level)
O
I
—
—
K1
H1
Subclock pins (for oscillator)
O
—
B8
System clock frequency select pin
L: Select CLK divided by internal PLL
H:Select subclock
SCLKSEL
I
I
—
—
—
J1
C8
System clock (SCLK) frequency select/
BCM crystal frequency select pins
SCLK
input
frequency
(RFSEL ≠
101)
BCM
crystal
frequency
(RFSEL =
101)
SFRQSEL
[1:0]
SFRQSEL
0–1
—
*[1]
*[2]
00
01
10
11
13 MHz
12 MHz
16 MHz
Reserved
19.68 MHz
19.2 MHz
19.8 MHz
13 MHz
RF-LSI select pins
RFSEL[2:0]
RF-LSI
001
010
011
ML7050 (OKI)
CX72303 (SKYWORKS)
ML70561 (OKI)
BCM2002X
(BROSDCOM)
RFSEL
0–2
I
—
—
*[3]
*[4]
101
Others
Reserved
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FEDL70512-04
OKI Semiconductor
ML70512
CLK and Configuration
Internal
Pull Up/
Down,
Schmitt
Schmitt
Schmitt
Pin Placement
Direc-
tion
Initial
Value
Pin Name
Description
ML70512HB ML70512LA
RESET
I
I
—
—
K8
J8
G10
G8
Hardware reset pin (Reset = L)
Sleep pin (Sleep = L)
DETACH
System clock (12/13/16 MHz) output
pins
SCLKO
O
—
—
B10
H3
[*1] SFRQSEL0: G2; SFRQSEL1: A6
[*2] SFRQSEL0: C7; SFRQSEL1: F2
[*3] RFSEL0: J9; RFSEL1: H8; RFSEL2: K10
[*4] RFSEL0: H10; RFSEL1: H8; RFSEL2: K10
PCM I/F
Internal
Pin Placement
ML70512HB ML70512LA
Direc-
tion
Initial
Value
Pull Up/
Down,
Schmitt
—
Pin Name
Description
PCMOUT
PCMIN
O
I
L
C9
E8
J4
PCM data output
Pull up
—
H5
PCM data input
PCM sync signal (8 kHz),
Initial setting: input
(can be switched by an internal register)
PCM clock (64 kHz/128 kHz)
Initial setting: input
Pull
down
PCMSYNC
PCMCLK
I/O
I/O
—
—
D10
D9
K4
H4
Pull
down
(can be switched by an internal register)
Note: The PCM sync signal (8 kHz) must be guaranteed at the accuracy of ±50 ppm if the PCMSYNC pin is
configured as an input.
UART I/F
Internal
Pin Placement
Direc-
tion
Initial
Value
Pull Up/
Down,
Schmitt
—
Pin Name
Description
ML70512HB ML70512LA
SOUT
SIN
O
I
H
—
—
H
B5
B7
E1
F1
K9
J9
ACE transmit serial data
ACE receive serial data
ACE transmit data ready
ACE transmit ready
Schmitt
—
RTS
CTS
O
I
J10
H6
—
8/29
FEDL70512-04
OKI Semiconductor
ML70512
Port
Internal
Pull Up/
Down,
Pin Placement
Direc-
Pin Name
Initial
Value
Description
tion
ML70512HB ML70512LA
Schmitt
CIO0
I/O
—
—
H
F9
H7
K7
I2C serial clock (output)
I2C serial data (input)
(SCL)
CIO1
I/O
—
G9
(SDA)
CIO2
CIO3
CIO4
CIO5
CIO6
I/O
I/O
I/O
I/O
I/O
—
—
—
—
—
—
L
G8
B8
H9
E9
B6
K8
H2
H9
H6
F3
General port (initial state: input)
General port (initial state: output)
General port (initial state: output)
General port (initial state: input)
General port (initial state: input)
H
—
—
NC
Internal
Pull Up/
Down,
Schmitt
—
Pin Placement
Direc-
tion
Initial
Value
Pin Name
NC
Description
ML70512HB ML70512LA
[*4]
—
—
—
No connection
[*4] NC: E3, J3
Note: Do not wire under the NC pin.
9/29
FEDL70512-04
OKI Semiconductor
ML70512
Power, GND
Internal
Pull Up/
Down,
Schmitt
—
Pin Placement
Direc-
Pin Name
Initial
Value
Description
tion
ML70512HB ML70512LA
VDD
—
—
—
—
[*5]
[*7]
[*6]
[*8]
I/O power supply pin 2.70 to 3.6 V
Power supply pin for internal circuit
1.65 to 1.95 V
CoreVDD
—
—
RF-I/O power suply pin (Same voltage
to the VDD for RF-LSI)
LVDD
GND
—
—
C5
D2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
[*9]
[*10]
[*12]
[*14]
[*16]
[*18]
Digital block ground pin
AVDD
0
1
[*11]
[*13]
[*15]
[*17]
Analog block power supply pin
1.65 to 1.95 V
AVDD
AGND0
AGND1
Analog block ground pin
[*5]
[*6]
V
V
DD: A4, C6, F1, F8, G1, H2, K7
DD: A8, B7, C6, D3, E2, F9, K1, K6
[*7] Core VDD: A8, C7, C10, D3, E1, E10, G10, K2, K5
[*8] Core VDD: A6, E8, G1, G3, J7, J10, K3, K5
[*9] GND: A5, A7, A9, A10, B9, C8, D2, D8, E3, F2, F3, F10, G3, H7, H10, J2, K9
[*10] GND: A7, A10, B4, B6, C4, D1, E9, G2, G9, H1, J1, J2, J5, J6, J8, K2
[*11] AVDD0: H5, K4
[*12] AVDD0: D8, D10
[*13] AVDD1: H4, J3
[*14] AVDD1: B9, B10
[*15] AGND0: J5, J6
[*16] AGND0: D9, E10
[*17] AGND1: J4, K3
[*18] AGND1: C9, C10
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OKI Semiconductor
ML70512
BLOCK DIAGRAM
ML70512
DETACH
UART I/F
GPIO I/F
Clock
11/29
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OKI Semiconductor
ML70512
DESCRIPTION OF INTERNAL BLOCKS
CLKGEN Block
• Generates a clock that is supplied to each block through SCLKP (12/13/16 MHz)
• STOP/HALT function
CTL/WDT Block
• Control of the frequency division function of the internal main clock
• Control of clock supplied to each peripheral
• Control of reset of each peripheral
• STOP/HALT control
• Watchdog timer function (interrupt/reset)
Timer Block
• 3 channels
• 18-bit timer counter
• Interrupt by compare function
• One shot, interval, or free-run mode
Base band Core Block
RF LSI
Tx SCO Buffer
Packet
TXD
CNT
Codec
Audio
Composer
Tx ACL Buffer
I/F
RF
FHCNT
Security
Timing
CNT
ARM
I/F
APB
Rx SCO Buffer
Rx ACL Buffer
Packet
Decomposer
RXD
• RF Controller
- RF power supply control (PLL, TX, RX)
- Local PLL frequency division ratio setting
- Receive clock regeneration function
- Synchronization detection (synchronizing within the permissable error limit of SyncWord)
- Receive clock re-timing function
• FH Controller hopping
- Sequence control
- Frequency hopping selection function
- CRC computation's initial value selection function
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ML70512
• Timing Generator
- Bluetooth clock generation
- Operation interrupts depend on mode (slot, scan, sniff, hold, park)
- Sync detection timing generation (sync window ±10 µs)
- PLL setting timing generation
- Transmit/Receive timing generation
- Multi-master timing management function
• Packet Composer
- Access code generation (SyncWord generation, appending PR*TRAILER)
- Packet header generation (HEC generation, scrambling, FEC encoding)
- Payload generation (CRC generation, encryption, scrambling, FEC encoding)
- Packet synthesis
• Packet Decomposer
- Packet decomposition (separating the packet header and the payload)
- Packet header processing (FEC decoding, descrambling, HEC error detection, header information
separation)
- Payload processing (FEC decoding, descrambling, encryption decoding, CRC judgement, payload
separation)
• Security
- Various key generation functions (initialization, link key, encryption key)
- Certification function
- Encryption function
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OKI Semiconductor
ML70512
UART Block
• Full-duplex buffering method
• All status reporting function
• Built-in 64-byte transmit/receive FIFO
• Modem control based on CTS
• Programmable serial interface
• 5-, 6-, 7-, 8-bit characters
• Generation and verification of odd parity, even parity, or no parity
• 1, 1.5, or 2 stop bits
• Programmable Baud Rate Generator (9600 bps to 921.6 kbps)
• Error servicing for parity, overrun, and framing errors
• Configuration of 1 Data Frame during Reception
5 data bits to
SIN
SAMPLE CLK
Start
Stop
Parity
8 data bits
• Configuration of 1 Data Frame during Transmission
5 data bits to
SOUT
Start
Stop
Parity
8 data bits
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ML70512
PCM-CVSD Transcoder Block
• Application side I/O:
- PCM Codec
• Application-side format:
- PCM linear (8, 14, 16 bits/sample, 8 kHz sampling frequency)/A-law/µ-law
• Bluetooth-side format:
- CVSD/A-law/µ-law
• All combinations of the above conversions are supported
• PCMSYNC/PCMCLK I/O can be switched (initial setting: input)
• Timing in Short Mode and in PCMCLK and PCMSYNC Output Mode
(For PCM data of 14 bits/sample, lower 2 bits of 16 bits are invalid.)
8 bits or 16 bits
PCMCLK(O)
64k/128kHz
PCMOUT
LSB
LSB
MSB
Data is output on the rising edge of CLK.
MSB DATA DATA
DATA
DATA
DATA
DATA
LSB
LSB
MSB
MSB
DATA
DATA
PCMIN
Data is shifted in on the falling edge of CLK
PCMSYNC(O)
125µs (8kHz)
• Timing in Short Mode and in PCMCLK and PCMSYNC Input Mode.
(For PCM data of 14 bits/sample, lower 2 bits of 16 bits are invalid.)
8 bits or 16 bits
PCMCLK(I)
64k/128kHz
PCMOUT
LSB
LSB
MSB
Data is output on the rising edge of CLK.
MSB DATA DATA
DATA
DATA
DATA
DATA
LSB
LSB
MSB
MSB
DATA
DATA
PCMIN
Data is shifted in on the falling edge of CLK
PCMSYNC(I)
125µs (8kHz)
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ML70512
• Timing in Long Mode and in PCMCLK and PCMSYNC Output mode
(For PCM data of 14 bits/sample, lower 2 bits of 16 bits are invalid.)
8 bits or 16 bits
PCMCLK(O)
64k/128kHz
MSB
MSB
DATA
DATA
DATA
DATA
LSB
MSB
MSB
DATA
DATA
PCMOUT
Data is shifted in on the falling edge of CLK
Data is output on the rising edge of CLK
DATA
DATA
DATA
DATA
LSB
PCMIN
PCMSYNC(O)
PCMCLK period × 3
125µs (8kHz)
• Timing in Long Mode and in PCMCLK and PCMSYNC Input Mode.
(For PCM data of 14 bits/sample, lower 2 bits of 16 bits are invalid.)
8 bits or 16 bits
PCMCLK(I)
64k/128kHz
MSB
Data is output on the rising edge of CLK.
MSB DATA DATA DATA
DATA
DATA
DATA
DATA
LSB
MSB
MSB
DATA
DATA
PCMOUT
Data is shifted in on the falling edge of CLK.
DATA
LSB
PCMIN
≥ PCMCLK period (Min.) or ≤ 62.5 µs (Max.)
125µs (8kHz)
DETACH Interface Block
• Generation of the request for change to (from) the stop mode by detection of the rising (falling) edge of
the DETACH signal
• Generation of the request for restore from the stop mode by detection of a SIN signal level change
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ML70512
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Conditions
—
Rating
Unit
V
I/O power supply voltage
VDD/LVDD
–0.3 to +4.5
Core power supply voltage
Input voltage
CoreVDD/AVDD
—
—
—
—
–0.3 to +2.5
–0.3 to +4.5
0.62
V
V
VI
Pd
Allowable power dissipation
Storage temperature
W
°C
Tstg
–55 to 150
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
VDD/LVDD
CoreVDD/AVDD
Vih
Conditions
Min. Typ. Max.
Unit
V
I/O power supply voltage
Core power supply voltage
“H” level input voltage
“L” level input voltage
Operating temperature
—
—
—
—
—
2.7
1.65
2.2
0
3.3
1.8
—
3.6
1.95
VDD
0.8
V
V
Vil
—
V
Ta
–40
—
85
°C
ELECTRICAL CHARACTERISTICS
DC Characteristics
(VDD = 2.7 to 3.6 V, CoreVDD = 1.65 to 1.95 V, Ta = –40 to +85°C)
Parameter
Symbol
Conditions
Min. Typ. Max. Unit
“H” level output voltage
Ioh =
–2 mA
3.0V≤Vdd≤3.6V
2.4
—
—
Voh
V
V
2.7V≤Vdd<3.0V
2.2
—
—
—
—
—
0.4
10
“L” level output voltage
Input leakage current
Vol
Iol = 2 mA
Vi = GND to 3.6 V
Vi = VDD
50 kΩ Pull-down
Vi = GND
50 kΩ Pull-up
Vo = GND to VDD
Vo = VDD
–10
10
66
200
Ii
µA
µA
–200 –66
–10
10
Output leakage current
–10
10
—
Io
66
200
50 kΩ Pull-down
Power supply current (during
operation)
Iddo
Idds
During 24 MHz operation
CLK stopped
0
23.4
50
33
mA
Power supply current (during
stand-by)
—
250
µA
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ML70512
Power Supply Current (IDDO) Characteristics by Power Saving Mode
(VDD = 2.7 V to 3.6V, CoreVDD = 1.65 V to 1.95V, Ta = -40 to 85°C)
Operating mode
Conditions
—
Min. Typ. Max.
Unit
STOP mode (DETACH = "L")
—
—
—
—
0.05
—
—
—
—
Interval:1.28sec
Window:22.5msec
Interval:40slot
Interval:2000slot
Attempt:4frame
Interval:4000slot
DH1/DM1
Page Scan operating mode
Poll Interval operating mod
Sniff operating mode
1.5
12.1
1.7
mA
Hold operating mode
—
—
4.9
—
—
23.4
RX:DH3/DM3
TX:DH1/DM1
RX:DH5/DM5
TX:DH1/DM1
—
—
20.5
19.6
—
—
ACL operating mode
AC Characteristics
~ System clock (SCLKP)
SCLKP
Tmc0 Tmc1
(VDD = 2.7 to 3.6V, CoreVDD = 1.65 to 1.95V, Ta = -40 to 85°C)
Description Min Typ Max Unit
Parameter
Tmc0
Tmc1
Duty in SCLKP “H” duration
Duty in SCLKP “L” duration
40
40
50
50
60
60
%
%
~ Sub-clock (XC32KP)
XC32KP
Tmp0
Tmp1
(VDD = 2.7 to 3.6V, CoreVDD = 1.65 to 1.95V, Ta = -40 to 85°C)
Description Min Typ Max Unit
Parameter
Tmp0
Tmp1
Duty in XC32KP “H” duration
Duty in XC32KP “L” duration
40
40
50
50
60
60
%
%
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ML70512
~ Reset
Power supply stable period
Vdd/LVdd
CoreVdd/AVdd
TRESW
RESET
(VDD = 2.7 to 3.6V, CoreVDD = 1.65 to 1.95V, Ta = -40 to 85°C)
Description Min Typ Max Unit
10 µs
Parameter
TRESW
Reset pulse width
—
—
Note : Apply "L" to the RESET pin for 10 µsec or more after the power supply has been settled.
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ML70512
~ PCM interface
PCMCLK(I)
PCMIN
Tpc0
Tpc1
PCMOUT
Tpc2
Tpc4
Tpc2
Tpc4
PCMSYNC(I)
Tpc3
Tpc3
PCMCLK(O)
PCMIN
Tpc6
Tpc5
PCMOUT
Tpc7
Tpc 7
Tpc 8
PCMSYNC(O)
(Vdd = 2.7 to 3.6V, CoreVdd = 1.65 to 1.95V, Ta = -40 to 85°C)
Description Min Typ Max Unit
Parameter
Tpc0
PCMIN setup time relative to PCMCLK (input) falling edge
PCMIN hold time relative to PCMCLK (input) falling edge
PCMOUT delay time relative to PCMCLK (input) rising edge
PCMSYNC (input) setup time relative to PCMCLK (input)
rising edge
100
100
—
—
—
—
—
—
ns
ns
ns
Tpc1
Tpc2
250
Tpc3
Tpc4
100
100
—
—
—
—
ns
ns
PCMSYNC (input) hold time relative to PCMCLK (input)
rising edge
Tpc5
Tpc6
PCMIN setup time relative to PCMCLK (output) falling edge 100
—
—
—
—
ns
ns
PCMIN hold time relative to PCMCLK (output) falling edge
100
PCMOUT delay time relative to PCMCLK (output) rising
edge
Tpc7
Tpc8
—
—
—
250
150
ns
ns
Delay time from PCMCLK (output) rising edge to PCMSYNC
(output)
—
~ AC Characteristic Measuring Points
VDD
0.8VDD
0.8VDD
0.2VDD
0.2VDD
0 V
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ML70512
REFERENCE FOR VOLTAGE SUPPLY CIRCUIT
ML70512
AVDD0
0.1µF
AGND0
AVDD1
0.1µF
AGND1
CoreVDD
CoreVDD
10 to 47µF
10 to 47µF
0.1µF
0.1µF
0.1µF
0.1µF
LVDD
VDD
GND
VDD
GND
10 to 47µF
0.1µF
0.1µF
Capacitors should locate close to LSI pins.
Feed lines should be separated
from LSI pins.
Example of ML70512 voltage supply circuit
• Insert appropriate bypass capacitors between the VDD and GND lines.
Note 1: Precautions to insert the bypass capacitors
- Use traces of VDD and GND lines wider than those of the other signal lines.
- Keep the length of traces between the bypass capacitors and the VDD line and between the bypass
capacitors and the GND line as short as possible.
- Keep the length of traces between the bypass capacitors and the VDD line and between the bypass
capacitors and the GND line as equal as possible.
The circuit is subject to change according to the specific LSI board design. Please contact Oki Electric Industry Co.,
Ltd. for detailed information.
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ML70512
REFERENCE FOR OSCILLATOR CIUCUIT
ML70512
R0
R2
R1
R3
C3
X’tal 1
X’tal 2
C1
C0
C2
Connect this oscillator circuit only when
connecting the OKI RF-LSI ML7050.
Example of oscillator circu
Note 1: The values of C0 and C1, and R0 and R1 should be determined according to the specifications for the
external crystal X’tal 1 (32 or 32.768 kHz).
The values of C2 and C3, and R2 and R3 should be determined according to the specifications for the
external crystal X’tal 2 (12, 13, or 16 MHz).
Note 2: The crystal oscillator circuit should be connected to pins SCLKP and SCLKN only when the OKI RF-LSI
(ML7050) is connected. In other cases, the system clock should be input from the RF-LSI to pin SCLKP.
Note 3: In the case of 12 MHz, 13 MHz, or 16 MHz system clock (SCLKP) input, make sure the crystal frequency
tolerance is ±20 ppm for temperature, supply voltage, and aging.
In the case of 32 kHz or 32.768 kHz sub-clock (XC32KP) input, make sure the crystal frequency tolerance
is ±250 ppm for temperature, supply voltage, and aging.
Note 4: Precautions to build a crystal oscillator circuit
- Keep length of wire traces as short as possible.
- Do not cross the crystal oscillator circuit wires over other signal line wires.
- Do not keep signal line wires through which high current flows close to the crystal oscillator circuit.
- Keep the grounding point of the capacitors in the oscillator circuit at the potential equal to GND. And do
not connect the capacitors to the GND or GND lines through which high current flows.
- Do not output signals from the oscillator circuit.
The circuit is subject to change according to the specific LSI board design. Please contact Oki Electric Industry Co.,
Ltd. for detailed information. It is recommended to determine the final circuit values including the capacitance of
the circuit board designed by the user.
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ML70512
APPLICATION NOTES
Clock Selection
• The system clock frequency is selected according to external pin SFRQSEL.
SFRQSEL = 00
SFRQSEL = 01
SFRQSEL = 10
:
:
:
A 13 MHz clock is input to external pin SCLKP.
A 12 MHz clock is input to external pin SCLKP.
A 16 MHz clock is input to external pin SCLKP.
A 12 MHz clock is input to external pin SCLKP regardless of SFRQSEL when BCM2002X is selected
(RFSEL = 101).
• The CPU clock supply source is selected according to external pin SCLKSEL.
SCLKSEL = 0 : Use the clock that was divided down from the internal PLL output of 192 MHz that
was generated from external pins SCLKP. (Dividing ratios are selectable in the range
of 1/6 to 1/16. Initial value is 1/8 (24 MHz).)
SCLKSEL = 1 : Use external pins XC32KP.
Note: The clock supply source can be set by the CLKCNTL register in the CTL/WDT block once the LSI
is powered up.
• The frequency of CPU clock is selectable from the high speed (24 MHz) and low speed (16 MHz). This
can be performed by the Vendor Specific Command.
Setting the Reset
• Apply “L” level to the RESET pin for more than 10 µs after power voltage is stabilized. When the system
clock oscillator circuit is stable and the RESET pin is at “H” level, the internal reset is released and
operation starts after the internal reset is held for 1.9 ms for the input clock of 13 MHz, 2.0 ms for the input
clock of 12 MHz, or 1.5 ms for the input clock of 16 MHz.
Moreover, after power voltage is stable, the values of SCLKSEL, SFRQSEL0-1, and RFSEL0-2 should
be determined before the RESET pin is at “H” level.
Setting the UART Baud Rate
• It is possible to set the UART baud rate using the Vendor Specific Commands.
Available baud rate settings:
9600/19.2k/38.4k/56k/57.6k/115.2k/230.4k/345.6k/460.8k/921.6k
(Initial value is 115.2 kbps.)
Setting the PCM-CVSD Transcoder
• It is possible to set the PCM-CVSD transcoders using the Vendor Specific Commands.
For command details, contact Oki Electric Industry Co., Ltd.
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ML70512
• It is possible to set the following parameters using the VCCTL command:
- PCMSYNC/PCMCLK mode (initial setting: input)
- Mute reception (initial setting: OFF)
- Mute transmission (initial setting: OFF)
- Aircoding
CVSD (initial setting)/µ-law/A-law
- Interface coding
Linear (initial setting)/µ-law/A-law
- PCM format (data width of one PCM Linear sample)
8-bit (initial setting)/14-bit/16-bit
- Serial interface format
Short frame (initial setting)/long frame
- Application interface mode
PCM Codec I/F (initial setting)/APB I/F
XTAL Input Frequency of BCM2002X
• If the system clock is supplied from BCM2002X, the XTAL input frequency of BCM2002X must be 13,
19.2, 19.68, or 19.8 MHz. 12 MHz should not be applied.
XTAL Input Frequency of CX72303
• If the system clock is supplied from CX72303, the XTAL input frequency of CX72303 must be 13 MHz.
10 MHz should not be applied.
Required processes when interface pins are unused
• The following tables show the processes that should be performed when interface pins are not used.
• The pins that are not included in the following table should be left open.
RF I/F
Pin Name
Process When Pin Not Used
Comments
RXD
GND
GND
GND
RSSI
PLLLOCK
UART I/F
Pin Name
SIN
Process When Pin Not Used
Comments
Comments
VDD
CTS
GND
PCM I/F
Pin Name
PCMIN
Process When Pin Not Used
Open or VDD
PCMSYNC
PCMCLK
Open or GND
Open or GND
Processes of Other Pins
TEST I/F etc.
Pin Name
Process When Pin Not Used
Pull up or VDD
Comments
DETACH
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ML70512
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ML70512
PACKAGE DIMENSIONS
ML70512HB - 83pinWCSP (P-VFLGA83-6.22 × 6.22-0.50-W)
(Unit: mm)
P-VFLGA83-6.22×6.22-0.50-W
Package material
Lead frame material
Pin treatment
Package weight (g)
Rev. No./Last Revised
Epoxy resin
Sn/Pb
Solder plating (≥5µm)
0.04 TYP.
1/July 5, 2002
5
Note: A lead-free package is available. Please contact Oki Sales Office/Distributors for more information.
Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name,
package name, pin number, package code and desired mounting conditions (reflow method, temperature and
times).
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ML70512
ML70512LA - 84pin BGA (P-LFBGA84-0909-0.80)
(Unit: mm)
P-LFBGA84-0909-0.80
Package material
Ball material
Epoxy resin
Sn/Pb
Package weight (g)
Rev. No./Last Revised
0.20 TYP.
1/May 15, 2000
5
Note: A lead-free package is available. Please contact Oki Sales Office/Distributors for more information.
Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name,
package name, pin number, package code and desired mounting conditions (reflow method, temperature and
times).
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ML70512
REVISION HISTORY
Page
Previous
Edition
Document
No.
Date
Description
Current
Edition
FEDL70512-01
Feb. 17, 2003
Mar. 18, 2003
–-
–-
Final edition 1
Final edition 2
–-
23
–-
18
2
–-
FEDL70512-02
Eliminated the “RESET” row in the table of the
“TEST I/F ” Section.
23
–-
18
2
Final edition 3
FEDL70512-03
FEDL70512-04
Apr. 8, 2003
Partially eliminated the contents of “Reset”
Section.
Partially eliminated the contents of
“SPECIFICATIONS” Section.
Partially eliminated the contents of “DC
Characteristics” Section.
17
17
Sep. 2, 2003
Partially eliminated the contents of “Power
Supply Current (IDDO) Characteristics by
Power Saving Mode” Section.
18
23
18
23
Partially eliminated the contents of “Setting
the Reset” Section.
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NOTICE
ML70512
1. The information contained herein can change without notice owing to product and/or technical improvements.
Before using the product, please make sure that the information being referred to is up-to-date.
2. The outline of action and examples for application circuits described herein have been chosen as an explanation
for the standard action and performance of the product. When planning to use the product, please ensure that the
external conditions are reflected in the actual circuit, assembly, and program designs.
3. When designing your product, please use our product below the specified maximum ratings and within the
specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating
temperature.
4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation
resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or
unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified
maximum ratings or operation outside the specified operating range.
5. Neither indemnity against nor license of a third party’s industrial and intellectual property right, etc. is granted
by us in connection with the use of the product and/or the information and drawings contained herein. No
responsibility is assumed by us for any infringement of a third party’s right which may result from the use
thereof.
6. The products listed in this document are intended for use in general electronics equipment for commercial
applications (e.g., office automation, communication equipment, measurement equipment, consumer
electronics, etc.). These products are not, unless specifically authorized by Oki, authorized for use in any
system or application that requires special or enhanced quality and reliability characteristics nor in any system
or application where the failure of such system or application may result in the loss or damage of property, or
death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace
equipment, nuclear power control, medical equipment, and life-support systems.
7. Certain products in this document may need government approval before they can be exported to particular
countries. The purchaser assumes the responsibility of determining the legality of export of these products and
will take appropriate and necessary steps at their own expense for these.
8. No part of the contents contained herein may be reprinted or reproduced without our prior permission.
Copyright 2003 Oki Electric Industry Co., Ltd.
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