ML7051LA [OKI]
Bluetooth Baseband Controller IC; 蓝牙基带控制器IC
| 型号： | ML7051LA |
| 厂家： | 
OKI ELECTRONIC COMPONETS |
| 描述： | Bluetooth Baseband Controller IC |
| 文件： | 总24页 (文件大小：161K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FEDL7051LA-02
1
This version: Sept. 2000
Semiconductor
ML7051LA
Bluetooth Baseband Controller IC
GENERAL DESCRIPTION
The ML7051LA is a CMOS digital IC for use in 2.4 GHz band Bluetooth systems. This IC incorporates the
ARM7TDMI as the CPU core, features a highly expandable architecture, and supports the interfaces for a variety
of applications. Used in conjunction with the ML7050LA (Bluetooth RF Transceiver IC) and the OKI Bluetooth
Protocol Stack Software, data/voice communications are possible while maintaining interconnectivity with other
Bluetooth systems.
FEATURES
•
•
•
•
•
•
•
•
•
Conforms to the Bluetooth Specification (Ver1.0B)
The ARM7TDMI is installed as the CPU (operation at a maximum of 32 MHz in this LSI)
1-Ch, 16-bit auto-reload timer
Interrupt controller (17 causes)
Built-in 8 kbyte, 4-Way Copy Back Unified Cache
Built-in 24 kbyte RAM (supports 16-byte burst access)
Up to a total of 2 Mbyte of SRAM, ROM, and Flash ROM can be connected to the external memory bus.
PCM-CVSD transcoder is installed.
Installed interfaces:
- UART(*) interface (up to 921.6 kbps)
- USB(*) interface (conforms to USB1.1)
- UART synchronous serial port interface
- General-purpose I/O interface (programmable interrupts)
- PCM interface (PCMLinear/A-law/µ-law can be selected)
- JTAG interface
(*) This mark indicates interfaces that support the HCI command.
Power supply voltages: For I/O: 3.0 to 3.6 V; for internal core: 2.25 to 2.75 V
Package: 144-pin BGA (P-LFBGA144-1111-0.80)
(Dimensions: 11 mm × 11 mm × 1.5 mm; pin pitch: 0.8 mm)
•
•
ARM and the ARM POWERED logo are registered trademarks of ARM Ltd., UK.
ARM7TDMI and Thumb are trademarks of ARM Ltd., UK.
The information contained herein can change without notice owing to the product being under development.
1/24
FEDL7051LA-02
1
Semiconductor
ML7051LA
ABSOLUTE MAXIMUM RATINGS
Parameter
Power supply voltage
Input voltage
Symbol
VDD
VI
Conditions
Rating
–0.3 to +4.5
–0.3 to +4.5
1.35
Unit
V
—
—
—
—
V
Allowable power dissipation
Storage temperature
Pd
W
°C
Tstg
–55 to 150
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Vdd_io
Conditions
Min.
3.0
2.25
2.2
0
Typ.
3.3
2.5
—
Max.
3.6
Unit
V
Power supply voltage (for I/O)
—
—
—
—
—
Power supply voltage (for the internal core) Vdd_core
2.75
3.6
V
“H” level input voltage
“L” level input voltage
Operating temperature
Vih
Vil
V
—
0.8
V
Ta
–40
—
85
°C
ELECTRICAL CHARACTERISTICS
DC Characteristics
(Vdd_io = 3.3 V ±0.3V, Vdd_core = 2.5 V ±10%, Ta = 0 to 70°C)
Parameter
“H” level output voltage
“L” level output voltage
Input leak current
Symbol
Voh
Vol
Ii
Conditions
Ioh = –4 mA
Min.
2.4
—
Typ.
—
Max.
—
Unit
V
Iol = 4 mA
—
0.4
10
V
Vi = GND to 3.6 V
Vo = GND to Vdd
–10
–10
—
µA
µA
Output leak current
Io
—
10
During 32 MHz
operation
Power supply current (during operation)
Power supply current (during stand-by)
Iddo
Idds
0
50
50
70
mA
CLK Stopped
—
500
µA
2/24
FEDL7051LA-02
1
Semiconductor
ML7051LA
PIN PLACEMENT
1
2
3
4
5
6
7
8
9
10
11
12
13
TEST_L TEST_L
TEST1 TEST3
PCM
SYNC
VTM
REMAP0 NC
SCLKSEL
NC
CIO14 PCMIN
TXD
PLL_LE VDD
A
B
C
D
E
CORE_
VDD
TEST_L TEST_L TEST_L
TEST0 TEST2 TEST4
CIO13 CIO15
PLL_PS GND PLL_CLK
GND
TDI
REMAP1
RX_POW
TEST_L
TEST5
CORE_
VDD
CIO11
GND
CIO8
CIO5
CIO12 PCMCLK RXC
GND PLL_OF TX_POW
BBWSEL TXCSEL
RESETn
CORE_
VDD
PLL_
POW
RSSI_ CORE_
PLL_
CIO10 PCMOUT
DATA
RSSI
GND
VDD TXC_IN
PLLLOCK
CLK
VDD
CIO7
CIO9
CIO6
A_GND
RXD SCLK12 XCLK
CIO4
GND
CIO3
VDD
CIO1
CIO0
CIO2
GND
GND
GND
PUCTL
DP
VDD
VDD
A_VDD
DM
F
G
H
J
CORE_
VDD
TEST_O
DPLOUT
MA15
MA12
MA10
GND
MA6
NC
MA17
MA16
MA13
MA9
MA19
MA11
MA18
MA14
MA8
SVCO0
SVCO1
TEST_L
PLLSEL
TEST_L
PLLEN
nTRST
TCK
CLK
CORE_
VDD
MD14
MA0
GND
VDD
MD9
GND
MD10
MD8
MD6
ND7
MD5
MD3
MD2
MCSn0 MOEn0
TMS
TDO
K
L
CORE_
VDD
CORE_
VDD
MA4
MA1
MA3
MA2
MD0
MD1
MOEn1
MA7
GND
MD13
MD15
MD11
MD12
MD4
GND
MREn MBSn1
GND
NC
M
N
CORE_
VDD
MA5
MWEn MCSn1 MBSn0
TOP VIEW
3/24
FEDL7051LA-02
1
Semiconductor
ML7051LA
PIN DESCRIPTIONS
RF I/F
Internal
Pin
Placement
Pin Name
I/O
O
I
Initial Value
Description
Transmit data output
Pull Up/Down
TXD
—
—
—
—
—
—
L
A5
E11
D5
(To ML7050LA Pin# A8)
Receive data input
(To ML7050LA Pin# H5)
RXD
PLL setting data output
(To ML7050LA Pin# H3)
PLL_DATA
PLL_CLK
O
O
PLL setting clock output
(To ML7050LA Pin# G3)
L
B6
PLL setting load enable output
(To ML7050LA Pin# H4)
PLL_LE
PLL_OFF
RSSI
O
O
I
—
L
L
A6
C7
PLL Open-loop/Closed-loop control signal
output (To ML7050LA Pin# G8)
—
Receive field strength data input
(To ML7050LA Pin# G6)
Pull down
—
—
H
D10
D8
RSSI transfer clock
(To ML7050LA Pin# H8)
RSSI_CLK
PLL_POW
TX_POW
O
O
O
—
—
—
Local transmit circuit power control signal
output (To ML7050LA Pin# A7)
D7
Transmit power control signal output
(To ML7050LA Pin# B6)
H
C8
Receive power control signal output
(To ML7050LA Pin# B3)
RX_POW
O
—
H
B7
PLL_PS
PLLLOCK
RXC
O
I
—
Pull down
—
L
L
L
B4
D6
C5
PLL power control signal output
PLL lock signal input
O
Bluetooth receive clock output (1 MHz)
Bluetooth transmit clock input (1 MHz)
When the transmit clock is used by a clock
(RXC) that is generated from the receive
data, set TXCSEL(Pin# C11) to H and
connect to RXC(Pin# C5).
TXC_IN
TXCSEL
I
I
Pull down
Pull down
L
L
D13
C11
Bluetooth transmit clock setting pin
L: Select 1 MHz divided by internal PLL.
H: Select TXC_IN input signal.
4/24
FEDL7051LA-02
1
Semiconductor
ML7051LA
CLK and Configuration
Internal
Initial
Value
Pin
Placement
Pin Name
I/O
Description
Pull Up/Down
Master clock (12 MHz) input pin
(Power level: CMOS level)
User clock input pin
SCLK12
XCLK
I
I
—
—
—
—
E12
E13
System clock select pin
L: Select CLK divided by internal PLL
H: Select XCLK input signal
Hardware reset pin (Reset = L)
BANK0 region bit width select pin
L: 8-bit
SCLKSEL
RESETn
BBWSEL
REMAP0
I
I
I
I
Pull down
—
—
—
—
A11
C13
C10
A12
—
—
—
H: 16-bit
REMAP select pin during boot up
REMAP[1:0] = “00” Reserved
“01” Stacked Flash ROM
REMAP1
I
B13
“10” External MCS[1] device
“11” External MCS[0] device
Memory I/F
Internal
Initial
Value
Pin
Placement
Pin Name
I/O
Description
Pull Up/Down
MA[19:0]
MD[15:0]
MWEn
O
I/O
O
—
—
—
—
—
—
—
—
L
Z
[*1]
[*2]
External address bus
External data bus
H
H
H
H
H
H
N10
M11
K10
N11
N12
M12
External write enable signal output
External read enable signal output
External RAM space chip select
External I/O space chip select
External lower byte select
External upper byte select
MREn
O
MCSn0
MCSn1
MBSn0
MBSn1
O
O
O
O
External MCS[0] device output enable
(MCSn0 and WREn OR output)
MOEn0
MOEn1
MWAIT
O
O
I
—
—
—
H
H
K11
L11
F3
External MCS[1] device output enable
(MCSn1 and WREn OR output)
External wait signal input
(Pin shared with GPIO1)
—
[*1] MA19: H3; MA18: H4;
MA13: K2; MA12: J1;
MA6: M1; MA5: N2;
MA17: H2;
MA11: J3;
MA4: L3;
MA16: J2;
MA10: K1;
MA3: N3;
MA15: H1; MA14: J4
MA9: L2;
MA2: L4;
MA8: K4;
MA1: M3; MA0: L5
MA7: M2
[*2] MD15: N5; MD14: K5;
MD13: M5; MD12: N6;
MD11: M6; MD10: M7
MD9: K7;
MD2: K9;
MD8: N7;
MD1: M10;
MD7: L8;
MD0: L10
MD6: K8;
MD5: M8; MD4: M9; MD3: N8;
5/24
FEDL7051LA-02
1
Semiconductor
ML7051LA
USB I/F
Pin Name
Internal
Initial
Value
Pin
Placement
I/O
Description
Pull Up/Down
DP
DM
I/O
I/O
O
—
—
—
Z
Z
L
G11
G13
F11
USB data
USB data
PUCTL
Pull-up control pin
VBUS
(GPIO0)
I
—
—
G3
USB detection pin
UART I/F
Internal
Initial
Value
Pin
Placement
Pin Name
I/O
O
I
Description
Pull Up/Down
ACE transmit serial data
(Pin shared with GPIO15)
SOUT
SIN
—
—
—
—
—
—
—
—
H
—
—
H
B2
A2
B1
C3
C1
D3
E3
D2
ACE receive serial data
(Pin shared with GPIO14)
Data carrier detection
(Pin shared with GPIO13)
DCD
RTS
CTS
DSR
DTR
RI
I
ACE transmit data ready
(Pin shared with GPIO12)
O
I
ACE transmit ready
(Pin shared with GPIO11)
—
—
H
Receive data ready
(Pin shared with GPIO10)
I
Receive ready
O
I
(Pin shared with GPIO9)
Ring indicator
—
(Pin shared with GPIO8)
SIO I/F
Internal
Initial
Value
Pin
Placement
Pin Name
I/O
O
Description
Pull Up/Down
Serial data output
(Pin shared with GPIO7)
STXD
SRXD
—
—
—
—
H
E1
E4
E2
F1
Serial data input
I
—
—
—
(Pin shared with GPIO6)
Clock for serial data output, in the input state
after initialization (Pin shared with GPIO5)
STDCLK
SRDCLK
I/O
I/O
Clock for serial data input, in the input state
after initialization (Pin shared with GPIO4)
6/24
FEDL7051LA-02
1
Semiconductor
ML7051LA
µPLAT_SIO I/F
Internal
Initial
Value
Pin
Placement
Pin Name
I/O
Description
Pull Up/Down
UTXD
URXD
O
I
—
—
H
F2
F4
Serial data output (Pin shared with GPIO3)
Serial data input (Pin shared with GPIO2)
—
GPIO I/F
Internal
Initial
Value
Pin
Placement
Pin Name
I/O
I/O
Description
Pull Up/Down
Parallel I/O data (in the input state after
initialization)
GPIO[15:0]
—
—
[*3]
JTAG I/F
Internal
Pull Up/Down
Pull down
—
Initial
Value
Pin
Placement
Pin Name
I/O
Description
TDI
TDO
I
O
I
—
L
B12
L12
J11
K12
J13
Serial data input
Serial data output
Reset pin
nTRST
TMS
Pull down
Pull down
Pull down
—
—
—
I
Mode setting pin
Serial data clock
TCK
I
PCM I/F
Internal
Pull Up/Down
—
Initial
Value
Pin
Placement
Pin Name
I/O
Description
PCMOUT
PCMIN
O
I
L
D4
A3
PCM data output
PCM data input
Pull down
—
PCM sync signal (8 kHz), in the input state
after initialization (can be switched by an
internal register)
PCMSYNC
PCMCLK
I/O
I/O
Pull down
Pull down
—
—
A4
C4
PCM clock (64 kHz/128 kHz), in the input
state after initialization (can be switched by an
internal register)
[*3]
CIO15: B2
CIO14: A2
CIO13: B1
CIO12: C3
CIO11: C1
CIO10: D3
CIO9: E3
CIO8: D2
CIO7: E1
CIO6: E4
CIO5: E2
CIO4: F1
CIO3: F2
CIO2: F4
CIO1: F3
CIO0: G3
GPIO15/SOUT (UART I/F)
GPIO14/SIN (UART I/F)
GPIO13/DCD (UART I/F)
GPIO12/RTS (UART I/F)
GPIO11/CTS (UART I/F)
GPIO10/DSR (UART I/F)
GPIO9/DTR (UART I/F)
GPIO8/RI (UART I/F)
GPIO7/STXD (SIO I/F)
GPIO6/SRXD (SIO I/F)
GPIO5/STXDCLK (SIIO I/F)
GPIO4/SRXDCLK (SIO I/F)
GPIO3/UTXD (UPLAT_SIO I/F)
GPIO2/URXD (UPLAT_SIO I/F)
GPIO1/NWAIT (Memory I/F)
GPIO0/VBUS (USB I/F)
7/24
FEDL7051LA-02
1
Semiconductor
ML7051LA
TEST I/F
Internal
Initial
Value
Pin
Placement
Pin Name
I/O
Description
Pull Up/Down
TEST_L
TEST_O
SVCO0
SVCO1
VTM
I
O
I
—
—
—
—
—
—
—
L
[*4]
H13
Test pin (input)
Test pin (output)
—
—
—
—
H10
Built-in PLL characteristics setting pin
Built-in PLL characteristics setting pin
Built-in Flash ROM test pin
I
H12
I
A10
CLK
O
K13
Built-in Flash ROM test pin
A1, A13
N1, N13
NC
—
—
—
No Connection
Power, GND
Internal
Initial
Value
Pin
Placement
Pin Name
I/O
Description
Pull Up/Down
VDD
CORE_VDD
GND
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
[*5]
[*6]
[*7]
F13
E10
I/O power pin 3.3 V ±0.3 V
Core power pin 2.5 V ±10%
Digital block ground pin
A_VDD
Analog block power pin 2.5 V ±10%
Analog block ground pin
A_GND
[*4] TEST_L (TEST5): C9
TEST_L (TEST4): B10
TEST_L (TEST3): A9
TEST_L (TEST2): B9
TEST_L (TEST1): A8
TEST_L (TEST0): B8
TEST_L (PLLSEL): J10
TSET_L (PLLEN): J12
[*5] A7, D12, F12, G2, G12, L6
[*6] B3, C12, D1, D9, H11, K3, L9, L13, N4
[*7] B5, B11, C2, C6, D11, F10, G1, G4, G10, K6, L1, L7, M4, M13, N9
8/24
FEDL7051LA-02
1
Semiconductor
ML7051LA
BLOCK DIAGRAM
16
ML7051LA
UART I/F
SIO I/F
PIO I/F
USB I/F
SIO I/F
Clock
9/24
FEDL7051LA-02
1
Semiconductor
ML7051LA
DESCRIPTION OF INTERNAL BLOCKS
CLKGEN Block
•
•
•
Generates from the SCLK12 (12 MHz) clock that is supplied to each block
STOP/HALT function
External clock selection function
CTL/WDT Block
•
•
•
•
•
•
•
•
Control of the frequency division function of the internal main clock
Control of clock supplied to each peripheral
Control of reset of each peripheral
STOP/HALT control
External clock selection control
CIO switching function
Watchdog timer function (interrupt/reset)
3 count stop functions
WDTB Block
•
•
Watchdog timer function (interrupts only)
3 count stop functions
Baseband Core Block
RF LSI
Tx SCO Buffer
Tx ACL Buffer
TXD
CNT
Packet
Composer
Codec
I/F
Audio
RF
FHCNT
Security
Timing
CNT
ARM
I/F
APB
Rx SCO Buffer
Rx ACL Buffer
Packet
Decomposer
RXD
•
•
RF Controller
- RF power supply control (PLL, TX, RX)
- Local PLL frequency division ratio setting
- Receive clock regeneration function
- Synchronization detection (synchronizing within the permissable error limit of SyncWord)
- Receive clock re-timing function
FH Controller hopping
- Sequence control
- Frequency hopping selection function
- CRC computation's initial value selection function
10/24
FEDL7051LA-02
1
Semiconductor
ML7051LA
•
Timing Generator
- Bluetooth clock generation
- Operation interrupts depend on mode (slot, scan, sniff, hold, park)
- Sync detection timing generation (sync window ±10 µs)
- PLL setting timing generation
- Transmit/Receive timing generation
- Multi-master timing management function
•
•
•
Packet Composer
- Access code generation (SyncWord generation, appending PR*TRAILER)
- Packet header generation (HEC generation, scrambling, FEC encoding)
- Payload generation (CRC generation, encryption, scrambling, FEC encoding)
- Packet synthesis
Packet Decomposer
- Packet decomposition (separating the packet header and the payload)
- Packet header processing (FEC decoding, descrambling, HEC error detection, header information separation)
- Payload processing (FEC decoding, descrambling, encryption decoding, CRC judgement, payload
separation)
Security
- Various key generation functions (initialization, link key, encryption key)
- Certification function
- Encryption function
USB Block
•
•
•
•
•
•
Conforms to USB standard Ver. 1.1.
Supports 12 Mbps transfer
Supports four data transfer types (control transfer, bulk transfer, interrupt transfer, and isochronous transfer)
Built-in USB transceiver circuit
5 or 6 built-in end points, and built-in FIFO for data storage
8-, 16-, 24-, 32-bit read/write is possible for the FIFOs of EP0 to EP5 (with byte control)
UART Block
•
•
•
•
•
•
•
•
•
•
Full-duplex buffering method
All status reporting function
Built-in 64-byte transmit/receive FIFO
Modem control based on CTS, DCD, and DSR
Programmable serial interface
5-, 6-, 7-, 8-bit characters
Generation and verification of odd parity, even parity, or no parity
1, 1.5, or 2 stop bits
Programmable Baud Rate Generator (1200 bps to 921.6 kbps)
Error servicing for parity, overrun, and framing errors
11/24
FEDL7051LA-02
1
Semiconductor
ML7051LA
SIO Block
•
•
UART/Synchronous type serial port interface
UART Mode:
- Data length: can be selected as 7 or 8 bits
- Supports odd parity, even parity, or no parity
- Error servicing for parity, overrun, and framing errors
- Supports 1 or 2 stop bits
- Full-duplex communication is possible
•
Clock synchronization mode:
- Data length: can be selected as as 7 or 8 bits
- Error servicing for overrun errors
- Full-duplex communication is possible
µPLAT-SIO Block
•
•
•
•
•
•
•
Start-stop synchronization type serial port interface
Built-in dedicated baud rate generator
Data length of 7 or 8 bits can be selected
1 or 2 stop bits can be selected.
Supports odd or even parity
Error servicing for parity, overrun, and framing errors
Full-duplex communication is possible
PCM-CVSD Transcoder Block
•
Application side I/O:
- PCM Codec
- APB-Bus (USB)
•
•
Application-side format:
- PCM linear (8, 16 bits/sample, 64 kHz sampling frequency)/A-law/µ-law
Bluetooth-side format:
- CVSD/A-law/µ-law
•
•
All combinations of the above conversions are supported
PCMSYMC/PCMCLK I/O can be switched (in the input state after initialization)
GPIO Block
•
•
•
•
•
All 16 bits
Input/Output selection possible for each bit
Interrupts can be used for all 16 bits
Interrupt masks and interrupt modes can be set for all bits
In the input state immediately after a reset
12/24
FEDL7051LA-02
1
Semiconductor
ML7051LA
APPLICATION NOTES
Operation During Boot Up
•
•
Remapping during boot up is performed according to external pins REMAP[1:0].
REMAP1
REMAP0
L
L
H
H
L
H
L
H
:
:
:
:
Reserved
Stack Flash ROM
Devices connected to external MCS[1]
Devices connected to external MCS[0]
Bit width that corresponds to BANK0 during boot up is set according to external pin BBWSEL.
BBWSEL = L : 8-bit
BBWSEL = H : 16-bit
Clock Selection
•
•
The CPU clock supply source is selected according to external pin SCLKSEL.
SCLKSEL = L : Use 32/16/8/4 MHz clock that was divided down from the internal PLL output of 192 MHz
that was generated from external pin SCLK12 (12 MHz). (Initial value is 32 MHz.)
SCLKSEL = H : Use external pin XCLK.
Note: The clock supply source can also be set by the CLKCNT register in the CTL/WDT block.
Bluetooth transmission clock is selected according to external pin TXCSEL.
TXCSEL = L : Use 1 MHz clock that was divided down from the internal PLL output (192 MHz).
TXCSEL = H : Use external pin TXC_IN.
Note: This clock can also be set by the CLKCNT register in the CTL/WDT block.
HCI Transport Selection
HCI is selected (USB/UART) according to the logical value of GPIO0 at initial powerup of ML7051LA.
•
GPIO0 = L
GPIO0 = H
: UART is used as HCI.
: USB is used as HCI.
13/24
FEDL7051LA-02
1
Semiconductor
ML7051LA
USB Peripheral Circuit
•
Please refer to the following peripheral circuit example when using USB.
3.3 V
ML7051LA
47 kΩ
G3
GPIO0
1.5 kΩ
F11
G11
G13
PUCTL
DP
16Ω
16Ω
D+ (3.3 V)
D- (3.3 V)
DM
Setting the UART Baud Rate
•
Use the HCI_VS_Set_LC_Parameters command of the Vendor Specific Commands to set the UART baud
rate.
Available baud rate settings:
1200/2400/4800/7200/9600/19.2K/38.4K/56K/57.6K/115.2K/230.4K/345.6K/460.8K/921.6K
(Initial value is 115.2 kbps.)
Setting the PCM-CVSD Transcoder
•
•
Please use the HCI_VS_Set_LC_Parameters command of the Vendor Specific Commands in HCI to set the
PCM-CVSD transcoder parameters.
It is possible to set the following parameters using the VCCTL command:
- PCMSYNC/PCMCLK mode (in the input state after initialization)
- Mute reception (initial setting: OFF)
- Mute transmission (initial setting: OFF)
- Air coding
CVSD (initial setting)/µ-law/A-law
- Interface coding
Linear (initial setting)/µ-law/A-law
- PCM format (data width of one PCM Linear sample)
8-bit (initial setting)/14-bit/16-bit
- Serial interface format
Short frame (initial setting)/long frame
- Application interface mode
PCM Codec I/F (initial setting)/APB I/F
14/24
FEDL7051LA-02
1
Semiconductor
ML7051LA
External Memory
•
•
ML7051LA specifications for the devices that are connected to MCS[0] and MCS[1] are explained below.
When connected to MCS[0] device:
- 1 memory bank
- Bus width: 8 or 16 bits
- Byte access control: BS/WE
- Supported devices:
Normal SRAM, Flash Memory, Page mode Flash memory
Bus timing to MCS[0] device
MREn
MWEn
XA
MCSn0
MBSn*
XD_I
[*1]
(read)
XD_O
(write)
[*1]
1 or 2
clocks
[*2]
1 or 2 clocks
1 clock fixed
[*1] Access time:
3, 4, 5, 6, 7, 8 clock cycles (including one clock cycle for set-up)
6, 8, 10, 12, 14, 16 clock cycles (including two clock cycles for set-up)
[*2] Data OFF time:
1, 2, 3, 4 clock cycles
Note: Oki software settings:
- Insert the maximum wait immediately after reset.
- Page mode: OFF
- During operation (32 MHz operation),
Access time: 3 clock cycles
Data OFF time: 1 clock cycle
Note: A device with an access time of 120 nsec or less is recommended.
15/24
FEDL7051LA-02
1
Semiconductor
ML7051LA
•
When connected to MCS[1] device:
- 1 memory bank
- Bus width: 8-bit or 16-bit
- Byte access control: BS/WE
Bus timing to MCS[1] device (IOWRTYPE = 0)
MREn
MWEn
XA
MCSn1
MBSn*
[*3]
[*1]
XD_I
(read)
XD_O
(write)
[*1]
[*3]
[*2]
1 clock fixed
Bus timing to MCS[1] device (IOWRTYPE = 1)
MREn
MWEn
XA
MCSn1
MBSn*
[*1]
[*3]
XD_I
(read)
[*4]
[*1]
XD_O
(write)
[*3]
[*2]
1 clock fixed
1 clock fixed
[*1] Access time:
2, 4, 8, 16, 32 clock cycles (including one clock cycle for set-up)
It is only possible to use the external pin nWAIT then insert a wait period of 16 × n clock
cycles when the 16 cycle clock is selected.
[*2] Data OFF time:
1, 2, 3, 4 clock cycles
[*3] Address set-up time:
1, 2, 3, 4 clock cycles
[*4] Write data set-up time:
0 clock cycles (IOWRTYPE = 0)
0, 1, 2, 3 clock cycles (IOWRTYPE=1)
16/24
FEDL7051LA-02
1
Semiconductor
ML7051LA
•
Relationship between address set-up time and write data set-up time (when IOWRTYPE = 1)
- Address set-up time:
1 clock cycle (write data set-up: 0 clock cycles)
2 clock cycles (write data set-up: 1 clock cycle)
3 clock cycles (write data set-up: 2 clock cycles)
4 clock cycles (write data set-up: 3 clock cycles)
Note: Oki software settings:
- Insert the maximum wait immediately after reset.
- IOWRTYPE = 0
- During operation (32 MHz operation),
Access time: 2 clock cycles
Data OFF time: 1 clock cycle
Address set-up time: 1 clock cycle
Note: A device with an access time of 120 nsec or less is recommended.
•
Miscellaneous
- MA0 is not used with devices that have a 16-bit data bus.
Connect MA1 to device A0. (MA0 is Open.)
- Connect MA0 to device A0 for devices that have an 8-bit data bus.
- MOEn[0] is the AND signal for MCS[0] and MREn.
Perform an open process when this is not in use.
- MOEn[1] is the AND signal for MCS[1] and MREn.
Perform an open process when this is not in use.
17/24
FEDL7051LA-02
1
Semiconductor
ML7051LA
Process when interface pins are unused
The following tables show the processes that are performed when interface pins are not used.
•
RF I/F
Pin Name
Process When Pin Not Used
Comments
PLL_DATA
PLL_CLK
PLL_LE
Open
Open
Open
PLL_OFF
PLL_POW
TX_POW
RX_POW
RSSI
Open
Open
Open
Open
Pull down to GND
Open
RSSI_CLK
PLL_PS
PLLLOCK
RXC
Open
Pull down to GND
Open
TXC_IN
Pull down to GND
Pull down to GND
TXCSEL
Memory I/F
Pin Name
Process When Pin Not Used
Comments
When connected
For 16-bit devices:
• Open MA0.
MA[19:0]
Open
• Connect from MA1 in order from A0 of the
connected device.
For 8-bit devices:
• Connect to each corresponding address.
MD[15:0]
MWEn
Open
Open
MREn
Open
MCSn0
MCSn1
MBSn0
MBSn1
MOEn0
MOEn1
MWAIT
Open
Open
Open
Open
Open
Only use when connecting to a device that has
only one, but not both of CEn or REn.
Open
Refer to GPIO1
18/24
FEDL7051LA-02
1
Semiconductor
ML7051LA
USB I/F
Pin Name
Process When Pin Not Used
Comments
DP
DM
Open
Open
Open
PUCTL
VBUS
(GPIO0)
Pull down/GND
Pull up to Vdd when using USB.
Comments
UART I/F
Pin Name
SOUT
SIN
Process When Pin Not Used
Refer to GPIO15
Refer to GPIO14
Refer to GPIO13
Refer to GPIO12
Refer to GPIO11
Refer to GPIO10
Refer to GPIO9
DCD
RTS
CTS
DSR
DTR
RI
Refer to GPIO8
19/24
FEDL7051LA-02
1
Semiconductor
ML7051LA
SIO I/F
Pin Name
Process When Pin Not Used
Refer to GPIO7
Comments
STXD
SRXD
Refer to GPIO6
STDCLK
SRDCLK
Refer to GPIO5
Refer to GPIO4
µPLAT_SIO I/F
Pin Name
UTXD
Process When Pin Not Used
Refer to GPIO3
Comments
Comments
URXD
Refer to GPIO2
GPIO I/F
Pin Name
Process When Pin Not Used
When using UART: Pull down to GND
When using USB: Pull up to Vdd
GPIO[0]
—
GPIO[15:1]
Pull down/GND
JTAG I/F
Pin Name
TDI
Process When Pin Not Used
Comments
Open
Open
Open
Open
Open
TDO
nTRST
TMS
TCK
PCM I/F
Pin Name
PCMOUT
PCMIN
Process When Pin Not Used
Comments
Open
Open
Open
Open
PCMSYNC
PCMCLK
Processes of Other Pins
TEST I/F, etc.
Pin Name
TEST_L
TEST_O
SVCO0
SVCO1
VTM
Process When Pin Not Used
Comments
GND
Open
Pull up to Vdd
Pull down to GND
Open
CLK
GND
NC
Open
20/24
FEDL7051LA-02
1
Semiconductor
ML7051LA
About the Oki Bluetooth Software
•
At Oki Electric Industry Co., Ltd., we have made available as Pack 1 the software protocol stack of the lower
layer up to HCI that conforms to the Bluetooth Specification Ver. 1.0B for external Flash memory.
Pack 1 contents: Baseband Controller, LMP, HCI.
•
•
We have also made available packs for the software protocol stack of the upper layer from HCI: Pack 2 (up to
RFCOMM) and Pack 3 (including the Middleware).
Please contact Oki Electric Industry Co., Ltd. for more information regarding software contents, pricing, etc.
Vender Specific Commands
•
•
Parameters can be set with the Pack 1 software by using the following Vendor Specific Commands.
Please contact Oki Electric Industry Co., Ltd. for more information.
(1) HCI_VS_Write_BD_ADDR:
Sets the BD address.
(2) HCI_VS_Write_Country_Code: Sets the country code.
(3) HCI_VS_Set_LC_Parameters: Sets the link control information.
The following table shows the link control information that can be set.
Link Control Information
Unit key
Comments
Use unit key
0: Do not use 1: Use
Channel count
Number of hopping channels
Minimum size of encryption key
Maximum size of encryption key
Appropriate size of encryption key
PCM of SCO link
0: µ-law, 1: A-law, 2: Linear
0: 1200 bps
2: 4800 bps
4: 9600 bps
6: 38.4 kbps
8: 57.6 kbps
1: 2400 bps
3: 7200 bps
5: 19.2 kbps
7: 56 kbps
UART baud rate
9: 115.2 kbps
9: 230.4 kbps 10: 345.6 kbps
11: 460.8 kbps 12: 921.6 kbps
Unit: 625 µsec
Polling interval
Initialization by MaskROM value
21/24
FEDL7051LA-02
1
Semiconductor
ML7051LA
System Development Kit (SDK)
•
At Oki Electric Industry Co., Ltd., we have made available the System Development Kit (SDK) for the
following objectives:
- Software development of the upper Bluetooth layer
- Overall system software
- Device development with embedded ML7050LA or ML7051LA
Please contact Oki Electric Industry Co., Ltd. for more information regarding System Development Kit
contents, pricing, etc.
22/24
FEDL7051LA-02
1
Semiconductor
ML7051LA
PACKAGE DIMENSIONS
(Unit: mm)
P-LFBGA144-1111-0.80
Package material
Ball material
Epoxy resin
Sn/Pb
Package weight (g)
0.3 TYP.
Rev. No./Last Revised 1/Aug.25,1999
Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow mounting and humidity
absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product
name, package name, pin number, package code and desired mounting conditions (reflow method,
temperature and times).
23/24
FEDL7051LA-02
1
Semiconductor
ML7051LA
NOTICE
1. The information contained herein can change without notice owing to product and/or technical improvements.
Before using the product, please make sure that the information being referred to is up-to-date.
2. The outline of action and examples for application circuits described herein have been chosen as an
explanation for the standard action and performance of the product. When planning to use the product, please
ensure that the external conditions are reflected in the actual circuit, assembly, and program designs.
3. When designing your product, please use our product below the specified maximum ratings and within the
specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating
temperature.
4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation
resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or
unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified
maximum ratings or operation outside the specified operating range.
5. Neither indemnity against nor license of a third party’s industrial and intellectual property right, etc. is
granted by us in connection with the use of the product and/or the information and drawings contained herein.
No responsibility is assumed by us for any infringement of a third party’s right which may result from the use
thereof.
6. The products listed in this document are intended for use in general electronics equipment for commercial
applications (e.g., office automation, communication equipment, measurement equipment, consumer
electronics, etc.). These products are not authorized for use in any system or application that requires special
or enhanced quality and reliability characteristics nor in any system or application where the failure of such
system or application may result in the loss or damage of property, or death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace
equipment, nuclear power control, medical equipment, and life-support systems.
7. Certain products in this document may need government approval before they can be exported to particular
countries. The purchaser assumes the responsibility of determining the legality of export of these products
and will take appropriate and necessary steps at their own expense for these.
8. No part of the contents contained herein may be reprinted or reproduced without our prior permission.
Copyright 2000 Oki Electric Industry Co., Ltd.
24/24
相关型号：
©2020 ICPDF网 联系我们和版权申明