ML7041TB [OKI]
single-channel full duplex CODEC LSI device which performs mutual transcoding between the analog voice band signals ranging from 300 to 3400 Hz and th; 单信道全双工CODEC芯片装置，其执行模拟话音频带信号，范围从300到3400赫兹和第之间相互转换
| 型号： | ML7041TB |
| 厂家： | 
OKI ELECTRONIC COMPONETS |
| 描述： | single-channel full duplex CODEC LSI device which performs mutual transcoding between the analog voice band signals ranging from 300 to 3400 Hz and th |
| 文件： | 总28页 (文件大小：236K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FEDL7041-04
Issue Date: Mar. 2, 2006
ML7041
Audio CODEC
GENERAL DESCRIPTION
The ML7041 is a single-channel full duplex CODEC LSI device which performs mutual transcoding between the
analog voice band signals ranging from 300 to 3400 Hz and the 64 kbps PCM serial data.
Provided with such functions as DTMF Tone generation, transmit/receive data gain control, side-tone path, and
low-dropout regulator, the ML7041 is best suited for telephone terminals in digital wireless systems.
FEATURES
• Single 3 V power supply
VDD: 2.4 to 3.3 V
• Coding format: PCM µ-law/PCM A-law/14-bit linear mode selectable
• PCM interface timing: Long frame synchronous timing/short frame synchronous timing selectable
• Transmit/receive full-duplex operation
• Serial PCM transmission data rate:
• Low power consumption
Operating mode:
64 to 2048 kbps
15 mW typ. (VDD = 3.0 V)
Power-down mode:
3 µW typ. (VDD = 3.0 V)
• Master clock frequency:
2.048 MHz (compatible with PCM shift clock)
• Analog output stage
100 mW (differential type) amplifier output for driving receiver speaker:
Capable of driving an 8 Ω load.
6.6 mW (single type) amplifier output for driving earphones speaker:
Capable of driving a 32 Ω load.
• Built-in two low-dropout regulators (150 mA × 2)
• Built-in four general purpose drivers (150 mA × 4)
• Transmit/receive mute, transmit/receive programmable gain control
• Built-in side tone path
• Built-in DTMF tone generator
• Transmit slope filter selectable
• I2C bus interface (MCU interface)
• Built-in transmit voice signal detector
• Package: 48-pin plastic TQFP (TQFP48-P-0707-0.50-K) (ML7041 TB)
1/28
FEDL7041-04
OKI Semiconductor
ML7041
BLOCK DIAGRAM
MIC1I
CR0-B0
Voice
detect
PCM
Com-p
and
CR1-B1
A/D
20 kΩ
PCMOUT
MIC1O
MIC2I
CR0-B2
CR4-B6
Slope
Filter
BPF
20 kΩ
20 kΩ
BCLK
SYNC
MIC2O
CR1-B7,6
TONE/DTMF
Gen
CR3-B7,6,5
LPF
MIC3–
CR3-B3,2,1,0
CR0-B0
MIC3+
MIC3O
PCM
D/A
PCMIN
Expand
CR2-B2,1,0
Regulator1
(150 mA)
RG1O (3.0 V)
EAR1O
32 Ω
RG1PDN (3.0 V/0 V)
RG2O (3.0 V)
Regulator2
(150 mA)
Sign bit
20 kΩ
RG2PDN (3.0 V/0 V)
EAR2O
CR1-B5,4
32 Ω
CR5-B7
GP1 (150 mA)
GP2 (150 mA)
GP3 (150 mA)
MCU I/F
(I2C)
SG
VREF
GP4 (150 mA)
AGGP
8 Ω
8 Ω
CR5-B3,2,1,0
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FEDL7041-04
OKI Semiconductor
ML7041
PIN CONFIGURATION (TOP VIEW)
AG
EAR2O
EAR1O
VA1
1
2
3
4
5
6
7
8
9
36
35
34
33
32
31
30
29
28
27
26
25
RG2IN
RG2O
AGR2
RG1IN
RG1O
AGR1
RG2PDN
RG1PDN
PDN
EXTO
EXTI
VA2
SPO–
AG2
AG3 10
11
SYNC
BCLK
SPO+
VA3 12
DG
48-Pin Plastic TQFP
3/28
FEDL7041-04
OKI Semiconductor
ML7041
PIN DESCRIPTIONS
Pin
1
Symbol
AG
Type
—
O
Description
State in power-down mode
Analog ground (0 V)
—
2
EAR2O
EAR1O
VA1
Receive side voice amplifier output 2
Receive side voice amplifier output 1
Analog power supply 1 (3.0 V)
High impedance
3
O
High impedance
4
—
O
—
5
EXTO
EXTI
Receive side voice amplifier output
Receive side voice amplifier input
Analog power supply 2 (3.0 V)
High impedance
6
I
—
—
7
VA2
—
O
8
SPO–
AG2
Receive side voice amplifier output–
Analog ground 2 (0 V)
High impedance
9
—
—
O
—
—
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
AG3
Analog ground 3 (0 V)
SPO+
VA3
Receive side voice amplifier output+
Analog power supply 3 (3.0 V)
High impedance
—
—
O
—
—
AGGP1
GP1
General purpose port ground 1 (0 V)
General purpose port 1 output (Open drain)
General purpose port 2 output (Open drain)
General purpose port 3 output (Open drain)
General purpose port 4 output (Open drain)
General purpose port ground 2 (0 V)
Digital power supply (3.0 V)
High impedance
GP2
O
High impedance
GP3
O
High impedance
GP4
O
High impedance
AGGP2
VDD
—
—
I
—
—
MCK
Master clock input (2.048 MHz)
—
SDA
I/O I2C data input/output (Pull-up resister required)
High impedance
SCL
I
I
I2C shift clock input
—
PCMIN
PCMOUT
DG
PCM receive signal input
—
O
—
I
PCM transmit signal output
Digital ground (0 V)
“H”
—
BCLK
SYNC
PDN
PCM data shift clock input
—
I
PCM data shift sync signal input
Power down control input
—
I
“L”
RG1PDN
RG2PDN
AGR1
RG1O
RG1IN
AGR2
RG2O
RG2IN
VA
I
Power down input for regulator 1 (3.0 V/0 V)
Power down input for regulator 2 (3.0 V/0 V)
Ground for regulator 1 (0 V)
Regulator 1 output (3.0 V)
“L”
I
“L”
—
O
I
—
“L” (RG1PDN = “L”)
Regulator 1 power input (3.6 V)
Ground for regulator 2 (0 V)
Regulator 2 power output (3.0 V)
Regulator 2 input (3.6 V)
—
—
—
O
I
“L” (RG2PDN = “L”)
—
—
Analog power supply (3.0 V)
—
SWA
SWB
I/O Analog switch A
I/O Analog switch B
I/O Analog switch C
—
—
SWC
MIC1I
MIC1O
MIC2I
MIC2O
MIC3+
MIC3–
MIC3O
SG
—
I
O
I
Transmit side amplifier 1 inverting input
—
Transmit side amplifier 1 output
High impedance
Transmit side amplifier 2 inverting input
Transmit side amplifier 2 output
—
O
I
High impedance
Transmit side amplifier 3 non-inverting input
Transmit side amplifier 3 inverting input
Transmit side amplifier 3 output
—
I
—
High impedance
“L”
O
O
Analog signal ground (1.4 V)
4/28
FEDL7041-04
OKI Semiconductor
ML7041
PIN AND FUNCTIONAL DESCRIPTIONS
MIC1I, MIC1O, MIC2I, MIC2O, MIC3–, MIC3+, MIC3–
Transmit analog inputs and outputs for transmit gain adjustment. Gains of input levels of the pins can be adjusted
using external resisters.
MIC1I, MIC2I, and MIC3– are connected to the inverting inputs of the internal transmit amplifiers. MIC3+ is
connected to the non-inverting input of the internal transmit amplifier 3. MIC1O, MIC2O, and MIC3O are
connected to the internal transmit amplifier outputs. Analog input signals are controlled by the control register
(CR1-B7, B6). Also, the amplifiers that are not being selected are deactivated and their outputs are put into high
impedance state.
Refer to Figure 1 for gain adjustment.
EAR1O, EAR2O, EXTO, EXTI, SPO–, SPO+
Receive analog outputs and inputs for receive gain adjustment. EAR1O, EAR2O, and EXTO are the receive filter
outputs. EAR1O and EAR2O can directly drive a 32 Ω load.
SPO+ and SPO– are differential analog signal outputs which can directly drive an 8 Ω load. The receive side
signal outputs can be selected by CR1-B5 and CR1-B4. If the amplifiers connected to EAR1O and EAR2O are not
being selected, the amplifiers are deactivated and their outputs are put into high impedance state. Gains of output
levels of the pins can be adjusted using the external resistors. The power control is accomplished by CR0-B6.
Refer to Figure 1.
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FEDL7041-04
OKI Semiconductor
ML7041
Transmit Gain
Vi
Vi
C
C
R1
R3
: VMIC1O/Vi = (R2/R1)
: VMIC2O/Vi = (R4/R3)
: VMIC3O/Vi = (R6/R5)
20 kΩ
20 kΩ
MIC1I
R2
R4
C
C
MIC1O
MIC2I
Input select
:CR1-B7, B6 “00” -> MIC1
:CR1-B7, B6 “01” -> MIC2
:CR1-B7, B6 “10” -> MIC3
:CR1-B7, B6 “11” -> no-input
A/D
MIC2O
Vi
R5
C
20 kΩ
MIC3–
MIC3+
Receive Gain
:Vspo/VEXTO = (R8/R7) × 2
R6
C
Output select
MIC3O
SG
:CR1-B5, B4 “00” -> EXTO
:CR1-B5, B4 “01” -> EAR1O
:CR1-B5, B4 “10” -> EAR2O
:CR1-B5, B4 “11” -> no-output
VREF
EAR1O
EAR2O
D/A
EXTO
EXTI
VEXTO
R7
R8
C
SPO–
VSPO
SPO+
Figure 1 Analog Interface
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FEDL7041-04
OKI Semiconductor
ML7041
SG
Analog signal ground.
The output voltage of this pin is approximately 1.4 V. Put the bypass capacitors 0.1 µF ceramic type between this
pin and GND to get the specified noise characteristics. During power-down, this output voltage is 0 V.
SWA, SWB, SWC
Used for an internal analog switch. The pin SWB is connected to the pin SWA or the pin SWC. This is controlled
by CR1-B1.
RG1PDN, RG1IN, RG1O
Used for Regulator 1. The RG1PDN pin is a power down input. When set to “L”, the Regulator 1 changes to the
power down state. Since the power down is controlled by a logical OR with CR5-B4 of the control register, set
CR5-B4 to logic “0” when using this pin. The RG1IN pin is input to the Regulator 1. The RG1O pin is output from
the Regulator 1, whose voltage is 3.0 V. A 1 µF ceramic type bypass capacitor must be connected between the
power input pin and GND, and a 10 µF tantalum bypass capacitor must be connected from the output pin to GND.
RG2PDN, RG2IN, RG2O
Used for Regulator 2. The RG2PDN pin is a power down input. When set to “L”, the Regulator 2 changes to the
power down state. Since the power down is controlled by a logical OR with CR5-B5 of the control register, set
CR5-B5 to logic “0” when using this pin. The RG2IN pin is the input to the Regulator 2. The RG2O pin is the
output from the Regulator 2, whose voltage is 3.0 V. A 1 µF ceramic type bypass capacitor must be connected
between the power input pin and GND, and a 10 µF tantalum bypass capacitor must be connected from the output
pin to GND.
Note1:The RG1O and RG2O outputs must not be used as the 3 V supply for the ML7041.
Note2:The RG1IN and RG2IN should be common near the device and supplied from the same power supply.
GP1, GP2, GP3, GP4
General purpose driver output. Each pin is controlled by CR5-B1 through CR5-B4. By selecting CR5-B7, the GP1
pin can be controlled by the receive side sign bit.
VDD, VA, VA1, VA2, VA3
VDD is the digital power supply. VA, VA1, VA2, and VA3 are the analog power supply pins. Since these pins are
separated in the device, connect them as close as possible on the PCB.
DG, AG, AG1, AG2, AG3, AGR1, AGR2, AGGP1, AGGP2
Ground. DG is the digital ground. AG, AG1, AG2, AG3, AGR1, AGR2, AGGP1 and AGGP2 are the analog
ground. Since these pins are separated in the device, connect them as close as possible on the PCB.
PDN
Power down and reset control input.
When set to digital “L”, the device changes to the power down state and the control register is reset. Since the
power down mode is controlled by a logical OR with CR0-B5 of the control register, set CR0-B5 to logic “0” when
using this pin. The reset pulse width must be 200 ns or more. Be sure to reset the control register after turning on
the power.
MCK
Master clock input.
The frequency must be 2.048 MHz. MCK can be asynchronous with SYNC and BCLK.
If a frequency of BCLK is 2.048 MHz, the BCLK can be shared with MCK.
BCLK
Shift clock input for the PCM data.
The frequency is set in the range of 64 kHz to 2048 kHz for A/µ-law PCM data and set in the range of 128 kHz to
2048 kHz for linear code selection.
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FEDL7041-04
OKI Semiconductor
ML7041
SYNC
8 kHz synchronous signal input for transmit and receive PCM data.
Synchronize this signal with BCLK signal. This signal is used to indicate the MSB of the PCM data stream.
PCMOUT
Transmit PCM data output. The PCM output signal is output from MSB, synchronously with the rising edges of
BCLK and SYNC. Refer to Figure 2. This is a logic output pin so that external pull-up is not required. This pin
outputs logic "L" except during effective PCM data bits, and outputs logic "H" during power-down.
PCMIN
Receive PCM data input.
The PCM input signal is shifted in on the falling edge of BCLK and is input from MSB.
8 kHz (125 µs)
SYNC
BCLK
PCMIN or
MSB
PCMOUT
* 14 bits when linear mode is selected
(a) Long frame synchronous interface
Refer to Figure 2.
8 kHz (125 µs)
SYNC
BCLK
PCMIN or
PCMOUT
LSB
MSB
* 14 bits when linear mode is selected
(b) Short frame synchronous interface
Figure 2 PCM Interface Basic Timing Diagram
8/28
FEDL7041-04
OKI Semiconductor
ML7041
SDA, SCL
SDA is the serial data input/output pin and SCL is the serial clock line input pin. A pull-up register of 1 to 10 kΩ is
required for the SDA pin. The master clock is required when data is written or read.
Transfer format
The control register can be controlled according to the I2C bus transfer format.
The control register address is 3 bits long and the register data is 8 bits long. The methods of writing and
reading of data are shown below.
SCL
A2 A1 A0
B7 B6 B5 B4 B3 B2 B1 B0
read-back
mode bit
“0”
register
address
register data
7-bit slave address
“0011010”
R/W
“0”
S
P
slave address write
register address write
register data write
Figure 3 I2C Interface Write Timing
SDA
SCL
A2 A1 A0
B7 B6 B5 B4 B3 B2 B1 B0
slave
address
read-back
mode bit
“0”
register
slave
address
register data
R/W
R/W
“0”
“1”
S
Sr
P
A
slave address write
register address write
slave address write
register data read
Figure 4 I2C Interface Read Timing: normal mode
SCL
A2 A1 A0
B7 B6
B1 B0
B7 B6
B1 B0
slave
read-back
mode bit
“1”
register
address
register data
register data
R/W
address
“0”
S
P
slave address write
register data write
register data read
register address write
Figure 5 I2C Interface Read Timing: read-back mode
ML7041 Slave address “0011010”
S
START condition
STOP condition
Acknowledged (ML7041 drive SDA to “0”)
Not Acknowledged
A
P
Sr Repeated START condition
Don’t care (“0” or “1”)
9/28
FEDL7041-04
OKI Semiconductor
ML7041
Table 1 shows the register map.
Table 1 Control Register Map
Address
Name
Control and Detect Data
RW
B0
A2 A1 A0
B7
A/µ
SEL
MIC
SEL1
B6
B5
B4
B3
B2
B1
SPOUT
PON
CR0
0
0
0
PDN ALL PDN TX PDN RX SLP SLP SEL LNR
R/W
SW
C/A
RX
SHORT
FRAME
CR1
CR2
CR3
0
0
0
0
1
1
1
0
1
MIC SEL0 SP SEL1 SP SEL0
—
RX PAD R/W
TX
ON/OFF
TX
RX
RX
RX
TX GAIN2 TX GAIN1
R/W
GAIN0 ON/OFF GAIN2 GAIN1 GAIN0
SIDE TONE SIDE TONE SIDE TONE TONE
TONE TONE
TONE TONE
R/W
GAIN2
GAIN1
GAIN0 ON/OFF GAIN3 GAIN2 GAIN1 GAIN0
DTMF/
OTHERS
SEL
TONE
SEND
CR4
1
0
0
—
TONE4 TONE3 TONE2 TONE1 TONE0 R/W
GP1 SEL
CR/TONE
VOX
ON/OFF
CR5
CR6
CR7
1
1
1
0
1
1
1
0
1
—
RG2PDN RG1PDN GP4C
GP3C
—
GP2C
—
GP1C R/W
ON LVL1
TX
—
—
—
—
—
—
—
R/W
R
VOX
OUT
TX
—
—
NOISE1 NOISE0
R/W: Read/Write enable R: Read only register
10/28
FEDL7041-04
OKI Semiconductor
ML7041
ABSOLUTE MAXIMUM RATINGS
Parameter
Power Supply Voltage
Analog Input Voltage
Digital Input Voltage
Storage Temperature
Symbol
Condition
Rating
–0.3 to +4.6
–0.3 to VDD+0.3
–0.3 to VDD+0.3
–55 to +150
+150
Unit
V
V
V
°C
°C
VDD
VAIN
VDIN
TSTG
Tjmax
—
—
—
—
—
Operating Junction Temperature *
RECOMMENDED OPERATING CONDITIONS
Parameter
Power Supply Voltage
Operating Temperature
Symbol
VDD
Condition
Min.
2.4
–40
Typ.
—
+25
Max.
3.3
+85
Unit
V
°C
—
—
Ta
Operating Junction Temperature
(Average) *
Tjmaxa
—
—
—
105
°C
Input High Voltage
Input Low Voltage
VIH
VIL
tir
all digital input pins
all digital input pins
all digital input pins
all digital input pins
all digital output pins
Between SG and AG
MCK
0.7 × VDD
0
—
—
—
—
—
—
2.048
—
VDD
0.20 × VDD
50
V
V
ns
ns
pF
µF
Digital Input Rise Time
Digital Input Fall Time
Digital Output Load
Bypass Capacitor for SG
Master Clock Frequency
—
—
—
0.1
–0.01%
64
128
—
tif
50
100
—
CDL
CSG
FMCK
+0.01% MHz
FBCK1 BCLK (A/µ-law)
FBCK2 BCLK (linear)
FSYNC SYNC
DCLK
TSB
TBS
tWS
2048
2048
—
60
100
—
kHz
kHz
kHz
%
ns
ns
Bit Clock Frequency
—
Synchronous Signal Frequency
Clock Duty Ratio
Sync Pulse Setting Time
8.0
50
—
—
—
MCK, BCLK
SYNC → BCLK
BCLK → SYNC
SYNC
40
-100
100
1BCLK
Synchronous Signal Width
100
µs
*
The device should be used in such a way that Tjmax (average) is less than 105°C.
jmax is given by the equation:
T
T
jmax = P × θ ja + Ta
where
P = Power dissipation (W)
A 48-pin TQFP package is used.
θ ja = 195°C (not mounted on a PCB, in still-air-ambient)
θ ja = 156°C (mounted on a typical PCB, in still-air-ambient)
For more details, refer to PACKAGE INFORMATION DATA BOOK.
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FEDL7041-04
OKI Semiconductor
ML7041
ELECTRICAL CHARACTERISTICS
DC Characteristics
(VDD = 2.4 to 3.3 V, Ta = –40 to +85°C)
Parameter
Symbol
IDD1
Condition
Operating mode
No signal (VDD = 3.0 V)
Min.
Typ.
Max.
Unit
0
5.0
11.0
mA
Operating mode
Power Supply Current
IDD2
No signal (VDD = 3.0 V)
SPO+, SPO– or EAR1, 2 is active
0
0
16.0
1.0
32.0
10
mA
Power down mode
(VDD = 3.0 V, Ta = 25°C)
IDD3
µA
IIH
IIL
VOH
VOL
CIN
VI = VDD
VI = 0 V
IOH = 0.4 mA
IOL = –1.2 mA
—
—
—
—
—
—
0.2
5
2.0
1.5
VDD
0.4
—
µA
µA
V
V
pF
Input Leakage Current
Output High Voltage
Output Low Voltage
Input Capacitance
0.5 × VDD
0
—
Analog Interface Characteristics
(VDD = 2.4 to 3.3 V, Ta = –40 to +85°C)
Parameter
Input Resistance
Symbol
Condition
MIC1I, MIC2I, MIC3–, MIC3+
MIC1O, MIC2O, MIC3O, EXTO
EAR1O, EAR2O
SPO+, SPO– differential output
Analog output
Min.
10
20
32
8
Typ.
—
—
—
—
Max.
—
—
—
—
Unit
MΩ
kΩ
Ω
RINX
RLGX1
RLGX2
RLGX3
CLGX
Output Load Resistance
Output Load Capacitance
Ω
—
—
50
pF
MIC1O, MIC2O, MIC3O,
EXTO, RL = 20 kΩ
VO1
—
—
1.3
VPP
EAR1O, EAR2O, RL = 32 Ω
SPO+, SPO–, (Differential output)
VDD = 3.0 V, RL = 8 Ω
SPO– (Single output)
VDD = 3.0 V, RL = 20 kΩ , THD = 1%
Output Amplitude *
VO2
VO3
—
—
2.6
—
VPP
VPP
2.0
2.6
EAR1O, EAR2O, SPO+, SPO–
Total Harmonic Distortion
Offset Voltage
THD
—
—
5.0
%
VDD = 3.0 V (at VO1, VO2)
VOFGX1
VOFGX2
MIC1O, MIC2O, MIC3O
EAR1O, EAR2O, SPO+, SPO–,
EXTO
–40
—
—
40
mV
mV
–100
100
SG Output Voltage
SG Output Impedance
VSG
RSG
SG
SG
—
—
1.4
40
—
80
V
kΩ
All internal analog switches
(1.4 V DC bias)
Internal switch ON
Impedance
RSW
—
—
300
Ω
* –7.7 dBm (600 Ω) = 0 dBm0, +3.17 dBm0 = 1.3 VPP
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ML7041
AC Characteristics
(VDD = 2.4 to 3.3 V, Ta = –40 to +85°C)
Condition
Parameter
Symbol
LOSS T1
Min.
Typ.
Max.
Unit
Frequency
(Hz)
Level
(dBm0)
Others
—
0 to 60
25
–0.15
—
—
—
0.20
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
LOSS T2 300 to 3000
LOSS T3
LOSS T4
LOSS T5
LOSS R6
1020
3300
3400
Reference
Transmit Frequency Response
0
0
–0.15
0
13
—
—
—
—
0.80
0.80
—
3968.75
LOSS R1 0 to 3000
–0.15
0.20
LOSS R2
LOSS R3
LOSS R4
LOSS R5
SD T1
SD T2
SD T3
SD T4
SD T5
SD R1
SD R2
SD R3
SD R4
SD R5
GT T1
GT T2
GT T3
GT T4
GT T5
GT R1
GT R2
GT R3
GT R4
GT R5
1020
3300
3400
Reference
Receive Frequency Response
*2
—
*1
*1
—
—
–0.15
0
13
35
35
35
28
23
35
35
35
28
23
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0.80
0.80
—
—
—
—
—
—
—
—
—
—
—
3968.75
3
0
–30
–40
–45
3
Transmit Signal to Distortion
Ratio
1020
1020
1020
1020
0
Receive Signal to Distortion
Ratio
–30
–40
–45
3
–10
–40
–50
–55
3
–10
–40
–50
–55
*2
–0.5
0.5
Reference
Transmit Gain Tracking
–0.5
–1.0
–1.2
–0.5
—
—
—
—
0.5
1.0
1.2
0.5
Reference
Receive Gain Tracking
*2
–0.5
–1.0
–1.2
—
—
—
0.5
1.0
1.2
*1 Use the P-message weighted filter.
*2 EXTO output
13/28
FEDL7041-04
OKI Semiconductor
ML7041
AC Characteristics (Continued)
(VDD = 2.4 to 3.3 V, Ta = –40 to +85°C)
Condition
Parameter
Symbol
NIDLT
Min.
Typ.
Max.
Unit
Frequency
(Hz)
Level
(dBm0)
MIC1I,
MIC2I,
MIC3 ±
= SG
Others
—
—
*1
—
—
—
–68 dBmOp
Idle Channel Noise
NIDLR
AVT
—
*1,*2,*4
—
–72
MIC1O,
MIC2O,
MIC3O
0.320
*3
0.285
0.359 Vrms
Absolute Signal Amplitude
1020
0
0.320
*3
AVR
EXTO
0.285
0.359 Vrms
Noise
Noise
level:
PSRRT
PSRRR
30
30
—
—
—
dB
dB
Power Supply Noise Rejection
Ratio
frequency:
—
—
0 to 50 kHz 50 mVpp
tSDX
tSDR
tXD1
tRD1
tXD2
tRD2
tXD3
tRD3
fSCL
tBUF
tHD:STA
tLOW
0
—
200
ns
1 LSTTL
0
0
0
—
—
—
200
200
200
ns
ns
ns
Digital Input/Output Timing PCM
Interface
See
—
+
Figure 6
100 pF
0
—
—
—
—
—
—
—
—
—
100
—
—
—
—
—
—
—
—
kHz
µs
µs
µs
µs
µs
µs
ns
µs
4.7
4.0
4.7
4.0
4.7
0
CL =
50 pF Figure 7
See
I2C Interface timing
—
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tSU:STO
250
4.0
*1 Use the P-message weighted filter.
*2 PCMIN input code “11010101” (A-law)
“11111111” (µ-law)
*3 0.320 Vrms = 0 dBm0 = –7.7 dBm
*4 EXTO output
14/28
FEDL7041-04
OKI Semiconductor
ML7041
AC Characteristics (DTMF and Other Tones)
(VDD = 2.4 to 3.3 V, Ta = –40 to +85°C)
Parameter
Frequency Difference
Symbol
Condition
Min.
–1.5
Typ.
—
Max.
+1.5
Unit
%
DFT DTMF Tones, Other Tones
DTMF (Low) and
Transmit tones
(gain setting of
0 dB)
VTL
–18
–16
–14 dBm0
–12 dBm0
Other Tones
DTMF (High)
DTMF (Low)
VTH
VRL
–16
–4
–14
–2
Original (reference) Tones Signal
Level *5
0
dBm0
dBm0
dB
Receive tones
(gain setting of
–6 dB)
DTMF (High) and
Other Tones
VRH
–2
+1
0
+2
+3
Relative Level of DTMF Tones
RDTMF VTH/VTL, VRH/VRL
+2
*5 Not including programmable gain set values
AC Characteristics (Programmable Gain Stages)
(VDD = 2.4 to 3.3 V, Ta = –40 to +85°C)
Parameter
Gain Accuracy
Symbol
DG
Condition
All gain stages, to programmed
value
Min.
Typ.
Max.
Unit
–1
0
+1
dB
AC Characteristics (Voice Detect Function)
(VDD = 2.4 to 3.3 V, Ta = –40 to +85°C)
Parameter
Symbol
TVON
Condition
Min.
Typ.
Max.
Unit
ms
ms
Silence → Voice
(Voice/silence differential: 10 dB)
—
5
—
Voice Detection Time
TVOF
140
160
180
For detection level set values by
CR6-B6
Voice Detection Accuracy
DVX
–2.5
0
2.5
dB
15/28
FEDL7041-04
OKI Semiconductor
ML7041
AC Characteristics (General Purpose Drivers)
(VDD = 2.4 to 3.3 V, Ta = –40 to +85°C)
Parameter
Output Voltage
Output Load Resistance
Symbol
VO
RO
Condition
Min.
—
20
Typ.
—
—
Max.
0.7
—
Unit
V
IOUT = 150 mA, GP1 - GP4
Ω
AC Characteristics (Regulator 1 and 2)
(VDD = 2.4 to 3.3 V, Ta = –40 to +85°C)
Parameter
Input Voltage
Symbol
Vi1
Condition
IOUT = 50 mA
Min.
3.3
3.5
Typ.
3.6
3.6
Max.
4.1
4.1
Unit
V
V
Vi2
IOUT = 150 mA
RGIN = 3.6 V,
Output Voltage
VO
2.93
3.00
3.07
V
I
OUT = 0 mA, Ta = 25°C
Load Current
Dropout Voltage
IO
3.5 V < RGIN < 4.1 V
—
—
—
—
150
200
mA
mV
VDROP IOUT = 150 mA , RGIN = 3.6 V
I
OUT = 50 mA
Output Voltage Line Regulation dVO/dVI
—
0.1
0.1
1.25
10
%/V
µA
3.3 V < RGIN < 4.1 V, Ta = 25°C
RG1PDN = 0, RG2PDN = 0
Standby Current
Istanby
16/28
FEDL7041-04
OKI Semiconductor
ML7041
TIMING DIAGRAM
Transmit Side PCM Timing (Normal Synchronous Interface)
1
2
4
7
BCLK
SYNC
tSB
tWS
tXD3
tXD1
tXD2
MSB
LSB
PCMOUT
tSDX
When tSB >= 0, the Delay of the MSB is defined as tXD1
When tSB < 0, the Delay of the MSB is defined as tSDX
.
.
Transmit Side PCM Timing (Short Frame Synchronous Interface)
BCLK
SYNC
tSB
tBS
tWS
tXD1
tXD2
tXD3
MSB
LSB
PCMOUT
Receive Side PCM Timing (Normal Synchronous Interface)
1
2
4
7
BCLK
SYNC
PCMIN
tSB
tWS
tRD3
tRD1
tRD2
MSB
LSB
tSDR
Receive Side PCM Timing (Short Frame Synchronous Interface)
1
2
4
7
BCLK
SYNC
PCMIN
tSB
tBS
tWS
tRD2
tRD3
tRD1
MSB
LSB
Figure 6 PCM Interface Timing
17/28
FEDL7041-04
OKI Semiconductor
ML7041
I2C Interface
SDA
tBUF
tHD:STA
tLOW
fSCL
SCL
tSU:STO
tHD:STA
tSU:STA
tSU:DAT
tHD:DAT
tHIGH
P
P
S
Sr
Figure 7 I2C Interface Timing
18/28
FEDL7041-04
OKI Semiconductor
ML7041
FUNCTIONAL DESCRIPTION
Control Registers
CR0 (Basic operating mode 1)
Note: The initial value means a value set when the device is reset by the PDN pin.
B7
A/µ
SEL
0
B6
B5
PDN
ALL
0
B4
PDN
TX
0
B3
PDN
RX
0
B2
SLP
0
B1
SLP
SEL
0
B0
LNR
0
SPOUT
PON
CR0
Initial value
0
B7....... PCM interface companding law select 0: µ-law 1: A-law
B6....... Power-on control for output amplifies (SPO+, SPO−) 0: Power down 1: Power on
B5....... Power down (entire circuitry)
0: Power on 1: Power down
ORed with the inverted PDN signal. When using this data, set PDN to “L”.
The control registers are not reset by this signal.
B4....... Power down (transmit only)
B3....... Power down (receive only)
B2....... Slope filter enable
0: Power on 1: Power down
0: Power on 1: Power down
0: Slope filter disable 1: Slope filter enable
B1....... Slope filter frequency response select 0: CASE1 1: CASE2
Either CASE1 or CASE2 can be selected in Figure 8.
B0....... PCM interface linear code select
0: PCM companding law selected by CR0-B7
1: 14-bit linear code (2’s complement)
6
4
2
0
CASE1
CASE2
–2
–4
–6
–8
–10
–12
–14
0
500
1000
1500
2000
Frequency [Hz]
Figure 8 Slope Filter Frequency Characteristics
2500
3000
3500
4000
19/28
FEDL7041-04
OKI Semiconductor
ML7041
CR1 (Basic operating mode 2)
B7
MIC
SEL1
0
B6
MIC
SEL0
0
B5
SP
SEL1
B4
SP
SEL0
B3
B2
—
0
B1
B0
SHORT
FRAME
SW
C/A
RX
PAD
CR1
Initial Value
0
0
0
0
0
B7, B6….. Selection of an input amplifier to encoder
(B7, B6) = (0, 0): MIC1
= (0, 1): MIC2
= (1, 0): MIC3
= (1, 1): No input
Amplifiers which are not selected are powered down and their outputs go in the high impedance
state.
B5, B4….. Selection of an output amplifier
(B5, B4) = (0, 0): EXTO
= (0, 1): EAR1O
= (1, 0): EAR2O
= (1, 1): No output
Amplifiers which are not selected are powered down and their outputs go in the high impedance
state.
B3 ……. Short frame synchronous interface select
0: Long frame synchronous interface,
1: Short frame synchronous interface
B2 ……. Not used. When writing data, write “0”.
B1 ……. Analog switch control
B0 ……. Receive side PAD
0: The SWB pin is internally connected to the SWA pin.
1: The SWB pin is internally connected to the SWC pin.
The unconnected pins go in a high impedance state.
0: No pad
1: A pad of 12 dB loss is inserted in the receive side voice path.
20/28
FEDL7041-04
OKI Semiconductor
ML7041
CR2 (PCM CODEC operating mode setting and transmit/receive gain adjustment)
B7
B6
B5
B4
B3
B2
B1
B0
TX
ON/OFF
RX
ON/OFF
CR2
TX GAIN2 TX GAIN1 TX GAIN0
RX GAIN2 RX GAIN1 RX GAIN0
Initial Value
0
0
1
1
0
0
1
1
B7 .................Transmit side PCM signal ON/OFF
0: ON 1: OFF
B6, B5, B4.....Transmit side signal gain adjustment (refer to Table 2)
B3 .................Receive side PCM signal ON/OFF
0: ON 1: OFF
B2, B1, B0.....Receive side signal gain adjustment (refer to Table 2)
Table 2 Transmit/Receive Gain Settings
B6
0
0
B5
0
0
B4
0
1
Transmit Gain
–6 dB
B2
0
0
B1
0
0
B0
0
1
Receive Gain
–12 dB
–9 dB
–4 dB
0
1
0
–2 dB
0
1
0
–6 dB
0
1
1
0 dB
0
1
1
–3 dB
1
1
1
1
0
0
1
1
0
1
0
1
+2 dB
+4 dB
+6 dB
+8 dB
1
1
1
1
0
0
1
1
0
1
0
1
0 dB
+3 dB
+6 dB
+9 dB
The above gain settings table shows the transmit/receive voice signal gain settings and the transmit side
gain settings for DTMF tones and other tones. The DTMF and other tone transmit signals are enabled
by CR4-B6, and the gain setting is referenced to the levels shown below.
DTMF tones (low group):.............................. –16 dBm0
DTMF tones (high group) and other tones: ... –14 dBm0
For example, if the transmit gain set value is set to +8 dB (B6, B5, B4) = (1,1,1), then the following tones
are output at the PCMOUT pin.
DTMF tones (low group):.............................. –8 dBm0
DTMF tones (high group) and other tones: ... –6 dBm0
Gains of the side tone (path to receive side from transmit side) and the receive side tone can be set by
register CR3.
21/28
FEDL7041-04
OKI Semiconductor
ML7041
CR3 (Side tone and other tone generator gain setting)
B7
B6
B5
B4
B3
B2
B1
B0
SIDE TONE SIDE TONE SIDE TONE TONE
TONE
GAIN3
TONE
GAIN2
TONE
GAIN1
TONE
GAIN0
CR3
GAIN2
0
GAIN1
0
GAIN0
0
ON/OFF
0
Initial Value
0
0
0
0
B7, B6, B5 ......... Side tone path gain setting (refer to Table 3)
B4...................... Tone generator ON/OFF 0: OFF 1: ON
B3, B2, B1, B0... Tone generator gain adjustment for receive side (refer to Table 4)
Table 3 Side Tone Gain Settings
B7
0
B6
0
B5
0
Side Tone Path Gain
OFF
0
0
0
1
0
1
1
0
1
0
1
0
–15 dB
–13 dB
–11 dB
–9 dB
1
0
1
–7 dB
1
1
0
–5 dB
1
1
1
–3 dB
Table 4 Receive Side Tone Generator Gain Settings
B3 B2 B1 B0 Tone Generator Gain B3 B2 B1 B0 Tone Generator Gain
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
OFF
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
–20 dB
–18 dB
–16 dB
–14 dB
–12 dB
–10 dB
–8 dB
–34 dB
–32 dB
–30 dB
–28 dB
–26 dB
–24 dB
–22 dB
–6 dB
The receive side tone generator gain settings shown in Table 4 are referenced to the following levels as
a reference.
DTMF tones (low group):..............................+4 dBm0
DTMF tones (high group) and others tones: .+6 dBm0
For example, if the tone generator gain set value is set to –6 dB (B3, B2, B1, B0) = (1, 1, 1, 1), then
tones at the following levels are output at EXTO.
DTMF tone (low group): ...............................–2 dBm0
DTMF tone (high group) and other tones:..... 0 dBm0
22/28
FEDL7041-04
OKI Semiconductor
ML7041
CR4 (Tone generator operating mode and frequency select)
B7
DTMF/
Others SEL SEND
B6
TONE
B5
—
0
B4
TONE4
0
B3
TONE3
0
B2
TONE2
0
B1
TONE1
0
B0
TONE0
0
CR4
Initial Value
0
0
B7...........................DTMF or other tones select
0: Others
1: DTMF
B6...........................Tone transmit enable (Transmit side) 0: Voice signal transmit 1: Tone transmit
B5...........................Not used. When writing data, write “0”.
B4, B3, B2, B1, B0.. Tone frequency setting (refer to Tables 5-1 and 5-2)
(a) B7 = 1 (DTMF tone)
Table 5-1 Tone Generator Frequency Settings
B4 B3 B2 B1 B0
Frequency
B4 B3 B2 B1 B0
Frequency
*
*
*
*
*
*
*
*
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
697 Hz + 1209 Hz
697 Hz + 1336 Hz
697 Hz + 1477 Hz
697 Hz + 1633 Hz
770 Hz + 1209 Hz
770 Hz + 1336 Hz
770 Hz + 1477 Hz
770 Hz + 1633 Hz
*
*
*
*
*
*
*
*
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
852 Hz + 1209 Hz
852 Hz + 1336 Hz
852 Hz + 1477 Hz
852 Hz + 1633 Hz
941 Hz + 1209 Hz
941 Hz + 1336 Hz
941 Hz + 1477 Hz
941 Hz + 1633 Hz
*Undefined
(b) B7 = 0 (Other tones)
B4 B3 B2 B1 B0
Table 5-2 Tone Generator Frequency Settings
Frequency
B4 B3 B2 B1 B0
Frequency
1200 Hz
2730 Hz/2500 Hz
8 Hz wamb.
2000 Hz/2667 Hz
8 Hz wamb.
1000 Hz/1333 Hz
8 Hz wamb.
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
1
1
0
0
0
0
0
0
0
0
1
0
1
0
1300 Hz
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
1
1
1
0
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
1477 Hz
1633 Hz
2000 Hz
2100 Hz
2400 Hz
2500 Hz
400 Hz
440 Hz
480 Hz
667 Hz
800 Hz
1000 Hz
2700 Hz
3000 Hz
23/28
FEDL7041-04
OKI Semiconductor
ML7041
CR5 (Regulator control, General purpose driver control)
B7
GP1 SEL
CR/TONE
0
B6
—
0
B5
B4
B3
GP4C
0
B2
GP3C
0
B1
GP2C
0
B0
GP1C
0
CR5
RG2PDN RG1PDN
Initial Value
0
0
B7...................... Selection of how to control General purpose driver 1.
0: Control register CR5-B0 1: GP1 is controlled by a sign bit of the receiver.
B6...................... Not used
B5...................... Power down control for Regulator 2
0: Power down
1: Power on
When using this data, set the RG2PDN pin at a “L” level.
B4...................... Power down control for Regulator 1
0: Power down
When using this data, set the RG1PDN pin at a “L” level.
B3, B2, B1, B0... General purpose driver control
0: Off (high impedance) 1: On (“L” output)
1: Power on
CR6 (VOX function control)
B7
VOX
ON/OFF
B6
ON
LVL1
0
B5
––
*
B4
––
0
B3
––
0
B2
––
0
B1
––
0
B0
––
0
CR6
Initial Value
0
B7................................Voice/silence detect function ON/ OFF 0: OFF 1: ON
If B7 is set to a logic “1”, B3 should be set to a logic “1”.
B6................................Voice detector level setting
0: –26 dBm0 1: –38 dBm0
B5................................Reserved bit. When writing data, write “0”.
B4, B3, B2, B1, B0.......Not used. When writing data, write “0”.
CR7 (Detect register, read only)
B7
VOX
OUT
0
B6
B5
B4
––
*
B3
––
*
B2
––
*
B1
––
*
B0
––
*
TX Noise TX Noise
Level1
0
CR7
Level0
0
Initial Value
*Used for testing the device and undefined
B7............................. Transmit side voice/silence detection 0: silence 1: voice detect
B6, B5....................... Transmit side silence detect level (indicator)
(0,0): Below –50 dBm0 (0,1): –40 to –50 dBm0
(1,0): –30 to –40 dBm0 (1,1): Above –30 dBm0
Note: These outputs are enabled only when the VOX (CR6-B7) = “1”.
B4, B3, B2, B1, B0.... Not used
24/28
FEDL7041-04
OKI Semiconductor
ML7041
APPLICATION CIRCUIT
VDD
VDD (3.0 V)
Mic
GND
C =
C = 1 µF
10 µF
R
MIC1I
20 kΩ
20 kΩ
Voice
detect
PCM
Com-
pand
PCMOUT
MIC1O
R
MIC2I
R
A/D
Slope
Filter
BPF
C
BCLK
SYNC
MIC2O
TONE/DTMF
Gen
C
MIC3–
MIC3+
VDD (3.6 V)
R
C
20 kΩ
D/A
LPF
PCM
Expand
MIC3O
R
C = 1 µF
SG
RG1IN(3.6 V)
C
EAR1O
Regulator1
(150 mA)
Other
IC
RG1O(3.0 V)
RG1PDN
32 Ω
+
Hands Free
Kit
C=10µF
RG2IN(3.6 V)
RG2O(3.0 V)
RG2PDN
Regulator2
(150 mA)
Other
IC
20 kΩ
Speaker
Phone
+
EAR2O
Sign bit
C=10µF
32 Ω
GP1(150 mA)
GP2(150 mA)
C
Buzzer
LCD
IN
Key Pad
Vibrator
MCU I/F
(I2C)
SG
VREF
Earphone
GP4(150 mA)
AGGP
8 Ω
8 Ω
C=0.1µF
R
3 V
R = 1k to 10 kΩ
R
C
C
Speaker
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FEDL7041-04
OKI Semiconductor
ML7041
PACKAGE DIMENSIONS
(Unit: mm)
TQFP48-P-0707-0.50-K
Mirror finish
Package material
Lead frame material
Pin treatment
Package weight (g)
Rev. No./Last Revised
Epoxy resin
42 alloy
Solder plating (≥5µm)
0.13 TYP.
4/Oct. 28, 1996
5
Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow mounting and humidity
absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product
name, package name, pin number, package code and desired mounting conditions (reflow method,
temperature and times).
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FEDL7041-04
OKI Semiconductor
ML7041
REVISION HISTORY
Page
Document
No.
Date
Description
Previous Current
Edition
Edition
FEDL7041-01
FEDL7041-02
Nov. 2000
―
―
1st Edition
Jun. 16, 2004
8
8
More clarification of PCMOUT output state
Addition of tSB
11
17
24
11
17
24
FEDL7041-03
FEDL7041-04
Nov. 2, 2005
Mar. 2, 2006
Addition of tSB
Addition of description about tXD1 and tSDX
Addition of description about CR6-B3
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FEDL7041-04
OKI Semiconductor
NOTICE
ML7041
1. The information contained herein can change without notice owing to product and/or technical improvements.
Before using the product, please make sure that the information being referred to is up-to-date.
2. The outline of action and examples for application circuits described herein have been chosen as an explanation
for the standard action and performance of the product. When planning to use the product, please ensure that the
external conditions are reflected in the actual circuit, assembly, and program designs.
3. When designing your product, please use our product below the specified maximum ratings and within the
specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating
temperature.
4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation
resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or
unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified
maximum ratings or operation outside the specified operating range.
5. Neither indemnity against nor license of a third party’s industrial and intellectual property right, etc. is granted
by us in connection with the use of the product and/or the information and drawings contained herein. No
responsibility is assumed by us for any infringement of a third party’s right which may result from the use
thereof.
6. The products listed in this document are intended for use in general electronics equipment for commercial
applications (e.g., office automation, communication equipment, measurement equipment, consumer
electronics, etc.). These products are not, unless specifically authorized by Oki, authorized for use in any
system or application that requires special or enhanced quality and reliability characteristics nor in any system
or application where the failure of such system or application may result in the loss or damage of property, or
death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace
equipment, nuclear power control, medical equipment, and life-support systems.
7. Certain products in this document may need government approval before they can be exported to particular
countries. The purchaser assumes the responsibility of determining the legality of export of these products and
will take appropriate and necessary steps at their own expense for these.
8. No part of the contents contained herein may be reprinted or reproduced without our prior permission.
Copyright 2006 Oki Electric Industry Co., Ltd.
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