TEA1206T [NXP]
High efficiency DC/DC converter; 高效率DC / DC转换器
| 型号： | TEA1206T |
| 厂家： | 
NXP |
| 描述： | High efficiency DC/DC converter |
| 文件： | 总16页 (文件大小：82K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
TEA1206T
High efficiency DC/DC converter
Preliminary specification
1999 Sep 16
Supersedes data of 1998 Mar 24
File under Integrated Circuits, IC03
Philips Semiconductors
Preliminary specification
High efficiency DC/DC converter
TEA1206T
FEATURES
APPLICATIONS
• Fully integrated DC/DC converter circuit
• Up-or-down conversion
• Cellular and cordless phones, PDAs and others
• Supply voltage source for low-voltage chip sets
• Portable computers
• Start-up from 1.8 V input
• Adjustable output voltage
• Battery backup supplies
• High efficiency over large load range
• Cameras.
• Power handling capability up to 1 A continuous
average current
GENERAL DESCRIPTION
• 600 kHz switching frequency
• Low quiescent power consumption
• Synchronizes to external 9 to 20 MHz clock
• True current limit for Li-ion battery compatibility
• Up to 100% duty cycle in down mode
• Undervoltage lockout
The TEA1206T (see Fig.1) is a fully integrated DC/DC
converter circuit. Efficient, compact and dynamic power
conversion is achieved using a novel, digitally controlled
Pulse Width and Frequency Modulation (PWFM) like
control concept, integrated low RdsON CMOS power
switches with low parasitic capacitances, and fully
synchronous rectification. The device operates at a high
590 kHz switching frequency which enables the use of
minimum size external components. Deadlock is
prevented by an on-chip undervoltage lockout circuit.
Compatibility with Li-ion batteries is guaranteed by an
accurate current limit function.
• Shut-down function
• 8-pin SO package.
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME
DESCRIPTION
plastic small outline package; 8 leads; body width 3.9 mm
VERSION
TEA1206T
SO8
SOT96-1
1999 Sep 16
2
Philips Semiconductors
Preliminary specification
High efficiency DC/DC converter
TEA1206T
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Voltage levels
VO(up)
VO(down)
Vi(up)
output voltage range in up mode
output voltage range in down mode
input voltage range in up mode
input voltage range in down mode
start-up voltage
U/D = LOW
2.80
−
−
−
−
5.50
V
U/D = HIGH
1.25
Vstart
2.80
1.40
1.19
5.50
5.50
5.50
1.85
1.29
V
V
V
V
V
U/D = LOW
Vi(down)
Vstart
U/D = HIGH
up mode; IL < 200 mA
1.60
1.24
Vfb
feedback voltage level
Current levels
Iq
quiescent current at pin 3
down mode, Vi = 3.6 V 65
75
2
85
µA
µA
A
Ishdwn
IlimN
IlimP
ILx
shut-down current
−
10
current limit NFET
up mode; note 1
0.5
0.5
−
−
5.0
5.0
1.0
current limit PFET
down mode; note 1
−
A
maximum continuous current at pin 4
−
A
Power MOSFETS
RdsON(N) pin-to-pin resistance NFET
RdsON(P) pin-to-pin resistance PFET
Efficiency; see Fig.5
0.08
0.10
0.14
0.16
0.20
0.25
Ω
Ω
η
efficiency
Vi = 3.6 V; L = 10 µH
IL = 1 mA
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
Vi = 3.6 up to 4.6 V
86
93
93
93
93
87
%
%
%
%
%
%
IL = 10 mA
IL = 50 mA
IL = 100 mA
IL = 500 mA
IL = 1000 mA; pulsed
load current
Vi = 3.6 down to 1.8 V
IL = 1 mA
−
−
−
−
−
−
83
90
91
87
88
82
−
−
−
−
−
−
%
%
%
%
%
%
IL = 10 mA
IL = 50 mA
IL = 100 mA
IL = 500 mA
IL = 1000 mA; pulsed
load current
Timing
fsw
switching frequency
PWM mode
475
9
560
13
645
20
−
kHz
MHz
µs
fsync
tres
sync input frequency
response time from standby to Pmax
−
25
Note
1. Current limit is defined by an external resistor Rlim, having 1% accuracy. The typical value is presettable between
0.5 and 5.0 A with a spread of ±17.5%.
1999 Sep 16
3
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P-type POWER FET
4
2
3
LX
UPOUT/DNIN
I/V
INTERNAL
SUPPLY
CONVERTER
sense FET
START-UP
ILIM
TEA1206T
CIRCUIT
7
CONTROL LOGIC
AND
MODE GEARBOX
FB
CURRENT LIMIT
COMPARATORS
I/V
CONVERTER
N-type
POWER
FET
TEMPERATURE
PROTECTION
BAND GAP
REFERENCE
TIME
COUNTER
sense
FET
13 MHz
OSCILLATOR
SYNC
GATE
DIGITAL CONTROLLER
6
5
8
1
MGM666
GND
SYNC
SHDN U/D
Fig.1 Block diagram.
Philips Semiconductors
Preliminary specification
High efficiency DC/DC converter
TEA1206T
PINNING
SYMBOL
U/D
PIN
DESCRIPTION
1
2
3
conversion mode selection input
current limit resistor connection
handbook, halfpage
U/D
1
2
3
4
8
7
6
5
SHDWN
FB
ILIM
ILIM
UPOUT/DNIN
up mode; output voltage/
down mode; input voltage
TEA1206T
UPOUT/DNIN
LX
GND
LX
4
5
6
7
8
inductor connection
synchronization clock input
ground
SYNC
SYNC
GND
FB
MGM667
feedback input
Fig.2 Pin configuration.
SHDWN
shut-down input
FUNCTIONAL DESCRIPTION
Control mechanism
cycle. As soon as more load current is taken from the
output the output voltage starts to decay. When the output
voltage becomes lower than the low limit of the window,
a corrective action is taken by a ramp-up of the inductor
current during a much longer time. As a result, the DC
current level is increased and normal PWM control can
continue. The output voltage (including ESR effect) is
again within the predefined window.
The TEA1206T DC/DC converter is able to operate in PFM
(discontinuous conduction) or PWM (continuous
conduction) operation. All switching actions are completely
determined by a digital control circuit which uses the
output voltage level as its control input. This novel digital
approach enables the use of a new pulse width and
frequency modulation scheme, which ensures optimum
power efficiency over the complete range of operation of
the converter. The scheme works as follows.
Figure 4 depicts the spread of the output voltage window.
The absolute value is most dependent on spread, while the
actual window size is not affected. For one specific device,
the output voltage will not vary more than 2% typically.
When high output power is requested, the device will
operate in PWM (continuous conduction) mode.
This results in minimum AC currents in the circuit
components and hence optimum efficiency, cost and
EMC. In this mode, the output voltage is allowed to vary
between two predefined voltage levels. As long as the
output voltage stays within this so-called window,
switching continues in a fixed pattern. When the output
voltage reaches one of the window borders, the digital
controller immediately reacts by adjusting the pulse width
and inserting a current step in such a way that the output
voltage stays within the window with higher or lower
current capability. This approach enables very fast
reaction to load variations.
In low output power situations, TEA1206T will switch over
to PFM (discontinuous conduction) mode operation. In this
mode, regulation information from earlier PWM mode
operation is used. This results in optimum inductor peak
current levels in PFM mode, which are slightly larger than
the inductor ripple current in PWM mode. As a result, the
transition between PFM and PWM mode is optimal under
all circumstances. In PFM mode, TEA1206T regulates the
output voltage to the high window limit shown in Fig.3.
Synchronous rectification
For optimal efficiency over the whole load range,
synchronous rectifiers inside TEA1206T ensure that
during the whole second switching phase, all inductor
current will flow through the low-ohmic power MOSFETS.
Special circuitry is included which detects that the inductor
current reaches zero. Following this detection, the digital
controller switches off the power MOSFET and proceeds
regulation.
Figure 3 shows the converter’s response to a sudden load
increase. The upper trace shows the output voltage.
The ripple on top of the DC level is a result of the current
in the output capacitor, which changes in sign twice per
cycle, times the capacitor’s internal Equivalent Series
Resistance (ESR). After each ramp-down of the inductor
current, i.e. when the ESR effect increases the output
voltage, the converter determines what to do in the next
1999 Sep 16
5
Philips Semiconductors
Preliminary specification
High efficiency DC/DC converter
TEA1206T
Start-up
Current limiters
Start-up from low input voltage in boost mode is realised
by an independent start-up oscillator, which starts
switching the N-type powerfet as soon as the voltage at
pin 3 is measured to be sufficiently high. The switch
actions of the start-up oscillator will increase the output
voltage. As soon as the output voltage is high enough for
normal regulation, the digital control system takes over the
control over the power MOSFETS.
If the current in one of the power switches exceeds its limit
in PWM mode, current ramping is stopped immediately,
and the next switching phase is entered. Current limitation
is required to enable optimal use of energy in Lithium-Ion
batteries, and to keep power conversion efficient during
temporary high loads. Furthermore, current limitation
protects the IC against overload conditions, inductor
saturation, etc. The current limit level is set by an external
resistor which must be connected to pin 2.
Undervoltage lockout
External synchronisation
As a result of too high load or disconnection of the input
power source, the output voltage can drop so low that
normal regulation cannot be guaranteed. In that case, the
device switches back to start-up mode. If the output
voltage would drop down even further, switching is
stopped completely.
If a high-frequency clock is applied to the external
synchronisation pin, the switching frequency in PWM
mode will be exactly that frequency divided by 22. In PFM
mode, the switching frequency is always lower.
The quiescent current of the device increases when an
external clock is applied. In case no external
synchronisation is necessary, the sync pin must be tied to
ground level.
Shut-down
When the shut-down pin is made HIGH, the converter
disables both switches and power consumption is reduced
to a few µA.
Behaviour at regulation limits
In two cases, the output voltage will not stay in normal
regulation because of excessive input voltage:
Power switches
• Upconversion (see Fig.6): the output voltage will exceed
the high window limit if the input voltage is higher than
this limit plus the voltage drop over the diode. In that
case, the converter will stop switching and the external
schottky diode will take over all current. The output
voltage will be equal to Vi minus the diode voltage drop.
The input voltage must not exceed 5.5 V. The current
limit function is not active since all current flows through
the external diode in this situation.
The power switches in the IC are one N-type and one
P-type MOSFET, having a typical pin-to-pin resistance of
0.14 Ω and 0.16 Ω respectively. The maximum average
current in the switches is 1.0 A.
Temperature protection
When the device operates in PWM mode, and the device
temperature gets too high (typically 175 °C), the converter
stops operating. It resumes operation when the device
temperature falls below 175 °C again. As a result,
low-frequent cycling between on and off state will occur.
It should be noted that in the event of device temperatures
around the cut-off limit, the application differs strongly from
maximum specifications.
• Downconversion (see Fig.7): the output voltage will get
lower than the lower window limit when the input voltage
is lower than this limit plus the voltage drop over the
P-type FET. In that case, the P-type FET will stay
conducting (100% duty cycle) resulting in Vo being equal
to Vi minus some resistive voltage drop. The input
voltage must not be lower than 2.8 V. The current limit
function remains active.
1999 Sep 16
6
Philips Semiconductors
Preliminary specification
High efficiency DC/DC converter
TEA1206T
load increase
start corrective action
V
o
high window limit
low window limit
time
I
L
MGK925
time
Fig.3 Response to load increase.
maximum positive spread
V
h
upper specification limit
2%
V
l
+4%
V
h
V
out, typ
2%
V
l
−4%
V
h
2%
lower specification limit
V
l
typical situation
maximum negative spread
MGM669
Fig.4 Output voltage window spread.
7
1999 Sep 16
Philips Semiconductors
Preliminary specification
High efficiency DC/DC converter
TEA1206T
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
Vn
PARAMETER
voltage on any pin
CONDITIONS
shut-down mode
operational mode
MIN.
−0.2
MAX.
+6.5
UNIT
V
V
−0.2
−25
+5.9
Tj
junction temperature
+150
+80
°C
°C
°C
V
Tamb
Tstg
Ves
Ves
operating ambient temperature
storage temperature
−40
−40
+150
+3000
+1000
electrostatic handling, pins 1,2,3,5,6,8 note 1
electrostatic handling, pins 4 and 7 note 1
−3000
−1000
V
Note
1. Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 kΩ series resistor.
THERMAL CHARACTERISTICS
SYMBOL
PARAMETER
CONDITIONS
in free air
VALUE
UNIT
Rth(j-a)
thermal resistance from junction to ambient
150
K/W
QUALITY SPECIFICATION
In accordance with “SNW-FQ-611 part E”.
1999 Sep 16
8
Philips Semiconductors
Preliminary specification
High efficiency DC/DC converter
TEA1206T
CHARACTERISTICS
Tj = −40 to +80 °C; all voltages with respect to ground; positive currents flow into the IC; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Voltage levels
VO(up)
VO(down)
Vi(up)
Vi(down)
Vstart
output voltage range in up mode
output voltage range in down mode
input voltage range in up mode
input voltage range in down mode
start-up voltage
U/D = LOW
2.80
−
−
−
−
5.50
V
V
V
V
V
V
U/D = HIGH
1.25
Vstart
2.80
1.40
1.19
5.50
5.50
5.50
1.85
1.29
3.0
U/D = LOW
U/D = HIGH; note 1
up mode; IL < 200 mA
1.60
1.24
2.0
Vfb
feedback voltage level
Vwdw
Vuvlo
output voltage window spread
undervoltage lockout level
PWM mode; see Fig.4 1.5
%
V
up mode; note 2
1.50
2.10
2.50
Current levels
Iq
quiescent current at pin 3
V3 = 3.6 V; note 3
65
−
75
2
85
µA
µA
A
Ishdwn
IlimN
IlimP
ILx
shut-down current
10
current limit NFET
up mode; note 4
0.5
0.5
−
−
5.0
5.0
1.0
current limit PFET
down mode; note 4
−
A
maximum continuous current at pin 4
−
A
Power MOSFETS
RdsON(N) pin-to-pin resistance NFET
RdsON(P) pin-to-pin resistance PFET
Efficiency; see Fig.5
0.08
0.10
0.14
0.16
0.20
0.25
Ω
Ω
η
efficiency
Vi = 3.6 V; note 5
IL = 1 mA
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
Vi = 3.6 up to 4.6 V
86
93
93
93
93
87
%
%
%
%
%
%
IL = 10 mA
IL = 50 mA
IL = 100 mA
IL = 500 mA
IL = 1000 mA; pulsed
load current
Vi = 3.6 down to 1.8 V
IL = 1 mA
−
−
−
−
−
−
83
90
91
87
88
82
−
−
−
−
−
−
%
%
%
%
%
%
IL = 10 mA
IL = 50 mA
IL = 100 mA
IL = 500 mA
IL = 1000 mA; pulsed
load current
Timing
fsw
switching frequency
PWM mode
475
9
560
13
645
20
−
kHz
MHz
µs
fsync
tres
sync input frequency
response time from standby to Pmax
−
25
1999 Sep 16
9
Philips Semiconductors
Preliminary specification
High efficiency DC/DC converter
TEA1206T
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Temperature
Tamb
Tmax
operating ambient temperature
internal cut-off temperature
−40
+25
+80
°C
150
175
200
°C
Digital levels
VlL
VIH
VIH
LOW-level input voltage pins 1, 5 and 8
0
−
0.5
V
HIGH-level input voltage pin 1
note 6
note 6
V3 − 0.4 −
0.55V3
V3 + 0.3 V
V3 + 0.3 V
HIGH-level input voltage pins 5 and 8
−
Notes
1. At Vi lower than the target output voltage, but higher than 2.8 V, the PFET will remain conducting (100% duty cycle),
resulting in Vo following the input voltage.
2. The undervoltage lockout level shows wide specification limits since it decreases at increasing temperature. Since
the minimum supply voltage of the digital control part also decreases when temperature goes up, correct operation
of this function is guaranteed over the whole temperature range.
3. V3 is the voltage at pin 3 (UPOUT/DNIN).
4. Current limit is defined by an external resistor Rlim, having 1% accuracy. The typical value is presettable between
0.5 and 5.0 A with a spread of ±17.5%.
5. The specified efficiency is valid when using an output capacitor having an ESR of 0.10 Ω and a Coilcraft
DT1608C-103 10 µH small size inductor.
6. If the applied high level is less than V3 − 1 V, the quiescent current level of the device will increase.
MGM668
100
efficiency
(1)
(2)
(%)
90
80
70
60
2
3
1
10
10
10
I
(mA)
L
(1) Represents the curve for upconversion from 3.6 to 4.6 V. The solid line indicates PFM and the dashed line indicates PWM.
(2) Represents the curve for downconversion from 3.6 to 1,8 V. The solid line indicates PFM and the dashed line indicates PWM.
Vi = 3.6 V; L = 10 µH (DT1608-103); Cout = 330 µF (Sprague 595D) capacitor.
Fig.5 Efficiency as a function of load current IL.
1999 Sep 16
10
Philips Semiconductors
Preliminary specification
High efficiency DC/DC converter
TEA1206T
APPLICATION INFORMATION
D1
UPOUT/DNIN
V
O
L1
R1
R2
V
LX
TEA1206T
I
FB
C2
C1
U/D GND SYNC SHDWN ILIM
R
lim
MGM670
Fig.6 Complete application for upconversion.
L1
V
V
UPOUT/DNIN
LX
I
O
TEA1206T
R1
R2
FB
C2
C1
U/D ILIM SYNC
GND SHDWN
D2
R
lim
MGM671
Fig.7 Complete application for downconversion.
11
1999 Sep 16
Philips Semiconductors
Preliminary specification
High efficiency DC/DC converter
TEA1206T
External component selection
OUTPUT VOLTAGE SETTING
INDUCTOR
The output voltage level is determined by the resistors R1
and R2. The following conditions apply:
The performance of the TEA1206 is not very sensitive to
inductance value. Best efficiency performance over a wide
load current range is achieved by using e.g. TDK
SLF7032-6R8M1R6, having an inductance of 6.8 µH and
a saturation current level of 1.6 A. In case the maximum
output current is lower, other inductors are also suitable
like the small sized Coilcraft DT1608 range.
• Use 1% accurate SMD type resistors only. In case larger
body resistors are used, the capacitance on pin 7 (FB)
will be too large, causing inaccurate operation.
• Resistors R1 and R2 shall have a maximum value of
50 kΩ when connected in parallel. A higher value will
result in inaccurate operation.
Under these conditions, the output voltage can be set by
the formula: Vout = 1.24 × (1 + R1/R2).
INPUT CAPACITANCE
The value of Cin strongly depends on the type of input
source. In general, a 100 µF tantalum capacitor will do, or
a 10 µF ceramic capacitor featuring very low series
resistance (ESR).
CURRENT LIMIT SETTING
The maximum instantaneous current is set by the external
resistor Rlim. Preferred type is SMD, 1% accurate.
The connection of Rlim differs per mode:
OUTPUT CAPACITOR
• In UP conversion mode, Rlim must be connected
between pin 2 (ILIM) and pin 3 (UPOUT/DNIN).
The current limit level is defined by: IlimN = 440/ Rlim
The value and type of Cout depends on the maximum
output current and the ripple voltage which is allowed in
the application. Low-ESR tantalum as well as ceramic
capacitors show good results. Most important specification
of Cout is its ESR, which mainly determines output voltage
ripple.
.
• In DOWN conversion mode, Rlim must be connected
between pin 2 (ILIM) and pin 6 (GND).
The current limit level is defined by: IlimP = 650/ Rlim
.
The average inductor current during current limit also
DIODE
depends on inductance value and resistive losses in all
components in the power path. Ensure that Ilim < Isat of the
inductor.
The schottky diode is only used during a small time during
takeover from N-type powerfet and P-type powerfet and
vice versa. Therefore, a medium-power diode like Philips
PRLL5819 is sufficient.
1999 Sep 16
12
Philips Semiconductors
Preliminary specification
High efficiency DC/DC converter
TEA1206T
PACKAGE OUTLINE
SO8: plastic small outline package; 8 leads; body width 3.9 mm
SOT96-1
D
E
A
X
c
y
H
v
M
A
E
Z
5
8
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
4
e
w
M
detail X
b
p
0
2.5
5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(2)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
5.0
4.8
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.27
0.050
1.05
0.041
1.75
0.25
0.01
0.25
0.01
0.25
0.1
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.20
0.014 0.0075 0.19
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.024
0.028
0.012
inches 0.069
0.01 0.004
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
95-02-04
97-05-22
SOT96-1
076E03S
MS-012AA
1999 Sep 16
13
Philips Semiconductors
Preliminary specification
High efficiency DC/DC converter
TEA1206T
SOLDERING
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
Introduction to soldering surface mount packages
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.
The footprint must incorporate solder thieves at the
downstream end.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Reflow soldering
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Manual soldering
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
Wave soldering
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
To overcome these problems the double-wave soldering
method was specifically developed.
If wave soldering is used the following conditions must be
observed for optimal results:
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
1999 Sep 16
14
Philips Semiconductors
Preliminary specification
High efficiency DC/DC converter
TEA1206T
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE
WAVE
REFLOW(1)
BGA, LFBGA, SQFP, TFBGA
HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS not suitable(2)
PLCC(3), SO, SOJ
LQFP, QFP, TQFP
SSOP, TSSOP, VSO
not suitable
suitable
suitable
suitable
suitable
suitable
suitable
not recommended(3)(4)
not recommended(5)
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1999 Sep 16
15
Philips Semiconductors – a worldwide company
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For all other countries apply to: Philips Semiconductors,
Internet: http://www.semiconductors.philips.com
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
68
SCA
© Philips Electronics N.V. 1999
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
465002/25/02/pp16
Date of release: 1999 Sep 16
Document order number: 9397 750 05984
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