TEA1210 [NXP]
High efficiency, high current DC/DC converter; 高英法fi效率，高电流的DC / DC转换器
| 型号： | TEA1210 |
| 厂家： | 
NXP |
| 描述： | High efficiency, high current DC/DC converter |
| 文件： | 总20页 (文件大小：87K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
TEA1210TS
High efficiency, high current DC/DC
converter
1999 Mar 08
Preliminary specification
File under Integrated Circuits, IC03
Philips Semiconductors
Preliminary specification
High efficiency, high current DC/DC converter
TEA1210TS
FEATURES
GENERAL DESCRIPTION
• Fully integrated DC/DC converter circuit, featuring
internal very low RDSon power MOSFETs
The TEA1210TS is a fully integrated DC/DC converter.
Efficient, compact and dynamic power conversion is
achieved using a novel digitally controlled concept like
Pulse Width Modulation (PWM) or Pulse Frequency
Modulation (PFM), integrated low R CMOS power
switches with low parasitic capacitances, and fully
synchronous rectification.
• Up-or-down conversion
• Start-up from 1.85 V input voltage
• Adjustable output voltage
• High efficiency over large load range
• 600 kHz switching frequency
• Low quiescent power consumption
• Synchronizing with external clock
The device operates at 600 kHz switching frequency
which enables the use of external components with
minimum size. The switching frequency can be locked to
an external high-frequency clock.
• Two selectable current limits for efficient battery use in
case of dynamic loads
Optionally, the device can be kept in the Pulse Width
Modulation (PWM) mode regardless of the load applied.
• Up to 100% duty cycle in down mode
• Undervoltage lockout
Deadlock is prevented by an on-chip undervoltage lockout
circuit.
• Shut-down function
Two selectable current limits in upconversion mode enable
efficient battery use even at highly dynamic loads such as
cellular phone electronics.
• 16-pin small body SSOP16 package.
APPLICATIONS
• Cellular phones, Personal Digital Assistants (PDAs) and
others
• Supply voltage source for low-voltage chip sets
• Portable computers
• Battery backup supplies.
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME
DESCRIPTION
plastic shrink small outline package; 16 leads; body width 4.4 mm
VERSION
TEA1210TS
SSOP16
SOT369-1
1999 Mar 08
2
Philips Semiconductors
Preliminary specification
High efficiency, high current DC/DC converter
TEA1210TS
QUICK REFERENCE DATA
Tamb = −40 to +80 °C; all voltages measured with respect to ground; positive currents flow into the IC; unless otherwise
specified.
SYMBOL
PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
Voltage levels
UPCONVERSION; pin U/D = LOW
VI
input voltage
VI(start)
2.90
−
5.50
5.50
1.85
2.70
V
V
V
V
VO
output voltage
−
VI(start)
VI(uvlo)
start-up input voltage
undervoltage lockout input voltage
IL < 200 mA
1.20
1.60
2.10
1.50
DOWNCONVERSION; pin U/D = HIGH
VI
input voltage
2.90
1.30
−
−
5.50
5.50
V
V
VO
output voltage
GENERAL
Vfb
feedback input voltage
output voltage window
1.20
1.5
1.25
2.0
1.30
3.0
V
∆Vwindow
PWM mode
%
Current levels
Iq
quiescent current on pins LX
VI =2.40 V; VO = 3.60 V
Ilim(up) set to 2.0 A
Tamb = 60 °C
100
−
125
2
150
10
µA
µA
%
A
Ishdwn
∆Ilim(up)
Ilim(down)
ILX
current in shut-down mode
current limit deviation in up mode
current limit in down mode
−12
−
+12
4.8
−
maximum continuous current on
pins LX
−
1.8
A
Power MOSFETs
RDSon(N) drain-to-source on-state resistance
Tj = 27 °C
Tj = 27 °C
−
−
56
68
63
77
mΩ
mΩ
NFET
RDSon(P)
drain-to-source on-state resistance
PFET
Efficiency
η
efficiency upconversion
VI = 2.4 V; VO = 3.6 V;
Tamb = 20 °C
IL = 1 mA
83
90
92
84
86
93
94
86
−
−
−
−
%
%
%
%
IL = 100 mA
IL = 500 mA
IL = 1.5 A; not continual
Timing
fsw
switching frequency
PWM mode
480
9
600
13
720
20
−
kHz
MHz
µs
fsync
tres
synchronization clock input frequency
response time
from standby to Po(max)
−
25
1999 Mar 08
3
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a
P-type POWER FET
4, 5, 12, 13
1, 16
LX
UPOUT
INTERNAL
SUPPLY
7
I/V
ILIMH
sense FET
START-UP
CONVERTER
SWITCH
10
TEA1210TS
CIRCUIT
ILIML
LPF
15
CONTROL LOGIC
AND
MODE GEARBOX
FB
CURRENT LIMIT
COMPARATORS
I/V
11
ILIMSEL
CONVERTER
N-type
POWER
FET
TEMPERATURE
PROTECTION
BAND GAP
REFERENCE
TIME
COUNTER
sense
FET
13 MHz
OSCILLATOR
SYNC
GATE
DIGITAL CONTROLLER
8, 9
GND
2
3
6
14
MGR725
SYNC
SHDWN
PWM
U/D
Fig.1 Block diagram.
Philips Semiconductors
Preliminary specification
High efficiency, high current DC/DC converter
TEA1210TS
PINNING
FUNCTIONAL DESCRIPTION
Control mechanism
SYMBOL
PIN
DESCRIPTION
The TEA1210TS DC/DC converter is able to operate in
PFM (discontinuous conduction) or PWM (continuous
conduction) operating mode. All switching actions are
completely determined by a digital control circuit which
uses the output voltage level as its control input. This novel
digital approach enables the use of a new pulse width and
frequency modulation scheme, which ensures optimum
power efficiency over the complete operating range of the
converter.
UPOUT
1, 16
output voltage in up mode;
input voltage in down mode
SYNC
SHDWN
LX
2
3
synchronization clock input
shut-down input
4, 5, 12, 13 inductor connection
U/D
6
up-or-down mode selection
input; active LOW for up mode
ILIMH
7
current limiting resistor 1
connection
When high output power is requested, the device will
operate in PWM (continuous conduction) operating mode.
This results in minimum AC currents in the circuit
components and hence optimum efficiency, cost and
EMC. In this operating mode, the output voltage is allowed
to vary between two predefined voltage levels. As long as
the output voltage stays within this so-called window,
switching continues in a fixed pattern. When the output
voltage reaches one of the window borders, the digital
controller immediately reacts by adjusting the pulse width
and inserting a current step in such a way that the output
voltage stays within the window with higher or lower
current capability. This approach enables very fast
reaction to load variations. Figure 3 shows the converter’s
response to a sudden load increase. The upper trace
shows the output voltage. The ripple on top of the DC level
is a result of the current in the output capacitor, which
changes in sign twice per cycle, times the capacitor’s
internal Equivalent Series Resistance (ESR). After each
ramp-down of the inductor current, i.e. when the ESR
effect increases the output voltage, the converter
determines what to do in the next cycle. As soon as more
load current is taken from the output the output voltage
starts to decay.
GND
8, 9
10
ground
ILIML
current limiting resistor 2
connection
ILIMSEL
PWM
11
14
current limiting selection input
PWM-only mode selection
input
FB
15
feedback input
handbook, halfpage
UPOUT
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
UPOUT
FB
SYNC
SHDWN
LX
PWM
LX
TEA1210TS
LX
LX
ILIMSEL
ILIML
GND
U/D
ILIMH
GND
When the output voltage becomes lower than the low limit
of the window, a corrective action is taken by a ramp-up of
the inductor current during a much longer time. As a result,
the DC current level is increased and normal PWM control
can continue. The output voltage (including ESR effect) is
again within the predefined window.
MGR726
Fig.2 Pin configuration.
Figure 4 depicts the spread of the output voltage window.
The absolute value is most dependent on spread, while the
actual window size is not affected. For one specific device,
the output voltage will not vary more than 2% typically.
For all possible applications, the following groups of pins
must be connected together:
In low output power situations, the TEA1210TS will switch
over to PFM (discontinuous conduction) operating mode in
case the PWM-only mode is not active.
• Pins 4, 5, 12 and 13 (pins LX)
• Pins 1 and 16 (pins UPOUT)
• Pins 8 and 9 (pins GND).
1999 Mar 08
5
Philips Semiconductors
Preliminary specification
High efficiency, high current DC/DC converter
TEA1210TS
In the PFM mode, regulation information from earlier PWM
operating modes is used. This results in optimum inductor
peak current levels in the PFM mode, which are slightly
larger than the inductor ripple current in the PWM mode.
As a result, the transition between PFM and PWM mode is
optimum under all circumstances. In the PFM mode,
TEA1210TS regulates the output voltage to the high
window limit shown in Fig.3.
that the inductor current does not fall below zero. In this
way, the achieved efficiency is higher than in standard
PWM-controlled converters.
Start-up
Start-up from low input voltage in boost mode is realized
by an independent start-up oscillator, which starts
switching the N-type power MOSFET as soon as the
voltage on pins UPOUT is measured to be sufficiently
high. The switch actions of the start-up oscillator will
increase the output voltage. As soon as the output voltage
is high enough for normal regulation, the digital control
system takes over the control of the power MOSFETs.
Synchronous rectification
For optimum efficiency over the whole load range,
synchronous rectifiers inside the TEA1210TS ensure that
during the whole second switching phase, all inductor
current will flow through the low-ohmic power MOSFETs.
Special circuitry is included which detects that the inductor
current reaches zero. Following this detection, the digital
controller switches off the power MOSFET and proceeds
regulation.
Undervoltage lockout
As a result of too high load or disconnection of the input
power source, the output voltage can drop so low that
normal regulation cannot be guaranteed. In that case, the
device switches back to start-up mode. If the output
voltage drops down even further, switching is stopped
completely.
PWM-only mode
When pin PWM is pulled to HIGH-level in the
upconversion mode, the TEA1210TS will use PWM
regulation independent of the load applied. As a result, the
switching frequency does not vary over the whole load
range. Furthermore, the P-type power MOSFET is always
on when the input voltage exceeds the target output
voltage. The internal synchronous rectifier still takes care
Shut-down
When the shut-down input is made HIGH, the converter
disables both switches and power consumption is reduced
to a few microamperes.
load increase
start corrective action
V
o
high window limit
low window limit
time
I
L
MGK925
time
Fig.3 Response to load increase.
1999 Mar 08
6
Philips Semiconductors
Preliminary specification
High efficiency, high current DC/DC converter
TEA1210TS
In the upconversion mode, the first current limit is set by an
external resistor connected between the pins ILIMH
and UPOUT and the second current limit is set by an
external resistor connected between the pins ILIML
and UPOUT. The digital signal on the current limiting
selection input determines which resistor sets the limit
level (pin ILIMSEL = HIGH results in the use of pin ILIMH).
The current limiting selection input can accept a digital
signal having a HIGH-level of just 55% of the voltage on
pins UPOUT. The noise margin on this input is increased
by a low-pass filter, having a cutoff frequency of about
50 MHz. However, for stability reasons the level on the
current limiting selection input shall not change within a
period shorter than 20 ms.
Power switches
The power switches in the IC are one N-type and one
P-type power MOSFET, having a typical drain-to-source
resistance of 56 and 68 mΩ respectively. The maximum
average current in the power switches is 1.8 A at
Tamb = 60 °C.
Temperature protection
When the device operates in the PWM mode, and the die
temperature gets too high (typically 175 °C), the converter
stops operating. It resumes operation when the die
temperature falls below 175 °C again. As a result,
low-frequent cycling between on and off state will occur.
It should be noted that in the event of device temperatures
around the cut-off limit, the application differs strongly from
maximum specifications.
In case just one current limit is sufficient, the unused pin
(pin ILIML or ILIMH) must be connected either to the other
pin (pin ILIMH or ILIML), or to pin UPOUT.
In the downconversion mode, the current limiting level is
set internally at a fixed value which is higher than the
current level that most applications require. It should be
regarded as a protection function only. In the
downconversion mode, pins ILIMH and ILIML must be
connected to pin UPOUT.
Current limiters
If the current in one of the power switches exceeds its limit
in the PWM mode, the current ramp is stopped
immediately, and the next switching phase is entered.
Current limiting is required to keep power conversion
efficient during temporary high loads. Furthermore, current
limiting protects the IC against overload conditions,
inductor saturation, etc.
maximum positive spread of V
fb
V
h
upper specification limit
2%
V
l
+4%
V
h
V
out, typ
2%
V
l
−4%
V
h
2%
lower specification limit
V
l
typical situation
maximum negative spread of V
MGR667
fb
Fig.4 Spread of location of output voltage window.
7
1999 Mar 08
Philips Semiconductors
Preliminary specification
High efficiency, high current DC/DC converter
TEA1210TS
voltage drop. In case the converter is in the PFM mode
at high input voltage, the output voltage will equal
VI minus the voltage drop over the external diode.
The current limiting function is not active.
External synchronization
If an external high-frequency clock is applied to the
synchronization clock input, the switching frequency in
PWM mode will be exactly that frequency divided by 22.
In PFM mode, the switching frequency is always lower.
The quiescent current of the device increases when an
external clock is applied. In case no external
• Downconversion: when the input voltage is lower than
the target output voltage, but higher than 2.9 V, the
P-type power MOSFET will stay conducting resulting in
an output voltage being equal to the input voltage minus
some resistive voltage drop. The current limiting
function remains active.
synchronization is necessary, the synchronization clock
input must be connected to ground level.
Behaviour at input voltage exceeding the specified
range
In general, an input voltage exceeding the specified range
is not recommended since instability may occur. There are
two exceptions:
• Upconversion: at an input voltage higher than the target
output voltage, but up to 6 V, the converter will stop
switching. As long as the device is in the PWM mode,
the internal P-type power MOSFET will be conducting
and the output voltage will equal VI minus some resistive
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL PARAMETER CONDITIONS
Vn voltage on any pin shut-down mode
operating mode
MIN.
−0.2
MAX.
+6.5
UNIT
V
V
−0.2
−40
−40
−40
+5.9
Tj
junction temperature
+150
+80
°C
°C
°C
V
Tamb
Tstg
Ves
operating ambient temperature
storage temperature
+125
+1500
+300
electrostatic handling
human body model; note 1 −1500
machine model; note 2 −300
V
Notes
1. Equivalent to discharging a 100 pF capacitor through a 1.5 kΩ resistor.
2. Equivalent to discharging a 200 pF capacitor via a 0.75 µH inductor.
THERMAL CHARACTERISTICS
SYMBOL
PARAMETER
CONDITIONS
VALUE
140
UNIT
Rth(j-a)
thermal resistance from junction to ambient in free air
K/W
QUALITY SPECIFICATION
Product lifetime is fully guaranteed over 2000 hours of operation at an ambient temperature of 60 °C with a continuously
repeating current profile on pins LX of 4 A during 577 µs followed by 1 A during 4.0 ms. All remaining quality
specifications are in accordance with “SNW-FQ-611 part E”.
1999 Mar 08
8
Philips Semiconductors
Preliminary specification
High efficiency, high current DC/DC converter
TEA1210TS
CHARACTERISTICS
Tamb = −40 to +80 °C; all voltages are measured with respect to ground; positive currents flow into the IC; unless
otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Voltage levels
UPCONVERSION; pin U/D = LOW
VI
input voltage
VI(start)
2.90
−
−
5.50
V
V
V
V
VO
output voltage
5.50
1.85
2.70
VI(start)
VI(uvlo)
start-up input voltage
undervoltage lockout input voltage
IL < 200 mA
1.20
1.60
2.10
note 1
1.50
DOWNCONVERSION; PIN U/D = HIGH
VI
input voltage
note 2
2.90
1.30
−
−
5.50
5.50
V
V
VO
output voltage
GENERAL
Vfb
feedback input voltage
1.20
1.5
1.25
2.0
1.30
3.0
V
∆Vwindow output voltage window
PWM mode
%
Current levels
Iq
quiescent current on pins LX
current in shut-down mode
up mode; note 3
note 4
100
125
2
150
10
µA
µA
Ishdwn
∆Ilim(up)
−
current limit deviation in up mode
I
I
lim(up) set to 0.4 A
lim(up) set to 2.0 A
−20
−12
−
−
+20
+12
−
%
%
A
−
Ilim(down)
ILX
current limit in down mode
4.8
−
maximum continuous current on
pins LX
Tamb = 80 °C
amb = 60 °C
−
1.5
1.8
0.65
A
T
−
−
A
IUPOUT
maximum continuous current on
pins UPOUT
up mode;
−
−
A
VI = 1.8 V; VO = 3.6 V;
Tamb = 80 °C
Power MOSFETs
RDSon(N) drain-to-source on-state resistance
Tj = 27 °C
Tj = 100 °C
Tj = 27 °C
Tj = 100 °C
−
−
−
−
56
75
68
92
63
mΩ
mΩ
mΩ
mΩ
NFET
84
RDSon(P)
drain-to-source on-state resistance
PFET
77
104
1999 Mar 08
9
Philips Semiconductors
Preliminary specification
High efficiency, high current DC/DC converter
TEA1210TS
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Efficiency
η1
efficiency upconversion
Tamb = 20 °C;
VI = 1.8 V; VO = 3.6 V;
note 5
IL = 1 mA
80
84
89
89
73
82
−
−
−
−
−
%
%
%
%
%
IL = 4 mA
86
91
91
75
IL = 100 mA
IL = 500 mA
IL = 1.5 A; note 6
η2
η3
η4
efficiency upconversion
efficiency upconversion
efficiency upconversion
Tamb = 80 °C;
VI = 1.8 V; VO = 3.6 V;
note 5
IL = 1 mA
78
82
87
88
67
80
84
89
90
72
−
−
−
−
−
%
%
%
%
%
IL = 4 mA
IL = 100 mA
IL = 500 mA
IL = 1.5 A; note 6
Tamb = 20 °C;
VI = 2.4 V; VO = 3.6 V;
note 5
IL = 1 mA
83
87
90
92
84
86
90
93
94
86
−
−
−
−
−
%
%
%
%
%
IL = 4 mA
IL = 100 mA
IL = 500 mA
IL = 1.5 A; note 6
Tamb = 80 °C;
VI = 2.4 V; VO = 3.6 V;
note 5
IL = 1 mA
81
85
88
91
82
83
87
90
93
85
−
−
−
−
−
%
%
%
%
%
IL = 4 mA
IL = 100 mA
IL = 500 mA
IL = 1.5 A; note 6
Timing
fsw
switching frequency
synchronization clock input frequency
start-up time
PWM mode
480
9
600
13
6
720
20
−
kHz
MHz
ms
fsync
tstart
tres
note 7
−
response time
from standby to Po(max)
−
25
−
µs
Temperature
Tamb
Tmax
operating ambient temperature
internal cut-off temperature
−40
+25
175
+80
200
°C
°C
150
1999 Mar 08
10
Philips Semiconductors
Preliminary specification
High efficiency, high current DC/DC converter
TEA1210TS
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Digital levels
VlL
LOW-level input voltage
on pins SHDWN, ILIMSEL, U/D
and SYNC
0
−
0.4
V
VIH
HIGH-level input voltage
on pins U/D and PWM
on pins SYNC and SHDWN
on pin ILIMSEL
note 8
V1 − 0.4
0.55V1
0.55V1
−
−
−
V1 + 0.3
V1 + 0.3
V1 + 0.3
V
V
V
note 8
notes 8 and 9
Notes
1. The undervoltage lockout voltage shows wide specification limits since it decreases at increasing temperature.
When the temperature increases, the minimum supply voltage of the digital control part of the IC decreases and
therefore the correct operation of this function is guaranteed over the whole temperature range.
2. When VI is lower than the target output voltage but higher than 2.9 V, the P-type power MOSFET will remain
conducting (100% duty cycle), resulting in VO following VI.
3. The quiescent current is specified as the input current in the upconversion configuration at VI = 2.40 V and
VO = 3.60 V, using L1 = 6.8 µH, R1 = 178 kΩ and R2 = 93.1 kΩ (see Fig.5).
4. The current limit is defined by the external current limiting resistors, see Section “Current limiting resistors”.
Rlimx = 996 Ω results in a typical current limit of 400 mA and Rlimx = 178 Ω results in a typical current limit of 2.0 A.
The spread of the current limit decreases with increasing the Ilim setpoint.
5. The specified efficiency is valid when using an output capacitor having an ESR of 0.04 Ω and an inductor having an
inductance of 6.8 µH, an ESR of 0.04 Ω, and a sufficient saturation current level. The current limit is assumed to be
set at 4.0 A. In the PWM-only mode, the efficiency at IL = 1 mA and IL = 4 mA is lower than the values specified.
6. The specified efficiency at IL = 1.5 A is only valid if the average input current does not exceed the maximum
value of ILX. In most practical applications, this means that the load current is not continuous.
7. The specified start-up time is the time between the connection of a 2.40 V input voltage source and the moment the
output reaches 3.60 V. The output capacitance equals 2000 µF, the inductance equals 6.8 µH, no load is present.
8. V1 is the voltage on the pins UPOUT. If the applied HIGH-level voltage is less than V1 − 1 V, the quiescent current
of the device will increase.
9. Maximum additional supply current on the pins UPOUT is 50 µA in case the voltage V1 = 5.0 V and the input voltage
on pin ILIMSEL is 2.2 V.
1999 Mar 08
11
Philips Semiconductors
Preliminary specification
High efficiency, high current DC/DC converter
TEA1210TS
APPLICATION INFORMATION
D1
UPOUT
FB
1, 16
V
O
L1
LX
4, 5,
12, 13
TEA1210TS
R1
R2
V
I
15
10
C2
6
8, 9
2
3
14
11
7
C1
GND SYNC SHDWN PWM ILIMSEL ILIMH
ILIML
U/D
C3
R
R
liml
limh
MGR727
Fig.5 Complete application for upconversion.
L1
UPOUT
LX
4, 5,
12, 13
V
I
V
1, 16
O
TEA1210TS
R1
FB
15
C1
C2
6
10
7
11
14
2
8, 9
3
U/D ILIML ILIMH ILIMSEL PWM SYNC GND SHDWN
D1
R2
C3
MGR728
Fig.6 Complete application for downconversion.
12
1999 Mar 08
Philips Semiconductors
Preliminary specification
High efficiency, high current DC/DC converter
TEA1210TS
External component selection
CURRENT LIMITING RESISTORS
The maximum instantaneous current in upconversion
INDUCTOR L1
mode is set by one of the external resistors Rlimh and Rliml
The preferred type is SMD, 1% accurate.
.
The performance of the TEA1210TS is not very sensitive
to inductance value. Best efficiency performance over a
wide load current range is achieved by using an
inductance of 6.8 µH and a saturation current level of 3.0 A
at least. In case the maximum output current is lower,
other inductors are also suitable such as the
TDK SLF7032 range.
The digital level on pin ILIMSEL defines which one of the
resistors is used to determine the current limiting level.
The functionality of both settings is identical.
In case one current limit is enough, the unused pin
(pin ILIML or ILIMH) must be connected either to the other
pin (pin ILIMH or ILIML), or to pin UPOUT.
DIODE D1
The values of the current limiting resistors can be derived
from the simplified formula:
The Schottky diode is only used a short time during
takeover from N-type power MOSFET and P-type power
MOSFET and vice versa. Therefore, a medium-power
diode such as Philips PRLL5819 is sufficient in most
applications.
346
Rlimh
=
=
, active when ILIMSEL = HIGH
, active when ILIMSEL = LOW
------------------------------------
Ilim (up) – 0.05
346
R liml
------------------------------------
Ilim (up) – 0.05
INPUT CAPACITOR C1
The value of capacitor C1 strongly depends on the type of
input source. In general, a 100 µF tantalum capacitor will
do, or a 10 µF ceramic capacitor featuring very low series
resistance (ESR value).
The average inductor current during limited current
operation also depends on the inductance value and the
resistive losses in all components in the power path.
Ensure that both current limiting levels do not exceed the
saturation current of the inductor.
OUTPUT CAPACITOR C2
The value and type of capacitor C2 depend on the
maximum output current and the ripple voltage which is
allowed in the application. Low-ESR tantalum capacitors
show best results. The most important specification of
capacitor C2 is its ESR value, which mainly determines the
output voltage ripple.
FEEDBACK CAPACITOR C3
Capacitor C3 prevents the feedback voltage from polluting
by switching noise. A ceramic type of capacitor having a
maximum value of 33 pF is recommended.
FEEDBACK RESISTORS R1 AND R2
The output voltage is determined by the resistors
R1 and R2. The following conditions apply:
• Use 1% accurate SMD type resistors
• Resistors R1 and R2 should have a maximum value of
50 kΩ when connected in parallel. A higher value will
result in inaccurate operation.
Under these conditions, the output voltage can be
R1
calculated by the formula: VO = 1.25 × 1 +
-------
R2
1999 Mar 08
13
Philips Semiconductors
Preliminary specification
High efficiency, high current DC/DC converter
TEA1210TS
PACKAGE OUTLINE
SSOP16: plastic shrink small outline package; 16 leads; body width 4.4 mm
SOT369-1
D
E
A
X
c
y
H
v
M
A
E
Z
9
16
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
8
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
10o
0o
0.15
0.00
1.4
1.2
0.32
0.20
0.25
0.13
5.30
5.10
4.5
4.3
6.6
6.2
0.75
0.45
0.65
0.45
0.48
0.18
mm
1.0
1.5
0.25
0.65
0.2
0.13
0.1
Note
1. Plastic or metal protrusions of 0.20 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
94-04-20
95-02-04
SOT369-1
1999 Mar 08
14
Philips Semiconductors
Preliminary specification
High efficiency, high current DC/DC converter
TEA1210TS
If wave soldering is used the following conditions must be
observed for optimal results:
SOLDERING
Introduction to soldering surface mount packages
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
The footprint must incorporate solder thieves at the
downstream end.
Reflow soldering
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Wave soldering
Manual soldering
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
To overcome these problems the double-wave soldering
method was specifically developed.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
1999 Mar 08
15
Philips Semiconductors
Preliminary specification
High efficiency, high current DC/DC converter
TEA1210TS
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE
WAVE
REFLOW(1)
BGA, SQFP
not suitable
suitable
suitable
suitable
suitable
suitable
HLQFP, HSQFP, HSOP, HTSSOP, SMS not suitable(2)
PLCC(3), SO, SOJ
LQFP, QFP, TQFP
SSOP, TSSOP, VSO
suitable
not recommended(3)(4)
not recommended(5)
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1999 Mar 08
16
Philips Semiconductors
Preliminary specification
High efficiency, high current DC/DC converter
TEA1210TS
NOTES
1999 Mar 08
17
Philips Semiconductors
Preliminary specification
High efficiency, high current DC/DC converter
TEA1210TS
NOTES
1999 Mar 08
18
Philips Semiconductors
Preliminary specification
High efficiency, high current DC/DC converter
TEA1210TS
NOTES
1999 Mar 08
19
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© Philips Electronics N.V. 1999
SCA62
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
465002/800/01/pp20
Date of release: 1999 Mar 08
Document order number: 9397 750 04337
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