TEA1211TW [PHILIPS]
Switching Regulator/Controller, Voltage-mode, 750kHz Switching Freq-Max, CMOS, PDSO20,;
| 型号： | TEA1211TW |
| 厂家： | 
PHILIPS SEMICONDUCTORS |
| 描述： | Switching Regulator/Controller, Voltage-mode, 750kHz Switching Freq-Max, CMOS, PDSO20, 光电二极管 |
| 文件： | 总24页 (文件大小：109K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
TEA1211TW
High efficiency auto-up/down
DC-to-DC converter
Objective specification
2002 Jul 24
Philips Semiconductors
Objective specification
High efficiency auto-up/down DC-to-DC
converter
TEA1211TW
CONTENTS
1
2
3
4
5
6
7
FEATURES
APPLICATIONS
GENERAL DESCRIPTION
ORDERING INFORMATION
QUICK REFERENCE DATA
BLOCK DIAGRAM
PINNING INFORMATION
7.1
7.2
Pinning
Pin description
8
FUNCTIONAL DESCRIPTION
8.1
Introduction
8.2
8.3
8.4
Control mechanism
Adjustable output voltage
Start-up
8.5
8.6
Undervoltage lockout
Shut-down
8.7
Power switches
8.8
8.9
Synchronous rectification
PWM-only mode
8.10
8.11
8.12
8.13
External synchronisation
Current limiter
Temperature protection
Serial interface (I2C-bus)
9
LIMITING VALUES
10
11
11.1
THERMAL CHARACTERISTICS
APPLICATION INFORMATION
Typical Li-Ion, 2 or 3 cell application with
I2C-bus programming
11.2
12
Component selection
PACKAGE OUTLINE
SOLDERING
13
13.1
Introduction to soldering surface mount
packages
13.2
13.3
13.4
13.5
Reflow soldering
Wave soldering
Manual soldering
Suitability of surface mount IC packages for
wave and reflow soldering methods
14
15
16
17
DATA SHEET STATUS
DEFINITIONS
DISCLAIMERS
PURCHASE OF PHILIPS I2C COMPONENTS
2002 Jul 24
2
Philips Semiconductors
Objective specification
High efficiency auto-up/down DC-to-DC
converter
TEA1211TW
1
FEATURES
• I2C-bus programmable output voltage range of
1.5 to 5.5 V
• Single inductor topology
• High efficiency up to 95% over wide load range
• Wide input voltage range; functional from 2.4 to 5.5 V
• 1.7 A maximum input/output current
• Low quiescent power consumption
• 600 kHz switching frequency
3
GENERAL DESCRIPTION
The TEA1211TW is a fully integrated DC-to-DC
auto-up/down converter circuit with an I2C-bus interface.
Efficient, compact and dynamic power conversion is
achieved using a digitally controlled Pulse Width
Modulation (PWM) and Pulse Frequency Modulation
(PFM) like control concept, four integrated low RDSon
CMOS power switches with low parasitic capacitances,
and fully synchronous rectification.
• Four integrated very low RDSon power MOSFETs
• Synchronizable to external clock
• Externally adjustable current limit for protection and
efficient battery use in case of dynamic loads
• Under-voltage lockout
The combination of auto-up/down conversion, high
efficiency and low switching noise makes the converter
well suited to supply a power amplifier in a cellular phone.
The output voltage can be programmed via the I2C-bus to
the exact voltage needed to achieve a certain output
power level with optimal system efficiency, thus enhancing
battery lifetime.
• PWM-only option
• Shut-down current typical 1 µA
• Thermal protection
• 20-pin small outline HTSSOP20 package.
2
APPLICATIONS
The TEA1211TW operates at 600 kHz switching
• Stable output voltage from Lithium-Ion batteries
frequency which enables the use of small-size external
components. The switching frequency can be locked to an
external high frequency clock. Deadlock is prevented by
an on-chip undervoltage lockout circuit. An adjustable
current limit enables efficient battery use even at high
dynamic loads. Optionally, the device can be kept in Pulse
Width Modulation mode regardless of the load applied.
• Variable voltage source for Power Amplifier (PA) in
cellular phones
• Wireless handsets
• Handheld instruments
• Portable computers.
4
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME
DESCRIPTION
VERSION
TEA1211TW
HTSSOP20
plastic, heatsink thin shrink small outline package; 20 leads;
body width 4.4 mm
SOT527-1
2002 Jul 24
3
Philips Semiconductors
Objective specification
High efficiency auto-up/down DC-to-DC
converter
TEA1211TW
5
QUICK REFERENCE DATA
Tamb = −40 to +85 °C; unless otherwise specified; all voltages with respect to ground; positive currents flow into the IC.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Voltage levels
Vo
output voltage
start-up voltage
1.50
−
5.50
V
V
V
V
V
%
Vi(start)
Vi
Vo = 3.5 V; IL < 100 mA
2.30
Vstart
−
2.40
2.50
5.50
−
input voltage
−
Vuvlo
Vfb
undervoltage lockout level
feedback voltage level
V
start − 0.15
1.20
1.5
1.25
2.0
1.30
3.0
Vwdw
output voltage window
as % of Vo
PWM mode
no load
Current levels
Iq
quiescent current
−
70
1
−
µA
µA
%
Ishdwn
∆Ilim
Ii/o(max)
current in shut-down mode
current limit deviation
−
2
IILIM = 1 A; note 1
−30
−
−
+30
1.7
maximum continuous
input/output current
Tamb < 20 °C
−
A
Power MOSFETs
RDSon(N) drain-to-source on-state
Tamb = 25 °C; Vi = 3.5 V
Tamb = 25 °C; Vi = 3.5 V
−
−
−
55
75
mΩ
mΩ
mΩ
resistance NFETs
RDSon(P)
drain-to-source on-state
resistance PFETs
55
75
RDSon(Pout) drain-to-source on-state
resistance between pins LXB
and OUT
Tamb = 25 °C; Vo = 1.5 V
100
135
Timing
fsw
switching frequency
sync input frequency
PWM mode
450
4.5
600
13
750
20
kHz
fi(sync)
MHz
Digital levels
VIL
LOW-level input voltage pins
SYNC/PWM, SHDWN, SCL
and SDA
0
−
−
0.4
V
V
VIH
HIGH-level input voltage pins note 2
SYNC/PWM, SHDWN, SCL
and SDA
0.6 × Vi
Vi + 0.3
Temperature
Tamb
Tco
ambient temperature
internal cut-off temperature
−40
+25
135
+85
150
°C
°C
120
Notes
1. The current limit level is defined by the external RILIM resistor, see Chapter 11.
2. To avoid additional supply current, it is advised to use HIGH levels not lower than Vi − 0.5 V.
2002 Jul 24
4
Philips Semiconductors
Objective specification
High efficiency auto-up/down DC-to-DC
converter
TEA1211TW
6
BLOCK DIAGRAM
LXA
LXB
4, 6, 9 12, 15, 17
P-type power FET
Pup
Pdown
P-type power FET
3, 5
IN
16, 18
TEA1211TW
OUT
INTERNAL
SUPPLY
sense FET
Ndown
Nup
N-type
power
FETs
TEMPERATURE
PROTECTION
19
DIGITAL
CONTROLLER
13 MHZ
OSCILLATOR
FB
window
comparator
CLOCK
SELECTOR
2
I C-BUS INTERFACE
BANDGAP
REFERENCE
current limit
comparator
1
20
10
SCL
11
SDA
2
ILIM
7
8
13, 14
GND
MBL512
SYNC/PWM
SHDWN
GND
GND
Fig.1 Block diagram.
7
PINNING INFORMATION
Pinning
7.2
Pin description
7.1
Table 1 HTSSOP20 package
SYMBOL
PIN
DESCRIPTION
handbook, halfpage
SYNC/PWM
1
synchronization clock input;
PWM-only input
SYNC/PWM
1
2
3
4
5
6
7
8
9
20 SHDWN
19 FB
ILIM
IN
ILIM
IN
2
current limit resistor connection
18 OUT
17 LXB
16 OUT
15 LXB
14 GND
13 GND
12 LXB
11 SDA
3 and 5 input voltage
LXA
IN
LXA
4, 6 and inductor connection 1
9
TEA1211TW
GND
7, 8, 13 ground
and 14
LXA
GND
GND
LXA
SCL
SDA
LXB
10
11
I2C-bus serial clock input
I2C-bus serial data input/output
12, 15 inductor connection 2
and 17
SCL 10
OUT
16 and output voltage
18
MBL513
FB
19
20
feedback voltage input
shut-down input
Fig.2 Pin configuration (Top view).
SHDWN
2002 Jul 24
5
Philips Semiconductors
Objective specification
High efficiency auto-up/down DC-to-DC
converter
TEA1211TW
8
FUNCTIONAL DESCRIPTION
Introduction
The output voltage (including ESR effect) is again within
the predefined window.
8.1
The TEA1211TW DC-to-DC converter can operate in PFM
(discontinuous conduction) or PWM (continuous
8.2.2
PULSE FREQUENCY MODULATION
In low output power situations, the TEA1211TW will switch
over to PFM (discontinuous conduction) mode operation in
the event that PWM-only mode is not activated. In this
mode, charge is transferred from the battery to the
converter output in single pulses with a wait-phase in
between. Regulation information from earlier PWM mode
operation is used. This results in optimum inductor peak
current levels in PFM mode, which are slightly larger than
the inductor ripple current in PWM mode. As a result, the
transition between PFM and PWM mode is optimal under
all circumstances.
conduction) mode. All switching actions are determined by
a digital control circuit which uses the output voltage level
as its control input. This novel digital approach enables the
use of a new pulse width and frequency modulation
scheme, which ensures optimum power efficiency over the
complete range of operation of the converter.
8.2
Control mechanism
Depending on load current and the Vi/Vo ratio, the
controller chooses a mode of operation. When high output
power is requested, the device will operate in PWM
(continuous conduction) mode, which is a 2-phase cycle in
Up mode as well as in Down mode. For small load currents
the controller will switch over to PFM (discontinuous
mode), which is either a 3 or 4-phase cycle depending on
the input/output ratio (see Fig.3).
In PFM mode, TEA1211TW regulates the output voltage to
the high window limit shown in Fig.5. Depending on the
Vn/Vo ratio the controller decides for a 3 or 4-phase cycle,
where the last phase is the wait-phase. When the input
voltage almost equals the output voltage, one of the slopes
of a 3-phase cycle will become so weak that the integral of
the pulse (its charge) approaches zero, this means that no
charge can be transferred. In this region the 4-phase cycle
is used. See Fig.3.
8.2.1
PULSE WIDTH MODULATION
Pulse Width Modulation results in minimum AC currents in
the circuit components and hence optimum efficiency,
cost, and EMC. In this mode, the output voltage is allowed
to vary between two predefined voltage levels. As long as
the output voltage stays within this so-called window,
switching continues in a fixed pattern.
8.2.3
VOLTAGE WINDOW
Figure 5 depicts the spread of the output voltage window.
The absolute value is mostly dependent on spread, while
the actual window size is not affected. For one specific
device, the output voltage will not vary more than 2%
typically.
When the output voltage reaches one of the window
borders, the digital controller immediately reacts by
adjusting the duty cycle and inserting a current step in
such a way that the output voltage stays within the window
with higher or lower current capability. This approach
enables very fast reaction to load variations.
8.2.4
SWITCHING SEQUENCE
Refer to Fig.1. In Up mode the cycle starts by making
Pdown and Nup conducting in the first phase. The second
phase Nup opens and Pup starts conducting. In
down-mode the cycle starts with in the first phase Pup and
Pdown conducting. The second phase Pdown opens and
Ndown starts conducting. In PFM these two phases are
followed by a third or wait-phase that opens all switches
except for Ndown, which is closed to prevent the coil from
floating.
Figure 4 shows the converter’s response to a sudden load
increase in the case of up-conversion. The upper trace
shows the output voltage. The ripple on top of the DC level
is a result of the current in the output capacitor, which
changes in sign twice per cycle, times the capacitor’s
internal Equivalent Series Resistance (ESR).
After each ramp-down of the inductor current, for example,
when the ESR effect increases the output voltage, the
converter determines what to do in the next cycle. As soon
as more load current is taken from the output the output
voltage starts to decay. When the output voltage becomes
lower than the low limit of the window, a corrective action
is taken by a ramp-up of the inductor current during a much
longer time. As a result, the DC current level is increased
and normal PWM control can continue.
The stationary mode or 4-phase cycle, which only occurs
in PFM, starts with in the first phase Pdown and Nup
conducting. In the second phase Pdown and Pup conduct
forming a short-cut from battery to output capacitor. In the
third phase Pup and Ndown conduct. The fourth or
wait-phase again opens all switches except for Ndown
which is closed to prevent the coil from floating.
2002 Jul 24
6
Philips Semiconductors
Objective specification
High efficiency auto-up/down DC-to-DC
converter
TEA1211TW
MBL514
I
load
PWM
PFM
0
V >V
V =V
V <V
i o
V /V ratio
i
o
i
o
i
o
Down
mode
Stationary
mode
Up mode
Fig.3 Waveform of I load coil current as a function of IL and the Vi/Vo ratio.
load increase
start corrective action
V
o
high window limit
low window limit
time
I
L
MGK925
time
Fig.4 Response to load increase in Up mode.
7
2002 Jul 24
Philips Semiconductors
Objective specification
High efficiency auto-up/down DC-to-DC
converter
TEA1211TW
maximum positive spread of V
fb
V
wdw(high)
upper specification limit
2%
V
wdw(low)
+4%
V
wdw(high)
V
2%
V
o (typ)
wdw(low)
−4%
V
wdw(high)
2%
lower specification limit
V
typical situation
wdw(low)
maximum negative spread of V
MBL515
fb
Fig.5 Output voltage window spread.
2002 Jul 24
8
Philips Semiconductors
Objective specification
High efficiency auto-up/down DC-to-DC
converter
TEA1211TW
8.3
Adjustable output voltage
Following this detection, the digital controller switches off
the power MOSFET and proceeds with regulation.
Negative currents are thus prevented.
The output voltage of the up/down converter can be set to
a fixed value by means of an external resistive divider.
After start-up through this divider, dynamic control of the
output voltage is made possible by use of the I2C-bus. The
output voltage can be programmed from 1.5 to 5.5 V in
40 increments, each of 0.1 V. For the power amplifiers, for
example, the output voltage of the DC-to-DC converter
can be adjusted to the output power to be transmitted by
the power amplifier in order to obtain maximum system
efficiency.
8.9
PWM-only mode
When the SYNC/PWM pin is lifted HIGH, the TEA1211TW
will use PWM regulation independent of the load applied.
As a result, the switching frequency does not vary over the
whole load range.
8.10 External synchronisation
If a high frequency clock is applied to the external
synchronisation pin, the switching frequency in PWM
mode will be exactly that frequency divided-by-22. PFM
mode is no longer possible if an external clock is applied.
8.4
Start-up
If the input voltage exceeds the start voltage of 2.4 V the
converter starts ramping-up the voltage at the output
capacitor. Ramping stops when the desired level, set by
the external resistors, is reached.
The quiescent current of the device increases when an
external clock is applied. If no external synchronisation is
necessary and the PWM-only option is not used, the
SYNC/PWM pin must be connected to ground.
8.5
Undervoltage lockout
As a result of a too high load or disconnection of the input
power source, the converter’s input voltage can drop so
low that normal regulation cannot be guaranteed. In that
case, the device switches to a shut-down mode stopping
the switching completely. Start-up is possible by crossing
the start-up level again.
8.11 Current limiter
If the peak input current of the DC-to-DC converter
exceeds its limit in PWM mode, current ramping is stopped
immediately, and the next switching phase is entered. The
current limitation protects the IC against overload
conditions, inductor saturation, etc. The current limit level
is user defined by the external resistor which must be
connected between pin ILIM and pin GND.
8.6
Shut-down
When the SHDWN pin is made HIGH, the converter
disables all switches except for Ndown (see Fig.1) and
power consumption is reduced to a few mA. Ndown is kept
conducting to prevent the coil from floating.
8.12 Temperature protection
When the device operates in PWM mode, and the die
temperature gets too high (typically 135 °C), the converter
stops operating. It resumes operation when the device
temperature falls below 135 °C again. As a result, low
frequency cycling between the on and off-state will occur.
8.7
Power switches
The power switches in the IC are two N-type and two
P-type MOSFETs, having a typical pin-to-pin resistance of
85 mΩ. The maximum average current in the switches is
1.7 A at 70 °C ambient temperature.
It should be noted that in the event of device temperatures
around the temperature cut-off limit, the application
exceeds the maximum specifications.
8.8
Synchronous rectification
8.13 Serial interface (I2C-bus)
For optimal efficiency over the whole load range,
synchronous rectifiers inside the TEA1211TW ensure that
in PFM mode, during the phase when the coil current is
decreasing, all inductor current will flow through the
low-ohmic power MOSFETS. Special circuitry is included
which detects when the inductor current reaches zero.
The serial interface of the TEA1211TW is the I2C-bus.
A detailed description of the I2C-bus specification,
including applications, is given in the brochure: “The
I2C-bus and how to use it”, Philips order number:
9398 393 40011.
2002 Jul 24
9
Philips Semiconductors
Objective specification
High efficiency auto-up/down DC-to-DC
converter
TEA1211TW
8.13.1 CHARACTERISTICS OF THE I2C-BUS
8.13.3 BIT TRANSFER
The I2C-bus is for bidirectional, 2-line communication
between different ICs or modules. The two lines are a
Serial Data line (SDA) and a Serial Clock Line (SCL). Both
lines must be connected to a positive supply via a pull-up
resistor (for best efficiency it is advised to use the input
voltage of the converter). In bus configurations with ICs on
different supply voltages, the pull-up resistors shall be
connected to the highest supply voltage.
One data bit is transferred during each clock pulse. The
data on the SDA line must remain stable during the HIGH
period of the clock pulse, as changes in the data line at this
time will be interpreted as a control signal; see Fig.8.
8.13.4 ACKNOWLEDGE
The number of data bytes transferred between the START
and STOP conditions from transmitter to receiver is
unlimited. Each byte of eight bits is followed by an
acknowledge bit. The acknowledge bit is a HIGH level
signal put on the bus by the transmitter during which time
the receiver generates an extra acknowledge related clock
pulse.
Data transfer may be initiated only when the bus is not
busy.
The I2C-bus supports incremental addressing. This
enables the system controller to read or write to multiple
registers in only one I2C-bus action. The TEA1211TW
supports the I2C-bus up to 400 kbits/s.
A slave receiver which is addressed must generate an
acknowledge after the reception of each byte. Also a
master receiver must generate an acknowledge after the
reception of each byte that has been clocked out of the
slave transmitter.
The I2C-bus system configuration is shown in Fig.6.
A device generating a message is a ‘transmitter’, a device
receiving a message is the ‘receiver’. The device that
controls the message is the ‘master’ and the devices which
are controlled by the master are the ‘slaves’. The
TEA1211TW is a slave only device.
The device that acknowledges must pull-down the SDA
line during the acknowledge clock pulse, so that the SDA
line is stable LOW during the HIGH period of the
acknowledge related clock pulse (set-up and hold times
must be taken into consideration).
8.13.2 START AND STOP CONDITIONS
Both data and clock lines remain HIGH when the bus is
inactive. A HIGH-to-LOW transition of the data line, while
the clock is HIGH is defined as the START condition (S).
A LOW-to-HIGH transition of the data line while the clock
is HIGH is defined as the STOP condition (P); see Fig.7.
A master receiver must signal an end of data to the
transmitter by not generating an acknowledge on the last
byte that has been clocked out of the slave. In this event
the transmitter must leave the data line HIGH to enable the
master to generate a STOP condition.
SDA
SCL
MASTER
TRANSMITTER /
RECEIVER
SLAVE
TRANSMITTER /
RECEIVER
MASTER
MASTER
TRANSMITTER
SLAVE
RECEIVER
TRANSMITTER /
RECEIVER
MBA605
Fig.6 I2C-bus configuration.
2002 Jul 24
10
Philips Semiconductors
Objective specification
High efficiency auto-up/down DC-to-DC
converter
TEA1211TW
SDA
SDA
SCL
SCL
S
P
STOP condition
START condition
MBC622
Fig.7 START and STOP conditions on the I2C-bus.
SDA
SCL
data line
stable;
data valid
change
of data
allowed
MBC621
Fig.8 Bit transfer on the I2C-bus.
DATA OUTPUT
BY TRANSMITTER
not acknowledge
DATA OUTPUT
BY RECEIVER
acknowledge
8
SCL FROM
MASTER
1
2
9
S
clock pulse for
acknowledgement
START
condition
MBC602
Fig.9 Acknowledge on the I2C-bus.
2002 Jul 24
11
Philips Semiconductors
Objective specification
High efficiency auto-up/down DC-to-DC
converter
TEA1211TW
8.13.5 I2C-BUS PROTOCOL
8.13.5.1 Addressing
Before any data is transmitted on the I2C-bus, the device which should respond, is addressed first. The addressing is
always carried out with the first byte transmitted after the START procedure. The (slave) address of the TEA1211TW is
0001 0000 (10H). The subaddress (or word address) is 0000 0000 (00H).
The TEA1211TW acts as a slave receiver only. Therefore, the clock signal SCL is only an input signal. The data signal
SDA is a bidirectional line, enabling the TEA1211TW to send an acknowledge.
8.13.5.2 Data
The data is built-up of one byte.
Table 2 Data byte
SUBADDRESS
7
6
5
4
3
2
1
0
00H
0
0
CVLVL5
CVLVL4
CVLVL3
CVLVL2
CVLVL1
CVLVL0
Table 3 Description of the Data byte
BIT
SYMBOL
DESCRIPTION
7 and 6
5 to 0
−
These 2 bits must be logic 0.
CVLVL[5:0] Up/down converter output voltage level select. These 6 bits are used to program
the up/down converter output voltage level. The decimal value set by CVLVL[5:0]
determines the number of 0.1 V increments that will be applied to the base voltage of
1.5 V. The valid range of CVLVL[5:0] is 0 to 40. The minimum voltage that can be
selected is 1.5 V and the maximum voltage that can be selected is 5.5 V.
8.13.5.3 Write cycle
The I2C-bus configuration for the different TEA1211TW write cycles are shown in Fig.10. The word address is an 8-bit
value that defines which register is to be accessed next.
acknowledge
from slave
acknowledge
from slave
acknowledge
from slave
S
SLAVE ADDRESS 0 A WORD ADDRESS
A
DATA
A
P
R/W
n bytes
auto increment
memory word address
MBL516
Fig.10 Master transmits to slave receiver (write mode).
2002 Jul 24
12
Philips Semiconductors
Objective specification
High efficiency auto-up/down DC-to-DC
converter
TEA1211TW
9
LIMITING VALUES
In accordance with the Absolute Maximum Rate System (IEC 60134).
SYMBOL
PARAMETER
CONDITIONS
MIN.
−0.5
MAX.
+6.0
UNIT
Vn
voltage on any pin with respect to GND
shut-down mode
operational mode
V
V
−0.5
−
+5.5
1000
+150
+85
+125
−
Ptot
Tj
total internal power dissipation
junction temperature
mW
°C
−40
−40
−40
class II
Tamb
Tstg
ambient temperature
°C
storage temperature
°C
Vesd
electrostatic discharge voltage
notes 1 and 2
Note
1. Human Body Model (HBM): equivalent to discharging a 100 pF capacitor via a 1.5 kΩ resistor.
2. Machine Model (MM): equivalent to discharging a 200 pF capacitor via a 0.75 µH series inductor.
10 THERMAL CHARACTERISTICS
SYMBOL
Rth j-a
PARAMETER
CONDITIONS
TYPE
UNIT
thermal resistance from junction to ambient in free air
50
K/W
2002 Jul 24
13
Philips Semiconductors
Objective specification
High efficiency auto-up/down DC-to-DC
converter
TEA1211TW
11 APPLICATION INFORMATION
11.1 Typical Li-Ion, 2 or 3 cell application with I2C-bus programming
ht
L1
10 µH
D1
D2
LXA
LXA
LXA
LXB
12
LXB
15
LXB
17
4
6
9
V
o
V
3.3 V
OUT
i 2.4 to 5.5 V
IN
IN
3
5
16
18
OUT
R1
120 kΩ
TEA1211TW
1 cell Li-Ion,
3 cell NiCd/NiMH
or 2 or 3 cell(A)AA
C
IN
100 µF
C
FB
OUT
19
100 µF
10
SCL
11
SDA
1
20
2
7
8
13
GND
14
GND
R2
75 kΩ
SYNC/ SHDWN ILIM
GND
GND
PWM
R
ILIM
1 kΩ
MBL517
The combination of the feedback resistances R1 and R2 in parallel should be approximately 50 kΩ.
When the I2C-bus interface is used for programming the output voltage, the SCL and SDA pins must be connected to a positive
supply using pull-up resistors (see Section 8.13.1). Note the VIH level (see Chapter 5). If the I2C-bus interface is not used,
connect pins SCL and SDA to ground.
No external clock is applied.
Pins should never be left open-circuit.
Fig.11 Typical auto-up/down converter application.
2002 Jul 24
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High efficiency auto-up/down DC-to-DC
converter
TEA1211TW
MBL518
100
η
(%)
90
V = 2.7 V
i
V = 3.3 V
i
V = 3.6 V
i
80
V = 4.2 V
i
V = 4.5 V
i
70
60
50
2
3
1
10
10
10
I
(mA)
load
Vo = 3.3 V
L1 = 10 µH (TDK SLF7032 series)
Fig.12 Efficiency versus load current.
MBL519
100
η
(%)
90
80
70
60
I
= 100 mA
= 10 mA
o
I
o
I
I
= 500 mA
o
o
= 1000 mA
50
2.5
3
3.5
4
4.5
5
V (V)
i
Vo = 3.3 V
L1 = 10 µH (TDK SLF7032 series)
Fig.13 Efficiency versus input voltage.
15
2002 Jul 24
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High efficiency auto-up/down DC-to-DC
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TEA1211TW
11.2 Component selection
11.2.1 INDUCTOR
The inductor should have a low ESR to reduce losses and must be able to handle the peak currents without saturating.
Table 4 Inductor selection
COMPONENT
VALUE
TYPE
DO3316-682
SLF7032T-100M1R4
SUPPLIER
L1
6.8 µH
10 µH
Coilcraft
TDK
11.2.2 CAPACITOR
For the output capacitor, Equivalent Series Resistance (ESR) is critical. The output voltage ripple is determined by the
product of the current through the output capacitor and its ESR. The lower the ESR, the smaller the ripple. A too low ESR
however could result in unstable operation.
Table 5 Capacitor selection
COMPONENT
CIN or COUT
VALUE
100 µF/10 V
TYPE
TPS-series
594D-series
SUPPLIER
AVX
Vishay/Sprague
If the I2C-bus interface is used to program large voltage steps at the output, it is preferable to increase the value of the
input capacitor. This will prevent the undervoltage lockout level being triggered because of the large current peaks drawn
from this capacitor.
Table 6 Input capacitor selection when the I2C-bus is used
COMPONENT
VALUE
470 µF/10 V
TYPE
TPS-series
594D-series
SUPPLIER
CIN
AVX
Vishay/Sprague
11.2.3 SCHOTTKY DIODES
The Schottky diodes provide a lower voltage drop during the break-before-make time of the internal power FETs. It is
advised to use Schottky diodes with fast recovery times.
Table 7 Schottky diode selection
COMPONENT
D1 or D2
TYPE
SUPPLIER
PRLL5819
Philips
2002 Jul 24
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TEA1211TW
11.2.4 FEEDBACK RESISTORS
The feedback resistors (R1 and R2) are used to set the fixed output voltage. Even if the I2C-bus is used for programming
the output voltage, external resistors are required for start-up. The ratio of the two resistors can be calculated by:
V o
R1
-------
R2
=
– 1 ; where Vref = Vfb (see Chapter 5)
--------
V ref
The two resistors in parallel should have a value of approximately 50 kΩ.
1
1
1
+
=
------- -------
---------------
50 kΩ
R1 R2
11.2.5 CURRENT LIMITER
The maximum input peak current can be set by the current limiter as follows:
1250
Ii(max)(pk)
R ILIM
=
---------------------
Note: The output current is not limited; in the event of down-conversion, the output current will be higher than the input
current, while the maximum continuous output current is not allowed to exceed 1.7 A (rms) at 70 °C.
Table 8 Resistor selection
COMPONENT
VALUE
TYPE
SMD 1% tolerance
R1, R2
RILIM
Vo dependent
IILIM dependent
10 kΩ
SMD 1% tolerance
SMD
R3, R4
2002 Jul 24
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12 PACKAGE OUTLINE
HTSSOP20: plastic, heatsink thin shrink small outline package; 20 leads; body width 4.4 mm
SOT527-1
D
E
A
X
c
y
H
v
M
A
heathsink side
E
D
h
Z
11
20
(A )
3
A
2
A
E
h
A
1
pin 1 index
θ
L
p
L
1
10
detail X
w
M
b
p
e
0
2.5
scale
5 mm
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
D
E
E
e
H
L
L
p
v
w
y
Z
θ
1
2
3
p
h
h
E
max.
8o
0o
0.15 0.95
0.05 0.80
0.30 0.20 6.6
0.19 0.09 6.4
4.3
4.1
4.5
4.3
3.1
2.9
6.6
6.2
0.75
0.50
0.5
0.2
mm
1.10
0.65
0.25
1.0
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
99-11-12
00-07-12
SOT527-1
2002 Jul 24
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13 SOLDERING
If wave soldering is used the following conditions must be
observed for optimal results:
13.1 Introduction to soldering surface mount
packages
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering can still be used for
certain surface mount ICs, but it is not suitable for fine pitch
SMDs. In these situations reflow soldering is
recommended.
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
The footprint must incorporate solder thieves at the
downstream end.
13.2 Reflow soldering
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Several methods exist for reflowing; for example,
convection or convection/infrared heating in a conveyor
type oven. Throughput times (preheating, soldering and
cooling) vary between 100 and 200 seconds depending
on heating method.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 220 °C for
thick/large packages, and below 235 °C for small/thin
packages.
13.4 Manual soldering
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
13.3 Wave soldering
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
To overcome these problems the double-wave soldering
method was specifically developed.
2002 Jul 24
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TEA1211TW
13.5 Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE(1)
WAVE
not suitable
REFLOW(2)
BGA, LBGA, LFBGA, SQFP, TFBGA, VFBGA
suitable
suitable
HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, not suitable(3)
HVSON, SMS
PLCC(4), SO, SOJ
LQFP, QFP, TQFP
SSOP, TSSOP, VSO
suitable
suitable
not recommended(4)(5) suitable
not recommended(6)
suitable
Notes
1. For more detailed information on the BGA packages refer to the “(LF)BGA Application Note” (AN01026); order a copy
from your Philips Semiconductors sales office.
2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
3. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder
cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side,
the solder might be deposited on the heatsink surface.
4. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
5. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not
suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
6. Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
2002 Jul 24
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Philips Semiconductors
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High efficiency auto-up/down DC-to-DC
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TEA1211TW
14 DATA SHEET STATUS
PRODUCT
DATA SHEET STATUS(1)
STATUS(2)
DEFINITIONS
Objective data
Development This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
Preliminary data
Qualification
This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
Product data
Production
This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Changes will be
communicated according to the Customer Product/Process Change
Notification (CPCN) procedure SNW-SQ-650A.
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
15 DEFINITIONS
16 DISCLAIMERS
Short-form specification
The data in a short-form
Life support applications
These products are not
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Right to make changes
Philips Semiconductors
reserves the right to make changes, without notice, in the
products, including circuits, standard cells, and/or
software, described or contained herein in order to
improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for
the use of any of these products, conveys no licence or title
under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that
these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified.
Application information
Applications that are
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.
2002 Jul 24
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Philips Semiconductors
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TEA1211TW
17 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
2002 Jul 24
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Philips Semiconductors
Objective specification
High efficiency auto-up/down DC-to-DC
converter
TEA1211TW
NOTES
2002 Jul 24
23
Philips Semiconductors – a worldwide company
Contact information
For additional information please visit http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
© Koninklijke Philips Electronics N.V. 2002
SCA74
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
403502/01/pp24
Date of release: 2002 Jul 24
Document order number: 9397 750 09362
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