TEA1401T-T [NXP]
IC 1 A SWITCHING REGULATOR, 150 kHz SWITCHING FREQ-MAX, PDSO20, 7.50 MM, PLASTIC, MS-013AC, SOT-163-1, SOP-20, Switching Regulator or Controller;
| 型号： | TEA1401T-T |
| 厂家： | 
NXP |
| 描述： | IC 1 A SWITCHING REGULATOR, 150 kHz SWITCHING FREQ-MAX, PDSO20, 7.50 MM, PLASTIC, MS-013AC, SOT-163-1, SOP-20, Switching Regulator or Controller 信息通信管理 开关 光电二极管 |
| 文件： | 总20页 (文件大小：119K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
TEA1401T
Power plug for the universal mains
1997 Mar 07
Preliminary specification
Supersedes data of 1996 Sep 27
File under Integrated Circuits, IC03
Philips Semiconductors
Preliminary specification
Power plug for the universal mains
TEA1401T
FEATURES
GENERAL DESCRIPTION
• Designed for compact power plugs supplying up to 20 W The TEA1401T is a Self Oscillating Power Supply (SOPS)
controller IC that operates directly from the rectified
universal mains. It is implemented in the BCD power logic
750 V process and includes the high voltage power switch
• Integrated high-voltage power DMOS FET 625 V/1 A
• Operates from all mains supplies (90 to 280 V AC)
• Major design: current regulation at the primary side
making an integrated single-switch flyback converter.
(no opto-coupler, no secondary electronics)
Dedicated circuitry for high power efficiency is built-in,
which makes a slim-line electronic power plug concept
possible.
• Low external/peripheral component count
• Combines accurate constant-voltage source (for supply)
and accurate constant-current source (for charging) in
one IC
The basic function is a galvanically isolated, combined
current and voltage source. No electronics are required at
the secondary side of the transformer. Implementation of
the TEA1401T renders a simple, small and accurate
battery charger system. The TEA1401T is capable of self
starting directly from the high voltage mains line.
• Foldback feature
• Requires simple input filter as a result of good EMC
design
• Overshoot protection (output voltage)
• Protects against under-voltage input, over-current and
over-temperature
• 20-pin SO medium-power package.
QUICK REFERENCE DATA
SYMBOL
V20
PARAMETER
output voltage at pin 20 (DRAIN)
current in MOS switch
CONDITIONS
20 times
peak value
MIN.
TYP. MAX. UNIT
−
−
625
1
V
I20
fsw
I1
−
5
−
−
−
A
operating switching frequency range CCPFM = 470 pF
input current at pin 1 (Vin), from the VAT < 10 V (peak)
high input voltage. VAT can supply
from the low voltage auxiliary
winding
−
150
3
kHz
mA
µA
−
VAT > 10 V (peak);
430
530
fsw = 90 kHz
VAT > 10 V (peak);
fsw = 150 kHz
−
560
660
µA
I17
average input current at pin 17 (VAT) VAT < 10 V (peak)
VAT > 10 V (peak)
−
−
−
−
300
3
µA
mA
°C
−
Tamb
operating ambient temperature
−20
+85
ORDERING INFORMATION
TYPE
PACKAGE
NUMBER
NAME
DESCRIPTION
VERSION
TEA1401T
SO20
plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
1997 Mar 07
2
Philips Semiconductors
Preliminary specification
Power plug for the universal mains
TEA1401T
BLOCK DIAGRAM
BM5H70
n d b o o k , f u l l p a g e w i
1997 Mar 07
3
Philips Semiconductors
Preliminary specification
Power plug for the universal mains
TEA1401T
PINNING
SYMBOL
Vin
PIN
DESCRIPTION
1
input for rectified and filtered mains
voltage for initial powering
n.c.
2
3
not connected
CPFM
frequency range setting for the
pulse frequency modulation
SOURCE
GND1
GND2
RI
4
5
6
7
8
source of internal MOS switch
ground 1
handbook, halfpage
V
1
2
20 DRAIN
in
ground 2
n.c.
n.c.
n.c.
V
19
18
17
setting of nominal output current
C
3
PFM
CI
frequency compensation of
current control loop
SOURCE
GND1
4
AT
Rref
CV
9
setting of reference current
5
16 GND4
TEA1401T
10 frequency compensation of voltage
control loop
GND2
6
15
14
GND3
R
I
V
7
IC
GOUT
RV
11 nulling of the output conductance
of the current source function
C
I
8
13 FOLDBACK
12 setting of the nominal output
voltage
R
R
V
9
12
11
ref
C
V
G
OUT
10
FOLDBACK 13 enabling of the foldback feature in
the output characteristic
MBH571
VIC
14 buffering of internal supply voltage
15 ground 3
GND3
GND4
VAT
16 ground 4
17 input for voltage and power from
auxiliary winding for timing and
powering
n.c.
18 not connected
n.c.
19 not connected
Fig.2 Pin configuration.
DRAIN
20 drain of internal MOS switch
1997 Mar 07
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Philips Semiconductors
Preliminary specification
Power plug for the universal mains
TEA1401T
FUNCTIONAL DESCRIPTION
Voltage control
The TEA1401T is the heart of a compact flyback DC-to-DC
converter, with the IC placed at the primary side.
An auxiliary primary winding of the transformer is used for
indirect feedback to control the isolated output. This extra
winding also powers the device.
The voltage from the auxiliary winding is sensed as a
measure of the secondary voltage. During the secondary
stroke the auxiliary winding delivers a negative voltage.
This voltage is converted into a current by an external
resistor at the RV pin between the transformer winding and
virtual ground. This current is compared with a reference
current.
Control of the converted power is carried out by current
mode control and Pulse Frequency Modulation (PFM), as
illustrated in Fig.1. The primary current is sensed by a
comparator. The frequency is determined by the maximum
of the transformer demagnetizing time and the time of the
voltage controlled monostable multivibrator (single-shot).
The difference between the reconstructed voltage and the
reference is integrated during the secondary stroke by a
capacitor on the CV pin. The voltage on the CV pin is
transferred, via a ‘track-and-hold’ circuit, to the connection
point of the current and the voltage loop.
The TEA1401T senses signals at the primary side of the
transformer to reconstruct the current and voltage which
are present at the secondary side. Comparison of these
reconstructions with the internal reference leads to
adaptation of the turn-off current level for the primary
switch and also to adaptation of the single-shot time.
The ‘track-and-hold’ output provides the turn-off current
level for the main switch and the single-shot time.
The ‘track-and-hold’ circuit itself is present for loop
stability.
Input from the current part of the loop is used to improve
the voltage reconstruction, resulting in lower output
impedance of the complete converter (analog to the
current control). In the block diagram this is denoted as
‘ROUT compensation’.
Current control (see Fig.3)
The current through the main switch is measured by the
peak detector shown in Fig.1. The timing block generates
a signal ‘secondary stroke’ which is logic 1 when the
voltage of the auxiliary winding is negative.
Combined control
The measured peak current, multiplied by the ratio of the
resistors connected to pins 4 (SOURCE) and 7 (RI), is
integrated by a capacitor during the secondary stroke.
The two loops, I loop and V loop, each request their own
turn-off current level for the main switch and single-shot
time. The block ‘minimum’ in the block diagram outputs the
lowest value of the two, preventing the output voltage or
current from exceeding its nominal value. The output
characteristics of the power plug are displayed in Fig.4
(with enabled foldback option).
In this way a reconstruction is made of the secondary
charge transfer. The charge estimation Q-pulse’
(see Fig.3) is drawn from the capacitor at pin 8 (CI) for
each pulse. Also this capacitor, the charge error memory,
is continuously charged with the reference current. In this
way the real (reconstructed) current is compared with the
reference yielding the voltage VCI at pin 8. The VCI level
provides the turn-off current level for the main switch and
the single-shot time.
Optional foldback (see Fig.4)
The optional foldback feature of the TEA1401T is
performed by sensing the voltage of the auxiliary winding
at the end of the flyback stroke. It is actually not a voltage,
but the current through pin 12 (RV) that is measured. When
this voltage is low, the reference current in the current
control loop is set to the low level Jref/3.
Input from the voltage part of the loop is used to improve
the current reconstruction, resulting in a lower output
conductance of the complete converter. In the block
diagram this is denoted as ‘GOUT compensation’.
The steep foldback enables a turn-down of the converter
by short-circuiting the output on the secondary side, for
example by a switch-transistor.
The block ‘IPEAK correction’ is able to increase the output
from the peak detector to improve line regulation.
1997 Mar 07
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Philips Semiconductors
Preliminary specification
Power plug for the universal mains
TEA1401T
At a high power level the transformer determines the
frequency. This mode of operation is called Self Oscillating
Power Supply (SOPS), and provides maximum efficiency
(for a non-continuous conducting flyback converter).
In SOPS the next primary stroke is started right after the
previous secondary stroke has ended. Timing information
is collected from the auxiliary winding.
Overshoot protection
Sensing the voltage during the previously mentioned
flyback stroke is also used to signal a voltage overshoot.
A voltage overshoot will delay and minimize the next active
stroke. This is achieved by discharging the capacitor in the
‘track-and-hold’ circuit (see Fig.1). In this way the power
level of the converter is turned down to its minimum
immediately in case of a voltage overshoot.
The SOPS frequency will increase when the power level
decreases. The frequency however is limited by the PFM
controller (single-shot). When the PFM controller takes
over, the frequency will be proportional to the required
power level. Thus the frequency is reduced when the
power level decreases. In PFM there is a variable dead
time after the secondary stroke. The next primary stroke is
started after the single-shot time has ended.
Minimum output power
Under no-load condition an additional external pre-load
resistor (or Zener diode) is necessary to keep the output
voltage at its nominal value (or at the Zener diode voltage).
This is due to the fact that under no-load condition and also
at voltage overshoot the converter will keep operating
instead of being switched off. Although the converter then
will operate with a short active stroke and a low frequency,
energy is still being converted to the output. To prevent
excessive output voltage this energy has to be dissipated.
Supply
Initially the IC is powered by a high DC input voltage at
pin 1 (Vin). In operation the auxiliary winding takes over.
In the event that the auxiliary winding delivers insufficient
power for the internal circuitry of the IC, this deficit is
supplemented again via pin 1 (Vin).
The advantage of a pre-load resistor over a Zener diode is
that the converter will stay in regulation, maintaining its fast
response to load variations.
The supply voltage for the internal circuitry is buffered with
an external capacitor at pin 14 (VIC). When the auxiliary
winding powers the IC, energy is stored during the active
stroke. The rest of the time energy is supplied by the buffer
capacitor.
Duty cycle control
The momentary power level required by the I/V control
loop is achieved by controlling the duty cycle of the
converter by two actions. First the peak value of the
primary current is controlled using a cycle-by-cycle current
control. Secondly the pulse frequency is modulated. There
is a broad region in which both regulation principles are
active simultaneously. Both controls have a minimum and
a maximum value which are set by the resistor on the
SOURCE pin and the capacitor on the CPFM pin.
Protections
The IC has a cycle-by-cycle current regulation, with a
built-in setting for the absolute maximum voltage across
the current sense resistor. Also a maximum time is set for
the duration of the active stroke. A provision for
temperature shut down has been implemented.
SOPS and PFM
The switching frequency fsw is set by the transformer
demagnetizing time or the frequency control block within
the IC (block ‘single-shot’ in Fig.1).
1997 Mar 07
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Philips Semiconductors
Preliminary specification
Power plug for the universal mains
TEA1401T
Q
pulse
handbook, halfpage
MBH575
V
handbook, halfpage
OUT
I
(V)
I
Q
pulse'
secondary
primary x n
V
nominal
t
V
0
auxiliary
I
(A)
I
I
nominal
OUT
FOLDBACK
(−V
)
t
secondary
MBH580
Fig.3 Reconstruction of secondary charge transfer.
Fig.4 V/I ideal characteristics.
1997 Mar 07
7
Philips Semiconductors
Preliminary specification
Power plug for the universal mains
TEA1401T
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134). All voltages are measured with respect to ground;
positive currents flow into the chip; pins 7, 9, 11 and 12 are not allowed to be voltage driven. The voltage ratings are
valid provided other ratings are not being violated; current ratings are valid provided the maximum power rating is not
violated.
SYMBOL
Voltages
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
V1
pin 1 (Vin)
continuous
−0.4
+400
V
V
V
V
V
V
V
V
V
V3
pin 3 (CPFM
)
−0.4
−0.4
−0.4
−0.4
−0.4
−
−
V4
pin 4 (SOURCE)
pin 8 (CI)
+2
V8
−
V10
V13
V14
V17
V20
pin 10 (CV)
−
pin 13 (FOLDBACK)
pin 14 (VIC)
VIC + 0.4
−
pin 17 (VAT)
−20
−
+60
pin 20 (DRAIN)
continuous
+550
Currents
I3
pin 3 (CPFM
)
−
0.2
+1
0
mA
A
I4
pin 4 (SOURCE)
pin 7 (RI)
−1
I7
−0.2
−0.2
−0.2
−0.2
−300
−1
mA
mA
mA
mA
mA
A
I9
pin 9 (Rref)
0
I11
I12
I14
I20
pin 11 (GOUT
pin 12 (RV)
pin 14 (VIC)
)
0
0
+1
+1
pin 20 (DRAIN)
General
Ptot
Tstg
Tamb
Tvj
total power dissipation
Tamb < 50 °C
−
1.4
W
storage temperature
−55
−20
−20
+150
+85
°C
°C
°C
operating ambient temperature
virtual junction temperature
+145
QUALITY SPECIFICATION
According to “SNW-FQ-611E”. This specification can be found in the “Quality reference Handbook”. The handbook can
be ordered using the code 9397 750 00192.
HANDLING
Every pin withstands the ESD test in accordance with the ‘Human Body Model’ except for pins Vin and DRAIN of which
the performance is:
• Pin Vin: 1000 V in accordance with the ‘Human Body Model’
• Pin DRAIN: 1500 V in accordance with the ‘Human Body Model’.
1997 Mar 07
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Philips Semiconductors
Preliminary specification
Power plug for the universal mains
TEA1401T
THERMAL CHARACTERISTICS
SYMBOL
Rth j-a
Note
PARAMETER
thermal resistance from junction to ambient in free air(1)
VALUE
65
UNIT
K/W
1. Pins GND1, GND2, GND3 and GND4 connected to sufficient copper area on the printed-circuit board.
CHARACTERISTICS
Vin = 330 V; VAT = 36 V; RRref = 31 kΩ; Tamb = 25 °C; IC not in current foldback mode; no over-voltage;
no over-temperature; unless otherwise specified. All voltages are measured with respect to ground; currents are
positive when flowing into the IC.
SYMBOL
Supply
PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
Vin
input voltage
60
−
400
−
V
input voltage limit
20 times
500
1.7
130
−
V
Iin
input supply current to VIC and gate
input supply current to gate only
VAT = 3 V
2.3
230
2.9
330
mA
µA
Iin(gate)
VAT = 36 V;
non-switching
VIC
regulated supply voltage at VIC
VAT = 3 V
6.7
7.2
−
7.2
7.9
−
7.7
8.6
200
V
VAT = 36 V
V
∆VIC/∆RO
voltage decrease at VIC due to its
output impedance
VAT = 20 V;
IVIC = 0 to −100 mA
mV
VPOR
power-on reset voltage level, with
respect to regulated VIC
−0.7
−0.5
−0.1
V
ILI(VAT)
VVAT
IVAT
leakage current into pin VAT
VAT input voltage
VAT = 6 V
−
−
2
µA
V
−20
−
+60
17
VAT input current
VAT = 70 V; IVIC = 0 mA 11
14
mA
Pulse peak modulator
VSOURCE(max) maximum peak voltage at
1.09
1.05
75
1.19
1.15
95
1.29
1.25
120
V
V
CV = VCI = 4 V;
pin SOURCE
dVSOURCE
= 1 V/µs
--------------------------
dt
V
VCV = VCI = 4 V;
dVSOURCE
= 0.1 V/µs
--------------------------
dt
VSOURCE(min)
minimum peak voltage at
pin SOURCE
VCV = VCI = 0 V;
ton > ton(min)
mV
∆VCV-SOURCE
∆VCI-SOURCE
ton(min)
level shift voltage VCI to VSOURCE
level shift voltage VCV to VSOURCE
VCV = 4 V
VCI = 4 V
−
2
−
V
−
2
−
V
minimum on-time (the minimum time V-mode
duration of the active stroke)
490
675
550
750
610
825
ns
ns
I-mode
1997 Mar 07
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Philips Semiconductors
Preliminary specification
Power plug for the universal mains
TEA1401T
SYMBOL
PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
Pulse (maximum) frequency modulator
Rdischarge
Icharge(min)
Icharge(max)
Icharge(fix)
GtransferCI
GtransferCV
Vsw(high)
discharge resistance to ground
VCPFM = 1.0 V
0.3
−
0.6
0.9
−
kΩ
minimum charge current
maximum charge current
fixed charge current
VCV = VCI = 0 V
VCV = VCI = 4 V
active stroke
2.5
µA
−
130
25
−
µA
−
−
µA
transfer from pin CI to pin CPFM
transfer from pin CV to pin CPFM
VCI = 2.1 to 3.1 V
VCV = 2.1 to 3.1 V
−
−104
−104
1.0
−
µA/V
µA/V
V
−
−
high switching voltage level at
pin CPFM
−
−
Vsw(low)
Vton(max)
∆fPFM
low switching voltage level at
pin CPFM
DC at pin CPFM
−
−
0.17
0.54
104
−
V
maximum on-time ton(max) switching
voltage level at pin CPFM
−
V
VCI = VCV = 2.1 to 3.1 V 93
115
µA/V2
frequency spread of the internal
GtransferCI G transferCV
oscillator;
;
------------------------ -------------------------
Vsw(high)
Vsw(high)
∆ton(max)
VCI = VCV = 4 V;
SOURCE < 1 V
19
22
25
V/mA
mV
V ton(max)
spread of ton(max)
;
----------------------
Icharge(fix)
V
SOPS
Vdemag
demagnetization recognition voltage
level
−250 −130 −10
Current regulation
Vi(pkc)
VPEAK-I converter input voltage
0.6
0.1
−
−
1.4
1.0
−
V
Vi(pkc)(slope)
Vpkc(offset)
VPEAK-I converter input voltage slope
VPEAK-I converter systematic offset
−
V/µs
mV
−13
dV
SOURCE > 0.1 V/µs
--------------------------
dt
Itransfer(RI-CI)
Itransfer(GOUT-CI)
IPEAKcor
RI to CI current transfer
IGOUT = 0
IRI = 0
−
−
7
−0.99
0.17
10
−
A/A
A/A
µA
GOUT to CI current transfer
−
current through sense capacitor in
block ‘IPEAK correction’ (see Fig.1);
sunk by pin FOLDBACK
under test conditions: in
lasting active stroke
13
Ichain(CI)
Ictrl(error)
CI chain error current
−3.3
−5
−1.0
+1.3
+5
µA
current control total measured error
−
%
1997 Mar 07
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Philips Semiconductors
Preliminary specification
Power plug for the universal mains
TEA1401T
SYMBOL
PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
Voltage regulation
Itransfer(RV-CV)
Vthres(RI)
RV to CV current transfer
VRI < 0.5 V
−
−
−1.00
−
−
A/A
V
ROUT converter voltage threshold at
pin RI
0.65
gm(ROUT)
Ichain(CV)
ROUT converter transconductance
VRI > 0.7 V
−
4.4
0
−
µA/V
µA
ICV/VRI
CV chain error current
ICV measurement,
analogue to that of
Ichain(CI)
−1.2
+1.2
Vctrl(error)
total error of voltage control loop in IC
−4
−
+4
%
Current foldback; FOLDBACK (pin 13) connected to VIC (pin 14)
RV/IRref current ratio discrimination level
I
0.05
0.26
0.1
0.2
0.4
A/A
A/A
ICI(foldback)/ICI(normal) current ratio
0.33
Voltage overshoot
IRV/IRref
current ratio discrimination level
1.1
75
1.2
95
1.3
A/A
mV
V4(overshoot)
peak voltage at pin 4
at overshoot;
ton > ton(min)
120
Icharge(overshoot)
CPFM charge current
at overshoot;
−
2.5
−
µA
VCPFM = 1 V
References
Vref
Rref reference voltage
1.24
−
1.28
0.99
0.99
1.32
−
V
Itransfer(Rref-CI)
Itransfer(Rref-CV)
Rref to CI current transfer
Rref to CV current transfer
A/A
A/A
−
−
Output stage
ILO
DRAIN output leakage current
DRAIN output voltage
VDRAIN = 550 V
continuous
−
−
−
−
−
100
550
−
µA
V
VDRAIN(cont)
VDRAIN(lim)
∆VDRAIN-SOURCE
0
DRAIN output voltage limit
DRAIN-SOURCE voltage drop
20 times
625
−
V
Tamb = 25 °C;
6
V
I
DRAIN = 500 mA
Tamb = 125 °C;
IDRAIN = 500 mA
−
−
−
11
V
tf
DRAIN fall time
Vin = 300 V;
100
−
ns
no external capacitor at
pin DRAIN
Temperature protection
Tprot(max) maximum temperature threshold
Tprot(hyst) hysteresis temperature
132
139
146
°C
°C
−
±1
−
1997 Mar 07
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Philips Semiconductors
Preliminary specification
Power plug for the universal mains
TEA1401T
OUTPUT CHARACTERISTICS OF COMPLETE
POWER PLUG
Efficiency
An efficiency of 72 to 75% at maximum output power can
be achieved for a complete 8 W converter designed for
universal mains.
Output power
Maximum switching frequency is approximately 150 kHz.
Internal MOS maximum switch current is 0.5 to 1 A.
Maximum handled power with universal mains is
approximately 10 W.
Ripple
The magnitude of the ripple in output voltage is determined
by the duty cycle of the converter, the output current level
and the value and Electrical Series Resistance (ESR) of
the output capacitor.
Accuracy of current regulation
The accuracy of the IC itself is ±5%. Accuracy of the
complete converter is approximately ±7%, depending on
the transformer and other components.
A minimal ripple is obtained in a system designed on a
maximum duty cycle of 50% under normal operating
conditions and a minimized dead time.
Accuracy of voltage regulation
Ripple is inversely proportional to input and output
voltages.
The voltage loop inside the IC has an accuracy of ±4%.
Accuracy of the complete converter is approximately ±7%.
INPUT CHARACTERISTICS OF COMPLETE
POWER PLUG
Voltage overshoot
When voltage overshoot is detected (during the secondary
stroke), the IC first has to wait until this stroke is finished in
the normal way. After that the power level of the converter
is set to the minimum level within one cycle.
Input voltage
The input voltage range comprises the universal AC-mains
(90 to 280 V). The input transient voltage must be filtered
to a maximum of 450 V.
Voltage overshoot is triggered at 20% above nominal
output voltage. If at the moment that overshoot is detected,
the transformer still contains energy; this energy can
cause some further increase of the output voltage.
In case of a pre-load resistor across the output,
the converter keeps the output voltage under static
conditions on its nominal value. Voltage overshoot will only
be a dynamic phenomenon in this situation. When only a
Zener diode is applied, the Zener voltage will appear at the
output continuously under no-load conditions.
1997 Mar 07
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Philips Semiconductors
Preliminary specification
Power plug for the universal mains
TEA1401T
The secondary diode also protects the power plug against
a short-circuited output (during the primary stroke), and
must therefore be placed inside the power plug cabinet.
A pre-load resistor or a Zener diode is required to handle
an open output which will cause an excessively high output
voltage. This is because the power plug continues
operating, provided it is connected to the mains, and thus
continuously converts energy to the secondary side, even
though it is a low, predefined level.
APPLICATION INFORMATION
A converter with the TEA1401T consists of an input filter,
a transformer with a third winding (auxiliary), a secondary
diode with a capacitor plus other external components as
illustrated in Fig.5. The load (user) determines the
operating mode of the power plug, current or voltage
source.
The capacitor at VIC (pin 14) buffers the internal supply
voltage of the IC which is powered via Vin and/or VAT
.
If a Zener diode is used, the Zener voltage must be
selected with care, because the over-voltage protection of
the IC should not be blocked. If the Zener diode voltage is
too close to the nominal output voltage of the converter no
voltage overshoot will be detected by the IC, causing
increased dissipation in the Zener during switching of the
load.
A sense resistor converts the primary current into a
voltage at SOURCE (pin 4). The voltage of the auxiliary
winding is converted into a current through resistor RRV
and fed to pin RV.
Nominal current and voltage are set by resistors RRI and
RRV. Output conductance of the current is nullified by
resistor RRGOUT. The band-gap voltage is converted into a
reference current by resistor RRref. Capacitor CCPFM
determines the frequency in non-SOPS mode.
A complete diagram with preliminary component values is
shown in Fig.6. More detailed information can be found in
the “Application Note AN96096”.
There are two loop capacitors, one for current control (CI),
and the other for voltage control (CV). The impedance at
CV (pin 10) can be made more complex, if required for
stability.
1997 Mar 07
13
Philips Semiconductors
Preliminary specification
Power plug for the universal mains
TEA1401T
BM5H73
a n d b o o k , f u l l p a g e w
1997 Mar 07
14
Philips Semiconductors
Preliminary specification
Power plug for the universal mains
TEA1401T
BM5H74
a n d b p a g e w i d t h
1997 Mar 07
15
Philips Semiconductors
Preliminary specification
Power plug for the universal mains
TEA1401T
PACKAGE OUTLINE
SO20: plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
D
E
A
X
c
y
H
E
v
M
A
Z
20
11
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
10
w
detail X
e
M
b
p
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
max.
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
θ
1
2
3
p
E
p
Z
0.30
0.10
2.45
2.25
0.49
0.36
0.32
0.23
13.0
12.6
7.6
7.4
10.65
10.00
1.1
0.4
1.1
1.0
0.9
0.4
mm
2.65
0.25
0.01
1.27
0.050
1.4
0.25 0.25
0.01
0.1
8o
0o
0.012 0.096
0.004 0.089
0.019 0.013 0.51
0.014 0.009 0.49
0.30
0.29
0.42
0.39
0.043 0.043
0.016 0.039
0.035
0.016
inches 0.10
0.055
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
92-11-17
95-01-24
SOT163-1
075E04
MS-013AC
1997 Mar 07
16
Philips Semiconductors
Preliminary specification
Power plug for the universal mains
TEA1401T
SOLDERING
Introduction
Wave soldering
Wave soldering techniques can be used for all SO
packages if the following conditions are observed:
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.
• The longitudinal axis of the package footprint must be
parallel to the solder flow.
• The package footprint must incorporate solder thieves at
the downstream end.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “IC Package Databook” (order code 9398 652 90011).
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Reflow soldering
Reflow soldering techniques are suitable for all SO
packages.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
6 seconds. Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.
Repairing soldered joints
Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
1997 Mar 07
17
Philips Semiconductors
Preliminary specification
Power plug for the universal mains
TEA1401T
DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1997 Mar 07
18
Philips Semiconductors
Preliminary specification
Power plug for the universal mains
TEA1401T
NOTES
1997 Mar 07
19
Philips Semiconductors – a worldwide company
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TAIPEI, Taiwan Tel. +886 2 2134 2870, Fax. +886 2 2134 2874
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MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421
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For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications,
Internet: http://www.semiconductors.philips.com
Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
© Philips Electronics N.V. 1997
SCA53
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
417027/1200/02/pp20
Date of release: 1997 Mar 07
Document order number: 9397 750 01503
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