UPD3753CY [NEC]

2088-BIT CCD LINEAR IMAGE SENSOR WITH PERIPHERAL CIRCUIT; 与外围电路2088位CCD线性图像传感器
UPD3753CY
型号: UPD3753CY
厂家: NEC    NEC
描述:

2088-BIT CCD LINEAR IMAGE SENSOR WITH PERIPHERAL CIRCUIT
与外围电路2088位CCD线性图像传感器

传感器 换能器 图像传感器 CD
文件: 总16页 (文件大小:223K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
DATA SHEET  
MOS INTEGRATED CIRCUIT  
µPD3753  
2088-BIT CCD LINEAR IMAGE SENSOR WITH PERIPHERAL CIRCUIT  
The µPD3753 is a 2088-bit high sensitivity CCD (Charge Coupled Device) linear image sensor which  
changes optical images to electrical signal.  
The µPD3753 consists of 2088-bit photocell array and a line of 2088-bit CCD charge transferred register.  
It contains a reset a feed-through level clamp circuit, a pulse generator, and a voltage amplifier to provide  
high sensitivity and low noise. It also supports low power consumption with single 5 V power supply. The  
µPD3753 can be driven by power supply and three input clocks owing to the built-in reset pulse generator  
and a clamp pulse generator.  
FEATURES  
• Valid photocell  
: 2088-bit  
• Photocell's pitch  
: 14 µm  
• High response sensitivity  
: Providing a response equal with the existing equivalent NEC  
product (µPD3743) to the light from a daylight fluorescent lamp  
• Low noise  
: Providing about two thirds register imbalance of the existing equivalent  
NEC product (µPD3743)  
• Peak response wavelength  
• Resolution  
: 550 nm (green)  
: 8 dot/mm across the shorter side of a B4-size (257 × 364 mm) sheet  
• Power supply  
: +5 V  
• Drive clock level  
• Scanning speed  
• Built-in circuit  
: CMOS output under +5 V operation  
: 1.0 ms/line  
: Reset feed-through level clamp circuit, reset pulse generator, clamp pulse  
generator  
ORDERING INFORMATION  
Part Number  
Package  
CCD LINEAR IMAGE SENSOR 22 PIN PLASTIC DIP (400 mil)  
Quality Grade  
Standard  
µPD3753CY  
Please refer to "Quality grade on NEC Semiconductor Devices" (Document number IEI-1209) published by  
NEC Corporation to know the specification of quality grade on the devices and its recommended applications.  
The information in this document is subject to change without notice.  
Document No. IC-3429  
(O. D. No. IC-9002)  
Date Published August 1994 P  
Printed in Japan  
1994  
©
µPD3753  
BLOCK DIAGRAM  
VOD  
3
Reset pulse/  
clamp pulse  
generator  
φ 2  
15  
9
Optical black (OB) 18 bits, invalid 2 bits,  
valid photocell 2088 bits, invalid 2 bits  
•Voltage amplifier  
•Reset feed-through  
level clamp circuit  
VOUT  
19  
φ TG  
φ 1  
CCD register  
14  
20  
13  
AGND  
DGND  
2
µPD3753  
PIN CONFIGURATION (Top View)  
CCD LINEAR IMAGE SENSOR 22 PIN PLASTIC DIP (400 mil)  
No connection  
No connection  
1
2
NC  
NC  
VOD  
NC  
NC  
NC  
NC  
NC  
NC  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
12  
No connection  
No connection  
Analog GND  
NC  
AGND  
Output unit drain voltage  
No connection  
3
4
VOUT  
Output  
No connection  
5
NC  
NC  
No connection  
No connection  
No connection  
Shift register clock 2  
Shift register clock 1  
Digital GND  
No connection  
6
No connection  
7
NC  
φ
φ
No connection  
8
2
φ
TG  
Transfer gate clock  
No connection  
9
1
10  
11  
NC  
NC  
DGND  
NC  
No connection  
No connection  
PHOTOCELL STRUCTURE DIAGRAM  
12  
µm  
2 µm  
µ
Channel stopper  
Aluminum  
electrode  
3
µPD3753  
ABSOLUTE MAXIMUM RATINGS (Ta = +25 °C)  
Parameter  
Output unit drain voltage  
Shift register clock voltage  
Transfer gate signal voltage  
Operating ambient temperature  
Storage temperature  
Symbol  
Ratings  
–0.3 to +8  
–0.3 to +8  
–0.3 to +8  
–25 to +60  
–40 to +70  
Unit  
V
VOD  
Vφ1, φ2  
VφTG  
Topt  
V
V
°C  
°C  
Tstg  
RECOMMENDED OPERATING CONDITIONS (Ta = –25 to + 60 °C)  
Parameter  
Output unit drain voltage  
Symbol  
MIN.  
4.7  
TYP.  
5.0  
5.0  
0
MAX.  
5.3  
Unit  
V
VOD  
Shift register clock φ1, φ2 signal high level  
Shift register clock φ1, φ2 signal low level  
Transfer gate signal high level  
Transfer gate signal low level  
Data rate  
Vφ1H, φ2H  
Vφ1L, φ2L  
VφTGH  
VφTGL  
4.5  
VOD + 0.2  
+0.5  
V
–0.3  
4.5  
V
Vφ1H  
0
Vφ1H  
V
–0.3  
0.2  
+0.5  
V
fφR  
1
2
MHz  
Caution When VφTGH > Vφ1H, image lag increases.  
4
µPD3753  
ELECTRICAL CHARACTERISTICS  
Ta = +25 °C, VOD = 5 V, fφ1 = 1 MHz, data rate = 1 MHz, storage time = 10 ms  
light source: 3200 K halogen lamp + C500 (infrared cut filter), input clock = 5 VP-P  
Parameter  
Saturation voltage  
Symbol  
Test Conditions  
MIN.  
1.0  
TYP.  
MAX.  
Unit  
Vsat  
1.2  
0.013  
± 2  
1.0  
± 4  
30  
V
lxs  
%
Saturation exposure  
Photo response non-uniformity  
Average dark signal  
Dark signal non-uniformity  
Power consumption  
Output impedance  
Response  
SE  
Daylight color fluorescent lamp  
VOUT = 500 mV  
PRNU  
ADS  
DSNU  
PW  
± 8  
8.0  
+ 8  
50  
Light shielding  
mV  
mV  
mW  
kΩ  
Light shielding  
– 8  
63  
ZO  
0.5  
90  
1
RF  
Daylight color fluorescent lamp  
VOUT = 1 V  
117  
V/lxs  
nm  
%
Response peak wavelength  
Image lag  
550  
7
IL  
14  
Offset level  
VOS  
2.5  
3.0  
3.5  
V
Cφ1  
Cφ2  
Input capacitance of shift register  
clock pin  
300  
pF  
pF  
Input capacitance of transfer gate  
signal pin  
CφTG  
100  
130  
Output fall delay time  
Total transfer efficiency  
Dynamic range  
td  
ns  
%
TTE  
DR  
VOUT = 1 V, data rate = 2 MHz  
Vsat/DSNU  
92  
0
375  
800  
10  
times  
mV  
Reset feed-through noise  
Bit noise  
RFSN  
BN  
Light shielding  
1500  
Light shielding  
mVP-P  
Modulation transfer function at  
nyquist frequency  
Resolution  
MTF  
65  
%
Remark When VOD = 4.7 V, the response typically decreases to 90 % of the value under 5 V operation.  
5
µPD3753  
TIMING CHART 1  
φ TG  
φ 1  
φ 2  
VOUT  
Invalid  
photocell  
2 bits  
Invalid  
photocell  
2 bits  
V
OUT unstable period  
12 bits*  
OB (Optical black)  
18 bits  
Valid photocell 2088 bits  
Caution Be sure not to use this period (indicated by *) as the black level, because this part is unstable.  
TIMING CHART 2  
t1  
t2  
90%  
90%  
φ
φ
1
2
10%  
90%  
10%  
90%  
10%  
10%  
td  
VOUT  
10%  
Remark  
: Signal output  
6
µPD3753  
TIMING CHART for φTG, φ1, φ2  
t3  
t5  
t4  
90 %  
φTG  
10 %  
t6  
t7  
90 %  
φ1  
φ 2  
CROSS POINTS for φ1, φ2  
φ1  
φ 2  
2 V or more  
2 V or more  
Note Adjust cross point of φ1, φ2 by φ1, φ2 pin external input resistors.  
(Unit: ns)  
Parameter  
t1 ,t2  
MIN.  
0
TYP.  
50  
MAX.  
(100)  
t3, t4  
0
50  
t5  
650  
0
1000  
100  
(2000)  
t6, t7  
Remark The MAX. in the table above shows the operation range in which the output characteristics are kept  
almost enough for general purpose, does not show the limit above which the µPD3753 is destroyed.  
7
µPD3753  
DEFINITIONS OF CHARACTERISTIC ITEMS  
1. Saturation voltage: Vsat  
Output signal voltage at which the response linearity is lost.  
2. Saturation exposure: SE  
Product of intensity of illumination (lx) and storage time (s) when saturation of output voltage occurs.  
3. Photo response non-uniformity: PRNU  
The peak/bottom ratio to the average output voltage of all the valid bits calculated by the following formula.  
VMAX. or VMIN.  
–1  
n
PRNU (%) =  
x 100  
1
n
Vj  
j=1  
n : Number of valid bits  
Vj : Output voltage of each bit  
n
1
VMIN.  
Vj  
VMAX.  
n
Register Dark  
DC level  
j=1  
4. Average dark signal: ADS  
Output average voltage in light shielding.  
n
1
Vj  
ADS(mV) =  
n
j=1  
5. Dark signal non-uniformity: DSNU  
The difference between peak or bottom output voltage in light shielding and ADS.  
ADS  
Register Dark  
DC level  
DSNU MIN.  
DSNU MAX.  
8
µPD3753  
6. Output impedance: Zo  
Output pin impedance viewed from outside.  
7. Response: R  
Output voltage divided by exposure (lxs).  
Note that the response varies with the light source.  
8. Image Lag: IL  
The rate between the last output voltage and the next one after read out the data of a line.  
φ
TG  
Light  
OFF  
ON  
VOUT  
V
1
V
OUT  
V1  
× 100 (%)  
IL =  
VOUT  
9. Bit Noise: BN  
Output signal distribution of a photocell by scan.  
9
µPD3753  
STANDARD CHARACTERISTIC CURVES (Ta = +25 °C)  
DARK OUTPUT TEMPERATURE  
CHARACTERISTIC  
STORAGE TIME OUTPUT VOLTAGE  
CHARACTERISTIC  
2
1
8
4
2
1
0.5  
0.2  
0.1  
0.25  
0.1  
1
5
10  
0
10  
20  
30  
40  
50  
Storage Time (ms)  
°
a
Ambient Temperature T ( C)  
SPECTRAL RESPONSE CHARACTERISTIC  
100  
80  
60  
40  
20  
0
400  
600  
800  
1000  
1200  
Wavelength (nm)  
10  
µPD3753  
POWER SUPPLY VOLTAGE RESPONSE RATIO CHARACTERISTIC  
110  
100  
90  
0
4.5  
4.7  
5.0  
5.3  
5.5  
Power Supply Voltage (V)  
11  
µPD3753  
APPLICATION EXAMPLE  
+5 V  
+5 V  
10 Ω  
10 µF  
/16 V  
0.1µF  
+
+
10 µF  
/16 V  
0.1µF  
µPD74HC04  
2.2 kΩ  
VOUT  
µPD3753CY  
2SA1005  
1
2
3
4
5
6
7
8
9
NC  
NC 22  
NC 21  
φ2  
NC  
VOD  
NC  
NC  
NC  
NC  
NC  
φTG  
100 Ω  
AGND 20  
VOUT 19  
NC 18  
100 Ω  
47 Ω  
NC 17  
NC 16  
φ2 15  
φ1 14  
φ1  
10 Ω  
47 Ω  
10 NC  
11 NC  
DGND 13  
NC 12  
φTG  
The application circuits and their parameters are for references only and are not intended for use in actual design-in's.  
12  
µPD3753  
PACKAGE DIMENSIONS  
CCD LINEAR IMAGE SENSOR 22PIN PLASTIC DIP (400 mil)  
(Unit : mm)  
1bit  
1.7±0.3  
37.5  
44.0±0.3  
10.16  
2.35±0.2  
1
2.54  
1.02±0.15  
0.46±0.1  
25.4  
Name  
Dimensions  
Refractive index  
2
Plastic cap  
42.9 × 8.35 × 0.7  
1.5  
1 The bottom of the package  
The surface of the chip  
2 The thickness of the cap over the chip  
22C-1CCD-PKG2  
13  
µPD3753  
RECOMMENDED SOLDERING CONDITIONS  
The following conditions (see table below) must be met when soldering this product.  
For more details, refer to our document “SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL”  
(IEI-1207).  
Please consult with our sales offices in case other soldering process is used, or in case soldering is done  
under different conditions.  
Table 1 Type of Through Hole Device  
µPD3753CY: CCD LINEAR IMAGE SENSOR 22 PIN PLASTIC DIP (400 mil)  
Soldering Process  
Soldering Conditions  
Wave soldering (Only lead part)  
Solder temperature: 260 °C or below,  
Flow time: 10 seconds or below  
Partial heating method  
Pin temperature: 260 °C or below,  
Time: 10 seconds or below  
Caution Do not jet molten solder on the surface of package.  
14  
µPD3753  
NOTES FOR CMOS DEVICES  
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS  
Note: Strong electric field, when exposed to a MOS device, can cause destruction of  
the gate oxide and ultimately degrade the device operation. Steps must be  
taken to stop generation of static electricity as much as possible, and quickly  
dissipate it once, when it has occurred. Environmental control must be  
adequate. When it is dry, humidifier should be used. It is recommended to  
avoid using insulators that easily build static electricity. Semiconductor  
devices must be stored and transported in an anti-static container, static  
shielding bag or conductive material. All test and measurement tools including  
work bench and floor should be grounded. The operator should be grounded  
using wrist strap. Semiconductor devices must not be touched with bare  
hands. Similar precautions need to be taken for PW boards with semiconductor  
devices on it.  
2 HANDLING OF UNUSED INPUT PINS FOR CMOS  
Note: No connection for CMOS device inputs can be cause of malfunction. If no  
connection is provided to the input pins, it is possible that an internal input  
level may be generated due to noise, etc., hence causing malfunction. CMOS  
devices behave differently than Bipolar or NMOS devices. Input levels of CMOS  
devices must be fixed high or low by using a pull-up or pull-down circuitry. Each  
unused pin should be connected to VDD or GND with a resistor, if it is considered  
to have a possibility of being an output pin. All handling related to the unused  
pins must be judged device by device and related specifications governing the  
devices.  
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES  
Note: Power-on does not necessarily define initial status of MOS device. Production  
process of MOS does not define the initial operation status of the device.  
Immediately after the power source is turned ON, the devices with reset  
function have not yet been initialized. Hence, power-on does not guarantee  
out-pin levels, I/O settings or contents of registers. Device is not initialized  
until the reset signal is received. Reset operation must be executed immedi-  
ately after power-on for devices having reset function.  
15  
µPD3753  
[MEMO]  
No part of this document may be copied or reproduced in any form or by any means without the prior written  
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this  
document.  
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual  
property rights of third parties by or arising from use of a device described herein or any other liability arising  
from use of such device. No license, either express, implied or otherwise, is granted under any patents,  
copyrights or other intellectual property rights of NEC Corporation or others.  
The devices listed in this document are not suitable for use in aerospace equipment, submarine cables, nuclear  
reactor control systems and life support systems. If customers intend to use NEC devices for above applications  
or they intend to use "Standard" quality grade NEC devices for applications not intended by NEC, please contact  
our sales people in advance.  
Application examples recommended by NEC Corporation  
Standard: Computer, Office equipment, Communication equipment, Test and Measurement equipment,  
Machine tools, Industrial robots, Audio and Visual equipment, Other consumer products, etc.  
Special: Automotive and Transportation equipment, Traffic control systems, Antidisaster systems, Anticrime  
systems, etc.  
M4 92.6  

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