UPD3778 [NEC]
10600 PIXELS x 3 COLOR CCD LINEAR IMAGE SENSOR; 10600像素× 3彩色CCD线性图像传感器
| 型号： | UPD3778 |
| 厂家： | 
NEC |
| 描述： | 10600 PIXELS x 3 COLOR CCD LINEAR IMAGE SENSOR |
| 文件： | 总24页 (文件大小：122K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD3778
10600 PIXELS × 3 COLOR CCD LINEAR IMAGE SENSOR
The µPD3778 is a color CCD (Charge Coupled Device) linear image sensor which changes optical images to
electrical signal and has the function of color separation.
The µPD3778 has 3 rows of 10600 pixels, and each row has a double-sided readout type of charge transfer register.
And it has reset feed-through level clamp circuits and voltage amplifiers. Therefore, it is suitable for 1200 dpi/A4 color
image scanners and so on.
FEATURES
• Valid photocell : 10600 pixels × 3
• Photocell's pitch : 4 µm
• Photocell size : 4 × 4 µm2
• Line spacing
• Color filter
• Resolution
: 48 µm (12 lines) Red line-Green line, Green line-Blue line
: Primary colors (red, green and blue), pigment filter (with light resistance 107 lx•hour)
: 48 dot/mm A4 (210 × 297 mm) size (shorter side)
1200 dpi US letter (8.5” × 11”) size (shorter side)
• Drive clock level : CMOS output under 5 V operation
• Data rate
: 5 MHz MAX.
: +12 V
• Power supply
• On-chip circuits : Reset feed-through level clamp circuits
Voltage amplifiers
ORDERING INFORMATION
Part Number
Package
µPD3778CY
CCD linear image sensor 32-pin plastic DIP (400 mil)
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability
and additional information.
Document No. S14374EJ1V0DS00 (1st edition)
Date published July 1999 N CP(K)
Printed in Japan
1999
©
BLOCK DIAGRAM
φ
2
φ
1
V
OD
GND
1
GND
16
29
22
19
CCD analog shift register
Transfer gate
φ
φ
φ
TG1
(Blue)
18
17
15
V
(Blue)
OUT
1
Photocell
(Blue)
........
........
........
30
31
32
Transfer gate
CCD analog shift register
CCD analog shift register
Transfer gate
TG2
(Green)
V
OUT2
Photocell
(Green)
(Green)
Transfer gate
CCD analog shift register
CCD analog shift register
Transfer gate
TG3
(Red)
V
(Red)
OUT3
Photocell
(Red)
Transfer gate
CCD analog shift register
3
2
14
11
µ
φ
φ
φ
φ
1
CLB
RB
2
µPD3778
PIN CONFIGURATION (Top View)
CCD linear image sensor 32-pin plastic DIP (400 mil)
•
µPD3778CY
Ground
GND
1
2
3
4
5
6
7
8
9
32
31
30
29
V
V
V
V
OUT
OUT
OUT
OD
3
2
1
Output signal 3 (Red)
Reset gate clock
φ
Output signal 2 (Green)
Output signal 1 (Blue)
Output drain voltage
No connection
RB
Reset feed-through level
clamp clock
φ
CLB
NC
NC
IC
No connection
No connection
28 NC
27 IC
26 IC
25 NC
24 NC
23 NC
Internal connection
Internal connection
No connection
Internal connection
Internal connection
No connection
IC
NC
NC
No connection
No connection
No connection
NC 10
No connection
φ
φ
2
11
22
Shift register clock 2
Internal connection
Internal connection
Shift register clock 1
1
Shift register clock 1
Internal connection
Internal connection
Shift register clock 2
IC 12
IC 13
21 IC
20 IC
φ
2
14
15
19
18
17
φ
φ
φ
1
Transfer gate clock 3
(for Red)
Transfer gate clock 1
(for Blue)
φ
TG1
TG2
TG3
Transfer gate clock 2
(for Green)
GND 16
Ground
Caution Leave pins 6, 7, 12, 13, 20, 21, 26, 27 (IC) unconnected.
Data Sheet S14374EJ1V0DS00
3
µPD3778
PHOTOCELL STRUCTURE DIAGRAM
PHOTOCELL ARRAY STRUCTURE DIAGRAM
(Line spacing)
4 µm
Blue photocell array
Green photocell array
Red photocell array
2
2 µm
µ
m
12 lines
(48 µm)
4 µm
4 µm
µ
Channel stopper
12 lines
(48 µm)
Aluminum
shield
4
Data Sheet S14374EJ1V0DS00
µPD3778
ABSOLUTE MAXIMUM RATINGS (TA = +25 °C)
Parameter
Output drain voltage
Symbol
Ratings
–0.3 to +15
–0.3 to +8
–0.3 to +8
–0.3 to +8
–0.3 to +8
–25 to +60
–40 to +70
Unit
V
VOD
Shift register clock voltage
Vφ1, Vφ2
VφRB
V
Reset gate clock voltage
V
Reset feed-through level clamp clock voltage
Transfer gate clock voltage
Operating ambient temperature
Storage temperature
VφCLB
V
VφTG1 to VφTG3
TA
V
°C
°C
Tstg
Caution Exposure to ABSOLUTE MAXIMUM RATINGS for extended periods may affect device reliability;
exceeding the ratings could cause permanent damage. The parameters apply independently.
RECOMMENDED OPERATING CONDITIONS (TA = +25 °C)
Parameter
Output drain voltage
Symbol
MIN.
11.4
4.5
TYP.
12.0
5.0
0
MAX.
12.6
5.5
Unit
V
VOD
Shift register clock high level
Shift register clock low level
Reset gate clock high level
Vφ1H, Vφ2H
Vφ1L, Vφ2L
VφRBH
V
–0.3
4.5
+0.5
5.5
V
5.0
0
V
Reset gate clock low level
VφRBL
–0.3
4.5
+0.5
5.5
V
Reset feed-through level clamp clock high level
Reset feed-through level clamp clock low level
Transfer gate clock high level
Transfer gate clock low level
Data rate
VφCLBH
5.0
V
VφCLBL
–0.3
4.5
0
+0.5
V
Vφ1HNote
Vφ1HNote
VφTG1H to VφTG3H
VφTG1L to VφTG3L
fφRB
V
–0.3
–
0
+0.5
5.0
V
1.0
MHz
Note When Transfer gate clock high level (VφTG1H to VφTG3H) is higher than Shift register clock high level (Vφ1H),
Image lag can increase.
Data Sheet S14374EJ1V0DS00
5
µPD3778
ELECTRICAL CHARACTERISTICS
TA = +25 °C, VOD = 12 V, data rate (fφRB) = 2 MHz, storage time = 5.5 ms, input signal clock = 5 Vp-p,
light source: 3200 K halogen lamp +C-500S (infrared cut filter, t = 1mm) + HA-50 (heat absorbing filter, t = 3 mm)
Parameter
Saturation voltage
Saturation exposure
Symbol
Vsat
Test Conditions
MIN.
2.0
TYP.
2.5
MAX.
–
Unit
V
Red
SER
SEG
SEB
PRNU
ADS
DSNU
PW
0.694
0.757
1.250
6
lx•s
lx•s
lx•s
%
Green
Blue
Photo response non-uniformity
Average dark signal
VOUT = 1.0 V
20
4.0
Light shielding
Light shielding
0.2
mV
mV
mW
kΩ
Dark signal non-uniformity
Power consumption
1.5
4.0
400
0.5
600
1
Output impedance
ZO
Response
Red
RR
2.52
2.31
1.40
3.60
3.30
2.00
2.0
4.68
4.29
2.60
10.0
7.0
V/lx•s
V/lx•s
V/lx•s
%
Green
Blue
RG
RB
Image lag
IL
VOUT = 1.0 V
Note1
Offset level
VOS
4.0
92
0
6.0
V
Note2
Output fall delay time
td
VOUT = 1.0 V
50
ns
Total transfer efficiency
TTE
VOUT = 1.0 V,
data rate = 5 MHz
VOUT = 1.0 V
98
%
Register imbalance
Response peak
RI
1.0
630
4.0
%
nm
Red
Green
Blue
540
nm
460
nm
Dynamic range
DR1
Vsat /DSNU
1666
2500
–300
1.0
times
times
mV
DR2
Vsat /σ CDS
Note1
Reset feed-through noise
Random noise (CDS)
RFTN
σ CDS
Light shielding
Light shielding
–1000
–
+500
–
mV
Notes 1. Refer to TIMING CHART 2.
2. When each fall time of φ1 and φ2 (t2, t1) is the TYP. value (refer to TIMING CHART 2).
6
Data Sheet S14374EJ1V0DS00
µPD3778
INPUT PIN CAPACITANCE (TA = +25 °C, VOD = 12 V)
Parameter
Symbol Pin name Pin No.
MIN.
TYP.
400
400
400
400
15
MAX.
Unit
pF
pF
pF
pF
pF
pF
pF
pF
pF
Shift register clock pin capacitance 1
Cφ1
φ1
11
19
14
22
2
Shift register clock pin capacitance 2
Reset gate clock pin capacitance
Cφ2
φ2
CφRB
φRB
Reset feed-through level clamp clock pin capacitance CφCLB
Transfer gate clock pin capacitance
φCLB
φTG1
φTG2
φTG3
3
15
CφTG
18
17
15
120
120
120
Remark Pins 11 and 19 (φ1), 14 and 22 (φ2) are each connected inside of the device.
Data Sheet S14374EJ1V0DS00
7
TIMING CHART 1 (for each color)
φ TG1 to
φ TG3
φ1
φ 2
φ RB
φ CLB
Note
Note
V
OUT1 to
V
OUT
3
Optical black
(49 pixels)
Valid photocell
(10600 pixels)
Invalid photocell
(2 pixels)
Invalid photocell
(3 pixels)
Note Input the φRB and φCLB pulses continuously during this period, too.
µ
TIMING CHART 2 (for each color)
t1
t2
90 %
10 %
φ
φ
1
2
90 %
10 %
t5
t6
t3
t4
t7
90 %
10 %
φ
RB
t8
t9
t10
t11
90 %
10 %
φ
CLB
+
_
td
td
RFTN
RFTN
VOUT
VOS
10 %
10 %
µ
µPD3778
φTG1 to φTG3, φ1, φ2 TIMING CHART
t13
t14
t12
90 %
10 %
φ
TG1 to TG3
φ
t16
t15
90 %
φ
φ
1
2
Symbol
t1, t2
MIN.
0
TYP.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
25
50
–
–
–
–
–
–
–
–
–
–
–
t3
20
70
0
t4
250
25
t5, t6
t7
30
0
50
t8, t9
t10
t11
t12
25
30
5
50
15
5000
0
10000
50
t13, t14
t15, t16
900
1000
φ1, φ2 cross points
φ
φ
1
2
2.0 V or more
2.0 V or more
Remark Adjust cross points of φ1 and φ2 with input resistance of each pin.
10
Data Sheet S14374EJ1V0DS00
µPD3778
DEFINITIONS OF CHARACTERISTIC ITEMS
1. Saturation voltage: Vsat
Output signal voltage at which the response linearity is lost.
2. Saturation exposure: SE
Product of intensity of illumination (IX) and storage time (s) when saturation of output voltage occurs.
3. Photo response non-uniformity: PRNU
The output signal non-uniformity of all the valid pixels when the photosensitive surface is applied with the light
of uniform illumination. This is calculated by the following formula.
∆x
PRNU (%) =
× 100
x
∆x : maximum of xj − x
10600
xj
Σ
j=1
x =
10600
xj : Output voltage of valid pixel number j
VOUT
x
Register Dark
DC level
∆x
4. Average dark signal: ADS
Average output signal voltage of all the valid pixels at light shielding. This is calculated by the following formula.
10600
dj
Σ
j=1
ADS (mV) =
10600
dj : Dark signal of valid pixel number j
5. Dark signal non-uniformity: DSNU
Absolute maximum of the difference between ADS and voltage of the highest or lowest output pixel of all the valid
pixels at light shielding. This is calculated by the following formula.
DSNU (mV) : maximum of d − ADS j = 1 to 10600
j
dj
: Dark signal of valid pixel number j
V
OUT
ADS
Register Dark
DC level
DSNU
Data Sheet S14374EJ1V0DS00
11
µPD3778
6. Output impedance: ZO
Impedance of the output pins viewed from outside.
7. Response: R
Output voltage divided by exposure (Ix•s).
Note that the response varies with a light source (spectral characteristic).
8. Image Lag: IL
The rate between the last output voltage and the next one after read out the data of a line.
TG
Light
ON
OFF
V
OUT
V
1
V
OUT
V1
IL (%) =
×100
VOUT
9. Register imbalance: RI
The rate of the difference between the averages of the output voltage of Odd and Even pixels, against the average
output voltage of all the valid pixels.
n
2
2
n
∑ (V2j – 1 – V2j)
j= 1
RI (%) =
× 100
n
n1∑Vj
j= 1
n : Number of valid pixels
Vj : Output voltage of each pixel
12
Data Sheet S14374EJ1V0DS00
µPD3778
10. Random noise (CDS): σCDS
Random noise (CDS) σCDS is defined as the standard deviation of a valid pixel output signal with 100 times (=
100 lines) data sampling at dark (light shielding). This is measured by the following procedure.
1. One valid photocell in one reading is fixed as measurement point.
2. The output level is measured during the Reset feed-through period which is averaged over 100 ns to get “VDi”.
3. The output level is measured during the Video output time averaged over 100 ns to get “VOi”.
4. The correlated double sampling output is defined by “VCDSi = VDi – VOi”.
5. Repeat the above procedure (1 to 4) for 100 times (= 100 lines).
6. Calculate the standard deviation σCDS using the following formula.
100
100
(VCDS
100
i
– V)2
1
Σ
σCDS (mV) =
, V =
VCDS
i
100 Σ
i=1
i=1
Reset feed-through
V
OUT
Video output
Data Sheet S14374EJ1V0DS00
13
µPD3778
STANDARD CHARACTERISTIC CURVES (Nominal)
DARK OUTPUT TEMPERATURE
CHARACTERISTIC
STORAGE TIME OUTPUT VOLTAGE
CHARACTERISTIC (TA = +25 °C)
8
4
2
1
2
1
0.5
0.25
0.2
0.1
0.1
0
10
20
30
40
50
1
5
10
Operating Ambient Temperature TA(°C)
Storage Time (ms)
TOTAL SPECTRAL RESPONSE CHARACTERISTICS
(without infrared cut filter and heat absorbing filter) (T = +25 °C)
A
100
80
R
B
G
60
40
20
G
B
0
400
500
600
700
800
Wavelength (nm)
14
Data Sheet S14374EJ1V0DS00
µPD3778
APPLICATION CIRCUIT EXAMPLE
µ
PD3778
1
2
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
GND
V
OUT
OUT
OUT
3
2
1
B3
B2
B1
47 Ω
φ
φ
φ
V
V
RB
RB
47 Ω
+12 V
3
φ
CLB
CLB
10 Ω
4
NC
NC
IC
VOD
+
5
NC
IC
47
µ
F/25 V
0.1 µF
+5 V
6
+5 V
7
IC
IC
+
8
NC
NC
NC
NC
NC
NC
+
10 µF/16 V 0.1 µF
9
10
µ
F/16 V
0.1 µF
10
11
12
13
14
15
16
4.7 Ω
4.7 Ω
φ
φ
φ
2
1
2
1
IC
IC
IC
IC
4.7 Ω
4.7 Ω
4.7 Ω
4.7 Ω
4.7 Ω
φ
φ
φ
2
φ
1
φ
φ
φ
TG1
TG2
TG
TG3
GND
Caution Leave pins 6, 7, 12, 13, 20, 21, 26, 27 (IC) unconnected.
Remark The inverters shown in the above application circuit example are the 74HC04 or 74AC04.
Data Sheet S14374EJ1V0DS00
15
µPD3778
B1 to B3 EQUIVALENT CIRCUIT
12 V
+
µ
47 F/25 V
100 Ω
100 Ω
CCD
VOUT
2SC945
2 kΩ
16
Data Sheet S14374EJ1V0DS00
µPD3778
PACKAGE DRAWING
CCD LINEAR IMAGE SENSOR 32-PIN PLASTIC DIP (400 mil)
(Unit : mm)
1st valid pixel
1
6.15±0.3
32
17
16
1
12.6±0.5
4.1±0.5
54.8±0.5
55.2±0.5
10.16
(1.80)
2
3
2.58±0.3
(5.42)
4.21±0.5
4.55±0.5
1.02±0.15
0.46±0.06
2.54
38.1
Name
Dimensions
Refractive index
1.5
4
Plastic cap
52.2×6.4×0.7
1 The 1st valid pixel
The center of the pin1
The top of the cap
2 The surface of the chip
3 The bottom of the package
The surface of the chip
4 Thickness of plastic cap over CCD chip
32C-1CCD-PKG3
Data Sheet S14374EJ1V0DS00
17
µPD3778
RECOMMENDED SOLDERING CONDITIONS
When soldering this product, it is highly recommended to observe the conditions as shown below.
If other soldering processes are used, or if the soldering is performed under different conditions, please make sure
to consult with our sales offices.
For more details, refer to our document "Semiconductor Device Mounting Technology Manual"(C10535E).
Type of Through-hole Device
µPD3778CY : CCD linear image sensor 32-pin plastic DIP (400 mil)
Process
Conditions
Partial heating method
Pin temperature: 300 °C or below,
Heat time: 3 seconds or less (per pin)
Caution During assembly care should be taken to prevent solder or flux from contacting the plastic cap.
The optical characteristics could be degraded by such contact.
18
Data Sheet S14374EJ1V0DS00
µPD3778
NOTES ON CLEANING THE PLASTIC CAP
1 CLEANING THE PLASTIC CAP
Care should be taken when cleaning the surface to prevent scratches.
The optical characteristics of the CCD will be degraded if the cap is scratched during
cleaning.
We recommend cleaning the cap with a soft cloth moistened with one of the recommended
solvents below. Excessive pressure should not be applied to the cap during cleaning. If the
cap requires multiple cleanings it is recommended that a clean surface or cloth be used.
2 RECOMMENDED SOLVENTS
The following are the recommended solvents for cleaning the CCD plastic cap. Use of
solvents other than these could result in optical or physical degradation in the plastic cap.
Please consult your sales office when considering an alternative solvent.
Solvents
Symbol
Ethyl Alcohol
EtOH
MeOH
IPA
Methyl Alcohol
Isopropyl Alcohol
N-methyl Pyrrolidone
NMP
Data Sheet S14374EJ1V0DS00
19
µPD3778
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
20
Data Sheet S14374EJ1V0DS00
µPD3778
[MEMO]
Data Sheet S14374EJ1V0DS00
21
µPD3778
[MEMO]
22
Data Sheet S14374EJ1V0DS00
µPD3778
[MEMO]
Data Sheet S14374EJ1V0DS00
23
µPD3778
[MEMO]
• The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
• No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
• NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from use of a device described herein or any other liability arising
from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights
or other intellectual property rights of NEC Corporation or others.
• Descriptions of circuits, software, and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these circuits,
software, and information in the design of the customer's equipment shall be done under the full responsibility
of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third
parties arising from the use of these circuits, software, and information.
• While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
• NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated “quality assurance program“ for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
M7 98.8
相关型号：
UPD3789CY
CCD Sensor, 5348 Horiz pixels, 5348 Vert pixels, 2-2.50V, Rectangular, Through Hole Mount, 10.16 MM, PLASTIC, DIP-32
NEC
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