UPD3768D-AZ_技术文档

DATA SHEET

MOS INTEGRATED CIRCUIT

µ PD3768

7500 PIXELS × 3 COLOR CCD LINEAR IMAGE SENSOR

DESCRIPTION

The µPD3768 is a high-speed and high sensitive color CCD (Charge Coupled Device) linear image sensor which

changes optical images to electrical signal and has the function of color separation.

The µPD3768 has 3 rows of 7500 pixels, and it is a 2-output/color type CCD sensor with 2 rows/color of charge

transfer register, which transfers the photo signal electrons of 7500 pixels separately in odd and even pixels.

Therefore, it is suitable for 600 dpi/A3 high-speed color digital copiers, color scanners and so on.

FEATURES

• Valid photocell : 7500 pixels × 3

• Photocell pitch : 9.325 µm

• Line spacing

• Color filter

• Resolution

: 37.3 µm (4 lines) Red line - Green line, Green line - Blue line

: Primary colors (red, green and blue), pigment filter (with light resistance 10⁷lx•hour)

: 24 dot/mm A3 (297 × 420 mm) size (shorter side)

• Drive clock level : CMOS output under 5 V operation

• Data rate

• Output type

• Power supply

: 44 MHz MAX. (22 MHz/1 output)

: 2 outputs in phase/color

: +10 V

• On-chip circuits : Reset feed-through level clamp circuits

Voltage amplifiers

ORDERING INFORMATION

Part Number

Package

CCD linear image sensor 36-pin ceramic DIP (CERDIP) (15.24 mm (600))

µPD3768D

The information in this document is subject to change without notice. Before using this document, please

confirm that this is the latest version.

Not all devices/types available in every country. Please check with local NEC representative for

availability and additional information.

Document No. S15418EJ2V0DS00 (2nd edition)

Date Published September 2002 NS CP (K)

Printed in Japan

The mark

shows major revised points.

2001

µ PD3768

BLOCK DIAGRAM

φ

CP

φ

2L

φ

20

GND

16

φ

1B

23

φ

2A

24

30

29

28

V

OD

31

32

V

OUT

2

CCD analog shift register

Transfer gate

(Blue, even)

Photocell

(Blue)

φ

TG1

(Blue)

. . . . .

22

21

15

GND

33

34

Transfer gate

VOUT1

CCD analog shift register

(Blue, odd)

GND

35

36

VOUT3

CCD analog shift register

Transfer gate

(Green, odd)

Photocell

(Green)

φ

TG2

(Green)

Transfer gate

VOUT4

CCD analog shift register

1

2

3

(Green, even)

GND

VOUT6

CCD analog shift register

Transfer gate

(Red, even)

Photocell

(Red)

φ

TG3

GND

4

5

(Red)

Transfer gate

VOUT5

CCD analog shift register

(Red, odd)

13

6

7

8

9

14

2B

φ

R

φ

2L

φ

10

φ

1A

φ

V

OD

2

Data Sheet S15418EJ2V0DS

µ PD3768

PIN CONFIGURATION (Top View)

CCD linear image sensor 36-pin ceramic DIP (CERDIP) (15.24 mm (600))

• µPD3768D

Output signal 4 (Green, even)

V

OUT

4

1

2

3

4

5

6

7

8

9

36

V

OUT

3

Output signal 3 (Green, odd)

Ground GND

35 GND

Ground

Output signal 6 (Red, even)

V

OUT

6

34

V

OUT

1

Output signal 1 (Blue, odd)

Ground

Ground GND

33 GND

Output signal 5 (Red, odd)

Output unit drain voltage

Reset gate clock

V

OUT

5

32

31

V

OUT

OD

2

Output signal 2 (Blue, even)

Output unit drain voltage

V

OD

Reset feed-through level

clamp clock

φ

30 CP

φ

R

φ

Last stage shift register clock

Shift register clock 10

φ

2L

10

29 2L

Last stage shift register clock

28 20

φ

Shift register clock 20

No connection

NC 10

NC 11

NC 12

27 NC

26 NC

25 NC

No connection

Shift register clock 2A

Shift register clock 1B

Shift register clock 1A

Shift register clock 2B

Transfer gate clock 3 (for Red)

φ

1A 13

2B 14

24

23

22

21

φ

2A

1B

φ

TG3 15

TG1 Transfer gate clock 1 (for Blue)

TG2 Transfer gate clock 2 (for Green)

Ground GND 16

No connection

NC 17

NC 18

20 NC

19 NC

No connection

Caution Connect the No connection pins (NC) to GND.

PHOTOCELL STRUCTURE DIAGRAM

PHOTOCELL ARRAY STRUCTURE DIAGRAM

(Line spacing)

9.325

µ

m

Blue photocell array

Green photocell array

Red photocell array

4 lines

(37.3

3 µm

6.325

µ

m

µ

m)

µ

Channel stopper

4 lines

(37.3

µ

Aluminum

shield

3

Data Sheet S15418EJ2V0DS

µ PD3768

ABSOLUTE MAXIMUM RATINGS (T^A= +25°C)

Parameter

Output drain voltage

Symbol

Ratings

−0.3 to +12

−0.3 to +8

−25 to +60

−40 to +100

Unit

V

V^OD

Shift register clock voltage

Last gate shift register clock voltage

Reset gate clock voltage

V^φ¹, V^φ²

V^φ^2L

V

V^φ^R

V

Clamp clock voltage

V^φ^CP

V

Transfer gate clock voltage

Operating ambient temperature ^Note

Storage temperature

V^φ^TG1to V^φ^TG3

V

T^A

°C

T^stg

Note Use at the condition without dew condensation.

Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any

parameter. That is, the absolute maximum ratings are rated values at which the product is on the

verge of suffering physical damage, and therefore the product must be used under conditions that

ensure that the absolute maximum ratings are not exceeded.

RECOMMENDED OPERATING CONDITIONS (T^A= +25°C)

Parameter

Output drain voltage

Symbol

Min.

9.5

Typ.

10.0

5.0

0

Max.

10.5

5.5

Unit

V

V^OD

Shift register clock high level

Shift register clock low level

Last gate shift register clock high level

Last gate shift register clock low level

Reset gate clock high level

Reset gate clock low level

Clamp clock high level

V^φ^1H, V^φ^2H

V^φ^1L, V^φ^2L

V^φ^2LH

4.5

V

−0.3

4.5

+0.5

5.5

V

5.0

0

V

V^φ^2LL

−0.3

4.5

+0.5

5.5

V

V^φ^RH

5.0

0

V

V^φ^RL

−0.3

4.5

+0.5

5.5

V

V^φ^CPH

5.0

0

V

Clamp clock low level

V^φ^CPL

−0.3

4.5

+0.5

V

Note

V^φ^1H

Note

V^φ^1H

Transfer gate clock high level

Transfer gate clock low level

Data rate

V^φ^TG1Hto V^φ^TG3H

V^φ^TG1Lto V^φ^TG3L

2f^φ^R

V

−0.3

1

0

2

+0.5

V

44

MHz

Note When Transfer gate clock high level (Vφ ^TG1Hto Vφ ^TG3H) is higher than Shift register clock high level (Vφ ^1H),

Image lag can increase.

4

Data Sheet S15418EJ2V0DS

µ PD3768

ELECTRICAL CHARACTERISTICS

T^A= +25°C, V^OD= 10 V, fφ ^R= 1 MHz, data rate = 2 MHz, storage time = 10 ms, input signal clock = 5 V^p-p,

light source (except Response1) : 2950 K halogen lamp + CM-500S (infrared cut filter, t = 1 mm)

Parameter

Saturation voltage

Saturation exposure

Symbol

V^sat

Test Conditions

Min.

1.5

−

Typ.

2.0

Max.

−

Unit

V

Red

SER

2950 K halogen lamp + CM-500S

0.14

0.13

0.26

6.0

−

lx•s

%

Green

Blue

SEG

SEB

−

Photo response non-uniformity

PRNU

V^OUT= 1.0 V

−

18.0

Photo response non-uniformity

at low illumination

PRNU2 V^OUT= 0.1 V

−

6.0

%

Average dark signal

ADS

Light shielding, data rate = 2 MHz,

−

1.0

3.0

5.0

mV

storage time = 10 ms

Dark signal non-uniformity

DSNU

Light shielding, data rate = 2 MHz,

storage time = 10 ms

12.0

Power consumption

Output impedance

P^W

−

700

0.2

22.0

18.0

8.0

14.0

15.3

7.6

40

900

0.4

28.6

23.4

10.4

18.2

19.9

9.9

80

20

30

5.2

−

mW

kΩ

Z^O

Response1

Red

R^R

3200 K halogen lamp + C-500S

+ HA-50

15.4

12.6

5.6

9.8

10.7

5.3

−

V/lx•s

mV

Green

Blue

R^G

R^B

Response2

Red

R^R

2950 K halogen lamp + CM-500S

Green

Blue

R^G

R^B

Image lag

IL

V^OUT= 500 mV

Image lag color difference

IL-DIF

IL-O/E

V^OS

t^d

−

5

mV

Image lag O/E

Offset level ^{Note 1}

Output fall delay time ^{Note 2}

Register imbalance

Total transfer efficiency

Response peak

−

10

mV

3.8

−

4.5

14

V

ns

RI

V^OUT= 1.0 V

−

0

5

%

TTE

V^OUT= 1.0 V, fφ ^R= 22 MHz

94

−

98

−

%

Red

630

540

445

666

870

−200

2.3

−

nm

Green

Blue

−

nm

−

nm

Dynamic range

DR1

V^sat/DSNU

−

times

mV

DR2

V^sat/σ dark

−

Reset feed-through noise

RFTN

σ dark

Light shielding

Bit clamp, t17 = 10 ns

−1000

−

+500

−

Light shielding random noise

mV

Notes 1. Refer to TIMING CHART 2 and TIMING CHART 4.

2. t^dis defined as periods from 10% of φ2L to 10% of V^OUT1 to V^OUT6 (refer to APPLICATION CURCUIT

EXAMPLE).

5

Data Sheet S15418EJ2V0DS

µ PD3768

INPUT PIN CAPACITANCE (T^A= +25°C, V^OD= 10 V)

Parameter

Symbol

C^φ¹

φ 10

Pin No.

9

Min.

−

Typ.

330

10

Max.

450

20

Unit

pF

Shift register clock pin capacitance

φ 1A

φ 1B

φ 2B

φ 2A

φ 20

φ 2L

13

23

14

24

28

8

−

C^φ²

−

Last stage shift register clock pin capacitance

C^φ^L

−

29

7

−

10

20

Reset gate clock pin capacitance

Clamp clock pin capacitance

C^φ^R

φ R

−

10

20

C^φ^CP

C^φ^TG

φ CP

φ TG1

φ TG2

φ TG3

30

22

21

15

−

10

20

Transfer gate clock pin capacitance

−

100

150

−

6

Data Sheet S15418EJ2V0DS

µ PD3768

TIMING CHART 2 (Bit clamp mode, for each color)

t6

t7

90%

10%

φ

10,

20,

φ

1A,

2A,

φ

1B

2B

90%

10%

t7L

90%

t6L

φ

2L

10%

t8

t10

t9

t17

t15

90%

10%

φ

R

t12

t16

t13 t14

90%

10%

φ

CP

t

d

+

V

OUT1 to VOUT6

RFTN

−

VOS

10%

Symbol

t6, t7

Min.

Typ.

50

Max.

Unit

ns

0

−

t6L, t7L

t8, t10

t9

5

0

5

10

0

125

5

t12, t14

t13

10

0

125

250

125

t15

t16

8

t17

8

Data Sheet S15418EJ2V0DS

µ PD3768

TIMING CHART 4 (Line clamp mode, for each color)

t6

t7

90%

10%

φ

10,

20,

φ

1A,

2A,

φ

1B

2B

90%

10%

t7L

90%

t6L

φ

2L

10%

t8

t10

t9

t20

90%

10%

φ

R

φ

CP

'L'

t

d

+

V

OUT1 to VOUT6

RFTN

−

VOS

10%

Symbol

t6, t7

Min.

Typ.

50

Max.

Unit

ns

0

−

t6L, t7L

t8, t10

t9

5

ns

0

5

ns

10

5

125

250

ns

t20

ns

10

Data Sheet S15418EJ2V0DS

µ PD3768

TIMING CHART 5 (Bit clamp mode, line clamp mode, for each color)

t2

t4

t3

90%

10%

t1

φ

TG1 to φ TG3

90%

φ

10,

20,

φ

1A,

2A,

φ

1B

2B

φ

2L

t8

t10

t17

Note

t5

90%

10%

t9

t15

φ

R

t12

t16

90%

10%

t13 t14

φ

CP

Symbol

Min.

Typ.

Max.

Unit

t1, t5

200

0

300

50

−

ns

t2, t4

t3

3000

0

5000

5

t8, t10

t9

10

0

125

5

t12, t14

t13

10

0

125

250

125

t15

t16

8

t17

8

Note Set the φ R and φ CP pulse to low level during this period.

11

Data Sheet S15418EJ2V0DS

µ PD3768

φ 10, φ 20 cross points

φ

10

20

2.0 V or more

φ 1A, φ 2A cross points

φ

1A

2A

φ 1B, φ 2B cross points

φ

1B

2B

φ 10, φ 2L cross points

φ

10

2L

2.0 V or more

0.5 V or more

Remark Adjust cross points (φ 10, φ 20), (φ 1A, φ 2A), (φ 1B, φ 2B) and (φ 10, φ 2L) with input resistance of each pin.

12

Data Sheet S15418EJ2V0DS

µ PD3768

DEFINITIONS OF CHARACTERISTIC ITEMS

1. Saturation voltage : V^sat

Output signal voltage at which the response linearity is lost.

2. Saturation exposure : SE

Product of intensity of illumination (lx) and storage time (s) when saturation of output voltage occurs.

3. Photo response non-uniformity : PRNU

The output signal non-uniformity of all the valid pixels when the photosensitive surface is applied with the light

of uniform illumination. This is calculated by the following formula, and it is defined by each six of them.

∆

x

PRNU (%) =

× 100

x

∆

x : maximum of x

j

− x 

7500

x

j

Σ

j=1

7500

: Output voltage of valid pixel number j

x =

xj

VOUT

x

Register Dark

DC level

∆

x

4. Average dark signal : ADS

Average output signal voltage of all the valid pixels at light shielding. This is calculated by the following

formula, and it is defined by each six of them.

7500

d

j

Σ

j=1

ADS (mV) =

7500

d

j

: Dark signal of valid pixel number j

13

Data Sheet S15418EJ2V0DS

µ PD3768

5. Dark signal non-uniformity : DSNU

Absolute maximum of the difference between ADS and voltage of the highest or lowest output pixel of all the

valid pixels at light shielding. This is calculated by the following formula, and it is defined by each six of them.

DSNU (mV) : maximum of d

j

− ADS j = 1 to 7500

dj

: Dark signal of valid pixel number j

VOUT

ADS

Register Dark

DC level

DSNU

6. Output impedance : Z^O

Impedance of the output pins viewed from outside.

7. Response : R

Output voltage divided by exposure (lx•s).

Note that the response varies with a light source (spectral characteristic).

8. Image lag : IL

The rate between the last output voltage and the next one after read out the data of a line.

φ

TG

Light

ON

OFF

V

OUT

V1

VOUT

IL (mV) = V

1

(VOUT = 500 mV)

9. Image lag color difference : IL-DIF

It is defined as a difference between colors of the average of image lag.

It is expressed with the next expression to be concrete.

| (average of image lag of blue output)

−

(average of image lag of green output) |

−

| (average of image lag of green output) (average of image lag of red output) |

−

| (average of image lag of red output) (average of image lag of blue output) |

14

Data Sheet S15418EJ2V0DS

µ PD3768

10. Image lag O/E : IL-O/E

It is defined as a difference of the average of image lag of odd and even pixels for each color.

11. Register imbalance : RI

The rate of the difference between the averages of the output voltage of Odd and Even pixels, against the

average output voltage of all the valid pixels.

n

2

n

∑

(V2j –1 – V2j)

j = 1

RI (%) =

× 100

n

1

n

∑

V

j

j = 1

n

V

: Number of valid pixels

: Output voltage of each pixel

j

12. Total transfer efficiency : TTE

The total transfer rate of CCD analog shift register. This is calculated by the following formula, it is difined by

each output.

TTE (%) = (1 − V^b/ average output of all the valid pixels) × 100

V

b

V

a−1 : The last pixel output − 1 (Odd pixel: 7631th pixel)

a

b

: The last pixel output (Odd pixel: 7633th pixel)

: The spilt pixel output (Odd pixel: 7635th pixel)

V

a−1

V

a

13. Light shielding random noise : σ dark

Light shielding random noise σdark is defined as the standard deviation of a valid pixel output signal with 100

times (=100 lines) data sampling at dark (light shielding).

100

(V

i

– V)²

100

1

Σ

σ

dark (mV) =

, V =

Vi

₁₀₀Σ

i = 1

Vi : A valid pixel output signal among all of the valid pixels for each color

V1

V2

VOUT

line 1

line 2

V100

line 100

This is measured by the DC level sampling of only the signal level, not by CDS (Correlated Double Sampling).

15

Data Sheet S15418EJ2V0DS

µ PD3768

STANDARD CHARACTERISTIC CURVES (Reference Value)

DARK OUTPUT TEMPERATURE

CHARACTERISTIC

STORAGE TIME OUTPUT VOLTAGE

CHARACTERISTIC (T = +25°C)

A

8

2

4

2

1

0.5

0.25

0.2

0.1

0

10

20

30

40

50

1

5

10

Operating Ambient Temperature T

A

(°C)

Storage Time (ms)

TOTAL SPECTRAL RESPONSE CHARACTERISTICS

(without infrared cut filter and heat absorbing filter) (T

A

= +25°C)

100

R

80

60

40

20

0

G

B

G

400

500

600

700

Wavelength (nm)

16

Data Sheet S15418EJ2V0DS

µ PD3768

APPLICATION CIRCUIT EXAMPLE

+5 V

+10 V

10 Ω

+

µ

PD3768

1

2

3

4

5

6

7

8

9

36

35

34

33

32

31

30

29

28

B4

B3

B1

B2

V

OUT

4

V

OUT

3

+5 V

10

µ

F/16 V 0.1

µ

F

0.1

µ

F

47

µ

F/25 V

GND

V

OUT

6

VOUT

1

B6

B5

+

GND

V

φ

OUT

5

V

OUT

2

0.1

µ

F

10

µ

F/16 V

OD

VOD

47 Ω

2 Ω

47 Ω

2 Ω

φ

R

2L

10

R

φ

CP

2L

20

CP

φ

2L

10

φ

2L

20

φ

10

11

12

13

14

15

16

17

18

27

26

25

24

23

22

21

20

19

NC

2 Ω

φ

1A

2B

φ

2A

1B

φ

1A

2B

TG3

φ

2 Ω

φ

1B

φ

TG3

φ

TG1

TG2

NC

TG1

TG2

GND

NC

Caution Connect the No connection pins (NC) to GND.

Remarks 1. Connect two inverters (74AC04) to each φ10, φ1A, φ1B, φ20, φ2A, φ2B pin.

2. Inverters shown in the above application circuit example are the 74AC04.

3. B1 to B6 in the application circuit example are shown in the figure below.

B1-B6 equivalent curcuit

+10 V

47

µ F/25 V

+

4.7 kΩ

110 Ω

2SC945

47 Ω

CCD

2SA1005

VOUT

1 kΩ

17

Data Sheet S15418EJ2V0DS

µ PD3768

PACKAGE DRAWING

CCD LINEAR IMAGE SENSOR 36-PIN CERAMIC DIP (15.24 mm (600))

94.0 0.7

3.0 0.1

1.28 0.1

3.00 0.08

1.0 0.08

26.0 0.2

7.33 0.3

1

33.3 0.6

The 1st valid pixel

(5.0)

3.85 0.38

(1.8)

3

1.27

(2.6)

24.13 0.20

0.46

(17.09 MAX.)

(15.24 MIN.)

20.32 0.13

48.26 0.40

20.32 0.13

2.54 0.13

2.0 0.2

2

2.4 0.3

5.0 0.2

0.25 0.05

Name

Dimension

Refractive index

1.5

Glass cap

91.0×9.0×1.1

1 1st valid pixel

Center of package

2 The bottom of package

3 The surface of the chip

The surface of the chip

The surface of the glass cap

4 The tolerance of packge dimension

0.25 : less than 10 mm from W/F edge

0.50 : equal or more than 10 mm from W/F edge

36D-1CCD-PKG3-1

18

Data Sheet S15418EJ2V0DS

µ PD3768

RECOMMENDED SOLDERING CONDITIONS

When soldering this product, it is highly recommended to observe the conditions as shown below.

If other soldering processes are used, or if the soldering is performed under different conditions, please make sure

to consult with our sales offices.

Type of Through-hole Device

µ PD3768D : CCD linear image sensor 36-pin ceramic DIP (CERDIP) (15.24 mm (600))

Process

Conditions

Partial heating method

Pin temperature : 300 °C or below, Heat time : 3 seconds or less (per pin)

Cautions 1. During assembly care should be taken to prevent solder or flux from contacting the glass cap.

The optical characteristics could be degraded by such contact.

2. Soldering by the solder flow method may have deleterious effects on prevention of glass cap

soiling and heat resistance. So the method cannot be guaranteed.

19

Data Sheet S15418EJ2V0DS

µ PD3768

NOTES ON HANDLING THE PACKAGES

1

MOUNTING OF THE PACKAGE

The application of an excessive load to the package may cause the package to warp or break, or cause chips

to come off internally. Particular care should be taken when mounting the package on the circuit board. Don't

have any object come in contact with glass cap. You should not reform the lead frame. We recommended to

use a IC-inserter when you assemble to PCB.

Also, be care that the any of the following can cause the package to crack or dust to be generated.

1. Applying heat to the external leads for an extended period of time with soldering iron.

2. Applying repetitive bending stress to the external leads.

3. Rapid cooling or heating

For this product, the reference value for the three-point bending strength ^Noteis 180 [N] (at distance between

supports: 70 mm), is 500 [N] (at distance between supports: 26 mm). Avoid imposing a load, however, on the

inside portion as viewed from the face on which the window (glass) is bonded to the package body (ceramic).

Note Three-point bending strength test

Distance between supports: 70 mm or 26 mm, Support R: R 2 mm, Loading rate: 0.5 mm/min.

Load

70 mm

Load

70 mm

Load

26 mm

2

GLASS CAP

Don’t either touch glass cap surface by hand or have any object come in contact with glass cap surface.

Care should be taken to avoid mechanical or thermal shock because the glass cap is easily to damage. For

dirt stuck through electricity ionized air is recommended.

20

Data Sheet S15418EJ2V0DS

µ PD3768

NOTES ON HANDLING THE PACKAGES

3

4

OPERATE AND STORAGE ENVIRONMENTS

Operate in clean environments. CCD image sensors are precise optical equipment that should not be subject

to mechanical shocks. Exposure to high temperatures or humidity will affect the characteristics. So avoid

storage or usage in such conditions.

Keep in a case to protect from dust and dirt. Dew condensation may occur on CCD image sensors when the

devices are transported from a low-temperature environment to a high-temperature environment. Avoid such

rapid temperature changes.

For more details, refer to our document "Review of Quality and Reliability Handbook" (C12769E)

ELECTROSTATIC BREAKDOWN

CCD image sensor is protected against static electricity, but destruction due to static electricity is sometimes

detected. Before handling be sure to take the following protective measures.

1. Ground the tools such as soldering iron, radio cutting pliers of or pincer.

2. Install a conductive mat or on the floor or working table to prevent the generation of static electricity.

3. Either handle bare handed or use non-chargeable gloves, clothes or material.

4. Ionized air is recommended for discharge when handling CCD image sensor.

5. For the shipment of mounted substrates, use box treated for prevention of static charges.

6. Anyone who is handling CCD image sensors, mounting them on PCBs or testing or inspecting PCBs on

which CCD image sensors have been mounted must wear anti-static bands such as wrist straps and ankle

straps which are grounded via a series resistance connection of about 1 MΩ.

21

Data Sheet S15418EJ2V0DS

µ PD3768

[ MEMO ]

22

Data Sheet S15418EJ2V0DS

µ PD3768

NOTES FOR CMOS DEVICES

1

PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note:

Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and

ultimately degrade the device operation. Steps must be taken to stop generation of static electricity

as much as possible, and quickly dissipate it once, when it has occurred. Environmental control

must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using

insulators that easily build static electricity. Semiconductor devices must be stored and transported

in an anti-static container, static shielding bag or conductive material. All test and measurement

tools including work bench and floor should be grounded. The operator should be grounded using

wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need

to be taken for PW boards with semiconductor devices on it.

2

HANDLING OF UNUSED INPUT PINS FOR CMOS

Note:

No connection for CMOS device inputs can be cause of malfunction. If no connection is provided

to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence

causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels

of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused

pin should be connected to V^DDor GND with a resistor, if it is considered to have a possibility of

being an output pin. All handling related to the unused pins must be judged device by device and

related specifications governing the devices.

3

STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note:

Power-on does not necessarily define initial status of MOS device. Production process of MOS

does not define the initial operation status of the device. Immediately after the power source is

turned ON, the devices with reset function have not yet been initialized. Hence, power-on does

not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the

reset signal is received. Reset operation must be executed immediately after power-on for devices

having reset function.

23

Data Sheet S15418EJ2V0DS

µ PD3768

•

The information in this document is current as of September, 2002. The information is subject to

change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or

data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all

products and/or types are available in every country. Please check with an NEC sales representative

for availability and additional information.

•

No part of this document may be copied or reproduced in any form or by any means without prior

written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.

NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of

third parties by or arising from the use of NEC semiconductor products listed in this document or any other

liability arising from the use of such products. No license, express, implied or otherwise, is granted under any

patents, copyrights or other intellectual property rights of NEC or others.

•

Descriptions of circuits, software and other related information in this document are provided for illustrative

purposes in semiconductor product operation and application examples. The incorporation of these

circuits, software and information in the design of customer's equipment shall be done under the full

responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third

parties arising from the use of these circuits, software and information.

While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers

agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize

risks of damage to property or injury (including death) to persons arising from defects in NEC

semiconductor products, customers must incorporate sufficient safety measures in their design, such as

redundancy, fire-containment, and anti-failure features.

NEC semiconductor products are classified into the following three quality grades:

"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products

developed based on a customer-designated "quality assurance program" for a specific application. The

recommended applications of a semiconductor product depend on its quality grade, as indicated below.

Customers must check the quality grade of each semiconductor product before using it in a particular

application.

"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio

and visual equipment, home electronic appliances, machine tools, personal electronic equipment

and industrial robots

"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster

systems, anti-crime systems, safety equipment and medical equipment (not specifically designed

for life support)

"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life

support systems and medical equipment for life support, etc.

The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's

data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not

intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness

to support a given application.

(Note)

(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.

(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for

NEC (as defined above).

M8E 00. 4


型号：	UPD3768D-AZ
厂家：	NEC
描述：	CCD Sensor, 7500 Horiz pixels, 7500 Vert pixels, 1.50-2V, Rectangular, Through Hole Mount, CERAMIC, DIP-36 传感器图像传感器 CD
文件：	总24页 (文件大小：185K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

UPD3768D-AZ [NEC]

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