UPD3777CY [NEC]
5400 PIXELS x 3 COLOR CCD LINEAR IMAGE SENSOR; 5400像素× 3彩色CCD线性图像传感器
| 型号： | UPD3777CY |
| 厂家： | 
NEC |
| 描述： | 5400 PIXELS x 3 COLOR CCD LINEAR IMAGE SENSOR |
| 文件： | 总20页 (文件大小：132K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
MOS INTEGRATED CIRCUIT
µ PD3777
5400 PIXELS × 3 COLOR CCD LINEAR IMAGE SENSOR
The µ PD3777 is a color CCD (Charge Coupled Device) linear image sensor which changes optical images to electrical
signal and has the function of color separation.
The µ PD3777 has 3 rows of 5400 pixels, and each row has a double-sided readout type of charge transfer register. And
it has reset feed-through level clamp circuits, a clamp pulse generation circuit and voltage amplifiers. Therefore, it is
suitable for 600 dpi/A4 color image scanners, color facsimiles and so on.
FEATURES
• Valid photocell : 5400 pixels × 3
• Photocell’s pitch : 5.25 µ m
• Photocell size
: 5.25 × 5.25 µ m2
• Line spacing
• Color filter
: 42 µ m (8 lines) Red line - Green line, Green line - Blue line
: Primary colors (red, green and blue), pigment filter (with light resistance 107 lx•hour)
• Resolution
: 24 dot/mm A4 (210 × 297 mm) size (shorter side)
600 dpi US letter (8.5” × 11”) size (shorter side)
:
• Drive clock level : CMOS output under 5 V operation
• Data rate
: 4 MHz MAX.
: +12 V
• Power supply
• On-chip circuits : Reset feed-through level clamp circuits
:
:
Clamp pulse generation circuit
Voltage amplifiers
ORDERING INFORMATION
Part Number
Package
µ PD3777CY
CCD linear image sensor 22-pin plastic DIP (10.16 mm (400))
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. S14583EJ1V0DS00 (1st edition)
Date Published December 1999 NS CP (K)
Printed in Japan
1999
©
BLOCK DIAGRAM
φ
V
OD
2L
GND
2
GND
11
φ
1
19
17
14
CCD analog shift register
Transfer gate
φ
φ
φ
TG1
(Blue)
13
12
10
V
(Blue)
OUT
1
Photocell
(Blue)
........
........
........
21
22
1
Transfer gate
CCD analog shift register
CCD analog shift register
Transfer gate
TG2
(Green)
VOUT
2
Photocell
(Green)
(Green)
Transfer gate
CCD analog shift register
CCD analog shift register
Transfer gate
TG3
(Red)
VOUT
3
Photocell
(Red)
(Red)
Transfer gate
Clamp pulse
generator
CCD analog shift register
µ
µ
3
4
9
φ
φ
φ
2
RB
1L
µ PD3777
PIN CONFIGURATION (Top View)
CCD linear image sensor 22-pin plastic DIP (10.16 mm (400))
• µ PD3777CY
Output signal 3 (Red)
Ground
V
OUT
3
1
2
22
21
V
V
OUT
2
1
Output signal 2 (Green)
Output signal 1 (Blue)
No connection
GND
OUT
Reset gate clock
Last stage shift register clock 1
No connection
φ
3
20 NC
19
18 NC
17
RB
φ
4
V
OD
Output drain voltage
No connection
1L
NC
NC
NC
NC
5
No connection
6
φ
Last stage shift register clock 2
No connection
2L
No connection
7
16 NC
15 NC
No connection
8
No connection
Shift register clock 2
φ
2
9
14
13
12
φ
φ
φ
1
Shift register clock 1
Transfer gate clock 3
(for Red)
Transfer gate clock 1
(for Blue)
φ
10
TG1
TG2
TG3
Transfer gate clock 2
(for Green)
GND 11
Ground
PHOTOCELL STRUCTURE DIAGRAM
PHOTOCELL ARRAY STRUCTURE DIAGRAM
(Line spacing)
5.25 µm
Blue photocell array
Green photocell array
Red photocell array
2.5
µm
2.75
µ
m
8 lines
(42 µm)
5.25 µm
5.25 µm
µ
Channel stopper
8 lines
(42 µm)
Aluminum
shield
3
Data Sheet S14583EJ1V0DS00
µ PD3777
ABSOLUTE MAXIMUM RATINGS (TA = +25 °C)
Parameter
Output drain voltage
Symbol
Ratings
−0.3 to +15
−0.3 to +8
−0.3 to +8
−0.3 to +8
−25 to +60
−40 to +70
Unit
V
VOD
Shift register clock voltage
Reset gate clock voltage
Transfer gate clock voltage
Operating ambient temperature
Storage temperature
Vφ 1, Vφ 2, Vφ 1L, Vφ 2L
V
Vφ RB
V
Vφ TG1 to Vφ TG3
V
TA
°C
°C
Tstg
Caution Exposure to ABSOLUTE MAXIMUM RATINGS for extended periods may affect device reliability;
exceeding the ratings could cause permanent damage. The parameters apply independently.
RECOMMENDED OPERATING CONDITIONS (TA = +25 °C)
Parameter
Output drain voltage
Symbol
MIN.
11.4
4.5
TYP.
12.0
5.0
0
MAX.
12.6
5.5
Unit
V
VOD
Shift register clock high level
Shift register clock low level
Reset gate clock high level
Reset gate clock low level
Transfer gate clock high level
Transfer gate clock low level
Data rate
Vφ 1H, Vφ 2H, Vφ 1LH, Vφ 2LH
Vφ 1L, Vφ 2L, Vφ 1LL, Vφ 2LL
Vφ RBH
V
−0.3
4.5
+0.5
5.5
V
5.0
0
V
Vφ RBL
−0.3
4.5
+0.5
V
Note
Vφ 1H
Note
Vφ TG1H to Vφ TG3H
Vφ TG1L to Vφ TG3L
fφ RB
Vφ 1H
+0.5
4.0
V
−0.3
−
0
V
1.0
MHz
Note When Transfer gate clock high level (Vφ TG1H to Vφ TG3H) is higher than Shift register clock high level (Vφ 1H), Image
lag can increase.
4
Data Sheet S14583EJ1V0DS00
µ PD3777
ELECTRICAL CHARACTERISTICS
TA = +25 °C, VOD = 12 V, data rate (fφ RB) = 1 MHz, storage time = 5.5 ms, input signal clock = 5 Vp-p,
light source : 3200 K halogen lamp + C−500S (infrared cut filter, t = 1 mm) + HA−50 (heat absorbing filter, t = 3 mm)
Parameter
Saturation voltage
Saturation exposure
Symbol
Vsat
Test Conditions
MIN.
2.0
TYP.
2.5
MAX.
Unit
V
−
Red
SER
SEG
SEB
PRNU
ADS
DSNU
PW
0.420
0.429
0.739
6
lx•s
lx•s
lx•s
%
Green
Blue
Photo response non-uniformity
Average dark signal
VOUT = 1.0 V
20
2.0
5.0
540
1
Light shielding
Light shielding
0.2
mV
mV
mW
kΩ
Dark signal non-uniformity
Power consumption
1.5
360
0.5
Output impedance
ZO
Response
Red
RR
4.15
4.07
2.36
5.94
5.82
3.38
2.0
7.72
7.57
4.39
7.0
7.0
V/lx•s
V/lx•s
V/lx•s
%
Green
Blue
RG
RB
Image lag
Offset level Note 1
Output fall delay time Note 2
Total transfer efficiency
Register imbalance
Response peak
IL
VOUT = 1.0 V
VOS
td
4.0
5.5
V
VOUT = 1.0 V
50
ns
TTE
RI
VOUT = 1.0 V, data rate = 4 MHz
VOUT = 1.0 V
92
0
98
%
1.0
4.0
%
Red
630
540
460
1666
2500
−300
1.0
nm
Green
Blue
nm
nm
Dynamic range
DR1
DR2
RFTN
σ
Vsat/DSNU
Vsat/σ
times
times
mV
mV
Reset feed-through noise Note 1
Random noise
Light shielding
Light shielding
−1000
+500
−
−
Notes 1. Refer to TIMING CHART 2.
2. When each fall time of φ 1L and φ 2L (t2’, t1’) is the TYP. value (refer to TIMING CHART 2).
5
Data Sheet S14583EJ1V0DS00
µ PD3777
INPUT PIN CAPACITANCE (TA = +25 °C,VOD = 12 V)
Parameter
Symbol Pin name Pin No.
MIN.
TYP.
650
650
10
MAX.
Unit
pF
pF
pF
pF
pF
pF
pF
pF
Shift register clock pin capacitance 1
Shift register clock pin capacitance 2
Last stage shift register clock pin capacitance
Cφ 1
Cφ 2
Cφ L
φ 1
14
9
φ 2
φ 1L
4
φ 2L
17
3
10
Reset gate clock pin capacitance
Transfer gate clock pin capacitance
Cφ RB
Cφ TG
φ RB
φ TG1
φ TG2
φ TG3
10
13
12
10
60
60
60
6
Data Sheet S14583EJ1V0DS00
TIMING CHART 1 (for each color)
φ TG1 to
φ TG3
φ1
φ 2
φ1L
φ 2L
φ RB
Note
Note
V
OUT1 to
V
OUT
3
Optical black
(49 pixels)
Valid photocell
(5400 pixels)
Invalid photocell
(2 pixels)
Invalid photocell
(3 pixels)
Note Input the φ RB pulse continuously during this period, too.
µ
µ
TIMING CHART 2 (for each color)
t1
t2
90 %
10 %
φ
φ
1
2
90 %
10 %
t1'
t2'
90 %
10 %
φ
φ
1L
2L
90 %
10 %
t5
t6
t3
t4
90 %
10 %
φ
RB
+
_
t
d
t
d
RFTN
RFTN
V
OUT
V
OS
10 %
10 %
µ
µ
µ PD3777
φ TG1 to φ TG3, φ 1, φ 2 TIMING CHART
t8
t9
t7
90 %
φ
TG1 to TG3
φ
10 %
t10
t11
90 %
φ
φ
1
2
Symbol
t1, t2
MIN.
TYP.
50
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
0
0
−
−
−
−
−
−
−
−
t1’, t2’
t3
5
20
130
0
150
300
50
t4
t5, t6
t7
3000
0
10000
50
t8, t9
t10, t11
900
1000
φ 1, φ 2 cross points
φ
1
2
2 V or more
2 V or more
φ
φ 1L, φ 2 cross points
φ
2
2 V or more
0.5 V or more
φ
1L
φ 1, φ 2L cross points
φ
1
2 V or more
0.5 V or more
φ
2L
Remark Adjust cross points (φ 1, φ 2), (φ 1L, φ 2) and (φ 1, φ 2L) with input resistance of each pin.
9
Data Sheet S14583EJ1V0DS00
µ PD3777
DEFINITIONS OF CHARACTERISTIC ITEMS
1. Saturation voltage : Vsat
Output signal voltage at which the response linearity is lost.
2. Saturation exposure : SE
Product of intensity of illumination (lx) and storage time (s) when saturation of output voltage occurs.
3. Photo response non-uniformity : PRNU
The output signal non-uniformity of all the valid pixels when the photosensitive surface is applied with the light of
uniform illumination. This is calculated by the following formula.
∆x
PRNU (%) =
× 100
∆x : maximum of x
x
j
− x
5400
x
j
Σ
j = 1
x =
5400
x
j
: Output voltage of valid pixel number j
V
OUT
x
Register Dark
DC level
∆x
4. Average dark signal : ADS
Average output signal voltage of all the valid pixels at light shielding. This is calculated by the following formula.
5400
dj
Σ
j = 1
ADS (mV) =
5400
dj : Dark signal of valid pixel number j
10
Data Sheet S14583EJ1V0DS00
µ PD3777
5. Dark signal non-uniformity : DSNU
Absolute maximum of the difference between ADS and voltage of the highest or lowest output pixel of all the valid
pixels at light shielding. This is calculated by the following formula.
DSNU (mV) : maximum of d
j
− ADS j = 1 to 5400
dj
: Dark signal of valid pixel number j
VOUT
ADS
Register Dark
DC level
DSNU
6. Output impedance : ZO
Impedance of the output pins viewed from outside.
7. Response : R
Output voltage divided by exposure (lx•s).
Note that the response varies with a light source (spectral characteristic).
8. Image lag : IL
The rate between the last output voltage and the next one after read out the data of a line.
φ
TG
Light
ON
OFF
VOUT
V1
VOUT
V1
IL (%) =
× 100
VOUT
9. Register imbalance : RI
The rate of the difference between the averages of the output voltage of Odd and Even pixels, against the average
output voltage of all the valid pixels.
n
2
2
n
∑
(V2j – 1 – V2j)
j = 1
RI (%) =
× 100
n
1
n
∑
V
j
j = 1
n : Number of valid pixels
V
j
: Output voltage of each pixel
11
Data Sheet S14583EJ1V0DS00
µ PD3777
10. Random noise : σ
Random noise σ is defined as the standard deviation of a valid pixel output signal with 100 times (= 100 lines)
data sampling at dark (light shielding).
100
(V
i
– V)2
Σ
100
1
i = 1
, V =
Vi
σ
(mV) =
100 Σ
100
i = 1
Vi : A valid pixel output signal among all of the valid pixels for each color
V
V
1
2
VOUT
line 1
line 2
V
100
line 100
This is measured by the DC level sampling of only the signal level, not by CDS (Correlated Double Sampling).
12
Data Sheet S14583EJ1V0DS00
µ PD3777
STANDARD CHARACTERISTIC CURVES (Nominal)
DARK OUTPUT TEMPERATURE
CHARACTERISTIC
STORAGE TIME OUTPUT VOLTAGE
CHARACTERISTIC (T = +25 °C)
A
8
2
1
4
2
1
0.5
0.25
0.2
0.1
0.1
0
10
20
30
40
50
1
5
10
Operating Ambient Temperature T
A
(°C)
Storage Time (ms)
TOTAL SPECTRAL RESPONSE CHARACTERISTICS
(without infrared cut filter and heat absorbing filter) (T
A
= +25 °C)
100
80
R
B
G
60
40
20
G
B
0
400
500
600
700
800
Wavelength (nm)
13
Data Sheet S14583EJ1V0DS00
µ PD3777
APPLICATION CIRCUIT EXAMPLE
+5 V
+12 V
10 Ω
+
+
µ
PD3777
10
µ
F/16 V 0.1
µ
F
0.1 µF 47 µF/25 V
1
2
3
22
21
20
19
18
+5 V
B3
V
OUT
3
V
OUT
2
1
B2
B1
GND
V
OUT
+
47 Ω
φ
φ
RB
1L
NC
φ
RB
0.1 µF 10 µF/16 V
150 Ω
4
5
6
V
OD
NC
NC
NC
NC
150 Ω
17
16
15
14
13
12
φ
2L
NC
NC
7
8
NC
4.7 Ω
10 Ω
4.7 Ω
10 Ω
10 Ω
9
φ
φ
2
φ1
φ
φ
1
φ
2
10
TG3
φ
φ
TG1
TG2
TG
11
GND
Remark The inverters shown in the above application circuit example are the 74HC04 (data rate < 2 MHz) or the
74AC04 (data rate: 2 to 4 MHz).
B1 to B3 EQUIVALENT CIRCUIT
12 V
+
µ
47 F/25 V
100 Ω
100 Ω
CCD
2SC945
VOUT
2 kΩ
14
Data Sheet S14583EJ1V0DS00
µ PD3777
PACKAGE DRAWING
CCD LINEAR IMAGE SENSOR 22-PIN PLASTIC DIP (10.16 mm (400))
(Unit : mm)
1bit
0.5±0.3
37.5
44.0±0.3
10.16
(1.79)
1
2.55±0.2
(5.42)
1.02±0.15
0.46±0.1
2.54
4.21±0.5
4.39±0.4
25.4
Name
Dimensions
Refractive index
2
42.9 × 8.35 × 0.7
Plastic cap
1.5
1 The bottom of the package
The surface of the chip
2 The thickness of the cap over the chip
22C-1CCD-PKG6-1
15
Data Sheet S14583EJ1V0DS00
µ PD3777
RECOMMENDED SOLDERING CONDITIONS
When soldering this product, it is highly recommended to observe the conditions as shown below.
If other soldering processes are used, or if the soldering is performed under different conditions, please make sure to
consult with our sales offices.
For more details, refer to our document “Semiconductor Device Mounting Technology Manual” (C10535E).
Type of Through-hole Device
µ PD3777CY : CCD linear image sensor 22-pin plastic DIP (10.16 mm (400))
Process
Conditions
Partial heating method
Pin temperature : 300 °C or below, Heat time : 3 seconds or less (per pin)
Caution During assembly care should be taken to prevent solder or flux from contacting the plastic cap. The
optical characteristics could be degraded by such contact.
16
Data Sheet S14583EJ1V0DS00
µ PD3777
[MEMO]
17
Data Sheet S14583EJ1V0DS00
µ PD3777
NOTES ON CLEANING THE PLASTIC CAP
1 CLEANING THE PLASTIC CAP
Care should be taken when cleaning the surface to prevent scratches.
The optical characteristics of the CCD will be degraded if the cap is scratched during
cleaning.
We recommend cleaning the cap with a soft cloth moistened with one of the recommended
solvents below. Excessive pressure should not be applied to the cap during cleaning. If the
cap requires multiple cleanings it is recommended that a clean surface or cloth be used.
2 RECOMMENDED SOLVENTS
The following are the recommended solvents for cleaning the CCD plastic cap. Use of
solvents other than these could result in optical or physical degradation in the plastic cap.
Please consult your sales office when considering an alternative solvent.
Solvents
Symbol
Ethyl Alcohol
EtOH
MeOH
IPA
Methyl Alcohol
Isopropyl Alcohol
N-methyl Pyrrolidone
NMP
18
Data Sheet S14583EJ1V0DS00
µ PD3777
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
19
Data Sheet S14583EJ1V0DS00
µ PD3777
[MEMO]
• The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
• No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
• NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
• Descriptions of circuits, software, and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these circuits,
software, and information in the design of the customer's equipment shall be done under the full responsibility
of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third
parties arising from the use of these circuits, software, and information.
• While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
• NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
M7 98. 8
相关型号：
UPD3789CY
CCD Sensor, 5348 Horiz pixels, 5348 Vert pixels, 2-2.50V, Rectangular, Through Hole Mount, 10.16 MM, PLASTIC, DIP-32
NEC
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