M6MGB166S4BWG-85 [MITSUBISHI]
Memory Circuit, 1MX16, CMOS, PBGA72, 0.80 MM PITCH, CSP-72;
| 型号： | M6MGB166S4BWG-85 |
| 厂家： | 
Mitsubishi Group |
| 描述： | Memory Circuit, 1MX16, CMOS, PBGA72, 0.80 MM PITCH, CSP-72 静态存储器 内存集成电路 |
| 文件： | 总30页 (文件大小：259K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MITSUBISHI LSIs
M6MGB/T166S4BWG
16,777,216-BIT (1,048,576 -WORD BY 16-BIT ) CMOS
3.3V-ONLY FLASH MEMORY &
4,194,304-BIT (262,144-WORD BY 16-BIT) CMOS SRAM
Stacked-CSP (Chip Scale Package)
DESCRIPTION
FEATURES
The MITSUBISHI M6MGB/T166S4BWG is a Stacked Chip
Scale Package (S-CSP) that contents 16M-bits flash
memory and 4M-bits Static RAM in a 72-pin S-CSP.
• Access time
Flash Memory
SRAM
90ns (Max.)
85ns (Max.)
Vcc=2.7 ~ 3.6V
• Supply voltage
• Ambient temperature
W version
16M-bits Flash memory is a 1,048,576 words, 3.3V-only,
and high performance non-volatile memory fabricated by
CMOS technology for the peripheral circuit and
DINOR(DIvided bit-line NOR) architecture for the memory
cell.
Ta=-20 ~ 85°C
• Package : 72-pin S-CSP , 0.8mm ball pitch
4M-bits SRAM is a 262,144words unsynchronous SRAM
fabricated by silicon-gate CMOS technology.
APPLICATION
Mobile communication products
M6MGB/T166S4BWG is suitable for the application of the
mobile-communication-system to reduce both the mount
space and weight .
PIN CONFIGURATION (TOP VIEW)
INDEX
H
G
F
E
D
C
B
A
NC
NC
1
2
F-VCC
:Vcc for Flash
NC
DU
A5
NC
S-VCC
F-GND
GND
:Vcc for SRAM
:GND for Flash
GND
F-A18 S-LB#
F-A17 S-UB#
F-WE#
F-
F-WP#
A16 DU
A8 A11
A10 A15
A9 A14
3
:Flash/SRAM common GND
F-RP# RY/BY#
DU
4
A0-A16
:Flash/SRAM
common Address
F-A19
A7
S-OE#
DU DU
A4
5
:Address for Flash
:Address for SRAM
F-A17-F-A19
S-A17
DQ11
S-A17
A0
A6 DU
DU
6
DQ0-DQ15
:Flash/SRAM
common Data I/O
F-CE#
F-GND
F-OE#
DU
NC
NC
DQ12
DQ13
DQ15
A3
A13
DQ9 DU
7
F-CE#
S-CE1#
S-CE2
F-OE#
S-OE#
F-WE#
S-WE#
F-WP#
F-RP#
:Flash Chip Enable
:SRAM Chip Enable
:SRAM Chip Enable
S-
CE2
DQ10
S-WE#
A2 DQ8
DQ6
A12
8
S-VCC
F-VCC
DQ14
A1
F-GND
DQ0 DQ2
DQ1 DQ3
DQ4
9
:Flash Output Enable
:SRAM Output Enable
S-
CE1#
DU
NC
NC
DQ5 DQ7
10
11
12
:Flash Write Enable
:SRAM Write Enable
:Flash Write Protect
:Flash Reset Power Down
:Flash Ready /Busy
:SRAM Lower Byte
:SRAM Upper Byte
F-RY/BY#
S-LB#
S-UB#
8.0 mm
NC:Non Connection
DU:Don't Use (Note: Should be open)
1
Apr. 1999 , Rev.1.7
MITSUBISHI LSIs
M6MGB/T166S4BWG
16,777,216-BIT (1,048,576 -WORD BY 16-BIT ) CMOS
3.3V-ONLY FLASH MEMORY &
4,194,304-BIT (262,144-WORD BY 16-BIT) CMOS SRAM
Stacked-CSP (Chip Scale Package)
BLOCK DIAGRAM
16Mb Flash Memory
F-A19
128 WORD PAGE BUFFER
F-A18
F-A17
A16
Main Block
32KW
F-VCC(3.3V)
A15
A14
A13
A12
A11
A10
A9
28
F-GND/GND
(0V)
X-DECODER
Main Block
32KW
16KW
Parameter Block7
Parameter Block6
Parameter Block5
Parameter Block4
Parameter Block3
Parameter Block2
ADDRESS
INPUTS
16KW
16KW
16KW
16KW
16KW
16KW
16KW
A8
A7
Parameter Block1
Boot Block
A6
A5
A4
A3
A2
A1
A0
Y-GATE / SENSE AMP.
MULTIPLEXER
Y-DECODER
STATUS / ID REGISTER
CHIP ENABLE INPUT F-CE#
OUTPUT ENABLE INPUT
F-OE#
WRITE ENABLE INPUT
F-WE#
F-WP#
CUI
WSM
WRITE PROTECT INPUT
INPUT/OUTPUT
BUFFERS
RESET/POWER DOWN INPUT
F-RP#
READY/BUSY OUTPUT F-RY/BY#
DQ15 DQ14DQ13DQ12
DQ3DQ2DQ1DQ0
4Mb SRAM
DATA INPUTS/OUTPUTS
A0
A1
DQ0
262144 WORD x
16 BITS
DQ7
DQ 8
A16
S-A17
15
DQ
S-CE1#
CLOCK
GENERATOR
S-CE2
S-LB#
S-UB#
S-VCC
GND
S-WE#
S-OE#
2
Apr. 1999 , Rev.1.7
MITSUBISHI LSIs
M6MGB/T166S4BWG
16,777,216-BIT (1,048,576 -WORD BY 16-BIT ) CMOS
3.3V-ONLY FLASH MEMORY &
4,194,304-BIT (262,144-WORD BY 16-BIT) CMOS SRAM
Stacked-CSP (Chip Scale Package)
1. Flash Memory
DESCRIPTION
The Flash Memory of M6MGB/T166S4BWG is 3.3V-only high speed 16,777,216-bit CMOS boot block Flash Memories with alternating
BGO (Back Ground Operation) feature. The BGO feature of the device allows Program or Erase operations to be performed in one bank
while the device simultaneously allows Read operations to be performed on the other bank. This BGO feature is suitable for mobile and
personal computing, and communication products. The Flash Memory of M6MGB/T166S4BWG is fabricated by CMOS technology for the
peripheral circuits and DINOR(Divided bit line NOR) architecture for the memory cells.
FEATURES
Boot Block
........................
........................
.................................
.............................
Organization
1048,576 word x 16bit
M6MGB166S4BWG
M6MGT166S4BWG
Bottom Boot
Top Boot
Other Functions
Supply voltage ................................
VCC = 2.7~3.6V
90ns (Max.)
Soft Ware Command Control
Selective Block Lock
Erase Suspend/Resume
Program Suspend/Resume
Status Register Read
..............................
Access time
Power Dissipation
.................................
Read
54 mW (Max. at 5MHz)
0.33µW (typ.)
Alternating Back Ground Program/Erase Operation
Between Bank(I) and Bank(II)
..........
(After Automatic Power saving)
Program/Erase
Standby
.................................
126 mW (Max.)
0.33µW (typ.)
.................................
.......................
Deep power down mode
Auto program for Bank(I)
Program Time
Program Unit
0.33µW (typ.)
.................................
4ms (typ.)
.........................
.........................
(Byte Program)
(Page Program)
1word
128word
Auto program for Bank(II)
.................................
.................................
Program Time
Program Unit
Auto Erase
Erase time
4ms (typ.)
128word
.................................
.....................
40 ms (typ.)
Erase Unit
Bank(I) Boot Block
Parameter Block
Bank(II) Main Block
16Kword x 1
16Kword x 7
32Kword x 28
..............
......................
.........................................
Program/Erase cycles
100Kcycles
3
Apr. 1999 , Rev.1.7
MITSUBISHI LSIs
M6MGB/T166S4BWG
16,777,216-BIT (1,048,576 -WORD BY 16-BIT ) CMOS
3.3V-ONLY FLASH MEMORY &
4,194,304-BIT (262,144-WORD BY 16-BIT) CMOS SRAM
Stacked-CSP (Chip Scale Package)
FUNCTION
Deep Power-Down
The Flash Memory of M6MGB/T166S4BWG includes on-chip
program/erase control circuitry. The Write State Machine (WSM)
controls block erase and byte/page program operations.
Operational modes are selected by the commands written to the
Command User Interface (CUI). The Status Register indicates the
status of the WSM and when the WSM successfully completes the
desired program or block erase operation.
When F-RP# is at VIL, the device is in the deep powerdown
mode and its power consumption is substantially low. During
read modes, the memory is deselected and the data
input/output are in a high-impedance(High-Z) state. After
return from powerdown, the CUI is reset to Read Array , and
the Status Register is cleared to value 80H.
During block erase or program modes, F-RP# low will abort
either operation. Memory array data of the block being altered
become invalid.
A Deep Powerdown mode is enabled when the F-RP# pin is at
GND, minimizing power consumption.
Automatic Power-Saving (APS)
Read
The Automatic Power-Saving minimizes the power
consumption during read mode. The device automatically
turns to this mode when any addresses or F-CE# isn't
changed more than 200ns after the last alternation. The
power consumption becomes the same as the stand-by
mode. While in this mode, the output data is latched and can
be read out. New data is read out correctly when addresses
are changed.
The Flash Memory of M6MGB/T166S4BWG has three read
modes, which accesses to the memory array, the Device Identifier
and the Status Register. The appropriate read command are
required to be written to the CUI. Upon initial device powerup or
after exit from deep powerdown, the Flash Memory automatically
resets to read array mode. In the read array mode, low level input
to F-CE# and F-OE#, high level input to F-WE# and F-RP#, and
address signals to the address inputs (F-A19-F-A17,A16-A0)
output the data of the addressed location to the data input/output (
D15-D0).
Write
Writes to the CUI enables reading of memory array data, device
identifiers and reading and clearing of the Status Register. They
also enable block erase and program. The CUI is written by
bringing F-WE# to low level, while F-CE# is at low level and F-OE#
is at high level. Address and data are latched on the earlier rising
edge of F-WE# and F-CE#. Standard micro-processor write
timings are used.
Alternating Background Operation (BGO)
The Flash Memory of M6MGB/T166S4BWG allows to read array
from one bank while the other bank operates in software
command write cycling or the erasing / programming operation in
the background. Read array operation with the other bank in BGO
is performed by changing the bank address without any additional
command. When the bank address points the bank in software
command write cycling or the erasing / programming operation,
the data is read out from the status register. The access time with
BGO is the same as the normal read operation.
Output Disable
When F-OE# is at VIH, output from the devices is disabled. Data
input/output are in a high-impedance(High-Z) state.
Standby
When F-CE# is at VIH, the device is in the standby mode and
its power consumption is reduced. Data input/output are in a
high-impedance(High-Z) state. If the memory is deselected
during block erase or program, the internal control circuits
remain active and the device consume normal active power
until the operation completes.
4
Apr. 1999 , Rev.1.7
MITSUBISHI LSIs
M6MGB/T166S4BWG
16,777,216-BIT (1,048,576 -WORD BY 16-BIT ) CMOS
3.3V-ONLY FLASH MEMORY &
4,194,304-BIT (262,144-WORD BY 16-BIT) CMOS SRAM
Stacked-CSP (Chip Scale Package)
C)Single Data Load to Page Buffer (74H)
/ Page Buffer to Flash (0EH/D0H)
SOFTWARE COMMAND DEFINITIONS
The device operations are selected by writing specific software
command into the Command User Interface.
Single data load to the page buffer is performed by writing 74H
followed by a second write specifying the column address and
data. Distinct data up to 128word can be loaded to the page
buffer by this two-command sequence. On the other hand, all of
the loaded data to the page buffer is programed simultaneously
by writing Page Buffer to Flash command of 0EH followed by the
confirm command of D0H. After completion of programing the
data on the page buffer is cleared automatically.
Read Array Command (FFH)
The device is in Read Array mode on initial device power up and
after exit from deep powerdown, or by writing FFH to the
Command User Interface. After starting the internal operation the
device is set to the read status register mode automatically.
This command is valid for only Bank(I) alike Word Program.
Read Device Identifier Command (90H)
Clear Page Buffer Command (55H)
It can normally read device identifier codes when Read Device
Identifier Code Command(90H) is written to the command latch.
Following the command write, the manufacturer code and the
device code can be read from address 00000H and 00001H,
respectively.
Loaded data to the page buffer is cleared by writing the Clear
Page Buffer command of 55H followed by the Confirm command
of D0H. This command is valid for clearing data loaded by Single
Data Load to Page Buffer command.
Suspend/Resume Command (B0H/D0H)
Read Status Register Command (70H)
Writing the Suspend command of B0H during block erase
operation interrupts the block erase operation and allows read out
from another block of memory. Writing the Suspend command of
B0H during program operation interrupts the program operation
and allows read out from another block of memory. The Bank
address is required when writing the Suspend/Resume Command.
The device continues to output Status Register data when read,
after the Suspend command is written to it. Polling the WSM
Status and Suspend Status bits will determine when the erase
operation or program operation has been suspended. At this
point, writing of the Read Array command to the CUI enables
reading data from blocks other than that which is suspended.
When the Resume command of D0H is written to the CUI,
the WSM will continue with the erase or program processes.
The Status Register is read after writing the Read Status Register
command of 70H to the Command User Interface. Also, after
starting the internal operation the device is set to the Read Status
Register mode automatically.
The contents of Status Register are latched on the later falling
edge of F-OE# or F-CE#. So F-CE# or F-OE# must be toggled
every status read.
Clear Status Register Command (50H)
The Erase Status, Program Status and Block Status bits are set to
"1"s by the Write State Machine and can only be reset by the Clear
Status Register command of 50H. These bits indicates various
failure conditions.
DATA PROTECTION
The Flash Memory of M6MGB/T166S4BWG provides selectable
block locking of memory blocks. Each block has an associated
nonvolatile lock-bit which determines the lock status of the block.
In addition, the Flash Memory has a master Write Protect pin
(F-WP#) which prevents any modifications to memory blocks
whose lock-bits are set to "0", when F-WP# is low. When F-WP#
is high, all blocks can be programmed or erased regardless of
the state of the lock-bits, and the lock-bits are cleared to "1" by
erase. See the BLOCK LOCKING table on P.9 for details.
Block Erase / Confirm Command (20H/D0H)
Automated block erase is initiated by writing the Block Erase
command of 20H followed by the Confirm command of D0H. An
address within the block to be erased is required. The WSM
executes iterative erase pulse application and erase verify
operation.
Program Commands
A)Word Program (40H)
Power Supply Voltage
Word program is executed by a two-command sequence. The
Word Program Setup command of 40H is written to the
Command Interface, followed by a second write specifying the
address and data to be written. The WSM controls the program
pulse application and verify operation. The Word Program
Command is Valid for only Bank(I).
When the power supply voltage (F-VCC) is less than VLKO, Low
VCC Lock-Out voltage, the device is set to the Read-only mode.
Regarding DC electrical characteristics of VLKO, see P.10.
A delay time of 2µs is required before any device operation is
initiated. The delay time is measured from the time F-Vcc reaches
F-Vccmin (2.7V).
During power up, F-RP#=GND is recommended. Falling in Busy
status is not recommended for possibility of damaging the device.
B)Page Program for Data Blocks (41H)
Page Program for Bank(I) and Bank(II) allows fast programming of
128words of data. Writing of 41H initiates the page program
operation for the Data area. From 2nd cycle to 129th cycle, write
data must be serially inputted. Address A6-A0 have to be
incremented from 00H to 7FH. After completion of data loading, the
WSM controls the program pulse application and verify operation.
MEMORY ORGANIZATION
The Flash Memory of M6MGB/T166S4BWG has one 16Kword
boot block, seven 16Kword parameter blocks, for Bank(I) and
twenty-eight 32Kword main blocks for Bank(II). A block is erased
independently of other blocks in the array.
5
Apr. 1999 , Rev.1.7
MITSUBISHI LSIs
M6MGB/T166S4BWG
16,777,216-BIT (1,048,576 -WORD BY 16-BIT ) CMOS
3.3V-ONLY FLASH MEMORY &
4,194,304-BIT (262,144-WORD BY 16-BIT) CMOS SRAM
Stacked-CSP (Chip Scale Package)
MEMORY ORGANIZATION
F8000H-FFFFFH
F0000H-F7FFFH
E8000H-EFFFFH
E0000H-E7FFFH
D8000H-DFFFFH
D0000H-D7FFFH
C8000H-CFFFFH
C0000H-C7FFFH
B8000H-BFFFFH
B0000H-B7FFFH
A8000H-AFFFFH
A0000H-A7FFFH
98000H-9FFFFH
90000H-97FFFH
FC000H-FFFFFH
16Kword BOOT BLOCK 35
32Kword MAIN BLOCK 35
32Kword MAIN BLOCK 34
32Kword MAIN BLOCK 33
32Kword MAIN BLOCK 32
32Kword MAIN BLOCK 31
32Kword MAIN BLOCK 30
32Kword MAIN BLOCK 29
32Kword MAIN BLOCK 28
32Kword MAIN BLOCK 27
32Kword MAIN BLOCK 26
32Kword MAIN BLOCK 25
32Kword MAIN BLOCK 24
32Kword MAIN BLOCK 23
32Kword MAIN BLOCK 22
32Kword MAIN BLOCK 21
F8000H-FBFFFH
F4000H-F7FFFH
F0000H-F3FFFH
EC000H-EFFFFH
E8000H-EBFFFH
E4000H-E7FFFH
E0000H-E3FFFH
D8000H-DFFFFH
D0000H-D7FFFH
C8000H-CFFFFH
C0000H-C7FFFH
B8000H-BFFFFH
B0000H-B7FFFH
16Kword PARAMETER BLOCK 34
16Kword PARAMETER BLOCK 33
16Kword PARAMETER BLOCK 32
16Kword PARAMETER BLOCK 31
16Kword PARAMETER BLOCK 30
16Kword PARAMETER BLOCK 29
16Kword PARAMETER BLOCK 28
32Kword MAIN BLOCK 27
32Kword MAIN BLOCK 26
32Kword MAIN BLOCK 25
32Kword MAIN BLOCK 24
32Kword MAIN BLOCK 23
32Kword MAIN BLOCK 22
88000H-8FFFFH
80000H-87FFFH
78000H-7FFFFH
70000H-77FFFH
68000H-6FFFFH
60000H-67FFFH
58000H-5FFFFH
50000H-57FFFH
48000H-4FFFFH
A8000H-AFFFFH
A0000H-A7FFFH
98000H-9FFFFH
90000H-97FFFH
88000H-8FFFFH
80000H-87FFFH
78000H-7FFFFH
70000H-77FFFH
68000H-6FFFFH
32Kword MAIN BLOCK 21
32Kword MAIN BLOCK 20
32Kword MAIN BLOCK 19
32Kword MAIN BLOCK 18
32Kword MAIN BLOCK 17
32Kword MAIN BLOCK 16
32Kword MAIN BLOCK 15
32Kword MAIN BLOCK 14
32Kword MAIN BLOCK 13
32Kword MAIN BLOCK 12
32Kword MAIN BLOCK 11
32Kword MAIN BLOCK 10
32Kword MAIN BLOCK 20
32Kword MAIN BLOCK 19
32Kword MAIN BLOCK 18
32Kword MAIN BLOCK 17
32Kword MAIN BLOCK 16
32Kword MAIN BLOCK 15
32Kword MAIN BLOCK 14
32Kword MAIN BLOCK 13
40000H-47FFFH
38000H-3FFFFH
60000H-67FFFH
58000H-5FFFFH
32Kword MAIN BLOCK 12
32Kword MAIN BLOCK 11
32Kword MAIN BLOCK 10
30000H-37FFFH
28000H-2FFFFH
20000H-27FFFH
1C000H-1FFFFH
50000H-57FFFH
48000H-4FFFFH
40000H-47FFFH
38000H-3FFFFH
32Kword MAIN BLOCK
32Kword MAIN BLOCK
9
8
32Kword MAIN BLOCK
32Kword MAIN BLOCK
32Kword MAIN BLOCK
32Kword MAIN BLOCK
32Kword MAIN BLOCK
9
8
7
6
5
16Kword PARAMETER BLOCK
16Kword PARAMETER BLOCK
7
6
18000H-1BFFFH
14000H-17FFFH
10000H-13FFFH
0C000H-0FFFFH
08000H-0BFFFH
04000H-07FFFH
30000H-37FFFH
28000H-2FFFFH
20000H-27FFFH
18000H-1FFFFH
10000H-17FFFH
08000H-0FFFFH
16Kword PARAMETER BLOCK
16Kword PARAMETER BLOCK
16Kword PARAMETER BLOCK
16Kword PARAMETER BLOCK
16Kword PARAMETER BLOCK
5
4
3
2
1
32Kword MAIN BLOCK
32Kword MAIN BLOCK
32Kword MAIN BLOCK
32Kword MAIN BLOCK
4
3
2
1
00000H-03FFFH
00000H-07FFFH
32Kword MAIN BLOCK
0
16Kword BOOT BLOCK 0
F-A19-F-A17,A16-A0
(Word Mode)
F-A19-F-A17,A16-A0
(Word Mode)
Flash Memory of M6MGT166S4BWG
Memory Map
Flash Memory of M6MGB166S4BWG
Memory Map
6
Apr. 1999 , Rev.1.7
MITSUBISHI LSIs
M6MGB/T166S4BWG
16,777,216-BIT (1,048,576 -WORD BY 16-BIT ) CMOS
3.3V-ONLY FLASH MEMORY &
4,194,304-BIT (262,144-WORD BY 16-BIT) CMOS SRAM
Stacked-CSP (Chip Scale Package)
BUS OPERATIONS
Bus Operations for Word-Wide Mode
Pins
F-WE#
F-CE#
Mode
F-RP#
DQ0-15
F-RY/BY#
F-OE#
VIL
Array
VIL
VIH
VIH
VIH
VIH
VIH
X
VIH
VIH
VIH
VIH
VIH
VIH
VIH
VIH
VIH
VIL
Data out
VOH (Hi-Z)
1)
Read
Status Register
Lock Bit Status
Identifier Code
VIL
VIL
VIL
VIL
Status Register Data
Lock Bit Data (DQ6)
X
X
VOH (Hi-Z)
VIL
VIL
VIH
VIL
VIL
VIL
X
VIL
VIH
Identifier Code
Hi-Z
Output disable
Stand by
X
2)
X
VIH
VIH
VIH
X
Hi-Z
X
Program
VIL
VIL
VIL
X
Command/Data in
Command
Command
Hi-Z
X
X
X
Write
Erase
Others
VOH (Hi-Z)
Deep Power Down
1) X at F-RY/BY# is VOL or VOH(Hi-Z).
*The F-RY/BY# is an open drain output pin and indicates status of the internal WSM. When low,it indicates that the WSM is Busy performing an operation.
A pull-up resistor of 10K-100K Ohms is required to allow the F-RY/BY# signal to transition high indicating a Ready WSM condition.
2) X can be VIH or VIL for control pins.
7
Apr. 1999 , Rev.1.7
MITSUBISHI LSIs
M6MGB/T166S4BWG
16,777,216-BIT (1,048,576 -WORD BY 16-BIT ) CMOS
3.3V-ONLY FLASH MEMORY &
4,194,304-BIT (262,144-WORD BY 16-BIT) CMOS SRAM
Stacked-CSP (Chip Scale Package)
SOFTWARE COMMAND DEFINITION
Command List
3rd ~129th bus cycles (Word Mode)
Data
2nd bus cycle
Address
1st bus cycle
Address
Command
Data
(DQ15-0)
Data
Mode
Address
Mode
Mode
(DQ15-0)
(DQ15-0)
Read Array
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
X
X
FFH
90H
70H
50H
55H
40H
41H
74H
0EH
20H
B0H
D0H
71H
77H
A7H
2)
2)
Device Identifier
Read Status Register
Clear Status Register
Clear Page Buffer
Read
Read
IA
ID
3)
4)
Bank
X
X
Bank
SRD
1)
Write
Write
Write
Write
Write
Write
X
D0H
WD
5)
5)
6)
6)
7)
Bank(I)
Word Program
WA
WA0
7)
7)
7)
7)
Page Program
Single Data Load to Page Buffer
Page Buffer to Flash
Bank
Bank(I)
WD0
WD
Write
WAn
WDn
5)
5)
WA
5)
8)
1)
1)
5)
D0H
D0H
Bank(I)
Bank
Bank
WA
9)
Block Erase / Confirm
Suspend
BA
Resume
Bank
X
Bank
X
10)
1)
Read Lock Bit Status
Lock Bit Program / Confirm
Erase All Unlocked Blocks
BA
Read
Write
Write
DQ6
D0H
D0H
Write
Write
BA
X
1)
1) In the word-wide version, upper byte data (DQ8-DQ15) is ignored.
2) IA=ID Code Address : A0=VIL (Manufacturer's Code) : A0=VIH (Device Code), ID=ID Code
3) Bank = Bank Address (Bank(I) or Bank(II)) : F-A19-F-A17.
4) SRD = Status Register Data
5) Word Program, Single Data Load and Page Buffer to Flash Command is valid for only Bank(I).
6) WA = Write Address,WD = Write Data
7) WA0,WAn=Write Address, WD0,WDn=Write Data.
Write Address and Write Data must be provided sequentially from 00H to 7FH for A6-A0. Page size is 128word (128word x 16bit).
and also F-A19-F-A17,A16-A7(Block Address, Page Address) must be valid.
8) WA = Write Address : Upper page address, F-A19-F-A17,A16-A7(Block Address, Page Address) must be valid.
9) BA = Block Address : BA = Block Address : F-A19-F-A17,A16-A14(Bank1) F-A19-F-A17,A16-A15(Bank2)
10) DQ6 provides Block Lock Status, DQ6 = 1 : Block Unlock, DQ6 = 0 : Block Locked.
8
Apr. 1999 , Rev.1.7
MITSUBISHI LSIs
M6MGB/T166S4BWG
16,777,216-BIT (1,048,576 -WORD BY 16-BIT ) CMOS
3.3V-ONLY FLASH MEMORY &
4,194,304-BIT (262,144-WORD BY 16-BIT) CMOS SRAM
Stacked-CSP (Chip Scale Package)
BLOCK LOCKING
Write Protection Provided
Lock
Bit
BANK(I)
BANK(II)
Data
Note
Lock Bit
F-WP#
X
F-RP#
VIL
(Internally)
Boot
Parameter
Locked
Deep Power Down Mode
X
0
1
X
Locked
Locked
Locked
Locked
Locked
Locked
Locked
Locked
Locked
VIL
VIH
Unlocked Unlocked
VIH
All Blocks Unlocked
Unlocked Unlocked Unlocked Unlocked
1) DQ6 provides Lock Status of each block after writing the Read Lock Status command (71H).
F-WP# pins must not be switched during performing Erase / Write operations or WSM Busy (WSMS = 0).
2) Erase/Write command for locked blocks is aborted. At this time read mode is not array read mode but status read mode and
00B0H is read. Please issue Clear Status Register command plus Read Array command to change the mode from status read mode
to array read mode.
STATUS REGISTER
Definition
Symbol
Status
"1"
Ready
Suspended
Error
"0"
Busy
Write State Machine Status
SR.7 (DQ7)
SR.6 (DQ6) Suspend Status
SR.5 (DQ5) Erase Status
Operation in Progress / Completed
Successful
Program Status
SR.4 (DQ4)
SR.3 (DQ3)
SR.2 (DQ2)
SR.1 (DQ1)
SR.0 (DQ0)
Error
Error
Successful
Successful
Block Status after Program
Reserved
-
-
-
-
-
-
Reserved
Reserved
*The F-RY/BY# is an open drain output pin and indicates status of the internal WSM. When low,it indicates that the WSM is Busy performing an operation.
A pull-up resistor of 10K-100K Ohms is required to allow the F-RY/BY# signal to transition high indicating a Ready WSM condition.
*DQ3 indicates the block status after the page programming, word programming and page buffer to flash. When DQ3 is "1", the page has the over-programed
cell . If over-program occurs, the device is block fail. However if DQ3 is "1", please try the block erase to the block. The block may revive.
9
Apr. 1999 , Rev.1.7
MITSUBISHI LSIs
M6MGB/T166S4BWG
16,777,216-BIT (1,048,576 -WORD BY 16-BIT ) CMOS
3.3V-ONLY FLASH MEMORY &
4,194,304-BIT (262,144-WORD BY 16-BIT) CMOS SRAM
Stacked-CSP (Chip Scale Package)
DEVICE IDENTIFIER CODE
Pins
Hex. Data
1CH
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
A0
Code
VIL
VIH
VIH
0
1
1
0
0
0
0
1
1
1
0
0
1
0
0
1
0
0
0
0
0
0
0
1
Manufacturer Code
Device Code (-T166S4BWG)
A0H
A1H
Device Code (-B166S4BWG)
The upper data(D15-8) is "0".
ABSOLUTE MAXIMUM RATINGS
Symbol
F-Vcc
VI1
Conditions
Parameter
Min
Max
Unit
V
Flash Vcc voltage
-0.2
-0.6
4.6
4.6
With respect to Ground
1)
All input or output voltage
V
Ta
Ambient temperature
-20
-50
-65
85
95
°C
°C
°C
mA
Tbs
Temperature under bias
Tstg
Storage temperature
125
100
I OUT
Output short circuit current
1) Minimum DC voltage is -0.5V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <20ns. Maximum DC voltage
on input/output pins is F-VCC+0.5V which, during transitions, may overshoot to F-VCC+1.5V for periods <20ns.
CAPACITANCE
Limits
Typ
Parameter
Symbol
Test conditions
Unit
Min
Max
8
pF
pF
CIN
COUT
Input capacitance (Address, Control Pins)
Output capacitance
Ta = 25°C, f = 1MHz, Vin = Vout = 0V
12
Note: The value of common pins to Flash Memory is the sum of Flash Memory and SRAM.
DC ELECTRICAL CHARACTERISTICS (Ta = -20~ 85°C, F-Vcc = 2.7V ~ 3.6V, unless otherwise noted)
Limits
Typ1)
Symbol
Parameter
Test conditions
0V≤VIN≤F-VCC
Unit
Min
Max
±2.0
±11
ILI
Input leakage current
Output leakage current
µA
µA
µA
ILO
0V≤VOUT≤F-VCC
ISB1
50
200
F-VCC = 3.6V, VIN=VIL/VIH, F-CE# = F-RP# =F-WP# = VIH
F-VCC standby current
F-VCC = 3.6V, VIN=GND or F-VCC,
F-CE# = F-RP# = F-WP# = F-VCC±0.3V
ISB2
0.1
5
µA
ISB3
ISB4
5
0.1
8
15
µA
µA
F-VCC = 3.6V, VIN=VIL/VIH, F-RP# = VIL
F-VCC = 3.6V, VIN=GND or F-VCC, F-RP# =GND±0.3V
F-VCC deep powerdown current
F-VCC read current for Word or Byte
F-VCC Write current for Word or Byte
5
15
4
5MHz
1MHz
F-VCC = 3.6V, VIN=VIL/VIH, F-CE# = VIL,
F-RP#=F-OE#=VIH, IOUT = 0mA
ICC1
ICC2
mA
mA
2
F-VCC = 3.6V,VIN=VIL/VIH, F-CE# =F-WE#= VIL,
F-RP#=F-OE#=VIH
15
F-VCC = 3.6V, VIN=VIL/VIH, F-CE# = F-RP# =F-WP# = VIH
ICC3
ICC4
ICC5
VIL
mA
mA
µA
V
F-VCC program current
F-VCC erase current
35
35
F-VCC = 3.6V, VIN=VIL/VIH, F-CE# = F-RP# =F-WP# = VIH
F-VCC = 3.6V, VIN=VIL/VIH, F-CE# = F-RP# =F-WP# = VIH
200
0.8
F-VCC suspend current
Input low voltage
– 0.5
2.0
(F-Vcc)+0.5
VIH
Input high voltage
Output low voltage
V
VOL
VOH1
VOH2
VLKO
IOL = 4.0mA
IOH = –2.0mA
IOH = –100µA
0.45
V
V
0.85(F-Vcc)
(F-Vcc)–0.4
Output high voltage
V
Low VCC Lock-Out voltage 2)
1.5
V
2.2
All currents are in RMS unless otherwise noted.
1) Typical values at F-Vcc=3.3V, Ta=25°C
2) To protect against initiation of write cycle during F-Vcc power-up/ down, a write cycle is locked out for F-Vcc less than VLKO.
If F-Vcc is less than VLKO, Write State Machine is reset to read mode. When the Write State Machine is in Busy state, if F-Vcc is less than VLKO, the alteration of memory contents
may occur.
10
Apr. 1999 , Rev.1.7
MITSUBISHI LSIs
M6MGB/T166S4BWG
16,777,216-BIT (1,048,576 -WORD BY 16-BIT ) CMOS
3.3V-ONLY FLASH MEMORY &
4,194,304-BIT (262,144-WORD BY 16-BIT) CMOS SRAM
Stacked-CSP (Chip Scale Package)
AC ELECTRICAL CHARACTERISTICS (Ta = -20 ~85°C, F-Vcc = 2.7V ~3.6V)
Read-Only Mode
Limits
F-Vcc=2.7-3.6V
90ns
Unit
Symbol
Parameter
Min
90
Typ
Max
tRC
tAVAV
Read cycle time
ns
ns
ns
ns
ns
ns
ns
ns
ta (AD)
90
90
30
tAVQV Address access time
ta (CE)
ta (OE)
tCLZ
tELQV Chip enable access time
tGLQV Output enable access time
tELQX Chip enable to output in low-Z
0
0
tDF(CE) tEHQZ Chip enable high to output in high Z
tOLZ tGLQX Output enable to output in low-Z
tDF(OE) tGHQZ Output enable high to output in high Z
25
25
F-RP# low to output high-Z
tPHZ
tOH
tPS
tPLQZ
tOH
ns
ns
ns
150
0
Output hold from F-CE#, OE#, addresses
F-RP# recovery to F-CE# low
tPHEL
150
Timing measurements are made under AC waveforms for read operations.
AC ELECTRICAL CHARACTERISTICS (Ta = -20 ~85°C, F-Vcc = 2.7V ~3.6V)
Write Mode (F-WE# control)
Limits
Symbol
F-Vcc=2.7-3.6V
Parameter
Unit
90ns
Typ
Min
90
50
0
Max
tWC
tAS
tAVAV
ns
ns
ns
ns
ns
ns
ns
Write cycle time
tAVWH
tWHAX
tDVWH
tWHDX
tWHGL
-
Address set-up time
tAH
tDS
tDH
tOEH
tRE
tCS
tCH
tWP
Address hold time
50
0
Data set-up time
Data hold time
F-OE# hold from F-WE# high
Latency between Read and Write FFH or 71H
Chip enable set-up time
Chip enable hold time
10
30
0
tELWL
tWHEH
ns
ns
ns
ns
0
tWLWH
60
30
0
Write pulse width
tWPH tWHWL
tGHWL tGHWL
Write pulse width high
F-OE# hold to F-WE# Low
Block Lock set-up to write enable high
ns
ns
tBLS
tBLH
tPHHWH
tQVPH
90
0
ns
Block Lockhold from valid SRD
tDAP
tDAE
tWHRH1
tWHRH2
80
600
90
ms
ms
ns
4
Duration of auto-program operation
Duration of auto-block erase operation
Write enable high to F-RY/BY# low
F-RP# high recovery to write enable low
40
tWHRL tWHRL
tPS tPHWL
ns
150
Read timing parameters during command write operations mode are the same as during read-only operations mode.
Typical values at F-Vcc=3.3V, Ta=25°C
11
Apr. 1999 , Rev.1.7
MITSUBISHI LSIs
M6MGB/T166S4BWG
16,777,216-BIT (1,048,576 -WORD BY 16-BIT ) CMOS
3.3V-ONLY FLASH MEMORY &
4,194,304-BIT (262,144-WORD BY 16-BIT) CMOS SRAM
Stacked-CSP (Chip Scale Package)
AC ELECTRICAL CHARACTERISTICS (Ta = -20 ~ 85°C, F-Vcc = 2.7V ~ 3.6V)
Write Mode (F-CE# control)
Limits
F-Vcc=2.7-3.6V
90ns
Symbol
Parameter
Unit
Min
90
50
0
Typ
Max
tWC
tAS
tAVAV
tAVWH
tEHAX
tDVWH
tEHDX
tEHGL
-
ns
ns
ns
ns
ns
ns
ns
Write cycle time
Address set-up time
tAH
Address hold time
tDS
50
0
Data set-up time
tDH
tOEH
tRE
Data hold time
10
F-OE# hold from F-CE# high
Latency between Read and Write FFH or 71H
Write enable set-up time
30
0
tWS
tWH
tCEP
tWLEL
ns
ns
ns
tEHWH Write enable hold time
0
tELEH
F-CE# pulse width
60
30
90
90
0
tCEPH tEHEL
tGHEL tGHEL
ns
ns
ns
F-CE# pulse width high
F-OE# hold to F-CE# Low
Block Lock set-up to write enable high
Block Lockhold from valid SRD
tBLS
tBLH
tPHHEH
tQVPH
ns
tDAP tEHRH1 Duration of auto-program operation
4
80
600
90
ms
ms
ns
tDAE
tEHRL tEHRL
tPS
tEHRH2
Duration of auto-block erase operation
F-CE# high to F-RY/BY# low
40
tPHWL F-RP# high recovery to write enable low
ns
150
Read timing parameters during command write operation mode are the same as during read-only operation mode.
Typical values at F-Vcc=3.3V, Ta=25°C
Erase and Program Performance
Typ
Unit
Parameter
Min
Max
ms
sec
ms
Block Erase Time
40
1.0
4
600
1.8
80
Main Block Write Time (Page Mode)
Page Write Time
Program Suspend Latency / Erase Suspend Time
Typ
Parameter
Min
Max
Unit
Program Suspend Latency
Erase Suspend Time
Please see page 20.
µs
µs
15
15
Vcc Power Up / Down Timing
Symbol
tVCS
Parameter
Min
2
Typ
Max
Unit
F-RP# =VIH set-up time from Vccmin
µs
Please see page 13.
During power up/down, by the noise pulses on control pins, the device has possibility of accidental erasure or programming.
The device must be protected against initiation of write cycle for memory contents during power up/down.
The delay time of min.2µsec is always required before read operation or write operation is initiated from the time F-Vcc reaches F-Vccmin
during power up/down.
By holding F-RP# VIL, the contents of memory is protected during F-Vcc power up/down.
During power up, F-RP# must be held VIL for min.2µs from the time F-Vcc reaches F-Vccmin.
During power down, F-RP# must be held VIL until Vcc reaches GND.
F-RP# doesn't have latch mode ,therefore F-RP# must be held VIH during read operation or erase/program operation.
12
Apr. 1999 , Rev.1.7
MITSUBISHI LSIs
M6MGB/T166S4BWG
16,777,216-BIT (1,048,576 -WORD BY 16-BIT ) CMOS
3.3V-ONLY FLASH MEMORY &
4,194,304-BIT (262,144-WORD BY 16-BIT) CMOS SRAM
Stacked-CSP (Chip Scale Package)
Vcc POWER UP / DOWN TIMING
Read /Write Inhibit
Read /Write Inhibit
Read /Write Inhibit
3.3V
F-VCC
GND
tVCS
VIH
F-RP#
VIL
VIH
F-CE#
VIL
tPS
tPS
VIH
VIL
F-WE#
AC WAVEFORMS FOR READ OPERATION AND TEST CONDITIONS
TEST CONDITIONS
FOR AC CHARACTERISTICS
VIH
ADDRESSES
ADDRESS VALID
tRC
VIL
Input voltage : VIL = 0V, VIH = 3.0V
Input rise and fall times : ≤5ns
Reference voltage
VIH
VIL
ta (AD)
F-CE#
F-OE#
tDF(CE)
at timing measurement : 1.5V
tRE
ta (CE)
VIH
VIL
Output load : 1TTL gate +
CL(30pF)
or
tOEH
tDF(OE)
tOH
VIH
VIL
F-WE#
DATA
F-RP#
ta (OE)
tOLZ
1.3V
VOH
VOL
tCLZ
HIGH-Z
HIGH-Z
OUTPUT VALID
tPHZ
1N914
3.3kΩ
tPS
VIH
VIL
DUT
CL =30pF
AC WAVEFORMS FOR WRITE FFH or 71H AND READ OPERATION
VIH
ADDRESSES
ADDRESS VALID
tRC
VIL
VIH
VIL
ta (AD)
F-CE#
F-OE#
tDF(CE)
ta (CE)
VIH
VIL
tRE
tDF(OE)
tOH
VIH
VIL
F-WE#
ta (OE)
tOLZ
FFH or 71H
Valid
VOH
VOL
tCLZ
HIGH-Z
HIGH-Z
DATA
F-RP#
OUTPUT VALID
tPHZ
tPS
VIH
VIL
In the case of use F-CE# is Low fixed, it is allowed to define a timming specification of tRE
from rising edge of F-WE# to falling edge of F-OE#, and valid data is read after spec of tRE+ta(CE).
(This is only for FFH,71H program and read)
13
Apr. 1999 , Rev.1.7
MITSUBISHI LSIs
M6MGB/T166S4BWG
16,777,216-BIT (1,048,576 -WORD BY 16-BIT ) CMOS
3.3V-ONLY FLASH MEMORY &
4,194,304-BIT (262,144-WORD BY 16-BIT) CMOS SRAM
Stacked-CSP (Chip Scale Package)
AC WAVEFORMS FOR PAGE PROGRAM OPERATION (F-WE# control)
READ STATUS
REGISTER
WRITE READ
The other bank
PROGRAM
ARRAY COMMAND
address
VIH
VIL
F-A19~F-A17,
A16~A7
BANK ADDRESS
VALID
VALID
VALID
ADDRESS VALID
BANK ADDRESS VALID
VIH
VIL
01H~7EH
A6 ~A0
00H
tAS
7FH
VALID
tAH ta(CE)
tWC
VIH
VIL
ta(CE)
ta(OE)
F-CE#
F-OE#
tCS
tCH
VIH
VIL
tOEH
tDAP
tGHWL
tWPH
tOEH
ta(OE)
VIH
VIL
F-WE#
DATA
tDH
tWP
41H
tDS
VIH
VIL
DOUT
SRD
FFH
DIN
DIN
DIN
tWHRL
VOH
VOL
F-RY/BY#
F-RP#
tPS
VIH
VIL
VIH
tBLH
tBLS
F-WP#
VIL
AC WAVEFORMS FOR PAGE PROGRAM OPERATION (F-CE# control)
READ STATUS
REGISTER
WRITE READ
The other bank
address
PROGRAM
ARRAY COMMAND
VIH
VIL
F-A19~F-A17,
A16~A7
BANK ADDRESS
VALID
VALID
VALID
ADDRESS VALID
BANK ADDRESS VALID
VIH
VIL
00H
tAS
01H~7EH
7FH
VALID
A6 ~A0
tAH ta(CE)
tWC
VIH
VIL
ta(CE)
ta(OE)
F-CE#
F-OE#
tCEPH
ta(OE)
VIH
VIL
tCEP
tOEH
tDAP
tOEH
tGHEL
tWS
tWH
VIH
VIL
F-WE#
DATA
tDH
tDS
VIH
VIL
FFH
41H
DIN
DOUT
DIN
DIN
SRD
tEHRL
VOH
VOL
F-RY/BY#
tPS
VIH
F-RP#
F-WP#
VIL
VIH
tBLH
tBLS
VIL
14
Apr. 1999 , Rev.1.7
MITSUBISHI LSIs
M6MGB/T166S4BWG
16,777,216-BIT (1,048,576 -WORD BY 16-BIT ) CMOS
3.3V-ONLY FLASH MEMORY &
4,194,304-BIT (262,144-WORD BY 16-BIT) CMOS SRAM
Stacked-CSP (Chip Scale Package)
AC WAVEFORMS FOR WORD PROGRAM OPERATION (F-WE# control) (to only BANK(I))
READ STATUS
REGISTER
WRITE READ
ARRAY COMMAND
PROGRAM
VIH
VIL
ADDRESS
VALID
BANK ADDRESS
VALID
BANK(I) ADDRESS VALID
ta(CE)
ADDR
F-CE#
tWC
tAS
tAH
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
tCS
tCH
ta(OE)
tWP
tWPH
F-OE#
tOEH
F-WE#
DATA
tDS
40H
DIN
SRD
FFH
tDH
F-RY/BY#
tWHRL
tPS
VIH
VIL
VIH
VIL
F-RP#
F-WP#
tDAP
tBLS
tBLH
AC WAVEFORMS FOR WORD PROGRAM OPERATION (F-CE# control) (to only BANK(I))
READ STATUS
REGISTER
WRITE READ
PROGRAM
ARRAY COMMAND
VIH
VIL
ADDRESS
VALID
BANK ADDRESS
VALID
ADDR
F-CE#
BANK(I) ADDRESS VALID
ta(CE)
tWC
tAS
tAH
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
ta(OE)
tCEP
tWH
F-OE#
tOEH
tWS
F-WE#
DATA
tDS
40H
DIN
SRD
FFH
tDH
F-RY/BY#
tEHRL
tPS
F-RP#
F-WP#
tDAP
tBLS
tBLH
15
Apr. 1999 , Rev.1.7
MITSUBISHI LSIs
M6MGB/T166S4BWG
16,777,216-BIT (1,048,576 -WORD BY 16-BIT ) CMOS
3.3V-ONLY FLASH MEMORY &
4,194,304-BIT (262,144-WORD BY 16-BIT) CMOS SRAM
Stacked-CSP (Chip Scale Package)
AC WAVEFORMS FOR ERASE OPERATIONS (F-WE# control)
READ STATUS
REGISTER
WRITE READ
ERASE
ARRAY COMMAND
VIH
VIL
BANK ADDRESS
VALID
ADDRESSES
BANK ADDRESS VALID
ADDRESS VALID
tAS
tWC
tAH
ta(CE)
VIH
VIL
F-CE#
F-OE#
tCS
tCH
ta(OE)
VIH
VIL
tOEH
tDAE
tWPH
VIH
VIL
F-WE#
tDH
tWP
tDS
VIH
VIL
SRD
FFH
20H
D0H
DATA
tWHRL
VOH
VOL
F-RY/BY#
tPS
VIH
F-RP#
F-WP#
tBLS
VIL
VIH
tBLH
VIL
AC WAVEFORMS FOR ERASE OPERATIONS (F-CE# control)
READ STATUS
REGISTER
WRITE READ
ERASE
ARRAY COMMAND
VIH
BANK ADDRESS
ADDRESSES
ADDRESS VALID
tAS
BANK ADDRESS VALID
VALID
VIL
tWC
tAH
ta(CE)
VIH
VIL
F-CE#
F-OE#
tCEPH
tCEP
ta(OE)
VIH
VIL
tOEH
tDAE
tWS
tWH
VIH
VIL
F-WE#
tDH
tDS
VIH
VIL
SRD
FFH
20H
D0H
DATA
tEHRL
VOH
VOL
F-RY/BY#
tPS
VIH
F-RP#
F-WP#
tBLS
VIL
VIH
VIL
tBLH
16
Apr. 1999 , Rev.1.7
MITSUBISHI LSIs
M6MGB/T166S4BWG
16,777,216-BIT (1,048,576 -WORD BY 16-BIT ) CMOS
3.3V-ONLY FLASH MEMORY &
4,194,304-BIT (262,144-WORD BY 16-BIT) CMOS SRAM
Stacked-CSP (Chip Scale Package)
AC WAVEFORMS FOR PAGE PROGRAM OPERATION WITH BGO (F-WE# control)
Change Bank Address
ARRAY READ FROM THE OTHER BANK
PROGRAM DATA TO ONE BANK
ADDRESS VALID
WITH BGO
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
F-A19~F-A17,
A16~A7
BANK ADDRESS
VALID
VALID
VALID
VALID
01H~7EH
tAH
00H
7FH
VALID
A6 ~A0
F-CE#
tWC
tAS
ta(CE)
tCS
tCH
ta(OE)
F-OE#
F-WE#
tOEH
tWP
tWPH
tDS
41H
DIN
DIN
DIN
SRD
DOUT
DOUT
DATA
tWHRL
tDH
VIH
VIL
F-RY/BY#
AC WAVEFORMS FOR PAGE PROGRAM OPERATION WITH BGO (F-CE# control)
Change Bank Address
PROGRAM DATA TO ONE BANK
ADDRESS VALID
ARRAY READ FROM THE OTHER BANK
WITH BGO
VIH
VIL
VIH
VIL
F-A19~F-A17,
A16~A7
BANK ADDRESS
VALID
VALID
VALID
01H~7EH
tAH
00H
7FH
VALID
VALID
A6 ~A0
tWC
tAS
tCEPH
ta(CE)
ta(OE)
VIH
F-CE#
F-OE#
VIL
VIH
tCEP
tWS
tOEH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
tCH
F-WE#
DATA
tDS
41H
DIN
DIN
DIN
SRD
DOUT
DOUT
tEHRL
tDH
F-RY/BY#
17
Apr. 1999 , Rev.1.7
MITSUBISHI LSIs
M6MGB/T166S4BWG
16,777,216-BIT (1,048,576 -WORD BY 16-BIT ) CMOS
3.3V-ONLY FLASH MEMORY &
4,194,304-BIT (262,144-WORD BY 16-BIT) CMOS SRAM
Stacked-CSP (Chip Scale Package)
AC WAVEFORMS FOR WORD PROGRAM OPERATION WITH BGO (F-WE# control)
Change Bank Address
ARRAY READ FROM BANK(II) WITH BGO
READ STATUS
REGISTER
PROGRAM DATA TO
BANK(I)
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
F-A19~F-A17,
A16~A7
BANK ADDRESS
VALID
ADDRESS VALID
VALID
VALID
VALID
VALID
VALID
A6 ~A0
F-CE#
tAH
tWC
tAS
ta(CE)
ta(OE)
tCS
tCH
F-OE#
F-WE#
DATA
tOEH
tWP
tWPH
tDS
40H
DIN
SRD
DOUT
DOUT
tDH
F-RY/BY#
VIL
tWHRL
AC WAVEFORMS FOR WORD PROGRAM OPERATION WITH BGO (F-CE# control)
Change Bank Address
READ STATUS
REGISTER
PROGRAM DATA TO
BANK(I)
ARRAY READ FROM BANK(II) WITH BGO
VIH
VIL
VIH
VIL
F-A19~F-A17,
A16~A7
BANK ADDRESS
VALID
ADDRESS VALID
VALID
VALID
VALID
VALID
tAS
VALID
A6 ~A0
tWC
ta(CE)
ta(OE)
VIH
F-CE#
F-OE#
tCEPH
VIL
VIH
tCEP
tWS
tOEH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
tCH
F-WE#
DATA
tDS
40H
DIN
SRD
DOUT
DOUT
tDH
F-RY/BY#
tEHRL
18
Apr. 1999 , Rev.1.7
MITSUBISHI LSIs
M6MGB/T166S4BWG
16,777,216-BIT (1,048,576 -WORD BY 16-BIT ) CMOS
3.3V-ONLY FLASH MEMORY &
4,194,304-BIT (262,144-WORD BY 16-BIT) CMOS SRAM
Stacked-CSP (Chip Scale Package)
AC WAVEFORMS FOR BLOCK ERASE OPERATION WITH BGO (F-WE# control)
Change Bank Address
READ STATUS
REGISTER
ARRAY READ FROM THE OTHER
BLOCK ERASE IN
ONE BANK
BANK WITH BGO
VALID
VIH
VIL
BANK ADDRESS
VALID
ADDRESS VALID
tAH
VALID
ADDRESSES
F-CE#
tWC
tAS
tCH
ta(CE)
ta(OE)
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
tCS
F-OE#
tOEH
tWP
tWPH
F-WE#
tDS
20H
D0H
SRD
DOUT
DOUT
DATA
tDH
F-RY/BY#
tWHRL
AC WAVEFORMS FOR BLOCK ERASE OPERATION WITH BGO (F-CE# control)
Change Bank Address
READ DATA FROM THE OTHER BANK
WITH BGO
BLOCK ERASE IN
ONE BANK
READ STATUS
REGISTER
VIH
VIL
BANK ADDRESS
VALID
ADDRESSES
ADDRESS VALID
VALID
VALID
tWC
tAS
tAH
ta(CE)
ta(OE)
VIH
F-CE#
F-OE#
tCEPH
VIL
VIH
tCEP
tWS
tOEH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
tCH
F-WE#
DATA
tDS
20H
D0H
SRD
DOUT
DOUT
tDH
F-RY/BY#
tEHRL
19
Apr. 1999 , Rev.1.7
MITSUBISHI LSIs
M6MGB/T166S4BWG
16,777,216-BIT (1,048,576 -WORD BY 16-BIT ) CMOS
3.3V-ONLY FLASH MEMORY &
4,194,304-BIT (262,144-WORD BY 16-BIT) CMOS SRAM
Stacked-CSP (Chip Scale Package)
AC WAVEFORMS FOR SUSPEND OPERATION (F-WE# control)
READ STATUS
REGISTER
VIH
VIL
ADDRESSES
BANK ADDRESS VALID
tAS
BANK ADDRESS VALID
tAH
ta(CE)
VIH
VIL
F-CE#
F-OE#
tCS
tCH
ta(OE)
VIH
VIL
tOEH
Program Suspend Latency
VIH
VIL
F-WE#
tWP
S.R.6,7=1
VALID SRD
VIH
VIL
B0H
DATA
VOH
VOL
F-RY/BY#
VIH
F-RP#
F-WP#
tBLS
VIL
VIH
tBLH
VIL
AC WAVEFORMS FOR SUSPEND OPERATION (F-CE# control)
READ STATUS
REGISTER
VIH
ADDRESSES
BANK ADDRESS VALID
tAS
BANK ADDRESS VALID
VIL
tAH
ta(CE)
VIH
VIL
tCEP
F-CE#
F-OE#
ta(OE)
VIH
VIL
tOEH
Program Suspend Latency
VIH
VIL
tWS
tWH
F-WE#
S.R.6,7=1
VALID SRD
VIH
VIL
B0H
DATA
VOH
VOL
F-RY/BY#
VIH
F-RP#
F-WP#
tBLS
tBLH
VIL
VIH
VIL
20
Apr. 1999 , Rev.1.7
MITSUBISHI LSIs
M6MGB/T166S4BWG
16,777,216-BIT (1,048,576 -WORD BY 16-BIT ) CMOS
3.3V-ONLY FLASH MEMORY &
4,194,304-BIT (262,144-WORD BY 16-BIT) CMOS SRAM
Stacked-CSP (Chip Scale Package)
FULL STATUS CHECK PROCEDURE
LOCK BIT PROGRAM FLOW CHART
STATUS REGISTER
READ
START
WRITE 77H
SR.4 =1
and
SR.5 =1
?
COMMAND SEQUENCE ERROR
BLOCK ERASE ERROR
YES
NO
NO
NO
WRITE D0H
NO
BLOCK ADDRESS
SR.5 = 0 ?
YES
SR.7 = 1 ?
NO
YES
PROGRAM ERROR
(PAGE, LOCK BIT)
SR.4 = 0 ?
YES
LOCK BIT PROGRAM
SR.4 = 0 ?
FAILED
NO
YES
PROGRAM ERROR
(BLOCK)
LOCK BIT PROGRAM
SUCCESSFUL
SR.3 = 0 ?
YES
SUCCESSFUL
(BLOCK ERASE, PROGRAM)
BYTE PROGRAM FLOW CHART
PAGE PROGRAM FLOW CHART
START
START
WRITE 40H
WRITE 41H
n = 0
WRITE
ADDRESS , DATA
n = n+1
WRITE
ADDRESS n, DATA n
STATUS REGISTER
READ
n = FFH ?
or
n = 7FH ?
NO
NO
NO
SR.7 = 1 ?
WRITE B0H ?
YES
YES
YES
STATUS REGISTER
READ
SUSPEND LOOP
WRITE D0H
FULL STATUS CHECK
IF DESIRED
NO
NO
SR.7 = 1 ?
YES
WRITE B0H ?
YES
PAGE PROGRAM
COMPLETED
YES
* Word program is admitted to only BANK(I).
SUSPEND LOOP
WRITE D0H
FULL STATUS CHECK
IF DESIRED
PAGE PROGRAM
COMPLETED
YES
21
Apr. 1999 , Rev.1.7
MITSUBISHI LSIs
M6MGB/T166S4BWG
16,777,216-BIT (1,048,576 -WORD BY 16-BIT ) CMOS
3.3V-ONLY FLASH MEMORY &
4,194,304-BIT (262,144-WORD BY 16-BIT) CMOS SRAM
Stacked-CSP (Chip Scale Package)
SUSPEND / RESUME FLOW CHART
CLEAR PAGE BUFFER
START
START
WRITE B0H
SUSPEND
WRITE 55H
STATUS REGISTER
READ
WRITE D0H
SR.7 = 1?
YES
NO
NO
PAGE BUFFER CLEAR
COMPLETED
PROGRAM / ERASE
COMPLETED
SR.6 =1?
SINGLE DATA LOAD TO PAGE BUFFER
YES
WRITE FFH
START
WRITE 74H
READ ARRAY DATA
WRITE
ADDRESS , DATA
DONE
READING ?
NO
YES
NO
DONE
LOADING?
RESUME
WRITE D0H
OPERATION
RESUMED
YES
SINGLE DATA LOAD
TO PAGE BUFFER
COMPLETED
* The bank address is required when writing this command. Also, there is
no need to suspend the erase or program operation when reading data
from the other bank. Please use BGO function.
BLOCK ERASE FLOW CHART
PAGE BUFFER TO FLASH
START
START
WRITE 20H
WRITE 0EH
WRITE D0H
BLOCK ADDRESS
WRITE D0H
PAGE ADDRESS
STATUS REGISTER
READ
STATUS REGISTER
READ
NO
NO
WRITE B0H ?
NO
NO
SR.7 = 1 ?
WRITE B0H ?
SR.7 = 1 ?
YES
YES
YES
FULL STATUS CHECK
IF DESIRED
SUSPEND LOOP
WRITE D0H
FULL STATUS CHECK
IF DESIRED
SUSPEND LOOP
WRITE D0H
BLOCK ERASE
COMPLETED
PAGE BUFFER TO FLASH
COMPLETED
YES
YES
22
Apr. 1999 , Rev.1.7
Read/Standby State
70H
71H
Read
Status Register
50H
Clear
Status Register
70H
90H
70H
90H
Read
Read
Lock Status
Device Identifier
71H
71H
90H
FFH
FFH
FFH
Read Array
D0H
WD
20H
A7H
Setup State
0EH
41H
40H
77H
55H
74H
Clear
Page Buffer
Setup
Single Data Load Page Buffer to Flash
Page Program
Setup
Lock Bit Program
Setup
Erase All Unlocked
Blocks Setup
Block Erase
Setup
Byte Program
Setup
to Page Buffer
Setup
Setup
OTHER
OTHER
D0H
D0H
WDi
i=0-127
WD
D0H
D0H
OTHER
OTHER
Internal State
Erase &
Verify
Program &
Verify
Ready
Read
Read
Status Register
Status Register
B0H
B0H
D0H
D0H
Suspend State
Change Bank
Address
70H
Read
Status Register
Read State with BGO
Change Bank
Address
70H
Read Array
FFH
(From The Other Bank)
Read Array
MITSUBISHI LSIs
M6MGB/T166S4BWG
16,777,216-BIT (1,048,576 -WORD BY 16-BIT ) CMOS
3.3V-ONLY FLASH MEMORY &
4,194,304-BIT (262,144-WORD BY 16-BIT) CMOS SRAM
Stacked-CSP (Chip Scale Package)
2. SRAM
When setting S-LB# at the high level and other pins are in
an active stage, upper-byte are in selectable mode in which
both reading and writing are enabled, and lower-byte are in
non-selectable mode. And when setting S-UB# at a high
level and other pins are in an active stage, lower-byte are in
a selectable mode and upper-byte are in a non-selectable
mode.
When setting S-LB# and S-UB# at a high level or S-CE1#
at high level or S-CE2 at a low level, the chips are in a non-
selectable mode in which both reading and writing are
disabled. In this mode, the output stage is in a high-
impedance state, allowing OR-tie with other chips and
memory expansion by S-LB#,S-UB# and S-CE1#,S-CE2.
The power supply current is reduced as low as
0.3µA(25°C,typical), and the memory data can be held at
+2V powersupply, enabling battery back-up operation during
power failure or power-down operation in the non-selected
mode.
The SRAM of M6MGB/T166S4BWG is organized as
262,144-word by 16-bit. These devices operate on a single
+2.7~3.6V powersupply, and are directly TTL compatible to both
input and output. Its fully static circuit needs no clocks and no
refresh, and makes it useful.
The operation mode are determined by a combination of the
device control inputs , S-LB#,S-UB#,S-CE1#,S-CE2, S-WE#
and S-OE#. Each mode is summarized in the function table.
A write operation is executed whenever the low level S-WE#
overlaps with the low level S-LB# and/or S-UB# and the low
level S-CE1#the high level S-CE2. The address A0~A16,SA-17
must be set up before the write cycle and must be stable during
the entire cycle.
A read operation is executed by setting S-WE# at a high level
and S-OE# at a low level while S-LB# and/or S-UB# and
S-CE1# and S-CE2 are in an active state(S-CE1#=L,S-CE2=H).
FUNCTION TABLE
S-CE1# S-CE2 S-LB# S-UB#
Mode
DQ0~7
High-Z
High-Z
DQ8~15
High-Z
High-Z
Icc
S-WE# S-OE#
H
L
H
X
L
L
L
L
L
L
L
L
L
X
X
X
H
L
X
X
X
H
H
H
H
L
X
X
X
X
L
X
X
X
X
X
Non selection
Non selection
Standby
Standby
L
Non selection
Non selection
Standby
Standby
H
X
H
H
H
H
H
H
H
H
High-Z
High-Z
High-Z
High-Z
Write
Read
Din
High-Z
High-Z
High-Z
Din
Active
Active
Active
Active
Active
Active
Active
Active
H
H
L
L
L
H
L
Dout
H
X
High-Z
High-Z
Write
Read
H
H
L
L
H
H
L
L
Dout
High-Z
High-Z
L
H
X
L
High-Z
Din
L
Write
Read
Din
L
L
H
Dout
Dout
L
H
L
L
H
H
High-Z
High-Z
Active
Apr. 1999 , Rev.1.7
24
MITSUBISHI LSIs
M6MGB/T166S4BWG
16,777,216-BIT (1,048,576 -WORD BY 16-BIT ) CMOS
3.3V-ONLY FLASH MEMORY &
4,194,304-BIT (262,144-WORD BY 16-BIT) CMOS SRAM
Stacked-CSP (Chip Scale Package)
ABSOLUTE MAXIMUM RATINGS
Conditions
Ratings
Symbol Parameter
Units
V
With respect to GND
With respect to GND
With respect to GND
S-V
cc
VI
Supply voltage
Input voltage
Output voltage
-0.5* ~ +4.6
-0.5* ~ S-Vcc + 0.5
0 ~ S-Vcc
VO
Pd
Power dissipation
700
mW
Ta=25°C
Operating
temperature
W-version
Ta
- 20 ~ +85°C
°C
°C
Storage temperature
Tstg
- 65 ~ +150°C
<
* -3.0V in case of AC (Pulse width 30ns)
=
( S-Vcc=2.7 ~ 3.6V, unless otherwise noted)
DC ELECTRICAL CHARACTERISTICS
Limits
Units
Symbol
Parameter
Conditions
Min
2.2
Max
Typ
High-level input voltage
Low-level input voltage
High-level output voltage 1
High-level output voltage 2
Low-level output voltage
Input leakage current
S-Vcc+0.3V
VIH
-0.3 *
2.4
VIL
VOH1
VOH2
0.6
IOH= -0.5mA
V
S-Vcc-0.5V
IOH= -0.05mA
IOL=2mA
VOL
0.4
+
1
VI =0 ~ S-Vcc
II
-
µA
S-LB# and S-UB#=VIH or S-CE1#=VIH or S-CE2=VIH
or S-OE#=VIH, VI/O=0 ~ S-Vcc
+
1
-
Output leakage current
IO
<
<
S-LB# and S-UB# 0.2V,S-CE1# 0.2V,
=
=
f= 10MHz
f= 1MHz
f= 10MHz
f= 1MHz
50
7
70
15
70
15
-
-
-
Active supply current
( AC,MOS level )
>
<
>
S-CE2 S-Vcc-0.2V other inputs 0.2V or
Icc1
Icc2
=
=
=
S-Vcc-0.2V Output-open(duty 100%)
mA
S-LB# and S-UB#=VIL,S-CE1#=VIL,
S-CE2=VIH other inputs=VIH or VIL
Output-open(duty 100%)
50
7
Active supply current
( AC,TTL level )
-
-
+70 ~ +85 °C
+40 ~ +70 °C
+25 ~ +40 °C
- 20 ~ +25 °C
40
20
-
-
-
-
-
<
Stand by supply current
( AC,MOS level )
S-CE2 0.2V
=
-W
µA
Icc3
Icc4
Other inputs=0~S-Vcc
1
3.6
1.2
0.3
Stand by supply current
( AC,TTL level )
S-LB# and S-UB#=VIH or S-CE1#=VIH or S-CE2=VIL
Other inputs= 0 ~ S-Vcc
-
-
0.5
mA
<
Note 1: Direction for current flowing into IC is indicated as positive (no mark)
Note 2: Typical value is for S-Vcc=3.0V and Ta=25°C
* -3.0V in case of AC (Pulse width 30ns)
=
(S-Vcc=2.7 ~ 3.6V, unless otherwise noted)
CAPACITANCE
Limits
Units
Parameter
Symbol
Conditions
Min
Typ
Max
10
CI
VI=GND, VI=25mVrms, f=1MHz
VO=GND,VO=25mVrms, f=1MHz
Input capacitance
Output capacitance
pF
CO
10
Note: The value of common pins to SRAM is the sum of Flash Memory and SRAM.
Apr. 1999 , Rev.1.7
25
MITSUBISHI LSIs
M6MGB/T166S4BWG
16,777,216-BIT (1,048,576 -WORD BY 16-BIT ) CMOS
3.3V-ONLY FLASH MEMORY &
4,194,304-BIT (262,144-WORD BY 16-BIT) CMOS SRAM
Stacked-CSP (Chip Scale Package)
(S-Vcc=2.7 ~ 3.6V, unless otherwise noted)
AC ELECTRICAL CHARACTERISTICS
(1) TEST CONDITIONS
Supply voltage
2.7V~3.6V
VIH=2.4V, VIL=0.4V
5ns
1TTL
Input pulse
DQ
Input rise time and fall time
CL
VOH=VOL=1.5V
Transition is measured 500mV from
steady state voltage.(for ten,tdis)
Reference level
+
Including scope and
jig capacitance
-
Fig.1,CL=30pF
Fig.1 Output load
Output loads
CL=5pF (for ten,tdis)
(2) READ CYCLE
Limits
SRAM
Parameter
Units
Symbol
Min
85
Max
tCR
ta(A)
ta(CE1)
ta(CE2)
ta(LB)
ta(UB)
Read cycle time
Address access time
Chip select 1 access time
Chip select 2 access time
Lower Byte control access time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
85
85
85
85
85
45
30
30
30
30
Upper Byte control access time
Output enable access time
ta(OE)
Output disable time after S-CE1# high
Output disable time after S-CE2 low
Output disable time after S-LB# high
Output disable time after S-UB# high
Output disable time after S-OE high
Output enable time after S-CE1# low
Output enable time after S-CE2 high
Output enable time after S-LB# low
Output enable time after S-UB# low
Output enable time after S-OE low
tdis(CE1)
tdis(CE2)
tdis(LB)
tdis(UB)
tdis(OE)
ten(CE1)
ten(CE2)
tdis(LB)
tdis(UB)
ten(OE)
30
10
10
10
10
5
10
ns
ns
ns
ns
ns
tV(A)
Data valid time after address
(3) WRITE CYCLE
Limits
SRAM
Units
ns
ns
ns
Symbol
Parameter
Min
85
60
0
Max
tCW
tw(W)
tsu(A)
Write cycle time
Write pulse width
Address setup time
Address setup time with respect to S-WE#
Lower Byte control setup time
Upper Byte control setup time
Chip select 1 setup time
Chip select 2 setup time
Data setup time
70
70
70
70
70
35
ns
ns
ns
ns
ns
ns
tsu(A-WH)
tsu(LB)
tsu(UB)
tsu(CE1)
tsu(CE2)
tsu(D)
th(D)
Data hold time
Write recovery time
0
0
ns
ns
trec(W)
30
30
ns
ns
ns
Output disable time from S-WE# low
Output disable time from S-OE# high
Output enable time from S-WE# high
tdis(W)
tdis(OE)
ten(W)
5
5
ns
ten(OE)
Output enable time from S-OE# low
26
Apr. 1999 , Rev.1.7
MITSUBISHI LSIs
M6MGB/T166S4BWG
16,777,216-BIT (1,048,576 -WORD BY 16-BIT ) CMOS
3.3V-ONLY FLASH MEMORY &
4,194,304-BIT (262,144-WORD BY 16-BIT) CMOS SRAM
Stacked-CSP (Chip Scale Package)
(4)TIMING DIAGRAMS
Read cycle
tCR
A0~16,
S-A17
ta(A)
tv
(A)
ta(LB)
ta(UB)
or
ta(CE1)
ta(CE2)
S-LB#,
S-UB#
(Note3)
(Note3)
tdis (LB) or tdis (UB)
tdis (CE1)
S-CE1#
S-CE2
(Note3)
(Note3)
(Note3)
(Note3)
tdis (CE2)
ta (OE)
S-OE#
(Note3)
(Note3)
ten (OE)
tdis (OE)
S-WE# = "H" level
ten (LB)
ten (UB)
DQ0~15
VALID DATA
ten (CE1)
ten (CE2)
Write cycle
(S-WE# control mode)
tCW
A0~16,
S-A17
tsu (LB) or tsu(UB)
S-LB#,
S-UB#
(Note3)
(Note3)
tsu (CE1)
tsu (CE2)
S-CE1#
S-CE2
(Note3)
(Note3)
(Note3)
(Note3)
S-OE#
tsu (A-WH)
tw (W)
tsu (A)
trec (W)
tdis (W)
S-WE#
ten(OE)
ten (W)
tdis(OE)
DATA IN
STABLE
DQ0~15
tsu (D)
th (D)
27
Apr. 1999 , Rev.1.7
MITSUBISHI LSIs
M6MGB/T166S4BWG
16,777,216-BIT (1,048,576 -WORD BY 16-BIT ) CMOS
3.3V-ONLY FLASH MEMORY &
4,194,304-BIT (262,144-WORD BY 16-BIT) CMOS SRAM
Stacked-CSP (Chip Scale Package)
Write cycle (S-LB#,S-UB# control mode)
tCW
A0~16,
S-A17
trec (W)
tsu (LB) or
tsu(UB)
tsu (A)
S-LB#,
S-UB#
S-CE1#
(Note3)
(Note3)
(Note3)
(Note3)
S-CE2
(Note5)
S-WE#
(Note4)
(Note3)
(Note3)
tsu (D)
DATA IN
th (D)
DQ0~15
STABLE
Note 3: Hatching indicates the state is "don't care".
Note 4: A Write occurs during S-CE1# low, S-CE2 high overlaps S-LB# and/or S-UB# low and W low.
Note 5: When the falling edge of S-WE# is simultaneously or prior to the falling edge of S-LB# and/or S-UB# or the falling edge of
S-CE1# or rising edge of S-CE2, the outputs are maintained in the high impedance state.
Note 6: Don't apply inverted phase signal externally when DQ pin is in output mode.
Apr. 1999 , Rev.1.7
28
MITSUBISHI LSIs
M6MGB/T166S4BWG
16,777,216-BIT (1,048,576 -WORD BY 16-BIT ) CMOS
3.3V-ONLY FLASH MEMORY &
4,194,304-BIT (262,144-WORD BY 16-BIT) CMOS SRAM
Stacked-CSP (Chip Scale Package)
Write cycle (S-CE1# control mode)
tCW
A0~16,
S-A17
S-LB#,
S-UB#
(Note3)
trec (W)
(Note3)
tsu (CE1)
tsu (A)
S-CE1#
S-CE2
(Note3)
(Note3)
(Note3)
(Note3)
(Note5)
S-WE#
(Note4)
tsu (D)
th (D)
DATA IN
STABLE
DQ0~15
Write cycle (S-CE2 control mode)
tCW
A0~16,
S-A17
S-LB#,
S-UB#
(Note3)
(Note3)
tsu (CE2)
trec (W)
tsu (A)
S-CE1#
S-CE2
(Note3)
(Note3)
(Note3)
(Note3)
(Note5)
S-WE#
(Note4)
tsu (D)
th (D)
DATA IN
STABLE
DQ0~15
29
Apr. 1999 , Rev.1.7
MITSUBISHI LSIs
M6MGB/T166S4BWG
16,777,216-BIT (1,048,576 -WORD BY 16-BIT ) CMOS
3.3V-ONLY FLASH MEMORY &
4,194,304-BIT (262,144-WORD BY 16-BIT) CMOS SRAM
Stacked-CSP (Chip Scale Package)
POWER DOWN CHARACTERISTICS
(1) ELECTRICAL CHARACTERISTICS
Limits
Symbol
Parameter
Units
Test conditions
Min
Typ
Max
S-Vcc (PD)
VI (S-BC)
Power down supply voltage
Byte control input S-LB#,S-UB#
V
V
V
V
2.0
2.0
2.0
VI (S-CE1#)
Chip select input S-CE1#
VI (S-CE2) Chip select input S-CE2
0.2
30
15
+70 ~ +85 °C
+40 ~ +70 °C
+25 ~ +40 °C
- 20 ~ +25 °C
-
-
-
-
S-Vcc=3.0V
Power down
supply current
<
S-CE2 0.2V
=
Icc (PD)
-W
µA
other inputs=0~3V
-
-
3
1
1
0.3
Typical value is for Ta=25°C
(2) TIMING REQUIREMINTS
Limits
Symbol
Units
Parameter
Test conditions
Min
Typ
Max
Power down set up time
t
t
su (PD)
rec (PD)
ns
0
5
Power down recovery time
ms
(3) TIMING DIAGRAM
S-LB#,S-UB# control mode
S-Vcc
2.7V
2.7V
tsu (PD)
trec (PD)
S-LB#,
S-UB#
2.2V
2.2V
>
S-LB#,S-UB# (S-Vcc) - 0.2V
=
S-CE1# control mode
S-Vcc
2.7V
2.7V
tsu (PD)
trec (PD)
2.2V
2.2V
S-CE1#
>
S-CE1# (S-Vcc) - 0.2V
=
S-CE2 control mode
S-Vcc
2.7V
2.7V
0.2V
0.2V
S-CE2
<
trec (PD)
S-CE2 0.2V
tsu (PD)
=
30
Apr. 1999 , Rev.1.7
相关型号：
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