LTC3330 [Linear]
Energy Harvesting DC/DC with Battery Backup Low Noise LDO Post Regulator; 能量收集DC / DC ，带有备用电池低噪声LDO后置稳压器
| 型号： | LTC3330 |
| 厂家： | 
Linear |
| 描述： | Energy Harvesting DC/DC with Battery Backup Low Noise LDO Post Regulator |
| 文件： | 总20页 (文件大小：179K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Electrical Specifications Subject to Change
LTC3330
Energy Harvesting DC/DC
with Battery Backup
FeaTures
DescripTion
The LTC®3330 integrates a high voltage energy harvesting
powersupplyplusaDC/DCconverterpoweredbyaprimary
cell battery to create a single output supply for alternative
energy applications. The energy harvesting power supply,
consisting of an integrated full-wave bridge rectifier and a
high voltage buck converter, harvests energy from piezo-
electric, solar, ormagnetic sources. The primary cellinput
powersabuck-boostconvertercapableofoperationdown
to 1.8V at its input. Either DC/DC converter can deliver en-
ergytoasingleoutput. Thebuckoperateswhenharvested
energy is available, reducing the quiescent current draw
on the battery to essentially zero. The buck-boost takes
over when harvested energy goes away.
n
Dual Input, Single Output DC/DC’s with Input
Prioritizer
Energy Harvesting Input: 3.0V to 18V Buck DC/DC
Primary Cell Input: 1.8V to 5.5V Buck-Boost DC/DC
n
Zero Battery I When Powering Load from
Q
Harvested Energy
n
n
n
n
n
Ultralow Quiescent Current: 900nA at No-Load
Low Noise LDO Post Regulator
Integrated Supercapacitor Balancer
Up to 50mA of Output Current
Programmable DC/DC and LDO Output Voltages,
Buck UVLO, and Buck-Boost Peak Input Current
Integrated Low Loss Full-Wave Bridge Rectifier
n
n
n
Input Protective Shunt–Up to 25mA at V ≥ 20V
5mm × 5mm QFN-32 Package
IN
A low noise LDO post regulator and a supercapacitor
balancerarealsointegrated,accommodatingawiderange
of output storage configurations.
applicaTions
Voltage and current settings for both inputs and outputs
are programmable via pin-strapped logic inputs.
n
Energy Harvesting
n
Solar Powered Systems with Primary Cell Backup
TheLTC3330isavailableina5mm×5mmQFN-32package.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
n
Wireless HVAC Sensors and Security Devices
Mobile Asset Tracking
n
Typical applicaTion
4V TO 18V
AC1
AC2
SW
PIEZO
MIDE
V25W
22µH
22µH
+
SOLAR
PANEL
3V TO 18V
V
IN
LTC3330
10µF
25V
1µF
6V
SWA
SWB
–
CAP
4.7µF, 6V
1.2V TO 5V
50mA
V
V
OUT
IN2
LDO_IN
SCAP
22µF
6V
10mF
2.5V
BAT
1µF
6V
PRIMARY
CELL
1.8V TO 5.5V
+
BAL
10mF
2.5V
3
OUT[2:0]
LDO[2:0]
IPK[2:0]
UV[3:0]
LDO_EN
EH_ON
3
3
4
OPTIONAL
PGVOUT
PGLDO
1.2V TO 3.6V
50mA
LDO_OUT
V
IN3
1µF
6V
2.2µF
6V
GND
3330 TA01a
3330p
1
For more information www.linear.com/LTC3330
LTC3330
absoluTe MaxiMuM raTings
pin conFiguraTion
(Note 1)
TOP VIEW
V
IN
Low Impedance Source ..........................–0.3 to 18V*
Current-Fed, I = 0A........................................25mA
SW
32 31 30 29 28 27 26 25
AC1, AC2.............................................................0 to V
BAT, V , V , LDO_IN, SCAP, PGVOUT, PGLDO,
IN
BAL
1
2
3
4
5
6
7
8
24 LDO0
23 LDO1
OUT IN3
SCAP
EH_ON........................................................–0.3 to 6V
....................–0.3V to [Lesser of (V + 0.3V) or 6V]
V
LDO2
22
21
IN2
V
IN2
IN
IN
UV3
UV2
UV1
UV0
AC1
LDO_IN
33
GND
CAP......................[Higher of –0.3V or (V – 6V)] to V
IN
20 LDO_OUT
IPK2
LDO_OUT, LDO[2:0], LDO_EN..–0.3V to LDO_IN + 0.3V
19
BAL...............................................–0.3V to SCAP + 0.3V
18 IPK1
17 IPK0
OUT[2:0].......... –0.3V to [Lesser of (V + 0.3V) or 6V]
IN3
IN3
IN2
9
10 11 12 13 14 15 16
UH PACKAGE
IPK[2:0] ........... –0.3V to [Lesser of (V + 0.3V) or 6V]
UV[3:0] ............ –0.3V to [Lesser of (V + 0.3V) or 6V]
I
I
I
, I .............................................................. 50mA
AC1 AC2
SW SWA SWB VOUT
LDO_OUT
, I
, I
, I
..........................................350mA
32-LEAD (5mm × 5mm) PLASTIC QFN
T
= 125°C, θ = 34°C/W
JMAX
JA
.................................................................50mA
EXPOSED PAD (PIN 33) IS GND, MUST BE SOLDERED TO PCB
Operating Junction Temperature Range
(Notes 2, 3)............................................ –40°C to 125°C
Storage Temperature Range .................. –65°C to 125°C
*V has an internal 20V clamp
IN
orDer inForMaTion
LEAD FREE FINISH
LTC3330EUH#PBF
LTC3330IUH#PBF
TAPE AND REEL
PART MARKING
3330
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC3330EUH#TRPBF
LTC3330IUH#TRPBF
–40°C to 85°C
–40°C to 125°C
32-Lead (5mm × 5mm) Plastic QFN
32-Lead (5mm × 5mm) Plastic QFN
3330
Consult LTC Marketing for parts specified with wider operating temperature ranges.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
3330p
2
For more information www.linear.com/LTC3330
LTC3330
elecTrical characTerisTics The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = 5V, BAT = 3.6V, SCAP = OV, LDO_IN = 0V unless
otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN
3.0
TYP
MAX
18
UNITS
l
l
V
V
Buck Input Voltage Range
Buck-Boost Input Voltage Range
V
V
IN
1.8
5.5
BAT
VIN
I
V Quiescent Current
IN
V
IN
Input in UVLO
V
IN
V
IN
V
IN
V
IN
= 2.5V, BAT = 0V
= 4V, BAT = 0V
= 18V, BAT = 0V
= 5V, BAT = 0V, I
450
1150
1650
150
700
1800
2500
250
nA
nA
nA
µA
Buck Enabled, Sleeping
Buck Enabled, Sleeping
Buck Enabled, Not Sleeping
= 0A (Note 4)
SW1
I
BAT Quiescent Current
BAT
BAT Input with V Active
BAT = 1.8V, V = 5V
10
1500
330
nA
nA
µA
IN
IN
Buck-Boost Enabled, Sleeping
BAT = 5V, V = 0V
900
200
IN
Buck-Boost Enabled, Not Sleeping
BAT = 5V, V = 0V, I
= I
SWB
= 0A
IN
SWA
(Note 4)
l
l
V
LDO_IN Input Range
1.8V
–2.0
5.5V
600
LDO_IN
I
I
LDO_IN Quiescent Current
LDO_OUT Leakage Current
LDO_IN = 5.0V, I
= 0A
400
125
nA
LDO_IN
LDO_OUT
LDO_IN = 5.0V, LDO_OUT = 5.0V
Error as a Percentage of Target
LDO_OUT = 1.2V, 10mA Load
LDO_IN = 5.0V, LDO_OUT = 3.3V
LDO_OUT = 3.3V, 10mA LOAD
LDO_IN = 5.0V
nA
LDO_OUT
LDO_OUT Regulated LDO Output Voltage
LDO Line Regulation (1.8V to 5.5V)
LDO Load Regulation (10µA to 10mA)
LDO Dropout Voltage
2.0
%
2
2
mV/V
mV/mA
mV
mA
nA
nA
mA
mA
%
V
90
LDO Current Limit
50
I
I
I
I
V
Leakage Current
V = 5.0V
OUT
125
165
VOUT
OUT
Supercapacitor Balancer Quiescent Current
Supercapacitor Balancer Source Current
Supercapacitor Balancer Sink Current
Supercapacitor Balance Point
SCAP = 5.0V
SCAP = 5.0V, BAL = 2.4V
SCAP = 5.0V, BAL = 2.6V
Percentage of SCAP Voltage
3V Level
250
SCAP
10
SOURCE
SINK
10
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
V
V
49
50
51
BAL
V
Undervoltage Lockout Thresholds
IN
2.85
3.80
4.75
5.70
6.65
7.60
8.55
9.50
10.4
11.4
12.3
13.3
14.2
15.2
16.1
17.1
19.0
3.00
4.00
5.00
6.00
7.00
8.00
9.00
10.0
11.0
12.0
13.0
14.0
15.0
16.0
17.0
18.0
20.0
3.15
4.20
5.25
6.30
7.35
8.40
9.45
10.5
11.6
12.6
13.7
14.7
15.8
16.8
17.9
18.9
21.0
INUVLO
(Rising or Falling)
4V Level
V
5V Level
V
6V Level
V
7V Level
V
8V Level
V
9V Level
V
10V Level
V
11V Level
V
12V Level
V
13V Level
V
14V Level
V
15V Level
V
16V Level
V
17V Level
V
18V Level
V
V
V
Shunt Regulator Voltage
I = 1mA
VIN
V
SHUNT
IN
3330p
3
For more information www.linear.com/LTC3330
LTC3330
elecTrical characTerisTics The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = 5V, BAT = 3.6V, SCAP = OV, LDO_IN = 0V unless
otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
I
Maximum Protective Shunt Current
25
mA
SHUNT
Internal Bridge Rectifier Loss (|V – V | – V ) I
= 10µA
= 50mA
700
1400
800
1500
900
1600
mV
mV
AC1
AC2
IN
BRIDGE
BRIDGE
I
Internal Bridge Rectifier Reverse Leakage Current
V
= 18V
= 1µA
20
nA
V
REVERSE
Internal Bridge Rectifier Reverse Breakdown
Voltage
I
V
30
REVERSE
SHUNT
V
Regulated Buck/Buck-Boost Output Voltage
1.8V Output Selected
Sleep Threshold
OUT
l
l
1.806
1.794
TBD
TBD
TBD
TBD
TBD
TBD
TBD
V
V
Wakeup Threshold
TBD
TBD
TBD
TBD
TBD
TBD
TBD
2.5V Output Selected
Sleep Threshold
l
l
2.508
2.492
V
V
Wakeup Threshold
2.8V Output Selected
Sleep Threshold
l
l
2.809
2.791
V
V
Wakeup Threshold
3.0V Output Selected
Sleep Threshold
l
l
3.010
2.990
V
V
Wakeup Threshold
3.3V Output Selected
Sleep Threshold
l
l
3.311
3.289
V
V
Wakeup Threshold
3.6V Output Selected
Sleep Threshold
l
l
3.612
3.588
V
V
Wakeup Threshold
4.5V Output Selected
Sleep Threshold
l
l
4.515
4.485
V
V
Wakeup Threshold
5.0V Output Selected
Sleep Threshold
l
l
5.017
4.983
TBD
350
V
V
Wakeup Threshold
TBD
200
100
I
I
I
Buck Peak Switch Current
250
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
PEAK_BUCK
l
Available Buck Output Current
Buck-Boost Peak Switch Current
BUCK
250mA Target Selected
150mA Target Selected
100mA Target Selected
50mA Target Selected
25mA Target Selected
15mA Target Selected
10mA Target Selected
5mA Target Selected
250
150
100
50
350
TBD
TBD
TBD
TBD
TBD
TBD
TBD
IPEAK_BB
25
15
10
5
l
I
BB
Available Buck-Boost Current
I
V
= 250mA, BAT = 1.8V,
IPEAK_BB
OUT
50
= 3.3V
R
R
R
R
R
Buck PMOS Switch On-Resistance
Buck NMOS Switch On-Resistance
Buck-Boost PMOS Switch On-Resistance
Buck-Boost NMOS Switch On-Resistance
LDO PMOS Switch On-Resistance
1.1
1.3
0.5
0.5
7
Ω
Ω
Ω
Ω
P_BUCK
N_BUCK
P_BB
Input and Output Switches
Input and Output Switches
N_BB
LDO_IN = 2.5V, I
= 50mA
LDO_OUT
Ω
P_LDO
3330p
4
For more information www.linear.com/LTC3330
LTC3330
elecTrical characTerisTics The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = 5V, BAT = 3.6V, SCAP = OV, LDO_IN = 0V unless
otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN
–20
–20
100
90
TYP
MAX
20
UNITS
nA
nA
%
I
I
PMOS Switch Leakage
NMOS Switch Leakage
Maximum Buck Duty Cycle
PGVOUT Threshold
PGLDO Threshold
Buck/Buck-Boost Regulators
Buck/Buck-Boost Regulators
Buck/Buck-Boost Regulators
LEAK(P)
LEAK(N)
20
l
l
l
l
As a Percentage of V
Target
92.5
92.5
95
95
%
OUT
As a Percentage of LDO_OUT Target
90
%
V
V
Digital Input High Voltage
Pins LDO_EN, OUT[2:0], LDO[2:0],
IPK[2:0], UV[3:0]
1.2
V
IH
l
Digital Input Low Voltage
Digital Input High Current
Digital Input Low Current
Pins LDO_EN, OUT[2:0], LDO[2:0],
IPK[2:0], UV[3:0]
0.4
10
10
V
nA
nA
IL
I
I
Pins LDO_EN, OUT[2:0], LDO[2:0],
IPK[2:0], UV[3:0]
0
0
IH
Pins LDO_EN, OUT[2:0], LDO[2:0],
IPK[2:0], UV[3:0]
IL
l
l
V
V
PGVOUT, PGLDO, EH_ON Output High Voltage
PGVOUT, PGLDO, EH_ON Output Low Voltage
V
V
= 5V, 10µA Out of Pin
= 5V, 10µA into Pin
4.6
V
V
OH
IN3
IN3
0.4
OL
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
consistent with these specifications is determined by specific operating
conditions in conjunction with board layout, the rated package thermal
impedance and other environmental factors.
Note 3: T is calculated from the ambient T and power dissipation PD
J
A
Note 2: The LTC3330E is tested under pulsed load conditions such that
according to the following formula: T = T + (P • θ ).
Note 4: Dynamic supply current is higher due to gate charge being
delivered at the switching frequency.
J A D JA
T ≈ T . The LTC3330E is guaranteed to meet specifications from 0°C to
J
A
85°C. The LTC3330I is guaranteed over the –40°C to 125°C operating
junction temperature range. Note that the maximum ambient temperature
3330p
5
For more information www.linear.com/LTC3330
LTC3330
Typical perForMance characTerisTics
IVIN in UVLO vs VIN
IVIN in Sleep vs VIN
IBAT in Sleep vs BAT
UVLO Rising vs Temperature
UVLO Falling vs Temperature
VSHUNT vs Temperature
Total Bridge Rectifier Drop vs
Bridge Current
Bridge Leakage vs Temperature
Bridge Frequency Response
3330p
6
For more information www.linear.com/LTC3330
LTC3330
Typical perForMance characTerisTics
VOUT vs Temperature (1.8V, 2.5V,
2.8V, 3.0V)
VOUT vs Temperature (3.3V, 3.6V,
4.5V, 5.0V)
IVOUT vs Temperature
VOUT Load Regulation Buck/Buck-
Boost
VOUT Line Regulation Buck/Buck-
Boost
IPEAK-BUCK vs Temperature
RDS(ON) of Buck PMOS/NMOS vs
Temperature
IPEAK_BB vs Temperature (250mA,
150mA, 100mA, 50mA)
IPEAK_BB vs Temperature (25mA,
15mA, 10mA, 5mA)
3330p
7
For more information www.linear.com/LTC3330
LTC3330
Typical perForMance characTerisTics
RDS(ON) of Buck-Boost PMOS/
NMOS vs Temperature
Buck Switching Waveforms
Buck-Boost Efficiency vs ILOAD
ISCAP vs SCAP
Buck-Boost Switching Waveforms
Prioritizer Buck-Boost to Buck
Transition
Buck Efficiency vs ILOAD
Prioritizer Buck to Buck-Boost
Transition
Supercapacitor Balancer Source/
Sink Current
3330p
8
For more information www.linear.com/LTC3330
LTC3330
Typical perForMance characTerisTics
ILDO_IN vs LDO_IN
LDO_OUT vs Temperature
LDO Load Step
LDO Load Regulation
LDO Line Regulation
LDO Current Limit
RDS(ON) of LDO PMOS
LDO Start-Up
3330p
9
For more information www.linear.com/LTC3330
LTC3330
pin FuncTions
BAL (Pin 1): Supercapacitor Balance Point. The common
node of a stack of two supercapacitors is connected to
BAL. A source/sink balancing current of up to 10mA is
available. Tie BAL along with SCAP to GND to disable the
balancer and its associated quiescent current.
SWA (Pin 15): Switch Node for the Buck-Boost Switching
Regulator.Connectanexternalinductorbetweenthisnode
and SWB of value per Table 3.
BAT (Pin 16): Input for Battery. BAT serves as the input
to the buck-boost switching regulator.
SCAP (Pin 2): Supply and Sense Point for Supercapacitor
Balancer. Tie the top of a 2-capacitor stack to SCAP and
the middle of the stack to BAL to activate balancing. Tie
SCAP along with BAL to GND to disable the balancer and
its associated quiescent current.
IPK0, IPK1, IPK2 (Pins 17, 18, 19): IPEAK Select Bits
for the Buck-Boost Switching Regulator. Tie high to V
IN3
or low to GND to select the desired IPEAK (see Table 3).
Do not float.
LDO_OUT (Pin 20): Regulated LDO Output. This output
canbeusedasaquietsupply. Onemodeisprovidedtorun
the LDO as a current limited switch to alternately power
up and power down circuitry without low power modes.
V
(Pin 3): Internal Low Voltage Rail to Serve as Gate
IN2
Drive for Buck NMOS Switch. Connect a 4.7µF (or larger)
capacitor from V to GND. This pin is not intended for
IN2
use as an external system rail.
LDO_IN (Pin 21): Input Voltage for the LDO regulator.
UV3, UV2, UV1, UV0 (Pins 4, 5, 6, 7): UVLO Select Bits
LDO2, LDO1, LDO0(Pins22, 23, 24):LDOVoltageSelect
Bits.TiehightoLDO_INorlowtoGNDtoselectthedesired
LDO_OUT voltage (see Table 2). Do not float.
for the Buck Switching Regulator. Tie high to V
or
IN2
low to GND to select the desired UVLO rising and falling
thresholds (see Table 4). Do not float.
LDO_EN(Pin25):LDOEnableInput.Activehighinputwith
AC1 (Pin 8): Input Connection for Piezoelectric Element
or Other AC Source (used in conjunction with AC2 for
differential AC inputs).
logic levels referenced to LDO_IN. Do not float.
V
(Pin 26): Internal Low Voltage Rail Used by the Priori-
IN3
tizer. Connect a 1µF (or larger) capacitor from V to GND.
AC2 (Pin 9): Input Connection for Piezoelectric Element
or Other AC Source (used in conjunction with AC1 for
differential AC inputs).
IN3
This pin is not intended for use as an external system rail.
PGLDO(Pin27):PowerGoodOutputforLDO_OUT. Logic
level output referenced to an internal maximum rail (see
Operation). PGLDO transitioning high indicates 92.5%
(typical)regulationhasbeenreachedonLDO_OUT.PGLDO
remains high until LDO_OUT falls to 90.0% (typical) of
the programmed regulation point.
V (Pin 10): Rectified Input Voltage. A capacitor on this
IN
pin serves as an energy reservoir and input supply for the
buck regulator. The V voltage is internally clamped to a
IN
maximum of 20V (typical).
CAP (Pin 11): Internal Rail Referenced to V to Serve
IN
PGVOUT (Pin 28): Power Good Output for V . Logic
as Gate Drive for Buck PMOS Switch. Connect a 1μF (or
OUT
level output referenced to an internal maximum rail (see
larger) capacitor between CAP and V . This pin is not
IN
Operation). PGVOUT transitioning high indicates regula-
intended for use as an external system rail.
tion has been reached on V
(V
= Sleep Rising).
OUT
OUT
SW (Pin 12): Switch Node for the Buck Switching Regula-
PGVOUT remains high until V
falls to 92.5% (typical)
OUT
tor. Connect a 22µH or greater external inductor between
of the programmed regulation point.
this node and V
.
OUT
BAT_ON (Pin 29): Switcher Status. Logic level output
V
(Pin 13): Regulated Output Voltage Derived from the
OUT
referenced to V . EH_ON is high when the buck switch-
IN3
Buck or Buck-Boost Switching Regulator.
ing regulator is in use. It is pulled low when buck-boost
SWB (Pin 14): Switch Node for the Buck-Boost Switching
Regulator.Connectanexternalinductorbetweenthisnode
and SWA of value per Table 3.
switching regulator is in use.
3330p
10
For more information www.linear.com/LTC3330
LTC3330
pin FuncTions
OUT0,OUT1,OUT2(Pins30,31,32):V
VoltageSelect
GND (Exposed Pad Pin 11): Ground. The exposed pad
must be connected to a continuous ground plane on the
second layer of the printed circuit board by several vias
directly under the LTC3330.
OUT
Bits. Tie high to V or low to GND to select the desired
IN3
V
OUT
(see Table 1). Do not float.
block DiagraM
V
IN
10
20V
INTERNAL
RAIL
GENERATION
UVLO
AC1
8
UVLO_SET
CAP
11
SW
12
AC2
9
V
IN2
3
V
IN3
26
BUCK
CONTROL
SLEEP
BANDGAP
REFERENCE
V
PRIORITZER
GND
SWA
SWB
REF
33
15
BAT
16
29
14
13
EH_ON
V
OUT
BUCK-BOOST
CONTROL
ILIM_SET
SLEEP
V
REF
–
+
+
–
PGVOUT
PGLDO
LDO_EN
LDO_IN
SLEEP
28
27
25
21
V
REF
–
0.925*V
REF
–
+
+
0.9*V
REF
LDO_OUT
SCAP
20
1
+
–
UVLO_SET
ILIM_SET
BAL
2
4
3
3
3
UV[3:0]
IPK[2:0]
OUT[2:0]
LDO[2:0]
4, 5, 6, 7
19, 18, 17
32, 31, 30
22, 23, 24
3330 BD
3330p
11
For more information www.linear.com/LTC3330
LTC3330
operaTion
Modes of Operation
Table 3. ILIM Selection
IPK
0
IPK
0
IPK
0
I
L
MIN
2
1
0
LIM
The following four tables detail all programmable settings
on the LTC3330.
5mA
10mA
15mA
25mA
50mA
100mA
150mA
250mA
1100µH
560µH
360µH
220µH
110µH
56µH
0
0
1
0
1
0
Table 1. Output Voltage Selection
0
1
1
OUT2
OUT1
OUT2
V
1
0
0
OUT
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1.8V
2.5V
2.8V
3.0V
3.3V
3.6V
4.5V
5.0V
1
0
1
1
1
0
36µH
1
1
1
22µH
Table 4. VIN UVLO Threshold Selection
UVLO
UVLO
UV3
0
UV2
0
UV1
0
UV0
0
RISING
FALLING
4V
5V
3V
4V
0
0
0
1
0
0
1
0
6V
5V
Table 2. LDO Voltage Selection
0
0
1
1
7V
6V
LDO2
LDO1
LDO0
LDO_OUT
1.2V
0
1
0
0
8V
7V
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
8V
5V
1.5V
0
1
1
0
10V
10V
12V
12V
14V
14V
16V
16V
18V
18V
9V
1.8V
0
1
1
1
5V
2.0V
1
0
0
0
11V
5V
2.5V
1
0
0
1
3.0V
1
0
1
0
13V
5V
3.3V
1
0
1
1
= LDO_IN
1
1
0
0
15V
5V
1
1
0
1
1
1
1
0
17V
5V
1
1
1
1
3330p
12
For more information www.linear.com/LTC3330
LTC3330
operaTion
OVERVIEW
quiescent current (450nA typical) in UVLO allows energy
to accumulate on the input capacitor in situations where
energy must be harvested from low power sources.
The LTC3330 combines a buck switching regulator and
a buck-boost switching regulator to produce an energy
harvestingsolutionwithbatterybackup.Theconvertersare
controlled by a prioritizer that selects which converter to
usebasedontheavailabilityofabatteryand/orharvestable
energy. If harvested energy is available the buck regula-
tor is active and the buck-boost is OFF. With an optional
LDO and supercapacitor balancer and an array of different
configurations the LTC3330 suits many applications.
INTERNAL RAIL GENERATION
Two internal rails, CAP and V , are generated from V
IN2
IN
and are used to drive the high side PMOS and low side
NMOSofthebuckconverter,respectively.Additionallythe
V
rail serves as logic high for the UVLO threshold select
IN2
bits UV[3:0]. The V rail is regulated at 4.8V above GND
IN2
while the CAP rail is regulated at 4.8V below V . These are
IN
BUCK CONVERTER
not intended to be used as external rails. Bypass capaci-
tors are connected to the CAP and V pins to serve as
IN2
The synchronous buck converter is an ultralow quiescent
currentpowersupplytailoredtoenergyharvestingapplica-
tions. It is designed to interface directly to a piezoelectric
or alternative A/C power source, rectify the input voltage,
and store harvested energy on an external capacitor while
maintaining a regulated output voltage. It can also bleed
off any excess input power via an internal shunt regulator.
energy reservoirs for driving the buck switches. When V
IN
is below 4.8V, V is equal to V and CAP is held at GND.
IN2
IN
Figure 1 shows the ideal V , V and CAP relationship.
IN IN2
18
16
14
V
IN
12
10
8
INTERNAL BRIDGE RECTIFIER
An internal full-wave bridge rectifier accessible via the
differential AC1 and AC2 inputs rectifies AC sources
such as those from a piezoelectric element. The rectified
6
V
IN2
4
CAP
2
output is stored on a capacitor at the V pin and can be
IN
0
used as an energy reservoir for the buck converter. The
bridge rectifier has a total drop of about 800mV with
typical piezo-generated currents (~10μA), but is capable
of carrying up to 50mA. Either side of the bridge can be
operated independently as single-ended AC or DC inputs.
0
5
10
15
V
(V)
IN
3330 F01
Figure 1. Ideal VIN, VIN2 and CAP Relationship
BUCK OPERATION
UNDERVOLTAGE LOCKOUT
The buck regulator uses a hysteretic voltage algorithm
to control the output through internal feedback from the
When the voltage on V rises above the UVLO rising
IN
threshold the buck converter is enabled and charge is
transferred from the input capacitor to the output capaci-
tor. When the input capacitor voltage is depleted below
the UVLO falling threshold the buck converter is disabled.
These thresholds can be set according to Table 4 which
offers UVLO rising thresholds from 4V to 18V with large
or small hysteresis windows (see Table 4). Extremely low
V
OUT
sense pin. The buck converter charges an output
capacitor through an inductor to a value slightly higher
than the regulation point. It does this by ramping the
inductor current up to 260mA through an internal PMOS
switch and then ramping it down to 0mA through an
internal NMOS switch. This efficiently delivers energy to
the output capacitor. The ramp rate is determined by V ,
IN
3330p
13
For more information www.linear.com/LTC3330
LTC3330
operaTion
V
, and the inductor value. When the buck brings the
OUT
comparator determines the mode of operation based on
output voltage into regulation the converter enters a low
quiescentcurrentsleepstatethatmonitorstheoutputvolt-
age with a sleep comparator. During this operating mode
load current is provided by the output capacitor. When the
output voltage falls below the regulation point the buck
regulator wakes up and the cycle repeats. This hysteretic
method of providing a regulated output reduces losses
associated with FET switching and maintains an output
at light loads. The buck delivers a minimum of 100mA of
BAT and V . Figure 2 shows the four internal switches
OUT
of the buck-boost converter. In each mode the inductor
current is ramped up to IPEAK. This IPEAK value is pro-
grammable via IPK[2:0] and ranges from 5mA to 250mA
(see Table 3).
SWA
SWB
M1
M4
BAT
V
OUT
M2
M3
average load current when it is switching. V
from 1.8V to 5V via OUT[2:0] (see Table 1).
can be set
OUT
3330 F02
When the sleep comparator signals that the output has
reached the sleep threshold the buck converter may be in
the middle of a cycle with current still flowing through the
inductor.Normallybothsynchronousswitcheswouldturn
off and the current in the inductor would freewheel to zero
through the NMOS body diode, but the NMOS switch is
kept on to prevent the conduction loss that would occur in
the diode if the NMOS were off. If the PMOS is on when the
sleep comparator trips theNMOS will turn on immediately
in order to ramp down the current. If the NMOS is on it
will be kept on until the current reaches zero.
Figure 2: Buck-Boost Power Switches
In BUCK mode M4 is always on and M3 is always off. The
inductor current is ramped up through M1 to IPEAK and
down to 0mA through M2. In boost mode M1 is always on
and M2 is always off. The inductor current is ramped up
to IPEAK when M3 is on and is ramped to 0mA when M4
is on as V
is greater than BAT in boost mode. Buck-
OUT
boost mode is very similar to boost mode in that M1 is
always on and M2 is always off. If BAT is less than V
OUT
Though the quiescent current when the buck is switching
is much greater than the sleep quiescent current, it is still
a small percentage of the average inductor current which
results in high efficiency over most load conditions. The
buck operates only when sufficient energy has been ac-
cumulated in the input capacitor and the length of time the
converter needs to transfer energy to the output is much
less than the time it takes to accumulate energy. Thus, the
buck operating quiescent current is averaged over a long
period of time so that the total average quiescent current
is low. This feature accommodates sources that harvest
small amounts of ambient energy.
the inductor current is ramped up to IPEAK through M3.
When M4 turns on the current in the inductor will start to
ramp down. However, because BAT is close to V
and
OUT
M1 and M4 have finite on-resistance the current ramp
will exhibit a slow exponential decay, lowering the aver-
age current delivered to V . For this reason the lower
OUT
current threshold is set to IPEAK/2 in buck-boost mode
to maintain high average current to the load. If BAT is
greater than V
in buck-boost mode the inductor cur-
OUT
rent still ramps up to IPEAK and down to IPEAK/2. It can
still ramp down If BAT is greater than V because the
OUT
final value of the current in the inductor is (V – V )/
IN
ON1
OUT
ON4
(R
+ R ). If BAT is exactly IPEAK/2•(R
+ R
)
ON1
ON4
BUCK-BOOST CONVERTER
aboveV
theinductorcurrentwillnotreachtheIPEAK/2
OUT
thresholdandswitchesM1andM4willstayonallthetime.
For higher BAT voltages the mode comparator will switch
the converter to buck mode. M1 and M4 will remain on
Thebuck-boostusesthesamehystereticvoltagealgorithm
as the buck to control the output, V , with the same
OUT
sleep comparator. The buck-boost has three modes of
operation: buck, buck-boost, and boost. An internal mode
for BAT voltages up to V
+ IPEAK•(R
+ R ). At
OUT
ON1
ON4
3330p
14
For more information www.linear.com/LTC3330
LTC3330
operaTion
A digital output, EH_ON, is low when the prioritizer has
selected the BAT input and is high when the prioritizer has
this point the current in the inductor is equal to IPEAK and
the IPEAK comparator will trip turning off M1 and turn-
ing on M2 causing the inductor current to ramp down to
IZERO, completing the transition from buck-boost mode
to buck mode.
selected the V input. The EH_ON output is referenced
IN
to V
.
IN3
Low Drop Out Regulator
V
Power Good
OUT
Anintegratedlowdropoutregulator(LDO)isavailablewith
its own input, LDO_IN. It will regulate LDO_OUT to seven
different output voltages based on the LDO[2:0] pins. An
eighth mode is provided to turn the LDO into a current-
limited switch in which the PMOS is always on. LDO_EN
enables the LDO when high and when low eliminates all
quiescent current on LDO_IN. The LDO is designed to
provide 50mA over a range of LDO_IN and LDO_OUT
combinations. A current limit set above 50mA is available
to dial back the current if the output is grounded or the
load demands more than 50mA. The LDO also features a
1ms soft-start for smooth output start-up.
A power good comparator is provided for the V
out-
OUT
put. It transitions high the first time the LTC3330 goes
to sleep, indicating that V has reached regulation. It
OUT
OUT
transitions low when V
falls to 92.5% (typical) of its
value at regulation. The PGVOUT output is referenced to
an internal rail that is generated to be the highest of V
,
IN2
BAT, and V
less a Schottky diode drop.
OUT
Prioritizer
TheinputprioritizerontheLTC3330decideswhethertouse
the energy harvesting input or the battery input to power
V
. If a battery is powering the buck-boost converter
A power good signal on the PGLDO pin indicates when
the voltage at LDO_OUT rises above 92.5% (typical) of its
finalvalue, oraftertripped, whentheLDO_OUTfallsbelow
90.0% of that value. The PGLDO output is referenced to
OUT
and harvested energy causes a UVLO rising transition on
V , the prioritizer will shut off the buck-boost and turn on
IN
the buck, orchestrating a smooth transitionthatmaintains
regulation of V . When harvestable energy disappears,
an internal rail that is generated to be the highest of V
,
OUT
IN2
theprioritizerwillfirstpollthebatteryvoltage.Ifthebattery
voltage is above 1.8V the prioritizer will switch back to
the buck-boost while maintaining regulation. If the bat-
tery voltage is below 1.8V the buck-boost is not enabled
BAT, and V
less a Schottky diode drop.
OUT
Supercapacitor
An integrated supercapacitor balancer with 165nA of
quiescent current is available to balance a stack of two
supercapacitors. Typically the input, SCAP, will tie to
and V
cannot be supported until harvestable energy
OUT
is again available. If either BAT or V is grounded, the
IN
prioritizer allows the other input to run if its input is high
V
OUT
to allow for increased energy storage at V
with
OUT
enough for operation.
supercapacitors. The BAL pin is tied to the middle of the
stack and can source and sink 10mA to regulate the BAL
pin’s voltage to half that of the SCAP pin’s voltage. To
disable the balancer and its associated quiescent current
the SCAP and BAL pins can be tied to ground.
When the prioritizer selects the V input the current on
IN
the BAT input drops to zero. However, if the voltage on
BAT is higher than V , 150nA (typical) will appear as
IN2
quiescent current on BAT due to internal level shifting.
This only affects a small range of battery voltages and
UVLO settings.
3330p
15
For more information www.linear.com/LTC3330
LTC3330
Typical applicaTions
3330p
16
For more information www.linear.com/LTC3330
LTC3330
Typical applicaTions
3330p
17
For more information www.linear.com/LTC3330
LTC3330
Typical applicaTions
3330p
18
For more information www.linear.com/LTC3330
LTC3330
package DescripTion
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
UH Package
32-Lead Plastic QFN (5mm × 5mm)
(Reference LTC DWG # 05-08-1693 Rev D)
0.70 ±0.05
5.50 ±0.05
4.10 ±0.05
3.45 ±0.05
3.50 REF
(4 SIDES)
3.45 ±0.05
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
RECOMMENDED SOLDER PAD LAYOUT
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
BOTTOM VIEW—EXPOSED PAD
PIN 1 NOTCH R = 0.30 TYP
OR 0.35 × 45° CHAMFER
R = 0.05
TYP
0.00 – 0.05
R = 0.115
TYP
0.75 ±0.05
5.00 ±0.10
(4 SIDES)
31 32
0.40 ±0.10
PIN 1
TOP MARK
(NOTE 6)
1
2
3.45 ±0.10
3.50 REF
(4-SIDES)
3.45 ±0.10
(UH32) QFN 0406 REV D
0.200 REF
0.25 ±0.05
0.50 BSC
NOTE:
1. DRAWING PROPOSED TO BE A JEDEC PACKAGE OUTLINE
M0-220 VARIATION WHHD-(X) (TO BE APPROVED)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
3330p
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
19
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
LTC3330
Typical applicaTion
UPS System for Wireless Mesh Networks with Output Supercapacitor Energy Storage
PIEZO
MIDE V25W
AC1
AC2
SW
100µH
100µH
V
IN
LTC3330
10µF
25V
1µF
6V
SWA
SWB
CAP
V
V
= 3.6V FOR EH_ON = 1
= 2.5V FOR EH_ON = 0
4.7µF, 6V
OUT
OUT
V
V
OUT
IN2
UV3
UV2
UV1
UV0
22µF
6V
10mF
2.5V
SCAP
BAL
10mF
2.5V
V
SUPPLY
T
X
3.65V
BAT
PGOOD
EHORBAT
PGVOUT
EH_ON
1µF
6V
+
IPK2
IPK1
IPK0
OUT2
OUT1
OUT0
Li-SOCI
2
GND
LINEAR TECHNOLOGY DC9003A-A/B
DUST MOTE FOR WIRELESS MESH NETWORKS
V
IN3
1µF
6V
GND
3330 TA02
relaTeD parTs
PART NUMBER DESCRIPTION
COMMENTS
800nA Operating Current, 1.25V/2.5V/4.096V
0.3μA I , Drives 0.01μF, Adjustable Hysteresis, 2V to 11V Input Range
LT1389
LTC1540
LT3009
LTC3108
Nanopower Precision Shunt Voltage Reference
Nanopower Comparator with Reference
Q
3μA I , 20mA Low Dropout Linear Regulator
Low 3μA I , 1.6V to 20V Range, 20mA Output Current
Q
Q
Ultralow Voltage Step-Up Converter and Power
Manager
Operates from 20mV inputs, LDO, Reserve Output, Power Good
LTC3109
Auto-Polarity, Ultralow Voltage Step-Up
Converter and Power Manager
Operates from 30mV Inputs, Auto-Polarity Architecture, LDO, Energy Storage
Capability, Power Good
LTC3388-1/
LTC3388-3
20V High Efficiency Nanopower Step-Down
Regulator
860nA I in Sleep, 2.7V to 20V Input, V : 1.2V to 5.0V, Enable and Standby Pins
Q OUT
LTC3588-1
LTC3588-2
Piezoelectric Energy Harvesting Power Supply
Piezoelectric Energy Harvesting Power Supply
<1μA I in Regulation, 2.7V to 20V Input Range, Integrated Bridge Rectifier
Q
<1μA I in Regulation, UVLO Rising = 16V, UVLO Falling = 14V, V
= 3.45V, 4.1V,
Q
OUT
4.5V, 5.0V
LTC4070
LTC4071
Li-Ion/Polymer Shunt Battery Charger System
450nA I , 1% Float Voltage Accuracy, 50mA Shunt Current 4.0V/4.1V/4.2V
Q
Li-Ion/Polymer Shunt Battery Charger System
with Low Battery Disconnect
550nA I , 1% Float Voltage Accuracy, 50mA Shunt Current 4.0V/4.1V/4.2V, 2.7V or
Q
3.2V Battery Disconnect Levels
3330p
LT 0313 • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
20
●
●
LINEAR TECHNOLOGY CORPORATION 2013
(408)432-1900 FAX: (408) 434-0507 www.linear.com/LTC3330
相关型号：
LTC3350EUHF#PBF
LTC3350 - High Current Supercapacitor Backup Controller and System Monitor; Package: QFN; Pins: 38; Temperature Range: -40°C to 85°C
Linear
©2020 ICPDF网 联系我们和版权申明