LTC3371 [ADI]
20V, 4-Channel Buck DC/DC with 8x Configurable 1.5A Power Stages;
| 型号： | LTC3371 |
| 厂家： | 
ADI |
| 描述： | 20V, 4-Channel Buck DC/DC with 8x Configurable 1.5A Power Stages |
| 文件： | 总28页 (文件大小：1625K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC3376
20V, 4-Channel Buck DC/DC with
8x Configurable 1.5A Power Stages
FEATURES
DESCRIPTION
The LTC®3376 is a highly flexible multioutput power
supply IC. The device includes four synchronous buck
n
Wide V Range: 3V to 20V
IN
n
Wide V
Range: 0.4V to 0.83 • V
OUT
IN
n
n
converters, configured to share eight 1.5A power stages,
powered from independent 3V to 20V inputs. The DC/DCs
are assigned to one of fifteen power configurations via pin
strappable CFG0 to CFG3 pins. The LTC3376 includes the
integration of ceramic capacitors into the package for the
BST pins thereby saving PCB space. The common buck
switching frequency may be programmed with an external
resistor, synchronized to an external oscillator, or set to a
default internal 2MHz clock.
8× 1.5A Buck Power Stages Configurable as 1 to 4
Output Channels
15 Unique Pin Selectable Output Configurations
(1.5A to 12A per Channel)
n
n
Internal Boost Capacitors for Reduced PCB Space
No Load I 27µA 1 Buck Enabled; 42µA All Bucks
Q
Enabled
n
n
1% V
Accuracy on All Channels
OUT
Peak Current Mode Control (Burst Mode®
Operation/Forced Continuous)
The operating mode for all DC/DCs may be programmed
via the SYNC/MODE pin for Burst Mode or forced continu-
ous mode operation. The PGOOD1 to PGOOD4 outputs
indicate when each enabled DC/DC is within a specified
percentage of its final output.
n
n
Precision RUN Inputs, Individual PGOOD Outputs for
Power Sequencing
1MHz to 3MHz Frequency (RT Programmable, PLL
SYNC, or Internal 2MHz Oscillator)
TEMP Pin Output Indicates Die Temperature
Output Current Monitors
n
n
n
Current monitors allow for external monitoring of each
buck’s load. The EXTV pin allows for the internal cir-
CC
Differential Output Sense
cuitry to run from a 3V to 5.5V rail for improved efficiency.
APPLICATIONS
Precision RUN pin thresholds facilitate power-up sequenc-
ing. The LTC3376 is available in a 64 lead 7mm × 7mm
BGA (0.8mm ball pitch).
n
Telecom/Industrial
n
12V Distributed Power Systems
All registered trademarks and trademarks are the property of their respective owners.
TYPICAL APPLICATION
1.5A Buck Efficiency vs ILOAD, VOUT=5V
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ꢀꢁꢂRꢃꢄꢅꢀꢆ
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L DCR = 12mΩ
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ꢀ0
ꢀ0
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ꢀ0
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0
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ꢋꢒꢂꢟ ꢃ ꢠꢃꢉꢡ
ꢋꢒꢂꢟ ꢝ ꢠꢃꢉꢡ
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ꢀ ꢁ0ꢂ
ꢃꢆ ꢁꢌ ꢍ0ꢆ
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ꢂꢂꢐꢑ
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ꢀꢁRꢂꢃꢄ ꢂꢁꢅꢆꢇꢅꢈꢁꢈꢉ ꢊꢁꢄꢃ
ꢀ0ꢁ ꢀ00ꢁ
ꢀꢁꢂꢃ ꢄꢅRRꢆꢇꢈ ꢉꢂꢊ
ꢃꢆ ꢁꢌ ꢞꢜꢞꢆ
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ꢖꢗꢁꢆ
ꢂꢂ
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ꢎꢣꢈꢂꢊꢙꢌꢛꢖ
ꢂꢔꢚꢤꢃꢥ0ꢦ
ꢁꢖꢙꢑ
Rꢁ
ꢀꢀꢁꢂ ꢃꢄꢀ
ꢚꢈꢛ
ꢃꢃꢄꢅ ꢁꢉ0ꢓꢢ
Rev 0
1
Document Feedback
For more information www.analog.com
LTC3376
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
TOP VIEW
V , V
................................................. –0.3V to 22V
CC INA-H
1
2
3
4
5
6
7
8
+
FB1-4 , RUN1-4, CFG1-3, EXTV , PGOOD1-4,
CC
INTV , INTV
SYNC/MODE .................. –0.3V to 6V
CC
CC_P,
A
B
C
D
E
BSTA SWA
V
PGNDA PGNDH
V
SWH BSTH
BSTG SWG
CFG0, RT, TEMP, I
........–0.3V to (INTV + 0.3V)
INA
INH
MON1-4
CC
INTV – INTV
................................... –0.3V to 0.3V
CC
CC_P
SWB BSTB INTV
V
GND INTV
CC
–
CC
CC_P
–
–
FB1-4 ....................................................... –0.3V to 0.3V
I
..................................................................5mA
V
EXTV
FB1
RUN1 RUN4 FB4
TEMP
V
ING
PGOOD1-4
INB
CC
Operating Junction Temperature
+
+
+
PGNDB PGOOD1 I
PGNDC PGOOD2 I
FB1
FB2
FB4
FB3
I
I
PGOOD4 PGNDG
PGOOD3 PGNDF
MON1
MON4
(Notes 2, 3)............................................ –40°C to 125°C
Storage Temperature Range .................. –65°C to 150°C
Maximum Reflow (Package Body) Temperature ... 260ºC
+
MON2
–
MON3
F
–
V
CFG0 FB2
RUN2 RUN3 FB3
CFG3
V
INF
INC
G
H
SWC BSTC SYNC/MODE CFG2 RT
CFG1 BSTF SWF
BSTD
SWD
V
IND
PGNDD PGNDE
V
INE
SWE
BSTE
BGA PACKAGE
64-Lead (7.00mm × 7.00mm × 1.34mm)
T
= 125°C, θ = 35°C/W, 0.8mm Ball Pitch
JMAX
JA
θ
= 23˚C/W, θ
= 16˚C/W
JCBOTTOM
JCTOP
θ Values Determined per JESD51-12
ORDER INFORMATION
PART MARKING*
PACKAGE
TYPE
MSL
TEMPERATURE RANGE
(SEE NOTE 2)
PART NUMBER
LTC3376EY#PBF
LTC3376IY#PBF
PAD OR BALL FINISH
DEVICE
LTC3376
LTC3376
FINISH CODE
RATING
–40°C to 125°C
–40°C to 125°C
SAC305 (RoHS)
e1
BGA
3
• Contact the factory for parts specified with wider operating temperature
ranges. *Pad or ball finish code is per IPC/JEDEC J-STD-609.
• Recommended LGA and BGA PCB Assembly and Manufacturing
Procedures
• Device temperature grade is indicated by a label on the shipping container.
• LGA and BGA Package and Tray Drawings
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating
temperature range, otherwise specifications are at TA = 25°C (Note 2). VCC = VINA-H = 12V, RT tied to INTVCC, VFB1-4¯ = 0V, unless
otherwise stated.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
l
V
V
V
Voltage Range
3
20
V
CC
CC
CC
I
Input Supply Current, EXTV = 0V
All Bucks in Shutdown
9
15
90
30
µA
µA
VCC
CC
+
1 Buck on, Sleeping, V = 0.41V
61
17
4.5
FB
Each Additional Buck, Sleeping
µA
1 Buck on (Configured to 1 Power Stage),
mA
SYNC/MODE = INTV (Note 3)
CC
V
CC
Input Supply Current, EXTV = 3.3V
At Least One Buck On
7
12
µA
CC
Rev 0
2
For more information www.analog.com
LTC3376
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating
temperature range, otherwise specifications are at TA = 25°C (Note 2). VCC = VINA-H = 12V, RT tied to INTVCC, VFB1-4¯ = 0V, unless
otherwise stated.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
+
Total System Current Bootstrapped
1 Buck on, Sleeping, V = 0.41V (Note 4)
27
32
42
µA
µA
µA
FB
+
2 Bucks on, Sleeping, V = 0.41V (Note 4)
FB
All Bucks on (Note 4)
+
EXTV Input Supply Current, EXTV = 3.3V 1 Buck on, Sleep, V = 0.41V
56
17
4.5
85
30
µA
µA
mA
CC
CC
FB
Each Additional Buck, Sleep
1 Buck on (Configured to 1 Power Stage),
SYNC/MODE = INTV (Note 3)
CC
l
Undervoltage Threshold on INTV
INTV Voltage Falling
2.55
2.6
2.65
V
CC
CC
Undervoltage Hysteresis on INTV
Internal Oscillator Frequency
250
mV
CC
l
l
f
osc
RT = INTV , SYNC/MODE = 0V
1.84
1.84
2
2
2.16
2.16
MHz
MHz
CC
RT = 402k, SYNC/MODE = 0V
l
Synchronization Frequency
1
3
MHz
External Low Voltage Supply (If Used)
l
l
EXTV
Optional External Supply Range
Undervoltage Threshold on EXTV
3
5.5
V
V
CC
EXTV Voltage Falling
2.8
2.85
75
2.95
CC
CC
Undervoltage Hysteresis on EXTV
mV
CC
1.5A Buck Regulators
l
l
V
IN
Buck Input Voltage Range
3
20
V
Undervoltage Threshold on V
V
Voltage Falling
IN
2.5
2.6
0.2
2.7
V
V
IN
Hysteresis
V
INA-H
Input Supply Current, V
= 12V
All Bucks Off
INA-H
V
V
, V , V , V
0.7
0
1.4
1.4
µA
µA
INB INC INF ING
, V , V , V
INA IND INE INH
+
Buck On, Sleeping, V = 0.41V
FB
V
V
, V , V , V
INA IND INE INH
0.7
0
µA
µA
INB INC INF ING
, V , V , V
Buck On, SYNC/MODE=INTV
(Note 5)
5.2
2.62
400
mA
A
CC
Top Switch Current Limit, Duty < 18%
Feedback Regulation Voltage
Feedback Leakage Current
2.3
396
–30
3.0
404
30
+
l
l
V
mV
nA
FB
+
+
I
FB
V
FB
= 0.41V
Minimum Off-Time
90
53
140
85
ns
Minimum On-Time
ns
Top Switch Power FET On-Resistance
Bottom Switch Power FET On-Resistance
Top Switch Power FET Leakage
Bottom Switch Power FET Leakage
SW Pull-Down Resistance in Shutdown
Soft-Start Time
170
90
mΩ
mΩ
µA
V
V
= 20V, SWA-H = 0V
= SWA-H = 20V
0.1
1
INA-H
0.003
µA
INA-H
RUN1-4 = 0V per Output Channel
(Note 6)
1
1
kΩ
ms
l
t
SS
0.3
2.5
Start-Up Delay Time
Starting Up from All EN’s Low
When at Least One EN Is Already High
100
40
250
100
500
250
µs
µs
+
+
l
l
PGOOD Lower Threshold
V
Falling, Percentage of Regulated V
95
96.75
1
98.5
%
%
%
%
µs
FB
FB
PGOOD Lower Threshold Hysteresis
PGOOD Upper Threshold
+
+
V
Rising, Percentage of Regulated V
104.5
107.5
2.5
110.5
FB
FB
PGOOD Upper Threshold Hysteresis
PGOOD Filtering Time
100
Rev 0
3
For more information www.analog.com
LTC3376
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating
temperature range, otherwise specifications are at TA = 25°C (Note 2). VCC = VINA-H = 12V, RT tied to INTVCC, VFB1-4¯ = 0V, unless
otherwise stated.
SYMBOL
Buck Regulators Combined
Top Switch Current Limit, Duty < 18%
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
1 Buck with 2 Power Stages Combined (Note 5)
1 Buck with 3 Power Stages Combined (Note 5)
1 Buck with 4 Power Stages Combined (Note 5)
1 Buck with 5 Power Stages Combined (Note 5)
1 Buck with 6 Power Stages Combined (Note 5)
1 Buck with 7 Power Stages Combined (Note 5)
1 Buck with 8 Power Stages Combined (Note 5)
5.25
7.88
10.5
13.1
15.8
18.4
21
A
A
A
A
A
A
A
Temperature Monitor
VTEMP(ROOM) TEMP Voltage at 25°C
220
0.9
250
10
280
1.1
mV
mV/°C
°C
∆V
OT
V
Slope
TEMP
TEMP/°C
Overtemperature Shutdown (Note 7)
Overtemperature Hysteresis
Temperature Rising
165
10
°C
Current Monitors
I
I
I
Voltage at 1.5A Load
Voltage at No Load
Slope
R
= 10k, Duty Cycle = 25%
IMON
1
0
V
V
MON1-4
MON1-4
MON1-4
SYNC/MODE = INTV
CC
R
= 10k
0.667
V/A
IMON
Interface Logic Pins (CFG0-3, SYNC/MODE, PGOOD1-4)
I
Output High Leakage Current
Output Low Voltage
PGOOD1-4 at 5.5V
1
µA
V
OH
V
V
V
PGOOD1-4, 3mA into Pin
CFG0-3, SYNC/MODE
CFG0-3, SYNC/MODE
0.03
0.4
OL
IH
IL
l
l
Input High Threshold
1.2
V
Input Low Threshold
0.4
V
I
I
Input High, Low Leakage Current
CFG0-3 Pins at INTV & 0V
1
1
µA
µA
IH, IL
CC
SYNC/MODE Pin at 5.5V & 0V
Interface Logic Pins (RUN1-4)
RUN Rising Threshold
l
l
First Regulator Turning On
One Regulator or More Already in Use
350
280
730
300
1200
320
mV
mV
RUN Falling Threshold
RUN Falling Threshold
Last Regulator Turning Off
690
200
mV
mV
l
One Regulator or More Kept On
180
220
1
RUN Pin Leakage Current
RUN1-4 = 5.5V
µA
Rev 0
4
For more information www.analog.com
LTC3376
ELECTRICAL CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 3: There will be additional switching current on V
Note 4: Total System current is defined as total current from V + V
pins.
INA-H
CC
INA-H
when all bucks are on (in Sleep), V = V
= 12V, and EXTV is boot-
CC
INA-H
CC
strapped to run off of a 3.3V buck.
Note 2: The LTC3376 is tested under pulsed load conditions such
Note 5: The current limit features of this part are intended to protect the
IC from short term or intermittent fault conditions. Continuous operation
above the specified maximum pin current rating may result in device
degradation over time.
that T ~ T . The LTC3376E is guaranteed to meet specifications from
J
A
0°C to 85°C junction temperature. Specifications over the –40°C to
125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LTC3376I is guaranteed over the –40°C to 125°C operating junction
temperature range. High junction temperatures degrade operating
lifetimes; operating lifetime is derated for junction temperatures greater
than 125°C. Note that the maximum ambient temperature consistent
with these specifications is determined by specific operating conditions
in conjunction with board layout, the rated package thermal impedance
Note 6: The Soft-Start Time is the time from the start of switching until
+
–
V
FB
– V reaches 360mV.
FB
Note 7: The LTC3376 includes overtemperature protection which protects
the device during momentary overload conditions. Junction temperature
exceeds the maximum operating junction temperature when overtemperature
protection is active. Continuous operation above the specified maximum
operating junction temperature may impair device reliability.
and other environmental factors. The junction temperature (T in °C) is
J
calculated from ambient temperature (T in °C) and power dissipation (P
A
D
in Watts) according to the formula:
T = T + (P • θ )
J
A
D
JA
where θ (in °C/W) is the package thermal impedance.
JA
Rev 0
5
For more information www.analog.com
LTC3376
TA = 25°C, unless otherwise noted.
TYPICAL PERFORMANCE CHARACTERISTICS
INTVCC Undervoltage Threshold
vs Temperature
EXTVCC Undervoltage Threshold
vs Temperature
VIN Undervoltage Threshold vs
Temperature
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ꢀꢁꢂ0
ꢀꢁꢂꢃ
ꢀꢁꢂ0
ꢀꢁꢂꢃ
ꢀꢁꢂ0
ꢀꢁꢂꢂ
ꢀꢁꢂ0
ꢀꢁꢂꢃ
ꢀꢁꢂ0
ꢀꢁꢂꢃ
ꢀꢁꢂ0
ꢀꢁꢂꢃ
ꢀꢁꢂ0
ꢀꢁꢂꢂ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢀ
ꢀꢁꢂꢃ
ꢀꢁꢂ0
ꢀꢁꢂꢃ
ꢀꢁꢂꢂ
ꢀꢁꢂꢃ
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Rꢀꢁꢀꢂꢃ
ꢀꢁꢂꢂꢃꢄꢅ
Rꢀꢁꢀꢂꢃ
ꢀꢁꢂꢂꢃꢄꢅ
Rꢀꢁꢀꢂꢃ
ꢀꢁꢂꢂꢃꢄꢅ
ꢀꢁ0 ꢀꢁꢂ
0
ꢀꢁ
ꢀ0
ꢀꢁ ꢀ00 ꢀꢁꢂ
ꢀꢁ0 ꢀꢁꢂ
0
ꢀꢁ
ꢀ0
ꢀꢁ ꢀ00 ꢀꢁꢂ
ꢀꢁ0 ꢀꢁꢂ
0
ꢀꢁ
ꢀ0
ꢀꢁ ꢀ00 ꢀꢁꢂ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢀꢀꢁꢂ ꢃ0ꢀ
ꢀꢀꢁꢂ ꢃ0ꢄ
ꢀꢀꢁꢂ ꢃ0ꢄ
Total System Current vs
Temperature with One Buck On
(Sleeping, Bootstrapped)
VCC Current vs Temperature with
One Buck On (Sleeping, Not
Bootstrapped)
V
CC Current vs Temperature with
All Bucks in Shutdown
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢀ
ꢀ0
ꢀ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢀ
ꢀ0
ꢀ0
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢀ
ꢀ0
ꢀ
ꢀꢁ
ꢀ ꢁ ꢀ ꢁꢂꢃ
ꢀꢀ
ꢀ
ꢀ
ꢀ ꢁꢂꢃ
ꢀꢀ
ꢀꢁ ꢀ00 ꢀꢁꢂ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢀ
ꢀ ꢁꢂꢃ
ꢀꢀ
ꢀ
ꢀꢁꢂ
ꢀ ꢁꢂꢁꢃ
ꢀ
ꢀꢁ0 ꢀꢁꢂ
0
ꢀꢁ
ꢀ0
ꢀꢁ0 ꢀꢁꢂ
0
ꢀꢁ
ꢀ0
ꢀꢁ ꢀ00 ꢀꢁꢂ
ꢀꢁ0 ꢀꢁꢂ
0
ꢀꢁ
ꢀ0
ꢀꢁ ꢀ00 ꢀꢁꢂ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢀꢀꢁꢂ ꢃ0ꢄ
ꢀꢀꢁꢂ ꢃ0ꢄ
ꢀꢀꢁꢂ ꢃ0ꢂ
VIN Current vs Temperature
(Forced Continuous Mode, One
Power Stage)
VCC Current vs Temperature with
One Buck On (Forced Continuous
Mode, One Power Stage)
V
IN Current vs Temperature
(Sleeping)
ꢀꢁꢀ0
ꢀꢁꢂꢃ
ꢀꢁꢂꢀ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢂ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂ0
ꢀꢁ00
ꢀꢁꢂꢃ
ꢀꢁꢂ0
ꢀꢁꢀꢂ
ꢀꢁ00
ꢀꢁꢂꢃ
ꢀꢁꢂ0
ꢀꢁꢂꢃ
ꢀꢁ00
0ꢀꢁꢂ
0ꢀꢁ0
ꢀꢁꢂ0
ꢀꢁꢂ0
ꢀꢁꢂ0
ꢀꢁꢂ0
ꢀꢁꢂ0
ꢀꢁꢀ0
ꢀꢁꢂ0
ꢀꢁꢂ0
ꢀꢁꢂ0
ꢀꢁꢂ0
ꢀꢁꢂ0
ꢀ
ꢀ ꢁꢂꢁꢃ
ꢀꢁꢂ
ꢀ
ꢀ ꢁ ꢀ ꢁꢂꢃ
ꢀꢀ
ꢀꢁ
ꢀ
ꢀ ꢁꢂꢃ
ꢀꢁ
ꢀ
ꢀ ꢁꢂꢁꢃ
ꢀꢁꢂ
ꢀꢁ ꢀ00 ꢀꢁꢂ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢀ
ꢀꢁꢂ
ꢀ ꢁꢂꢁꢃ
ꢀꢁ0 ꢀꢁꢂ
0
ꢀꢁ
ꢀ0
ꢀꢁ0 ꢀꢁꢂ
0
ꢀꢁ
ꢀ0
ꢀꢁ ꢀ00 ꢀꢁꢂ
ꢀꢁ0 ꢀꢁꢂ
0
ꢀꢁ
ꢀ0
ꢀꢁ ꢀ00 ꢀꢁꢂ
ꢀꢀꢁꢂ ꢃ0ꢁ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢀꢀꢁꢂ ꢃ0ꢄ
ꢀꢀꢁꢂ ꢃ0ꢄ
Rev 0
6
For more information www.analog.com
LTC3376
TA = 25°C, unless otherwise noted.
TYPICAL PERFORMANCE CHARACTERISTICS
RT-Programmed Oscillator
Frequency vs Temperature
Default Oscillator Frequency vs
Temperature
Oscillator Frequency vs RT
ꢀꢁ0ꢂ
ꢀꢁ0ꢀ
ꢀꢁ0ꢂ
ꢀꢁ00
ꢀꢁꢂꢂ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁ00ꢂ
ꢀꢁ00ꢂ
ꢀꢁ000
ꢀꢁꢂꢂꢃ
ꢀꢁꢂꢂꢃ
ꢀꢁꢂꢃꢃ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃ0
ꢀꢁꢂ0
ꢀꢁ00
ꢀꢁꢂ0
ꢀꢁ00
ꢀꢁꢂ0
ꢀꢁ00
0ꢀꢁ0
0
R
ꢀ
ꢀ ꢁꢂꢃꢄ
ꢀꢀ
R
ꢀ
= 402kΩ
ꢀꢁ0 ꢀꢁꢂ
0
ꢀꢁ
ꢀ0
ꢀꢁ ꢀ00 ꢀꢁꢂ
ꢀꢁ0
ꢀꢁ0
ꢀꢀ0
ꢀꢁ0
ꢀꢁ0
ꢀꢁ0
ꢀ00
ꢀꢁ0 ꢀꢁꢂ
0
ꢀꢁ
ꢀ0
ꢀꢁ ꢀ00 ꢀꢁꢂ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
RT PIN RESISTANCE (kΩ)
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢀꢀꢁꢂ ꢃꢄꢄ
ꢀꢀꢁꢂ ꢃꢄꢅ
ꢀꢀꢁꢂ ꢃꢄ0
RUN Pin Rising Threshold vs
Temperature
RUN Pin Threshold vs
Temperature
V
TEMP vs Temperature
ꢀꢁꢂꢃ
ꢀꢁ00
0ꢀꢁꢂ
0ꢀꢁ0
0ꢀꢁꢂ
0
ꢀ00
ꢀꢁ0
ꢀ00
ꢀꢁ0
ꢀ00
ꢀꢁ0
ꢀ00
ꢀꢀ0
ꢀ00
ꢀꢁ0
ꢀ00
ꢀꢁ0
ꢀꢁ0
ꢀꢁ0
ꢀꢁ0
ꢀꢁ0
ꢀꢁ0
ꢀꢁ0
ꢀꢀ0
ꢀꢁ0
ꢀ00
ꢀꢁ0
ꢀꢁꢁ ꢂꢃꢄeꢅ Rꢆꢇ
ꢀꢁꢂꢃ ꢄꢅꢆ
ꢀꢁ ꢂeꢃꢄꢁ ꢅꢆe ꢅꢁꢇeꢈ
Rꢀꢁ ꢂꢃꢄ ꢅꢃꢆꢅ
Rꢀꢁꢀꢂꢃ
ꢀꢁꢂꢂꢃꢄꢅ
ꢀꢁꢂꢃꢄꢅ ꢆ
ꢀꢁeꢂꢃ ꢄ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀ0ꢁꢂꢃ
ꢀ0ꢁꢂ0
ꢀꢁ0 ꢀꢁꢂ
0
ꢀꢁ
ꢀ0
ꢀꢁ ꢀ00 ꢀꢁꢂ
ꢀꢁ0 ꢀꢁꢂ
0
ꢀꢁ
ꢀ0
ꢀꢁ ꢀ00 ꢀꢁꢂ
ꢀꢁ0 ꢀꢁꢂ
0
ꢀꢁ
ꢀ0
ꢀꢁ ꢀ00 ꢀꢁꢂ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢀꢀꢁꢂ ꢃꢄꢅ
ꢀꢀꢁꢂ ꢃꢄꢅ
ꢀꢀꢁꢂ ꢃꢄꢀ
Rev 0
7
For more information www.analog.com
LTC3376
TA = 25°C, unless otherwise noted.
TYPICAL PERFORMANCE CHARACTERISTICS
Top Switch Current Limit vs
Top Switch Leakage vs
VFB+ – VFB– vs Temperature
Temperature
Temperature
ꢀ0ꢀꢁ0
ꢀ0ꢁꢂꢃ
ꢀ0ꢁꢂꢀ
ꢀ0ꢁꢂꢃ
ꢀ00ꢁꢂ
ꢀ00ꢁ0
ꢀꢁꢁꢂꢃ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃ0
ꢀꢁꢂꢃ
ꢀꢁꢂꢀ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂ0
ꢀꢁꢂꢃ
ꢀꢁꢂꢂ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
0ꢀꢁ
0ꢀꢁ
0ꢀꢁ
0ꢀꢁ
0ꢀꢁ
0ꢀꢁ
0ꢀꢁ
0ꢀꢁ
0
ꢀ
ꢀ
ꢀ 0
ꢀ ꢁꢂ0ꢃꢄ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁ0 ꢀꢁꢂ
0
ꢀꢁ
ꢀ0
ꢀꢁ ꢀ00 ꢀꢁꢂ
ꢀꢁ0 ꢀꢁꢂ
0
ꢀꢁ
ꢀ0
ꢀꢁ ꢀ00 ꢀꢁꢂ
ꢀꢁ0 ꢀꢁꢂ
0
ꢀꢁ
ꢀ0
ꢀꢁ ꢀ00 ꢀꢁꢂ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢀꢀꢁꢂ ꢃꢄꢁ
ꢀꢀꢁꢂ ꢃꢄꢅ
ꢀꢀꢁꢂ ꢃꢄꢂ
Top Switch RDS(ON) vs
Temperature
Bottom Switch RDS(ON) vs
Temperature
Minimum On-Time vs
Temperature
ꢀꢁ0
ꢀꢁ0
ꢀꢁ0
ꢀꢁ0
ꢀꢁ0
ꢀ00
ꢀꢁ0
ꢀꢁ0
ꢀꢀ0
ꢀ0
ꢀꢁ0
ꢀꢁ0
ꢀꢁ0
ꢀ00
ꢀ0
ꢀꢁ
ꢀꢀ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀꢁ0 ꢀꢁꢂ
0
ꢀꢁ
ꢀ0
ꢀꢁ ꢀ00 ꢀꢁꢂ
ꢀꢁ0 ꢀꢁꢂ
0
ꢀꢁ
ꢀ0
ꢀꢁ ꢀ00 ꢀꢁꢂ
ꢀꢁ0 ꢀꢁꢂ
0
ꢀꢁ
ꢀ0
ꢀꢁ ꢀ00 ꢀꢁꢂ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢀꢀꢁꢂ ꢃꢄꢅ
ꢀꢀꢁꢂ ꢃꢄ0
ꢀꢀꢁꢂ ꢃꢄꢅ
Rev 0
8
For more information www.analog.com
LTC3376
TA = 25°C, unless otherwise noted.
TYPICAL PERFORMANCE CHARACTERISTICS
Minimum Off-Time vs
Temperature
1.5A Buck Efficiency vs ILOAD
,
1.5A Buck Efficiency vs ILOAD
,
VOUT=5V
VOUT=3.3V
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀꢀ
ꢀ00
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
0
ꢀ00
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
0
ꢀꢁꢂꢃꢄ ꢅꢆꢇe
ꢀꢁꢂRꢃꢄꢅꢀꢆ
ꢀ ꢁ ꢂꢃꢄꢅꢆ
L DCR = 12mΩ
ꢀ ꢁ ꢂꢃꢄꢅꢆ
L DCR = 14.5mΩ
ꢀꢁꢂꢃꢄ ꢅꢆꢇe
ꢀꢁꢂRꢃꢄꢅꢀꢆ
ꢀ
ꢀ ꢁꢂꢃꢄ
ꢀ
ꢀ ꢁꢂꢃꢄ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂꢃ ꢀ ꢁꢂꢁꢃ
ꢀꢁꢂꢃ ꢀ ꢁꢂꢁꢃ
ꢀꢀ
ꢀꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ ꢁꢂ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ ꢁꢂ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀ ꢁꢂꢃ
ꢀ ꢁ0ꢂ
ꢀ ꢁꢂ
ꢀ ꢁꢂꢃ
ꢀ ꢁ0ꢂ
ꢀ ꢁꢂ
ꢀ ꢁꢂꢃ
ꢀ ꢁ0ꢂ
ꢀ ꢁꢂꢃ
ꢀ ꢁ0ꢂ
ꢀꢁRꢂꢃꢄ ꢂꢁꢅꢆꢇꢅꢈꢁꢈꢉ ꢊꢁꢄꢃ
ꢀ0ꢁ ꢀ00ꢁ
ꢀꢁꢂꢃ ꢄꢅRRꢆꢇꢈ ꢉꢂꢊ
ꢀꢁRꢂꢃꢄ ꢂꢁꢅꢆꢇꢅꢈꢁꢈꢉ ꢊꢁꢄꢃ
ꢀ0ꢁ ꢀ00ꢁ
ꢀꢁꢂꢃ ꢄꢅRRꢆꢇꢈ ꢉꢂꢊ
ꢀꢀꢁꢂ ꢃꢄꢅ
ꢀꢁ0 ꢀꢁꢂ
0
ꢀꢁ
ꢀ0
ꢀꢁ ꢀ00 ꢀꢁꢂ
ꢀꢁ
ꢀ
ꢀ
ꢀꢁ
ꢀ
ꢀ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢀꢀꢁꢂ ꢃꢄꢄ
ꢀꢀꢁꢂ ꢃꢄꢀ
1.5A Buck Efficiency vs ILOAD
,
1.5A Buck Efficiency vs ILOAD
,
3A Buck Efficiency vs ILOAD
,
VOUT=1.8V
VOUT=1.2V
VOUT=3.3V
ꢀ00
ꢀ0
ꢀ00
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
0
ꢀ00
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
0
ꢀ0
ꢀ ꢁ ꢂꢃꢂꢄꢅ
L DCR = 13.2mΩ
ꢀ ꢁ ꢂꢃꢂꢄꢅ
L DCR = 6.0mΩ
ꢀ0
ꢀꢁꢂꢃꢄ ꢅꢆꢇe
ꢀꢁꢂRꢃꢄꢅꢀꢆ
ꢀꢁꢂꢃꢄ ꢅꢆꢇe
ꢀꢁꢂRꢃꢄꢅꢀꢆ
ꢀꢁꢂꢃꢄ ꢅꢆꢇe
ꢀ ꢁ ꢂꢃꢄꢅꢆ
L DCR = 15mΩ
ꢀ0 ꢀꢁꢂRꢃꢄꢅꢀꢆ
ꢀ
ꢀ ꢁꢂꢃꢄ
ꢀ
ꢀ ꢁꢂꢃꢄ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂꢃ ꢀ ꢁꢂꢁꢃ
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀꢁꢂꢃ ꢀ ꢁꢂꢁꢃ
ꢀꢀ
ꢀꢀ
ꢀ
ꢀ ꢁꢂꢃꢄ
ꢀꢁꢂ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ ꢁꢂꢁꢃ
ꢀ ꢁꢂ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ ꢁꢂ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁꢂꢃ ꢀ ꢁꢂꢁꢃ
ꢀꢀ
ꢀ ꢁꢂꢃ
ꢀ ꢁ0ꢂ
ꢀ ꢁꢂ
ꢀ
ꢀ
ꢀ
ꢀ
ꢃ ꢄꢅꢄꢀ
ꢃ ꢄꢀ
ꢃ ꢄꢅꢄꢀ
ꢃ ꢄꢀ
ꢀ ꢁꢂꢃ
ꢀ ꢁꢂꢁꢃ
ꢀ ꢁꢂ
ꢁꢂ
ꢁꢂ
ꢁꢂ
ꢁꢂ
ꢀ ꢁꢂꢃ
ꢀ ꢁ0ꢂ
ꢀ ꢁꢂꢃ
ꢀꢁRꢂꢃꢄ ꢂꢁꢅꢆꢇꢅꢈꢁꢈꢉ ꢊꢁꢄꢃ
ꢀ0ꢁ ꢀ00ꢁ
ꢀꢁꢂꢃ ꢄꢅRRꢆꢇꢈ ꢉꢂꢊ
ꢀꢁRꢂꢃꢄ ꢂꢁꢅꢆꢇꢅꢈꢁꢈꢉ ꢊꢁꢄꢃ
ꢀ0ꢁ ꢀ00ꢁ
ꢀꢁꢂꢃ ꢄꢅRRꢆꢇꢈ ꢉꢂꢊ
ꢀꢁRꢂꢃꢄ ꢂꢁꢅꢆꢇꢅꢈꢁꢈꢉ ꢊꢁꢄꢃ
ꢀ0ꢁ ꢀ00ꢁ
ꢀꢁꢂꢃ ꢄꢅRRꢆꢇꢈ ꢉꢂꢊ
0
ꢀꢁ
ꢀ
ꢀ
ꢀꢁ
ꢀ
ꢀ
ꢀꢁ
ꢀ
ꢀ
ꢀꢀꢁꢂ ꢃꢄꢅ
ꢀꢀꢁꢂ ꢃꢄꢂ
ꢀꢀꢁꢂ ꢃꢄꢁ
Rev 0
9
For more information www.analog.com
LTC3376
TA = 25°C, unless otherwise noted.
TYPICAL PERFORMANCE CHARACTERISTICS
6A Buck Efficiency vs ILOAD
,
1.5A Buck Efficiency vs Frequency
(Forced Continuous Mode)
1.5A Buck Efficiency vs Frequency
(Forced Continuous Mode)
VOUT=3.3V
ꢀ00
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢀ
ꢀ0
ꢀ00
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢀ
ꢀ0
ꢀ00
ꢀ0
ꢀ0
ꢀ ꢁ ꢂꢃꢂꢄꢅ
L DCR = 3.0mΩ
ꢀ0
ꢀ
ꢀ
ꢀ
ꢀ 0ꢁꢂꢃ
ꢀ 0ꢁꢂꢃ
ꢀ 0ꢁ0ꢂꢃ
ꢀꢁꢂꢃꢄ ꢅꢆꢇe
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀ
ꢀ ꢁꢂ
ꢀꢁ
ꢀꢁ
ꢀ0 ꢀꢁꢂRꢃꢄꢅꢀꢆ
ꢀ
ꢀ ꢁꢂꢃꢄ
ꢀꢁꢂ
ꢀ
ꢀ ꢁꢂꢃ
ꢀꢁꢂꢃ ꢀ ꢁꢂꢁꢃ
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
0
ꢀꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ ꢁꢂ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁꢂꢃ ꢀ ꢁꢂꢁꢃ
ꢀ ꢁꢂꢃ
ꢀ ꢁ0ꢂ
ꢀ ꢁꢂ
ꢀꢁꢂꢃ ꢀ ꢁꢂꢁꢃ
ꢀꢀ
ꢀꢀ
ꢀ
ꢀ ꢁꢂꢃ
ꢀ
ꢀ ꢁꢂꢁꢃ
ꢀꢁ
ꢀꢁꢂ
ꢀ ꢁꢂꢃ
ꢀ ꢁ0ꢂ
ꢀ
ꢀ ꢁꢂꢁꢃ
ꢀꢁꢂ
ꢀ
ꢀ 0ꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀ ꢁ ꢂꢃꢄꢅꢆ
ꢀ ꢁ ꢂꢃꢄꢅꢆ
ꢀꢁꢂ
ꢀꢁRꢂꢃꢄ ꢂꢁꢅꢆꢇꢅꢈꢁꢈꢉ ꢊꢁꢄꢃ
ꢀ
ꢀꢁꢂ
ꢀ
ꢀꢁꢂ
ꢀ
ꢀꢁ
ꢀ0ꢁ
ꢀ00ꢁ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀꢁꢂ
ꢀ
ꢀRꢁꢂꢃꢁꢄꢅꢆ ꢇꢈꢉꢊꢋ
ꢀꢁꢂꢃ ꢄꢅRRꢆꢇꢈ ꢉꢂꢊ
ꢀRꢁꢂꢃꢁꢄꢅꢆ ꢇꢈꢉꢊꢋ
ꢀꢀꢁꢂ ꢃꢀ0
ꢀꢀꢁꢂ ꢃꢄꢅ
ꢀꢀꢁꢂ ꢃꢄꢅ
1.5A Buck Regulator Load
Regulation (Forced Continuous
Mode)
1.5A Buck Regulator Line
Regulation (Forced Continuous
Mode)
1.5 Buck Current Limit vs Duty
Cycle
ꢀꢁꢀꢂ0
ꢀꢁꢀ00
ꢀꢁꢂꢃ0
ꢀꢁꢂꢃ0
ꢀꢁꢂꢃ0
ꢀꢁꢂꢃ0
ꢀꢁꢂꢃ0
ꢀꢁꢂꢃ0
ꢀꢁꢂꢀ0
ꢀꢁꢂꢂ0
ꢀꢁ00
ꢀꢁꢂ0
ꢀꢁꢂ0
ꢀꢁꢂ0
ꢀꢁꢂ0
ꢀꢁꢂ0
ꢀꢁꢂ0
ꢀꢁꢂ0
ꢀꢁꢀ0
ꢀꢁꢂ0
ꢀꢁ00
ꢀꢁꢀꢂ0
ꢀꢁꢀ0ꢂ
ꢀꢁꢀ0ꢂ
ꢀꢁꢀ0ꢂ
ꢀꢁꢀ0ꢂ
ꢀꢁꢀ00
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃꢂ
ꢀꢁꢂꢃ0
ꢀ
ꢀ ꢁꢂꢃꢄ
ꢀꢁꢂ
ꢀ ꢁ ꢂꢃꢄꢅꢆ
ꢀꢁe ꢂꢃ ꢄꢅꢆꢅꢄꢁꢄ
ꢀꢁꢁꢂꢃꢄꢅe
ꢀ
ꢀ ꢁꢂꢃꢄ
ꢀꢁꢂ
ꢀ
ꢀ ꢁꢂꢁꢃ
ꢀꢁꢂ
ꢀ ꢁ ꢂꢃꢄꢅꢆ
ꢀ ꢁꢂꢃ
ꢀ ꢁꢂ0ꢃꢄ
ꢀ
ꢀ
ꢀ
ꢀ ꢁꢂ
ꢀ ꢁꢂꢃ
ꢀ ꢁ0ꢂ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀ
ꢀ ꢁꢂꢃꢄ
ꢀ
ꢀ
ꢀꢁꢂ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀ ꢁ ꢂꢃꢄꢅꢆ
ꢀ
ꢀ
ꢀ
ꢀ0 ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀ0
ꢀꢁꢂ
ꢀ0 ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢀ ꢀ0 ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀ0
ꢀꢁ
ꢀ0ꢁ
ꢀ00ꢁ
ꢀ
ꢀ
ꢀ
ꢀꢁꢂꢃ ꢄꢃꢄꢅꢆ ꢇꢈꢉ
ꢀꢁꢂꢃ ꢄꢅRRꢆꢇꢈ ꢉꢂꢊ
ꢀꢁ
ꢀꢀꢁꢂ ꢃꢀꢄ
ꢀꢀꢁꢂ ꢃꢀꢀ
ꢀꢀꢁꢂ ꢃꢀꢄ
Rev 0
10
For more information www.analog.com
LTC3376
TA = 25°C, unless otherwise noted.
TYPICAL PERFORMANCE CHARACTERISTICS
1.5A Buck Regulator No Load
Start-Up Transient
IMON Voltage vs ILOAD
ꢀꢁ
ꢀ
ꢀꢁꢂ
ꢀꢁꢂꢃꢄꢁ
ꢀ00
ꢀ0
ꢀ
ꢀꢁꢂꢃꢄꢅꢆR
ꢀꢁRRꢂꢃꢄ
ꢀꢁ0ꢂꢃꢄꢅꢆꢇ
ꢀ
ꢀ ꢁꢂꢃ
ꢀꢁ
Rꢀꢁ
ꢀꢁꢂꢃꢄꢁ
ꢀ
ꢀ ꢁꢂꢁꢃ
ꢀꢁꢂ
R
= 10kΩ
ꢀꢁꢂꢃ
ꢀꢀꢁꢂ ꢃꢀꢄ
ꢀ00ꢁꢂꢃꢄꢅꢆ
ꢀ
ꢀ ꢁꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀ ꢁ ꢂꢃꢄꢅꢆ
ꢀ
ꢀ ꢁꢂꢃ
ꢀꢁ
ꢀꢁꢂꢃꢄꢂꢅꢁꢅꢆ ꢇꢁꢈe
ꢀ
ꢀ ꢁꢂꢁꢃ
ꢀꢁꢂ
ꢀ
ꢀ ꢁꢂꢃꢄ
ꢀꢁꢂꢃꢄ ꢅꢆꢇe
ꢀꢁꢂ
0ꢀꢁ
ꢀ ꢁ ꢂꢃꢄꢅꢆ
ꢀꢁ
ꢀ0ꢁ
ꢀ00ꢁ
ꢀ
ꢀ
ꢀꢁꢂꢃ ꢄꢅRRꢆꢇꢈ ꢉꢂꢊ
ꢀꢀꢁꢂ ꢃꢀꢄ
1.5A Buck Regulator, Transient
Response (Forced Continuous
Mode)
1.5A Buck Regulator, Transient
Response (Burst Mode Operation)
ꢀ
ꢀꢁꢂ
ꢀ
ꢀꢁꢂ
ꢀ00ꢁꢂꢃꢄꢅꢂ
ꢀ00ꢁꢂꢃꢄꢅꢂ
ꢀꢁꢂꢁꢃꢄꢅꢆꢇꢈ
ꢀꢁꢂꢁꢃꢄꢅꢆꢇꢈ
ꢀꢁꢂꢃꢄꢅꢆR
ꢀꢁRRꢂꢃꢄ
ꢀ00ꢁꢂꢃꢄꢅꢆ
0ꢀꢁ
ꢀꢁꢂꢃꢄꢅꢆR
ꢀꢁRRꢂꢃꢄ
ꢀ00ꢁꢂꢃꢄꢅꢆ
0ꢀꢁ
ꢀꢀꢁꢂ ꢃꢀꢁ
ꢀꢀꢁꢂ ꢃꢀꢂ
ꢀ0ꢁꢂꢃꢄꢅꢆ
ꢀ0ꢁꢂꢃꢄꢅꢆ
ꢀꢁꢂꢃ ꢄꢅꢆꢇꢈ ꢉꢊ0ꢋꢂ ꢌꢍ ꢉꢎ0ꢊꢂ
ꢀꢁꢂꢃ ꢄꢅꢆꢇꢈ ꢉꢊ0ꢋꢂ ꢌꢍ ꢉꢎ0ꢊꢂ
ꢀ
ꢀ
ꢀ
ꢀ ꢁꢂꢃ
ꢀ ꢁ ꢂꢃꢄꢅꢆ
ꢀ ꢁꢂꢃꢄ
ꢀ
ꢀ
ꢀ
ꢀ ꢁꢂꢃ
ꢀ ꢁ ꢂꢃꢄꢅꢆ
ꢀ ꢁꢂꢃꢄ
ꢀꢁ
ꢀꢁ
ꢀ ꢁꢂ
ꢀ
ꢀ
ꢀ ꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀ ꢁꢁꢂꢃ
ꢀ ꢁꢁꢂꢃ
ꢀꢁꢂ
ꢀꢁꢂ
Rev 0
11
For more information www.analog.com
LTC3376
PIN FUNCTIONS
BSTA (Pin A1): Boost Node for Power Stage A.
BSTB (Pin B2): Boost Node for Power Stage B.
BSTC (Pin G2): Boost Node for Power Stage C.
BSTD (Pin H1): Boost Node for Power Stage D.
BSTE (Pin H8): Boost Node for Power Stage E.
BSTF (Pin G7): Boost Node for Power Stage F.
BSTG (Pin B7): Boost Node for Power Stage G.
BSTH (Pin A8): Boost Node for Power Stage H.
FB3+ (Pin E5): Positive Feedback Pin for Buck Regulator 3.
Receives feedback by a resistor divider connected across
the output.
FB4+ (Pin D5): Positive Feedback Pin for Buck Regulator 4.
Receives feedback by a resistor divider connected across
the output.
FB1– (Pin C3): Negative Feedback Pin for Buck Regulator 1.
Connect directly to the GND side of the feedback resistor
divider that connects across the output.
FB2– (Pin F3): Negative Feedback Pin for Buck Regulator 2.
Connect directly to the GND side of the feedback resistor
divider that connects across the output.
FB3– (Pin F6): Negative Feedback Pin for Buck Regulator 3.
Connect directly to the GND side of the feedback resistor
divider that connects across the output.
FB4– (Pin C6): Negative Feedback Pin for Buck Regulator 4.
Connect directly to the GND side of the feedback resistor
divider that connects across the output.
CFG0 (Pin F2): Configuration Input Bit. With CFG1, CFG2
and CFG3, CFG0 configures the Buck output current power
stage combinations. CFG0 should be tied to either INTVCC
or GND. Do not float.
CFG1 (Pin G6): Configuration Input Bit. With CFG0, CFG2,
and CFG3, CFG1 configures the Buck output current power
stage combinations. CFG1 should be tied to either INTVCC
or GND. Do not float.
CFG2 (Pin G4): Configuration Input Bit. With CFG0, CFG1,
and CFG3, CFG2 configures the Buck output current power
stage combinations. CFG2 should be tied to either INTVCC
or GND. Do not float.
GND (Pin B5): LTC3376 Ground Pin. Connect this pin
to system ground and to the ground plane. Do not float.
I
(Pin D3): Current Monitor Pin for Buck Regulator 1.
IMON1 outputs a current of 100µA (typical) at 1.5A load
cMuOrrNe1nt for each power stage configured. Connect a
CFG3 (Pin F7): Configuration Input Bit. With CFG0, CFG1
and CFG2, CFG3 configures the Buck output current power
stage combinations. CFG3 should be tied to either INTVCC
or GND. Do not float.
resistor from I
to GND. The value of this resistor
MON1
should be chosen so that I
is 1V at full load (1.5A
per power stage). The IMOMNO1Nv1oltage will decrease by
0.67V/A at lower load currents. The I
output current
MON1
EXTV (Pin C2): External V Low Voltage Supply. The
CC
CC
will be 0 when the regulator is sleeping in Burst Mode or
is disabled.
internal LDO regulator draws current from EXTV instead
CC
of from V when EXTV is tied to a voltage higher than
CC
CC
I
(Pin E3): Current Monitor Pin for Buck Regulator 2.
3V. For output voltages of 3.3V and above this pin can be
IMON2 outputs a current of 100µA (typical) at 1.5A load
tied to that V . If this pin is tied to a supply other than a
cMuOrrNe2nt for each power stage configured. Connect a
OUT
buck output, use a 4.7µF local bypass capacitor on this pin.
resistor from I
to GND. The value of this resistor
MON2
EXTV should be tied to ground if not used. Do not float.
CC
should be chosen so that I
is 1V at full load (1.5A
per power stage). The IMOMNO2Nv2oltage will decrease by
FB1+ (Pin D4): Positive Feedback Pin for Buck Regulator 1.
Receives feedback by a resistor divider connected across
the output.
FB2+ (Pin E4): Positive Feedback Pin for Buck Regulator 2.
Receives feedback by a resistor divider connected across
the output.
0.67V/A at lower load currents. The I
output current
MON2
will be 0 when the regulator is sleeping in Burst Mode or
is disabled.
Rev 0
12
For more information www.analog.com
LTC3376
PIN FUNCTIONS
I
(Pin E6): Current Monitor Pin for Buck Regulator 3.
PGNDD (Pin H4): Ground Supply for Power Stage D.
Connect the GND side of the VIND bypass capacitors
directly to this pin and then to the ground plane.
IMON3 outputs a current of 100µA (typical) at 1.5A load
cMuOrrNe3nt for each power stage configured. Connect a
resistor from I
to GND. The value of this resistor
MON3
PGNDE (Pin H5): Ground Supply for Power Stage E.
Connect the GND side of the VINE bypass capacitors
directly to this pin and then to the ground plane.
should be chosen so that I
is 1V at full load (1.5A
per power stage). The IMOMNO3Nv3oltage will decrease by
0.67V/A at lower load currents. The I
output current
MON3
PGNDF (Pin E8): Ground Supply for Power Stage F.
Connect the GND side of the VINF bypass capacitors
directly to this pin and then to the ground plane.
will be 0 when the regulator is sleeping in Burst Mode or
is disabled.
I
(Pin D6): Current Monitor Pin for Buck Regulator 4.
IMON4 outputs a current of 100µA (typical) at 1.5A load
PGNDG (Pin D8): Ground Supply for Power Stage G.
Connect the GND side of the VING bypass capacitors
directly to this pin and then to the ground plane.
cMuOrrNe4nt for each power stage configured. Connect a
resistor from I
to GND. The value of this resistor
MON4
should be chosen so that I
is 1V at full load (1.5A
per power stage). The IMOMNO4Nv4oltage will decrease by
PGNDH (Pin A5): Ground Supply for Power Stage H.
Connect the GND side of the VINH bypass capacitors
directly to this pin and then to the ground plane.
0.67V/A at lower load currents. The I
output current
MON4
will be 0 when the regulator is sleeping in Burst Mode or
is disabled.
PGOOD1 (Pin D2): Power Good Pin for Buck Regulator 1
(Active High). Open-drain output. This pin is driven low
when Buck 1’s regulated output voltage falls below its
PGOOD threshold or rises above its overvoltage thresh-
old. PGOOD1 is also pulled low in the following scenarios:
if the buck is disabled, if the buck is going through soft-
INTV (Pin B3): Internal 3V V Regulator Bypass Pin.
CC
CC
The control circuits are powered from this voltage. Do not
load the INTV pin with external circuitry exceeding 2mA.
If overloadedCCthe LTC3376 will shut down. INTV cur-
CC
rent is supplied from EXTV if V
> 3V, otherwise
CC
EXTVCC
start, if INTV is below the UVLO threshold, or if the
CC
current is drawn from V . Bypass to GND with a single
CC
LTC3376 is in OT.
4.7µF or larger low ESR ceramic capacitor.
PGOOD2 (Pin E2): Power Good Pin for Buck Regulator 2
(Active High). Open-drain output. This pin is driven low
when Buck 2’s regulated output voltage falls below its
PGOOD threshold or rises above its overvoltage thresh-
old. PGOOD2 is also pulled low in the following scenarios:
if the buck is disabled, if the buck is going through soft-
INTV
(Pin B6): Internal V Power Stage Supply. The
CC
CC_P
internal power drivers are powered from this voltage. The
INTV pin is for internal use only. Bypass to GND with
CC_P
a single 10µF or larger low ESR ceramic capacitor. In all
applications, INTV must connect to INTV .
CC_P
CC
start, if INTV is below the UVLO threshold, or if the
PGNDA (Pin A4): Ground Supply for Power Stage A.
Connect the GND side of the VINA bypass capacitors
directly to this pin and then to the ground plane.
CC
LTC3376 is in OT.
PGOOD3 (Pin E7): Power Good Pin for Buck Regulator 3
(Active High). Open-drain output. This pin is driven low
when Buck 3’s regulated output voltage falls below its
PGOOD threshold or rises above its overvoltage thresh-
old. PGOOD3 is also pulled low in the following scenarios:
if the buck is disabled, if the buck is going through soft-
PGNDB (Pin D1): Ground Supply for Power Stage B.
Connect the GND side of the VINB bypass capacitors
directly to this pin and then to the ground plane.
PGNDC (Pin E1): Ground Supply for Power Stage C.
Connect the GND side of the VINC bypass capacitors
directly to this pin and then to the ground plane.
start, if INTV is below the UVLO threshold, or if the
CC
LTC3376 is in OT.
Rev 0
13
For more information www.analog.com
LTC3376
PIN FUNCTIONS
PGOOD4 (Pin D7): Power Good Pin for Buck Regulator 4
(Active High). Open-drain output. This pin is driven low
when Buck 4’s regulated output voltage falls below its
PGOOD threshold or rises above its overvoltage thresh-
old. PGOOD4 is also pulled low in the following scenarios:
if the buck is disabled, if the buck is going through soft-
SWF (Pin G8): Switch Node for Power Stage F. External
inductor connects to this pin.
SWG (Pin B8): Switch Node for Power Stage G. External
inductor connects to this pin.
SWH (Pin A7): Switch Node for Power Stage H. External
inductor connects to this pin.
start, if INTV is below the UVLO threshold, or if the
CC
LTC3376 is in OT.
SYNC/MODE (Pin G3): Oscillator Synchronization and
Mode Select Pin. Driving SYNC/MODE with an external
clock signal synchronizes all switches to the applied fre-
quency, and configures the buck converters to operate in
forced continuous mode. Slope compensation automati-
cally adapts to the external clock frequency. The absence
of an external clock signal enables the frequency to be
programmed by the RT pin. When not synchronizing to
an external clock this input determines how the LTC3376
operates at light loads. Connecting this pin to ground
selects Burst Mode operation. Connecting this pin to
RT (Pin G5): Timing Resistor Pin for Setting Oscillator
Frequency. This pin provides two modes of setting the
switching frequency when not synchronizing to an exter-
nal clock. Connecting a resistor from RT to GND sets the
switching frequency based on the resistor value. If RT is
tied to INTVCC the default internal 2MHz oscillator is used.
Do not float.
RUN1 (Pin C4): Enable Input for Buck Regulator 1. Active
high. Do not float.
RUN2 (Pin F4): Enable Input for Buck Regulator 2. Active
high. In configurations where the Enable Input for Buck 2
is not used, tie RUN2 to GND. Do not float.
INTV selects forced continuous mode operation. Do
CC
not float.
TEMP (Pin C7): Temperature Indication Pin. TEMP out-
puts a voltage of 250mV (typical) at 25°C. The TEMP
voltage changes by 10mV/°C (typical) giving an external
indication of the LTC3376 internal die temperature.
RUN3 (Pin F5): Enable Input for Buck Regulator 3. Active
high. In configurations where the Enable Input for Buck 3
is not used, tie RUN3 to GND. Do not float.
RUN4 (Pin C5): Enable Input for Buck Regulator 4. Active
high. In configurations where the Enable Input for Buck 4
is not used, tie RUN4 to GND. Do not float.
V
(Pin B4): Internal Bias Supply. Bypass to GND with a
CC
4.7µF or larger ceramic capacitor. V has to be present
even when the EXTVCC pin is usedCaCnd must come up
before EXTV .
CC
SWA (Pin A2): Switch Node for Power Stage A. External
inductor connects to this pin.
V
(Pin A3): Input Supply for Power Stage A. Bypass to
INA
PGNDA with a 1µF ceramic capacitor and 10µF or larger
ceramic capacitor.
SWB (Pin B1): Switch Node for Power Stage B. External
inductor connects to this pin.
V
(Pin C1): Input Supply for Power Stage B. Bypass to
INB
SWC (Pin G1): Switch Node for Power Stage C. External
inductor connects to this pin.
PGNDB with a 1µF ceramic capacitor and 10µF or larger
ceramic capacitor.
SWD (Pin H2): Switch Node for Power Stage D. External
inductor connects to this pin.
V
(Pin F1): Input Supply for Power Stage C. Bypass to
INC
PGNDC with a 1µF ceramic capacitor and 10µF or larger
SWE (Pin H7): Switch Node for Power Stage E. External
inductor connects to this pin.
ceramic capacitor.
Rev 0
14
For more information www.analog.com
LTC3376
PIN FUNCTIONS
VIND (Pin H3): Input Supply for Power Stage D. Bypass to
PGNDD with a 1µF ceramic capacitor and 10µF or larger
ceramic capacitor.
VING (Pin C8): Input Supply for Power Stage G. Bypass to
PGNDG with a 1µF ceramic capacitor and 10µF or larger
ceramic capacitor.
V
(Pin H6): Input Supply for Power Stage E. Bypass to
VINH (Pin A6): Input Supply for Power Stage H. Bypass to
PGNDH with a 1µF ceramic capacitor and 10µF or larger
ceramic capacitor.
INE
PGNDE with a 1µF ceramic capacitor and 10µF or larger
ceramic capacitor.
V
(Pin F8): Input Supply for Power Stage F. Bypass to
INF
PGNDF with a 1µF ceramic capacitor and 10µF or larger
ceramic capacitor.
Rev 0
15
For more information www.analog.com
LTC3376
BLOCK DIAGRAM
ꢓꢔꢂꢉ
ꢉ
ꢊꢊ
ꢊꢊ
ꢋꢄꢉ ꢂꢌ ꢍ0ꢉꢎ
ꢗꢒꢂꢉ
ꢊꢊꢠꢙ
ꢋꢄꢉ ꢂꢌ ꢕꢖꢕꢉꢎ
ꢂꢌ ꢙꢌꢘꢓR ꢁꢂꢃꢐꢓꢁ
ꢀꢁꢂꢃ
ꢗꢒꢂꢉ
ꢊꢊ
ꢙRꢗꢌRꢗꢂꢗꢨꢓR
ꢟ
ꢞ
ꢄꢉ
ꢉ
ꢗꢒꢃ
ꢄꢉ
ꢑꢖꢕꢃ ꢙꢌꢘꢓR
ꢁꢂꢃꢐꢓ ꢃ
ꢂꢓꢛꢙ
ꢂꢓꢛꢙ
ꢛꢌꢒꢗꢂꢌR
ꢁꢘꢃ
ꢙꢐꢒꢇꢃ
Rꢂ
ꢈ
Rꢓꢏ
ꢀꢁꢂꢀ
ꢊꢢꢡ
ꢝꢉ
ꢀꢃꢒꢇꢐꢃꢙ
ꢝꢉꢢꢌ
ꢌꢁꢊꢗꢢꢢꢃꢂꢌR
ꢌꢂ
ꢁꢦꢒꢊꢧꢛꢌꢇꢓ
ꢙꢐꢌꢌꢇꢈ
ꢉ
ꢗꢒꢀ
ꢛꢌꢇꢓ
ꢑꢖꢕꢃ ꢙꢌꢘꢓR
ꢁꢂꢃꢐꢓ ꢀ
ꢁꢘꢀ
ꢙꢐꢒꢇꢀ
ꢁꢇ
ꢀꢁꢂꢊ
ꢙꢐꢌꢌꢇꢄ
ꢙꢐꢌꢌꢇꢍ
ꢙꢐꢌꢌꢇꢑ
ꢉ
ꢗꢒꢊ
ꢑꢖꢕꢃ ꢙꢌꢘꢓR ꢁꢂꢃꢐꢓ
ꢗꢒꢂꢉ
ꢑꢖꢕꢃ ꢙꢌꢘꢓR
ꢁꢂꢃꢐꢓ ꢊ
ꢁꢘꢊ
ꢈ
ꢙꢐꢌꢌꢇ
ꢊꢊꢠꢙ
ꢙꢐꢒꢇꢊ
ꢀꢁꢂꢪ
ꢀꢁꢂꢇ
ꢑ0ꢫꢏ
ꢉ
ꢗꢒꢪ
ꢉ
ꢗꢒꢇ
ꢑꢖꢕꢃ ꢙꢌꢘꢓR
ꢁꢂꢃꢐꢓ ꢇ
ꢛꢒꢂꢌꢙꢪ
ꢁꢘꢇ
ꢙꢐꢒꢇꢇ
ꢁꢘꢪ
ꢢꢌꢐꢗꢊ
ꢗ
ꢈ
ꢗ
ꢛꢌꢒꢑꢜꢈ
ꢛꢌꢒ
ꢗꢒꢂꢉ
ꢊꢊꢠꢙ
ꢀꢁꢂꢓ
ꢁꢇ
Rꢓꢏ ꢊꢢꢡ ꢛꢌꢇꢓ
ꢈ
ꢛꢒꢀꢌꢂꢪ
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ꢗꢒꢓ
ꢑꢖꢕꢃ ꢙꢌꢘꢓR
ꢁꢂꢃꢐꢓ ꢓ
ꢁꢘꢓ
ꢗꢒꢂꢉ
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ꢗꢒꢀ
Rꢝꢒꢑ
ꢙꢐꢒꢇꢪ
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ꢞ
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ꢊꢌꢒꢂRꢌꢢ
ꢏꢀꢑ
ꢀꢁꢂꢏ
Φ ꢣ ꢤ0ꢥ
ꢟ
ꢏꢀꢑ
ꢉ
ꢗꢒꢏ
ꢗꢒꢂꢉ
ꢉ
ꢗꢒꢊ
Rꢝꢒꢍ
ꢊꢊ
ꢑꢖꢕꢃ ꢙꢌꢘꢓR
ꢁꢂꢃꢐꢓ ꢏ
ꢁꢘꢏ
ꢞ
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ꢊꢌꢒꢂRꢌꢢ
ꢏꢀꢍ
ꢙꢐꢒꢇꢏ
Φ ꢣ 0ꢥ
ꢟ
ꢏꢀꢍ
ꢀꢁꢂꢐ
ꢗꢒꢂꢉ
ꢉ
ꢗꢒꢏ
Rꢝꢒꢄ
ꢊꢊ
ꢉ
ꢗꢒꢐ
ꢑꢖꢕꢃ ꢙꢌꢘꢓR
ꢁꢂꢃꢐꢓ ꢐ
ꢞ
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ꢊꢌꢒꢂRꢌꢢ
ꢏꢀꢄ
ꢁꢘꢐ
Φ ꢣ ꢍꢅ0ꢥ
ꢟ
ꢙꢐꢒꢇꢐ
ꢏꢀꢄ
ꢗꢒꢂꢉ
ꢉ
ꢗꢒꢐ
Rꢝꢒꢈ
ꢀꢁꢂꢚ
ꢊꢊ
ꢞ
ꢉ
ꢀꢝꢊꢡ RꢓꢐꢝꢢꢃꢂꢌR ꢈ
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ꢗꢒꢚ
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ꢁꢂꢃꢐꢓ ꢚ
Φ ꢣ ꢑꢩ0ꢥ
ꢁꢘꢚ
ꢟ
ꢏꢀꢈ
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ꢊꢌꢒꢏꢗꢐꢝRꢃꢂꢗꢌꢒ ꢢꢗꢒꢓꢁ
ꢊꢏꢐ0 ꢊꢏꢐꢑ ꢊꢏꢐꢍ ꢊꢏꢐꢄ
ꢐꢒꢇ
ꢄꢄꢅꢆ ꢀꢇ
Rev 0
16
For more information www.analog.com
LTC3376
OPERATION
Buck Switching Regulators
buck is shut down to a low quiescent current state and the
SW pin is pulled to PGND through a 1k resistor. If all buck
regulatorsareoff,mosttoplevelcircuitsareshutdown,and
the quiescent current of the LTC3376 is 9µA(typ). When a
buck is enabled there is a 100μs(typ) delay before switch-
ing commences and the soft start ramp begins. If a buck
is the first one to be enabled, then this delay is 250µs(typ).
TheLTC3376isa20Vmonolithic,constantfrequency,four
channel, 12A configurable, peak current mode step-down
DC/DC converter. The device includes four synchronous
buck converters, configured to share eight 1.5A power
stages. The LTC3376 includes the integration of ceramic
capacitors into the package for all BST pins. These capaci-
tors reduce PC board space by eliminating the need for
external BST capacitors.
The buck switching regulators are phased in 90° steps to
reduce noise and input ripple. The phase step determines
the fixed edge of the switching sequence, which is when
the top switch turns on. The top switch off (bottom switch
on) phase is subject to the duty cycle demanded by the
regulator. Buck 2 is set to 0°. Buck 1 is set to 90°. Buck 4
is set to 180°. Buck 3 is set to 270°.
Thebuckswitchingregulatorsareinternallycompensated
and require external feedback resistors to set the output
voltage. An internal oscillator, which can be synchronized
to an external oscillator, turns on the internal top power
switch at the beginning of each clock cycle. Current in the
inductorrampsupuntilthetopswitchcurrentcomparator
tripsandturnsoffthetoppowerswitch. Thepeakinductor
current at which the top switch turns off is controlled by
Buck Regulators with Combined Power Stages
Up to four buck regulators may be combined in a master-
slave configuration in various combinations by setting the
CFG0, CFG1, CFG2, and CFG3 pins. These configuration
an internal V voltage which the error amplifier regulates
C
by comparing the voltage on the feedback pin with an in-
ternal 400mV reference. When the load current increases,
it causes a reduction in the feedback voltage relative to the
pins should either be tied to ground or tied to INTV in
CC
accordance with the desired configuration (Table 1). Any
combined SW pins must be tied together, as must any of
referencecausingtheerroramplifiertoraisetheV voltage
C
the combined V and BST pins. The bucks have a com-
until the average inductor current matches the new load
current. When the top power switch turns off, the bottom
power switch turns on until the next clock cycle begins or,
if in Burst Mode, until the inductor current falls to zero.
IN
monV buteachV pinshouldhaveitsowninputbypass
IN
IN
+
capacitors (see Applications Information). RUN1, FB1 ,
–
+
FB1 , I
, and PGOOD1 are utilized by Buck 1. RUN2,
MON1
FB2 , FB2 , I
–
+
, and PGOOD2 are utilized by Buck 2.
MON2
Each buck converter can operate at an independent V
voltage and has its own FB , FB , RUN, I
–
IN
RUN3,FB3 ,FB3 ,I
3. RUN4, FB4 , FB4 , I
,andPGOOD3areutilizedbyBuck
MON3
+
–
, and PGOOD
+
–
MON
, and PGOOD4 are utilized by
MON4
pins to maximize flexibility. The RUN pins have two differ-
ent enable threshold voltages that depend on the operating
state of the LTC3376. The first buck regulator to turn on
will have a RUN pin rising threshold of 730mV(typ). The
last buck regulator to turn off will have a RUN pin falling
threshold of 690mV(typ). If any one buck regulator is on,
all other RUN pins will use the bandgap-based precision
thresholds off 300mV(typ) rising and 200mV(typ) falling.
The precision RUN thresholds may be used to provide
event-based power-up sequencing by connecting the RUN
pin to the output of another buck through a resistor divider.
All buck regulators have forward and reverse-current limit-
ing, short-circuit protection, and soft-start to limit inrush
current during start-up. If the RUN pin of a buck is low, that
Buck4.Ifabuckisnotutilizedinaparticularconfiguration,
+
–
then the RUN, FB , and FB , I
, PGOOD pins should
MON
be tied to GND. Its V , SW, and BST pins will be used as
IN
a slave to another master and must be connected to that
master’s respective power pins.
Buck regulators can be combined to provide 3A, 4.5A, 6A,
7.5A,9A,10.5A,or12Aofoutputloadcurrent.Forexample,
code 0110 (CFG[3:0]) configures Buck 1 to operate as a
4.5A regulator through V /SW/BST pairs A, B, and H,
IN
while Buck 2 is disabled, Buck 3 operates as a 6A regula-
tor through V /SW/BST pairs C, D, E, and F, and Buck 4
IN
operates as a 1.5A regulator through V /SW/BST pair G.
IN
Rev 0
17
For more information www.analog.com
LTC3376
OPERATION
Table 1. Master-Slave Program Combinations
regulator will burst only at light loads. At higher loads it
will operate in constant frequency PWM mode.
(Each Letter Corresponds to a VIN/SW/BST/PGND Pair)
OUTPUT CONFIGURATION
CFG3 CFG2 CFG1 CFG0
BUCK 1
AB
BUCK 2 BUCK 3 BUCK 4
Synchronizing the Oscillator to an External Clock
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CD
EF
GH
G
Selectionoftheoperatingfrequencyisatrade-offbetween
efficiency and component size. High frequency operation
allows the use of smaller inductor and capacitor values
and improves transient response. Operation at lower
frequencies improves efficiency by reducing internal gate
ABH
CD
EF
ABH
CDE
F
G
ABDH
AB
C
EF
G
CDE
-
FGH
GH
G
ABCD
ABH
-
-
EF
chargelossesandallowsmoreextremeV toV
ratios.
IN
OUT
CDEF
However, this also requires larger inductance values and/
or capacitance to maintain low output voltage ripple. The
LTC3376 has a default operating frequency of 2MHz.
ABCD
ABDEH
ABCDH
ABCDE
ABCDEH
ABCDEF
ABCDEFH
ABCDEFGH
AB
-
-
F
EFGH
G
C
-
EF
-
G
-
FGH
G
The LTC3376’s internal oscillator can alternatively be
synchronizedthroughaninternalPLLcircuittoanexternal
frequency by applying a square wave clock signal to the
MODE/SYNC pin. During synchronization, the top power
device turn-on of buck 2 is locked to 110ns after the ris-
ing edge of the external frequency source. Buck 1 will be
90° out of phase with Buck 2. Buck 4 will be 180° out of
phase with Buck 2. Buck 3 will be 270° out of phase with
Buck 2. When synchronizing to an external clock, the
buck regulators operate in forced continuous mode. The
synchronization frequency range is 1MHz to 3MHz.
-
F
-
-
GH
G
-
-
-
-
-
CD
EF
GH
Mode Selection
The buck switching regulators can operate in two different
modes set by the SYNC/MODE pin: Burst Mode (when
the SYNC/MODE pin is set low) and forced continuous
PWM mode (when the SYNC/MODE pin is set high). The
SYNC/MODE pin sets the same operating mode for all
buck switching regulators.
After detecting an external clock on the first rising edge
of the SYNC pin, the internal PLL starts at the default
frequency. The internal PLL then requires up to 1ms to
gradually adjust its operating frequency to match the
frequency and phase of the SYNC signal.
Inforcedcontinuousmode,theoscillatorrunscontinuously
and the buck switch currents are allowed to reverse under
light load conditions to maintain regulation. This mode
allows the buck to run at a fixed frequency with minimal
output ripple, even with zero output load.
WhentheexternalclockisremovedtheLTC3376willdetect
the absence of the external clock, and the oscillator gradu-
ally adjusts its operating frequency back to the default.
InBurstModeoperation,atlightloadstheoutputcapacitor
is charged to a voltage slightly higher than its regulation
point. The regulator then goes into a sleep state, during
which time the output capacitor provides the load current.
In sleep most of the regulator’s circuitry is powered down,
helping conserve input power. When the output capacitor
dropsbelowitsprogrammedvalue,thecircuitryispowered
onandanotherburstcyclebegins.Thesleeptimedecreases
as load current increases. In Burst Mode operation, the
Power Failure Reporting Via PGOOD Pins
Power failure conditions are reported back by each buck’s
associatedPGOODpin. Eachbuckswitchingregulatorhas
an internal power good (PGOOD_INT) signal. When the
regulatedoutputvoltageofanenabledswitcherrisesabove
97.75% of its regulation output voltage the PGOOD_INT
signal transitions high. If the regulated output voltage
subsequently falls below 96.75%(typ) of the regulation
Rev 0
18
For more information www.analog.com
LTC3376
OPERATION
output voltage the PGOOD_INT signal is pulled low. If
a buck is enabled, its PGOOD_INT signal must be high
for its external PGOOD pin to be high. An enabled buck’s
internal PGOOD_INT signal must stay low for greater
than 100μs(typ) before its external PGOOD pin is pulled
low, indicating to a microprocessor that a power failure
fault has occurred. This 100μs filter time prevents the pin
from being pulled low during a load transient. In addition,
whenever the internal PGOOD_INT signal transitions high
there will also be a 100μs assertion delay.
mode but can function in Burst Mode at moderate loads
withreducedaccuracyifanexternalcapacitorisappliedto
the I
pin. This capacitor should be selected such that
MON
the RC time constant is about 250µs or larger. The capaci-
tor value to use on the I
pin (if desired) is given by:
MON
250µs
C
≥
(2)
IMON
R
IMON
Temperature Monitoring and Overtemperature
Protection
The LTC3376 also reports overvoltage conditions at the
PGOODpins. Ifanenabledbuckregulator’soutputvoltage
risesabove107.5%(typ)oftheregulationvalue,itsPGOOD
pinispulledlowafter100μs.Similarly,ifanenabledoutput
that is overvoltage subsequently falls below 105% (typ)
of its regulated output voltage, its PGOOD pin transitions
high again after 100μs.
To prevent thermal damage to the LTC3376 and its sur-
rounding components, the LTC3376 incorporates an
overtemperature (OT) function. When the LTC3376 die
temperature reaches 165°C (typical) all enabled buck
switching regulators are shut down and remain in shut-
down until the die temperature falls to 155°C (typical).
The die temperature may be read by sampling the analog
TEMP pin voltage. The temperature, T, indicated by the
TEMP pin voltage is given by:
An error condition that pulls the PGOOD pin low is not
latched. When the error condition goes away, the PGOOD
pin is released and is pulled high if no other error condi-
tion exists. PGOOD is also pulled low in the following
scenarios: if the buck is disabled, if the buck is going
V
TEMP
T =
•1°C
(3)
10mV
through soft-start, if INTV is below the UVLO threshold,
CC
where V
is the voltage on the TEMP pin.
or if the LTC3376 is in OT (see below).
TEMP
The typical voltage at the TEMP pin is 250mV at 25°C.
readings are valid for die temperatures higher
Current Monitors
V
TEMP
Each buck regulator has a current monitor that supplies a
than approximately 10°C. A bypass cap is not needed
on the TEMP pin. If stray capacitance is present on the
TEMP pin that is greater than 30pF, then a 15k resistor
must be added in series at the pin to ensure the stability
of the temperature monitor. If temperature monitoring
functionality is not needed, the user may shut down the
current to the I
pin that is proportional to the average
MON
buck load current. The external resistor required from the
pintogroundisafunctionofhowmanypowerstages
I
MON
are configured for a particular buck. If a buck regulator is
configured to have only one power stage then a 10k resis-
tor should be connected from I
to ground. At full load
temperature monitor by tying TEMP to INTV . This will
MON
CC
(1.5A) the voltage on the I
pin will be 1V (typical). At
reduce quiescent current by 5µA (typical). If none of the
buck switching regulators are enabled, the temperature
monitor is also shutdown to reduce quiescent current.
MON
half load (0.75A) the voltage on the I
pin will be 0.5V.
MON
For combined output stages, the resistor required at the
pin is given by:
I
MON
INTV Regulator
CC
10kΩ
[# of channels]
R
=
(1)
IMON
An internal low dropout (LDO) regulator produces a 3V
supply from V that powers the INTV pin and internal
CC
CC
The I
pin voltage represents the average buck load
bias circuitry. The INTV can supply enough current for
MON
CC
and will take a few 100µs to settle. The current monitor
is designed to be most accurate in continuous conduction
the LTC3376’s circuitry and must be bypassed to ground
with a minimum of 4.7µF ceramic capacitor. The INTV
CC_P
Rev 0
19
For more information www.analog.com
LTC3376
OPERATION
pin powers all of the MOSFET gate drivers, must have its
3V or above. If EXTV is connected to a supply other than
CC
own10µFbypasscap,andmustbeconnectedontheboard
a buck output, be sure to bypass it with a local ceramic
toINTV .Goodbypassingisnecessarytosupplythehigh
capacitor. IftheEXTV pinisbelow2.8V, theinternalLDO
CC
CC
transient currents required by the power MOSFET drivers.
will consume current from V . Applications with high
CC
input voltage and high switching frequency in which the
To improve efficiency the internal LDO can also draw cur-
LDO pulls current from V will increase die temperature
CC
rent from the EXTV pin if the EXTV pin is 3V or higher.
CC
CC
CC
becauseofthehigherpowerdissipationintheLDO.Donot
V
has to be present even if EXTV is used. Typically
CC
loadtheINTV pinwithexternalcircuitryexceeding2mA.
CC
the EXTV pin can be tied to an output of one of the
CC
LTC3376 bucks, or it can be tied to an external supply of
APPLICATIONS INFORMATION
Buck Switching Regulator Output Voltage and
Feedback Network
Operating Frequency Selection and Trade-Offs
Selection of the operating frequency is a trade-off between
efficiency, component size, transient response, and input
voltage range. The advantage of high frequency operation
is that smaller inductor and capacitor values may be used.
Higher switching frequencies allow for higher control loop
bandwidth and, therefore, faster transient response. The
disadvantages of higher switching frequencies are lower
efficiency, because of increased switching losses, and a
smaller input voltage range, because of minimum switch
on-time limitations.
The output voltage of each buck switching regulator is
programmed by a resistor divider across the switching
regulator’s output connecting to its feedback pin and is
+
given by V
= V (1 + R2/R1) as shown in Figure 1
OUT
FB
+
where V
= 400mV. Typical values for R1 range from
FB
20k to 200k. 1% or better resistors are recommended
to maintain output voltage accuracy. The buck regulator
transient response may improve with an optional phase
lead capacitor C that helps cancel the pole created by the
FF
+
feedback resistors and the input capacitance of the FB
The operating frequency for all of the LTC3376 buck regu-
lators can be determined by an external resistor that is
connected from the RT pin to ground. The operating fre-
quency is calculated using the following equation:
pin. Experimentation with capacitor values between 2pF
and 22pF may improve transient response if the resistor
+
divider has a large V /V ratio.
OUT FB
The LTC3376 includes low offset, high input impedance
differential sense for applications that require remote
sensing. Connect FB+ to the center tap of the feedback
⎛
⎜
⎝
⎞
⎟
⎠
402kΩ
f
= 2MHz
(4)
OSC
R
T
–
divider across the output load, and FB to the load ground.
While the LTC3376 is designed to function with operat-
ing frequencies between 1MHz and 3MHz, it has internal
safety clamps that prevent the oscillator from running
faster than 4MHz (typical) or slower than 500kHz (typi-
cal). Tying the RT pin to INTV sets the oscillator to the
default internal operating frequency of 2MHz (typical).
ꢄꢅ
ꢐ
Rꢑ
Rꢒ
ꢂ
ꢂ
ꢎꢁꢇ
ꢏꢏ
ꢐ
ꢗ
ꢀꢁꢂꢃ
ꢄꢅꢆꢇꢂꢈꢆꢉꢊ
RꢋꢊꢁꢌꢍꢇꢎR
ꢏꢀ
ꢏꢀ
CC
ꢎꢓꢇꢆꢎꢉꢍꢌ
ꢔꢔꢕꢖ ꢏ0ꢒ
Although the maximum programmable switching fre-
quency is 3MHz for the LTC3376, the minimum on-time
of the LTC3376 imposes a minimum operating duty
cycle. The typical minimum on-time is 53ns. The highest
Figure 1. Feedback Components
Rev 0
20
For more information www.analog.com
LTC3376
APPLICATIONS INFORMATION
switching frequency (fSW(MAX)) for low duty cycle applica-
tions can be calculated as follows:
To avoid overheating of the inductor, choose an inductor
with an RMS current rating that is greater than the maxi-
mum expected output load of the application. Overload
and short-circuit conditions should also be taken into
consideration.
V
+ V
BOTSW
OUT
f
=
(5)
SW(MAX)
t
V
– V
+ V
IN(MAX)
ON(MIN)
TOPSW BOTSW
In addition, ensure that the saturation current rating (typi-
where VIN(MAX) is the maximum input voltage, VOUT is
cally labeled I ) is higher than the maximum expected
SAT
the output voltage, V
switch drops, and t
and V
are the internal
TOPSW
is theBmOTiSnWimum top switch
load plus half the inductor ripple:
on-time. This equatOioNn(MsINh)ows that a slower switching
1
I
>I
+ ΔI
(9)
frequency is necessary to accommodate a very high V /
L
SAT LOAD(MAX)
IN
2
V
OUT
ratio.
where I
L
is the maximum output load current and
LOAD(MAX)
For higher duty cycle applications, the minimum off-time
also imposes a max switching frequency which can be
calculated as follows:
∆I is the inductor ripple current as calculated by:
⎛
⎞
V
V
OUT
V
IN(MAX)
OUT
⎜
⎟
ΔI =
• 1–
(10)
L
⎜
⎝
⎟
V – V
– V
TOPSW
L • f
IN
OUT
SW
⎠
f
=
(6)
SW(MAX)
t
V + V
– V
TOPSW
(
)
IN
OFF(MIN)
BOTSW
A more conservative choice would be to choose an induc-
where t
is the minimum top switch off-time. This
tor with an I
rating higher than the maximum current
OFF(MIN)
SAT
equation shows that a slower switching frequency is also
necessary to accommodate a very low V /V ratio.
limit of the LTC3376 which is 3.0A per power stage.
IN OUT
For highest efficiency, choose an inductor with the low-
est series resistance (DCR). The core material should be
intended for high frequency applications. Table 2 shows
recommended inductors from several manufacturers.
Inductor Selection and Maximum Output Current
Considerations in choosing an inductor are inductance
value, RMS current rating, saturation current rating, DCR,
and core loss.
Input Capacitors
If the duty cycle of operation is 50% or less, choose the
inductor based on the following equation:
The LTC3376 has individual input supply pins for each
buck power stage. All of these pins must be decoupled
with low ESR capacitors to their own PGND. These capaci-
tors should be placed as close to the pins as possible.
Ceramic dielectric capacitors are a good compromise
between high dielectric constant and stability versus
temperature and DC bias. Note that the capacitance of a
capacitor deteriorates at higher DC bias. It is important
to consult manufacturer data sheets and obtain the true
capacitance of a capacitor at the DC bias voltage that it will
operate at. For this reason, avoid the use of Y5V dielec-
tric capacitors. The X5R/X7R dielectric capacitors offer
good overall performance. See Table 3 for recommended
ceramic capacitor manufacturers.
V
OUT
1–
V
V
IN(MAX)
OUT
L = V
•
for
≤ 0.5
(7)
OUT
0.2 •I
• f
V
IN
MAX
SW
where fSW is the switching frequency, VIN(MAX) is the max-
imum input voltage that the buck will run at, and I is
MAX
1.5A times the number of power stages (the maximum
rated load current for the LTC3376). For operation at duty
cycles higher than 50%, use instead the following equa-
tion to select the inductor:
V
V
IN(MAX)
OUT
L = 1.25 •
for
> 0.5
(8)
Regardless of how the power stages are configured, each
f
•I
V
IN
MAX
SW
input supply voltage pin, V , needs to be decoupled
INA-H
Rev 0
21
For more information www.analog.com
LTC3376
APPLICATIONS INFORMATION
Table 2. Recommended Inductors
L
(µH)
MAX DCR
(mΩ)
CURRENT RATING
(A)
DIMENSIONS
(L × W × H)
PART NUMBER
VENDOR
XEL4030-102MEB
XFL4020-152MEB
XEL4030-222MEB
XFL4020-472MEB
1
9.78
15.8
22.1
57.4
10.7
9.1
7.8
5
4mm × 4mm × 3.1mm
4.3mm × 4.3mm × 2.1mm
4mm × 4mm × 3.1mm
Coilcraft
www.coilcraft.com
1.5
2.2
4.7
4.3mm × 4.3mm × 2.1mm
744383360068
74438357010
74404042015
74439344022
0.68
1
1.5
2.2
27
13.5
31
4.5
7.4
2.95
8
3mm × 3mm × 2mm
4.1mm × 4.1mm × 3.1mm
4mm × 4mm × 1.8mm
Wurth Electronics Inc.
www.we-online.com
10.5
6.65mm × 6.65mm × 3.3mm
PCMB042T-1R0MS
PCMB053T-1R5MS
1
1.5
27
20
4.5
6
4.15mm × 4mm × 1.8mm
4.7mm × 4.85mm × 2.8mm
Susumu
www.susumu-usa.com
FDSD0420-H-R68M=P3
FDSD0420D-1R0M=P3
FDSD0420D-2R2M=P3
0.68
1
2.2
22
29
47
6.5
5.1
3.6
4.2mm × 4.2mm × 2mm
4.2mm × 4.2mm × 2mm
4.2mm × 4.2mm × 2mm
Murata
www.murata.com
independently to PGNDA-H with a 1µF capacitor as close
to the pins as possible and at least a 10µF capacitor.
Connect each ground of each capacitor to a wide PCB
trace on the top layer of the PCB that connects directly to
the PGND pin and then to the GND plane.
the LTC3376 SW pins to produce the DC output. In this
role it determines the output ripple. Thus, low imped
-
ance at the switching frequency is important. The second
function is to store energy in order to satisfy transient
loads and to stabilize the LTC3376’s control loop. Ceramic
capacitors have very low equivalent series resistance
(ESR) and provide the best ripple performance. For good
starting values, see the Typical Applications. Use X5R or
X7R ceramic capacitors. This choice will provide low out-
put ripple and good transient response.
Note that larger input capacitance is required when a lower
switching frequency is used. If the input power source has
high impedance, or if there is significant inductance due to
long wires or cables, additional bulk capacitance may be
necessary. This can be provided with a low performance
electrolytic capacitor.
The LTC3376 is internally compensated and has been
designed to operate at a high bandwidth for fast transient
A ceramic input capacitor combined with trace or cable
inductance forms a high quality (underdamped) tank cir-
cuit. If the LTC3376 circuit is plugged in to a live supply,
the input voltage can ring to twice its nominal value, pos-
sibly exceeding the LTC3376’s voltage rating. This situa-
tion is easily avoided (see Linear Technology Application
Note 88).
response capability. The selection of C
will affect the
OUT
bandwidth of the system and the optimal value is given
by the following equation:
(# of power stages)
C
= 100 •
(11)
OUT
f
• V
OUT
SW
where f is the switching frequency.
SW
Table 3. Ceramic Capacitor Manufacturers
This calculated COUT value is the capacitance required
after voltage and temperature derating. A lower value of
output capacitor can be used to save space and cost but
transient performance will suffer and may cause loop
instability. See the Typical Applications in this data sheet
for suggested capacitor values.
VENDOR
AVX
URL
www.avxcorp.com
www.murata.com
www.tdk.com
www.t-yuden.com
Murata
TDK
Taiyo Yuden
When choosing a capacitor, special attention should be
given to the data sheet to calculate the effective capaci-
tance under the relevant operating conditions of voltage
Rev 0
Output Capacitor, Output Ripple, and Loop Response
The output capacitor has two essential functions. Along
with the inductor, it filters the square wave generated at
22
For more information www.analog.com
LTC3376
APPLICATIONS INFORMATION
bias and temperature. A physically larger capacitor or one
with a higher voltage rating may be required.
input impedance sensitive nodes, such as the feed-
back nodes, should be kept far away or shielded from
the switching nodes or poor performance could result.
PCB Considerations
+
–
4. Keep the FB , FB , RT, TEMP, and RUN nodes small
so that ground traces will shield them from the SW
and BST nodes.
When laying out the printed circuit board, the following
list should be followed to ensure proper operation of the
LTC3376:
5. The GND pin should connect directly to the ground
side of the INTVCC bypass cap and then connect to the
ground connection of other analog components (RT
1. The input supply pins (VINA-H) should each have local
decoupling capacitors with their ground pins connect-
ing back to the PGND pin (PGNDA-H) of the IC with as
short and wide a trace as possible before connecting
resistor, I
resistor, V and EXTV bypass caps)
MON
CC CC
before connecting down to the GND plane.
to the GND plane. The V and PGND pins are placed
IN
6. The bypass capacitor from INTV to GND should be
CC
next to each other on the outer edge of the IC for
as close to the INTV pin as possible and connected
CC
this purpose. Note that large switched currents flow
with a wide trace.
in the LTC3376’s V and PGND pins, and in the V
IN
IN
input capacitor. The loop formed by the input capaci-
tor should be made as tight as possible by placing
7. The bypass capacitor from INTV
to GND should
CC_P
be as close to the INTV
pin as possible and con-
CC_P
the capacitor adjacent to the V and PGND pins and
nected with a wide trace. The ground side of this
capacitor should connect directly to the GND plane.
IN
choosing a small case size such as 0402 for the 1µF
capacitor and 0603 for the 10µF capacitor. Place a
local, unbroken ground plane under the application
circuit on the layer closest to the surface layer.
8. The GND side of the switching regulator output capac-
itors should connect to the GND plane.
–
9. The FB pin should connect directly to the GND side
2. When connecting BST pins together for ganging, the
BST trace should be as short as possible.
of the feedback resistor.
10. The power stages should have a symmetric layout
3. The switching power traces connecting SWA-H to
their respective inductors should be short and wide
to reduce radiated EMI and parasitic coupling. Due to
the large voltage swing of the switching nodes, high
with respect to V , PGND, BST, and SW traces.
IN
11. See Evaluation Kit Design Files for recommended
layouts.
Rev 0
23
For more information www.analog.com
LTC3376
TYPICAL APPLICATIONS
Four Rail (1.8V/4.5A, 2.5V/3A, 3.3V/3A, 5V/1.5A) System with Bootstrapped EXTVCC Drive
3V TO 20V
4.7µF
V
CC
3V TO 13V
V
V
V
INA
INB
INH
15µF
×3
1µF
×3
BSTA
BSTB
BSTH
SWA
SWB
SWH
EXTV
EXTV
CC
CC
4.7µF
1µH
698k
1.8V
4.5A
INTV
CC
INTV
INTV
CC
(3V)
4.7µF
+
CC_P
FB1
2x68µF
10µF
200k
LTC3376
–
FB1
PGNDA
PGNDB
PGNDH
RUN1
RUN2
RUN3
RUN4
V
INC
IND
3.3V TO 18V
1µF
×2
15µF
×2
V
BSTC
BSTD
SWC
SWD
PGOOD1
PGOOD2
PGOOD3
PGOOD4
2.2µH
2.5V
3A
1.05MΩ
200k
+
FB2
68µF
–
I
I
I
I
MON1
MON2
MON3
MON4
FB2
PGNDC
PGNDD
V
V
4.3V TO 20V
3.32k
4.99k
4.99k
10k
INE
1µF
×2
15µF
×2
INF
BSTE
BSTF
SWE
SWF
2.2µH
EXTV
CC
3.3V
TEMP
3A
1.15MΩ
158k
SYNC/MODE
RT
+
FB3
47µF
536k
(1.5MHz)
–
FB3
PGNDE
PGNDF
CFG0
CFG1
CFG2
CFG3
INTV
CC
V
6.5V TO 20V
ING
1µF
6.8µH
15µF
5V
CONFIGURATION 0001
BSTG
SWG
1.5A
1.15MΩ
+
FB4
33µF
100k
–
FB4
PGNDG
GND
3376 TA03
Rev 0
24
For more information www.analog.com
LTC3376
TYPICAL APPLICATIONS
Four Rail (3.3V/6A, 5V/1.5A, 1V/3A, 1.8V/1.5A) System with Bootstrapped EXTVCC Drive
4.7V TO 18V
V
V
V
V
INA
INB
IND
INH
1µF
×4
10µF
×4
3V TO 20V
4.7µF
V
CC
BSTA
BSTB
BSTD
BSTH
SWA
SWB
SWD
SWH
EXTV
EXTV
CC
CC
1µH
4.7µF
EXTV
CC
3.3V, 6A
1.15MΩ
158k
INTV
CC
Note: 6A includes
input currents of
Bucks 3 and 4.
+
INTV
INTV
CC
(3V)
4.7µF
FB1
100µF
CC_P
10µF
–
FB1
LTC3376
PGNDA
PGNDB
PGNDD
PGNDH
RUN1
RUN2
RUN3
RUN4
7.2V TO 20V
V
INC
1µF
10µF
PGOOD1
PGOOD2
PGOOD3
PGOOD4
BSTC
SWC
4.7µH
5V
1.5A
1.15MΩ
+
FB2
22µF
100k
–
I
I
I
I
MON1
MON2
MON3
MON4
FB2
PGNDC
V
INE
1µF
×2
10µF
×2
V
INF
2.49k
10k
4.99k
10k
BSTE
BSTF
SWE
SWF
680nH
1V
3A
294k
196k
TEMP
+
FB3
100µF
SYNC/MODE
RT
INTV
INTV
2MHz
CC
CC
–
FB3
PGNDE
PGNDF
V
ING
CFG0
CFG1
CFG2
CFG3
1µF
10µF
CONFIGURATION 0011
BSTG
SWG
1.5µH
1.8V
1.5A
698k
200k
+
FB4
33µF
–
FB4
PGNDG
GND
3376 TA04
Rev 0
25
For more information www.analog.com
LTC3376
TYPICAL APPLICATIONS
Two Rail (3.3V/10.5A, 5V/1.5A) System
4.7V TO 18V
V
V
V
INA
INB
INC
IND
1µF
×7
10µF
×7
3V TO 20V
V
CC
V
4.7µF
V
INE
V
INF
V
INH
BSTA
BSTB
BSTC
BSTD
BSTE
BSTF
BSTH
EXTV
CC
INTV
CC
INTV
INTV
(3V)
4.7µF
CC
CC_P
10µF
LTC3376
SWA
SWB
SWC
SWD
SWE
SWF
SWH
RUN1
RUN1
RUN2
RUN3
680nH
3.3V
10.5A
RUN4
1.15MΩ
158k
+
FB1
120µF
PGOOD1
PGOOD2
PGOOD3
–
FB1
PGNDA
PGNDB
PGNDC
PGNDD
PGNDE
PGNDF
PGNDH
PGOOD4
I
MON1
I
I
MON2
MON3
1.43k
7.2V TO 20V
V
I
ING
MON4
1µF
4.7µH
10µF
10k
BSTG
SWG
5V
1.5A
TEMP
1.15MΩ
931k
22µF
66.5k
SYNC/MODE
RT
+
FB4
RUN1
INTV
INTV
CC
CC
100k
–
FB4
CFG0
CFG1
CFG2
CFG3
PGNDG
CONFIGURATION 1101
+
FB2
FB2
FB3
FB3
–
+
–
GND
3376 TA05
Rev 0
26
For more information www.analog.com
LTC3376
PACKAGE DESCRIPTION
ꢟ
ꢟ
ꢷ ꢷ ꢧ ꢧ ꢧ
ꢟ
ꢕ ꢇ ꢥ 0
ꢕ ꢇ 0 0
ꢆ ꢇ ꢕ 0
0 ꢇ ꢑ 0
0 ꢇ ꢑ 0
ꢆ ꢇ ꢕ 0
ꢕ ꢇ 0 0
ꢕ ꢇ ꢥ 0
0 ꢇ 0 0 0
ꢶ ꢶ ꢶ
ꢟ
× ꢕ
Rev 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
27
subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
For more information www.analog.com
LTC3376
TYPICAL APPLICATION
Four Rail (5V/3.3V/2.5V/1.8V, 3A) System with Bootstrapped EXTVCC Drive
3V TO 20V
4.7µF
V
CC
V
V
7.2V TO 20V
INA
1µF
×2
10µF
×2
INB
BSTA
BSTB
2.2µH
EXTV
5V
3A
CC
SWA
SWB
INTV
INTV
CC
(3V)
4.7µF
1.15MΩ
100k
CC_P
+
FB1
22µF
10µF
–
LTC3376
FB1
4.7V TO 18V
V
V
INC
1µF
×2
10µF
×2
RUN1
RUN2
RUN3
RUN4
IND
BSTC
BSTD
2.2µH
SWC
SWD
3.3V, 3A
1.15MΩ
Note: 3A includes
input current of Buck 4.
+
FB2
PGOOD1
PGOOD2
PGOOD3
PGOOD4
33µF
158k
–
FB2
V
3.6V TO 13.6V
INE
1µF
×2
10µF
×2
V
INF
I
I
I
I
MON1
MON2
MON3
MON4
BSTE
BSTF
1.5µH
2.5V
SWE
SWF
3A
4.99k
4.99k
4.99k
4.99k
1.05MΩ
+
FB3
47µF
200k
–
FB3
TEMP
V
V
ING
INH
SYNC/MODE
RT
1µF
×2
10µF
×2
402k
BSTG
BSTH
680nH
698k
1.8V
3A
SWG
SWH
CFG0
CFG1
CFG2
CFG3
+
FB4
68µF
CONFIGURATION 0000
200k
–
FB4
GND PGNDA-H
8
3376 TA02
RELATED PARTS
PART NUMBER DESCRIPTION
COMMENTS
LTC3370/
LTC3371
4-Channel 8A Configurable 1A Four Synchronous Buck Regulators with 8× 1A Power Stages. Can Connect Up to Four Power Stages in
Buck DC/DCs
Parallel to Make a High Current Output (4A Max) with a Single Inductor. 8 Configurations Possible, Precision
PGOOD Indication. 800mV FB Regulation. LTC3371 Has a Watchdog Timer; Buck 1 Accuracy 1%, others
2.5%; LTC3370: 32-Lead 5mm × 5mm QFN. LTC3371: 38-Lead 5mm × 7mm QFN and TSSOP.
LTC3374/
LTC3375
8-Channel Parallelable 1A Buck Eight 1A Synchronous Buck Regulators. Can Connect Up to Four Power Stages in Parallel to Make a
DC/DCs
High Current Output (4A Max) with a Single Inductor. 15 Configurations Possible. 800mV FB Regulation.
2
All Bucks 2.5% Accuracy. LTC3375 Has I C Programming with a Watchdog Timer and Pushbutton;
LTC3374: 38-Lead 5mm × 7mm QFN and TSSOP, LTC3375: 48-Lead 7mm × 7mm QFN.
LTC3374A
High Accuracy 8-Channel
Parallelable 1A Buck DC/DCs
Eight 1A Synchronous Buck Regulators. Can Connect Up to Four Power Stages in Parallel to Make a
High Current Output (4A Max) with a Single Inductor; 15 Configurations Possible. 800mV FB Regulation.
Buck 1 Accuracy 1%, Others 2%; Overvoltage Monitor Included in PGOOD.
Rev 0
06/19
www.analog.com
ANALOG DEVICES, INC. 2019
28
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