LTC3350_技术文档

LTC4041

2.5A Supercapacitor

Backup Power Manager

FEATURES

DESCRIPTION

The LTC^®4041 is a complete supercapacitor backup sys-

tem for 2.9V to 5.5V supply rails. It contains a high cur-

rent step-down DC/DC converter to charge a single super-

capacitor or two supercapacitors in series. When input

power is unavailable, the step-down regulator operates

in reverse as a step-up regulator to backup the system

output from the supercapacitor(s).

n

2.5A Step-Down Supercapacitor Charger and 2.5A

Step-Up Backup Supply

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6.5A Switches for 2.5A Backup from One

Supercapacitor or Two in Series

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Input Current Limit Prioritizes Load over

Charge Current

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Input Disconnect Switch Isolates Input During Backup

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Automatic Seamless Switch-Over to Backup Mode

The LTC4041’s adjustable input current limit function

reduces charge current to protect the input supply from

overload while an external disconnect switch isolates the

input supply during backup. When the input supply drops

below the adjustable PFI threshold, the 2.5A boost regula-

tor delivers power from the supercapacitor to the system

output.

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Internal Supercapacitor Balancer (No External

Resistors)

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Programmable Charge Current and Charge Voltage

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Input Power Fail Indicator

System Power Good Indicator

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Optional OVP Circuitry Protects Device to >60V

Constant Frequency Operation

Thermally Enhanced 24-Lead 4mm × 5mm

QFN Package

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An optional input overvoltage protection (OVP) circuit

protects the LTC4041 from high voltage damage at the V_IN

pin. An internal supercapacitor balancing circuit maintains

equal voltages across each supercapacitor and limits the

maximum voltage of each supercapacitor to a pre-deter-

mined value. The LTC4041 is available in a low profile

(0.75mm) 24-Lead 4mm × 5mm QFN package.

APPLICATIONS

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Ride-Through “Dying Gasp” Supplies

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High Current Ride-Through 3V to 5V UPS

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Power Meters/Industrial Alarms

Servers/Solid State Drives

All registered trademarks and trademarks are the property of their respective owners. Protected

by U.S. Patents, including 6522118, 6570372, 6700364, 8139329.

n

TYPICAL APPLICATION

Single Supercapacitor 3.3V Backup Application

Complete Backup Event with

a Single 10F Supercapacitor

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12mΩ

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PFO

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CAPFLT

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CHGEN BSTEN ꢀꢁꢂ ꢀAꢁꢂꢃꢄ ꢀꢁꢂ ꢀRꢁꢂ

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ꢌAꢍ

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Rev A

1

Document Feedback

For more information www.analog.com

LTC4041

ABSOLUTE MAXIMUM RATINGS

PIN CONFIGURATION

(Note 1)

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V (Transient) t < 1ms, Duty Cycle < 1% ..... –0.3V to 7V

IN

V (Steady State), SCAP, BAL, CLN,

IN

V

SYS

, BSTFB, PFI, CPF, CAPFB, CAPFLT,

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PFO, SYSGD, OVSNS, IMON............................–0.3V to 6V

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BSTEN, CHGEN, CAPGD, RSTFB,

CAPSEL........... –0.3V to [Max (V , V

, V ) +0.3V]

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IN SCAP SYS

CHGEN

BSTEN

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PFO

I

.................................................................. 10mA

CAPGD PFO SYSGD

OVSNS

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, I , I

...............................................10mA

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ꢌAꢄꢎꢋ

I

....................................................................–1.1mA

PROG

ꢀ

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Operating Junction Temperature Range

(Notes 2, 3)............................................ –40°C to 125°C

Storage Temperature Range .................. –65°C to 150°C

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ORDER INFORMATION

LEAD FREE FINISH

TAPE AND REEL

PART MARKING

PACKAGE DESCRIPTION

TEMPERATURE RANGE

LTC4041EUFD#PBF

LTC4041EUFD#TRPBF

4041

24-Lead (4mm × 5mm × 0.75mm)

Plastic QFN

–40°C TO 125°C

LTC4041IUFD#PBF

LTC4041IUFD#TRPBF

4041

24-Lead (4mm × 5mm × 0.75mm)

Plastic QFN

–40°C TO 125°C

Consult ADI Marketing for parts specified with wider operating temperature ranges.

Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.

Rev A

2

For more information www.analog.com

LTC4041

ELECTRICAL CHARACTERISTICS ^Theldenotes the specifications which apply over the specified operating

temperature range, otherwise specifications are at T_A= 25°C. (Note 3) V_IN= V_SYS= 5V, V_SCAP= 2.5V, R_PROG= 2k, unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

5.5

UNITS

l

V

Input Voltage Range

2.9

V

IN

Supercapacitor Voltage Range (Backup

Boost Input)

5.4

SCAP

Quiescent Current in Charger Mode with

Charging Complete and Backup Boost

Active (CAPSEL = 1)

V

and V

Total Quiescent Current

800

13

1600

26

µA

IN

SYS

SCAP Quiescent Current

Quiescent Current in Charger Mode with

Charging Complete and Backup Boost in

Sleep (CAPSEL = 1)

V

and V Total Quiescent Current

275

13

550

26

µA

IN

SYS

SCAP Quiescent Current

l

Quiescent Current in Backup Mode with

Backup Boost in Sleep

IN

V

Quiescent Current

75

1

150

2

µA

SYS

SCAP Quiescent Current

(V = 0V, CAPSEL = 1)

Quiescent Current in Shutdown

V

Quiescent Current

5.5

0

11

1

µA

IN

(CHGEN = BSTEN = CAPSEL = 1, V

= 0V)

SYS

l

SCAP Quiescent Current

Buck Supercapacitor Charger

V

CAPFB Pin Servo Voltage

0.788

–50

0.80

0

0.812

50

V

nA

CAPFB

CHG

I

CAPFB Pin Input Leakage Current

Regulated Supercapacitor Charge Current

R

= 2k, V

>1V

950

1000

1050

mA

PROG

SCAP

V

-to-V

Differential Undervoltage

(V

– V

) Falling

SCAP

) Rising

SCAP

30

100

50

150

70

200

mV

SYS

SCAP

SYS

Lockout Threshold

V

PROG

PROG Pin Servo Voltage

800

mV

h

Ratio of Charge Current to PROG Pin Current

Input Current Limit Threshold Voltage

2500

mA/mA

PROG

V

– V

23.5

22

25

26.5

28

mV

IN

CLN

l

A

V

Input Current Limit Amplifier Gain

CLN Input Bias Current

Ratio of V

to (V – V )

CLN

32

V/V

nA

IMON

IN

V

= V

300

CLN

IN

Recharge Threshold Voltage

End-of-Charge Indication

As a Percentage of the Regulated V

PROG Pin Average Voltage

96.2

90

97.5

100

92.5

2.5

98.8

%

RECHRG

SCAP

mV

%

CAPGD Rising Threshold

As a Percentage of the Regulated V

95

SCAP

Hysteresis

%

SCAP

f

Step-Down Converter Switching Frequency

High Side Switch On-Resistance

Low Side Switch On-Resistance

PMOS Switch Current Limit

V

>1V

SCAP

2.0

2.25

130

120

4.3

2.5

MHz

mΩ

A

OSC(BUCK)

R

P(BUCK)

N(BUCK)

I

3

LIM(BUCK)

Supercapacitor Balancer

V

Supercapacitor Balance Point

Balancer Source Current

Balancer Sink Current

As a Percentage of V

, V = 5V

SCAP SCAP

49

50

2.7

51

%

mA

V

BAL

I

V

= 5V, V

= 2.4V

SOURCE

SINK

SCAP

BAL

= 2.6V

l

Top/Bottom Supercapacitor Overvoltage

Threshold

(V

SCAP

– V ) and/or V Rising, CAPSEL = 1

2.8

BAL

Hysteresis

55

mV

Top/Bottom Supercapacitor Undervoltage

Threshold

(V

SCAP

– V ) and/or V Falling, CAPSEL = 1

–50

–20

BAL

Hysteresis

30

mV

Rev A

3

For more information www.analog.com

LTC4041

ELECTRICAL CHARACTERISTICS ^Theldenotes the specifications which apply over the specified operating

temperature range, otherwise specifications are at T_A= 25°C. (Note 3) V_IN= V_SYS= 5V, V_SCAP= 2.5V, R_PROG= 2k, unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Backup Boost Switching Regulator

l

V

BSTFB Pin Servo Voltage

0.78

–20

2.7

0.8

0.82

20

V

nA

V

BSTFB

I

BSTFB Pin Input Leakage Current

Programmed Boost Output Voltage Range

Step-Up Converter Switching Frequency

NMOS Switch Current Limit

V

= 0.9V

BSTFB

V

5

SYS-BACKUP

OSC(BST)

f

I

1.0

1.125

6.5

75

1.25

7.5

MHz

A

5.5

LIM(BST)

R

High Side Switch On-Resistance

Low Side Switch On-Resistance

mΩ

V

P(BST)

70

N(BST)

V

Overvoltage Shutdown Threshold

Rising

SYS

5.3

5.5

100

2.5

150

88

5.7

SYS

Hysteresis

mV

V

Boost Undervoltage Lockout

Hysteresis

Max(V , V

) Falling

SYS SCAP

mV

%

D

Maximum Boost Duty Cycle

NMOS Switch Leakage Current

PMOS Switch Leakage Current

Minimum Backup Time

MAX

BSTEN = 1, CHGEN = 1

0

1

µA

ms

0

t

C

= 1nF

CPF

2.2

MIN-BACKUP

SYSGD Comparator

RSTFB Threshold

l

V

Falling

0.72

–50

0.74

20

0.76

50

V

mV

nA

RSTFB

Hysteresis

I

RSTFB Pin Input Leakage Current

SYSGD Delay

V

= 0.9V

0

RSTFB

Rising & Falling

100

µs

RSTFB

Power-Fail Comparator

PFI Input Threshold

V

Falling

1.17

1.16

1.19

1.21

1.22

V

PFI

l

Hysteresis

40

0

mV

nA

µs

PFI Pin Leakage Current

V

= 1.3V

–100

100

PFI

PFI Delay to PFO

Falling

= 5V

0.5

0

PFI

PFO Pin Leakage Current

1

µA

mV

PFO

PFO Pin Output Low Voltage

Logic Input (BSTEN, CHGEN, CAPSEL, CAPFLT)

I

= 5mA

65

200

l

V

Logic Low Input Voltage

0.4

V

IL

Logic High Input Voltage

1.2

IH

I

IL

I

IH

Logic Low Input Leakage Current

Logic High Input Leakage Current

CAPSEL Pin Leakage Current

BSTEN, CHGEN

CAPSEL = 1

0

1

µA

10

Rev A

4

For more information www.analog.com

LTC4041

ELECTRICAL CHARACTERISTICS ^Theldenotes the specifications which apply over the specified operating

temperature range, otherwise specifications are at T_A= 25°C. (Note 3) V_IN= V_SYS= 5V, V_SCAP= 2.5V, R_PROG= 2k, unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Open-Drain Output (SYSGD, CAPGD)

Pin Leakage Current

5V at Pin

0

1

µA

Pin Output Low Voltage

CAPFLT Status Pin

5mA Into Pin

65

200

mV

CAPFLT Pin Pull-Down Current

Pin Leakage Current

V

= 200mV

10

0

µA

CAPFLT

5V at Pin

1

Overvoltage Protection

V

Overvoltage Protection Threshold

IGATE Output Voltage Active

IGATE Voltage Under Load

V

Rising, R = 6.2k

OVSNS

6.0

8

6.4

9.4

8.6

40

6.8

12

V

OV(CUTOFF)

OVGT

OVSNS

= V

= 5V

IN

OVSNS

5V Through 6.2k Into OVSNS, I

= 1μA

IGATE

V

OVGT(LOAD)

OVSNSQ

I

OVSNS Quiescent Current

V

= 5V

µA

ms

OVSNS

OVSNS Quiescent Current in Shutdown

IGATE Time to Reach Regulation

BSTEN = 1, CHGEN = 1

= 2.2nF

25

C

3.5

IGATE

Overtemperature (OT) Protection

Overtemperature Shutdown

Hysteresis

Temperature Rising

160

15

°C

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: This IC includes overtemperature protection that is intended

to protect the device during momentary overload conditions. Junction

temperature will exceed 125°C when overtemperature protection is active.

Continuous operation above the specified maximum operating junction

temperature may impair device reliability.

characterization and correlation with statistical process control. The

LTC4041I is guaranteed over the full –40°C to 125°C operating junction

temperature range. The junction temperature (T in °C) is calculated from

J

the ambient temperature (T , in °C) and power dissipation (P , in watts)

A

D

according to the formula:

T = T + (P • θ

)

JA

J

A

D

where the package thermal impedance θ = 43°C/W.

JA

Note that the maximum ambient temperature consistent with these

specifications is determined by specific operating conditions in

conjunction with board layout, the rated package thermal resistance and

other environmental factors.

Note 3: The LTC4041E is tested under pulsed load conditions such that

T ≈ T . The LTC4041E is guaranteed to meet performance specifications

J

A

from 0°C to 85°C junction temperature. Specifications over the –40°C

to 125°C operating junction temperature range are assured by design,

Rev A

5

For more information www.analog.com

LTC4041

T_A= 25°C, unless otherwise noted.

TYPICAL PERFORMANCE CHARACTERISTICS

I_SCAPvs V_SCAPwith Different

PROG Resistor Values

Step-Down Charger Efficiency

vs V_SCAP

V_CAPFBvs Temperature

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R

ꢀRꢁꢂ

R

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R

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R

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R

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ꢀꢁꢀꢂ ꢃꢁꢂ

ꢀꢁꢀꢂ ꢃꢁꢄ

Step-Down Charger Oscillator

Frequency vs Temperature

Step-Down Charger PMOS

On-Resistance vs V_SYS

Step-Down Charger NMOS

On-Resistance vs V_SYS

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ꢀꢁꢂ

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ꢀꢁꢀꢂ ꢃꢁꢀ

ꢀꢁꢀꢂ ꢃꢁꢄ

Charging Profile: Two 10F

Supercapacitors In Series

Backup to Normal Mode

Transition Waveform

Normal to Backup Mode

Transition Waveform

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ꢀꢁꢀ

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ꢀꢁ

R

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R

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R

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ꢀRꢁꢂ

ꢀꢁꢂꢃꢄꢁ

ꢀAꢁꢂꢃꢄ

ꢀ

ꢀꢁAꢂ

ꢀ

ꢀ ꢁA

ꢀꢁꢀ

ꢀAꢁꢂꢃꢄ

ꢀA

ꢀꢁ

ꢀA

ꢀꢁ

ꢀꢁꢀꢂ ꢃꢁꢄ

ꢀꢁꢂꢃꢄꢅꢆ

ꢀꢁꢁꢂꢃꢄꢅꢆꢇ

ꢀꢁꢂꢃꢄꢅ

Rev A

6

For more information www.analog.com

LTC4041

T_A= 25°C, unless otherwise noted.

TYPICAL PERFORMANCE CHARACTERISTICS

Charge Current Reduction Due to

Input Current Limit

PROG Voltage Transient

Backup Boost Output Voltage

(V_SYS) vs Temperature

Response To System Step Load

ꢀꢁꢁꢁ

ꢀꢁꢂꢂ

ꢀꢁꢁꢁ

ꢀꢁꢂꢂ

ꢀꢁꢁꢁ

ꢀꢁꢁ

ꢀꢁꢂ

ꢀ

ꢀꢁꢂ

ꢀ

ꢀ ꢁꢂꢃ ꢃꢄ ꢅꢆ

ꢀꢁꢀ

ꢀ

ꢀ ꢁꢂꢃꢄ

ꢀꢁAꢂ

ꢀꢁꢀAꢂ ꢃꢄꢅꢆꢀ ꢇꢆRRꢈꢄꢀ

ꢀ

ꢀꢁAꢂ

ꢀ ꢁꢂꢃꢄ

ꢀ

ꢀ ꢁꢂA

ꢀꢁꢀ

ꢀꢁꢂ

ꢀ

ꢀRꢁꢂ

ꢀ

ꢀꢁAꢂ

ꢀꢁꢀ

ꢀ

ꢀꢁꢂꢃ

ꢀꢁAꢂ

ꢀ

ꢀ ꢁꢂ

ꢀꢁꢀ

ꢀ

ꢀꢁꢀ

ꢀ

ꢀꢁAꢂ

ꢀ ꢁꢂꢃꢄ

R

ꢀ ꢁꢂ

ꢀRꢁꢂ

R = 10mΩ

ꢀ

R

ꢀRꢁꢂ

ꢀ ꢁꢂ

R

ꢀ

= 10mΩ

ꢀ

ꢀꢁꢂꢃ

ꢀ

ꢀꢁꢁ ꢀꢁꢁꢁ ꢀꢁꢂꢂ ꢀꢁꢁꢁ ꢀꢁꢂꢂ ꢀꢁꢁꢁ

ꢀꢁꢂꢃ

ꢀ

ꢀꢁꢂ

ꢀꢁꢂꢃ ꢄꢅꢆꢇ

ꢀꢁꢂ

ꢀꢁ

ꢀꢁꢂ

ꢀꢁꢀꢂꢃꢄ ꢅꢆAꢇ ꢈꢉRRꢃꢊꢂ ꢋꢌAꢍ

ꢀꢁꢂꢃꢁRAꢀꢄRꢁ ꢅꢆꢇꢈ

ꢀꢁꢀꢂ ꢃꢂꢁ

ꢀꢁꢀꢂ ꢃꢂꢂ

ꢀꢁꢀꢂ ꢃꢂꢄ

Backup Boost Oscillator

Frequency vs Temperature

Backup Boost Maximum

Duty Cycle vs Temperature

Backup Boost Efficiency

vs Load Current for V_SYS= 5V

ꢀꢁꢂꢃ

ꢀꢁꢀꢂ

ꢀꢁꢂꢂ

ꢀꢁꢂꢀ

ꢀꢁ

ꢀꢀ

ꢀꢁ

ꢀꢁꢁ

ꢀꢁ

ꢀ

ꢀ ꢁꢂ

ꢀꢁꢀ

ꢀ ꢁꢂꢃꢄ

ꢀ

ꢀ ꢁꢂ

ꢀꢁꢀ

ꢀ

ꢀ ꢁꢂꢃꢄ

ꢀꢁAꢂ

ꢀ

ꢀ ꢁꢂꢃꢄ

ꢀ

ꢀ ꢁꢂ

ꢀꢁꢀ

ꢀ

ꢀ ꢁꢂꢃꢄ

ꢀ

ꢀ ꢁꢂꢃꢄ

ꢀꢁAꢂ

ꢀꢁꢂ

ꢀꢁ

ꢀꢁꢂ

ꢀꢁ

ꢀꢁꢂ

ꢀꢁ

ꢀꢁꢂ

ꢀꢁꢁꢂ

ꢀ

ꢀꢁꢂꢃꢁRAꢀꢄRꢁ ꢅꢆꢇꢈ

ꢀꢁAꢂ ꢃꢄRRꢅꢆꢇ ꢈAꢉ

ꢀꢁꢀꢂ ꢃꢂꢄ

ꢀꢁꢀꢂ ꢃꢂꢀ

ꢀꢁꢀꢂ ꢃꢂꢄ

Backup Boost Efficiency

vs Load Current for V_SYS= 3.3V

Backup Boost NMOS

Backup Boost PMOS

On-Resistance vs V_SYS

ꢀꢁꢁ

ꢀꢁ

ꢀ

ꢀꢁꢂ

ꢀꢁꢁ

ꢀꢁ

ꢀꢁꢂ

ꢀꢁꢁ

ꢀꢁ

ꢀꢁꢂꢃꢄ

ꢀꢁꢂꢃ

ꢀ

ꢀ ꢁꢂꢁꢃ

ꢀꢁꢀ

ꢀꢁꢂꢃ

ꢀꢁꢂꢃꢄ

ꢀ

ꢀ ꢁꢂꢃꢄ

ꢀꢁAꢂ

ꢀꢁ

ꢀꢁꢂꢃꢄ

ꢀ

ꢀ ꢁꢂꢃꢄ

ꢀ

ꢀ ꢁꢂꢃꢄ

ꢀꢁ

ꢀꢁꢂ

ꢀꢁꢁꢂ

ꢀ

ꢀꢁꢂꢃ ꢀꢁꢂꢃ ꢀꢁꢂꢃ ꢀꢁꢂꢃ ꢀꢁꢂꢃ ꢀꢁꢂꢃ ꢀꢁꢂꢀ

ꢀꢁAꢂ ꢃꢄRRꢅꢆꢇ ꢈAꢉ

ꢀ

ꢀꢁꢂ

ꢀ

ꢀꢁꢂ

ꢀꢁꢀ

ꢀꢁꢀꢂ ꢃꢂꢄ

Rev A

7

For more information www.analog.com

LTC4041

T_A= 25°C, unless otherwise noted.

TYPICAL PERFORMANCE CHARACTERISTICS

Burst Mode to Constant

Frequency Mode Transition

Waveform

Boost Sleep Mode I_SYSQand

I_SCAPQvs Temperature

Backup Boost Transient

Response to Load Step

ꢀꢁ

ꢀ

ꢀꢁꢂ

ꢀ

ꢀꢁꢂ

ꢀ

ꢀ ꢁꢂ

ꢀ ꢁ ꢂꢃꢂꢄꢅ

ꢀ

ꢀ ꢁꢂꢃꢄ

ꢀꢁꢀ

ꢀAꢁꢂꢃꢄ ꢅ ꢆꢇ

ꢀ

ꢀ ꢁꢂꢃꢄ

ꢀꢁAꢂ

ꢀ

ꢀꢁꢀ

ꢀ ꢁꢂꢂꢃꢄ

ꢀ

ꢀ ꢁꢂꢂꢃꢄ

ꢀꢁꢀ

ꢀ ꢁ ꢂꢃꢂꢄꢅ

ꢀ

ꢀꢁꢀ

ꢀ

ꢀ ꢁ

ꢀ ꢁꢂꢃꢄ

ꢀꢁAꢂꢃ ꢀꢁAꢂ

ꢀ ꢁ

ꢀꢁꢀꢂ ꢀꢁAꢂ

ꢀ ꢁ

ꢀ ꢁꢂꢃꢄ

ꢀꢁAꢂꢃ ꢀꢁAꢂ

ꢀ ꢁ ꢀ ꢁꢂꢃꢄ

ꢀ

ꢀꢁꢀꢂ ꢀꢁAꢂ

ꢀ

ꢀꢁꢀ

ꢀ

ꢀꢁꢀ

ꢀ

ꢀꢁꢂ

ꢀꢁ

ꢀꢁꢂ

ꢀꢁꢂꢃ

ꢀꢁꢀ

ꢀꢁꢂ

ꢀꢁꢂꢃ

ꢀꢁꢀ

ꢀꢁꢂ

ꢀꢁꢂꢃꢁRAꢀꢄRꢁ ꢅꢆꢇꢈ

ꢀꢁꢂꢃ ꢄꢅꢆꢇ

ꢀꢁꢀꢂ ꢃꢂꢄ

ꢀꢁꢀꢂ ꢃꢄꢁ

ꢀꢁꢀꢂ ꢃꢄꢂ

OVP Module Shutdown Voltage

(Through 6.2k) vs Temperature

OVSNS Pin Quiescent Current

vs Temperature

ꢀꢁꢂꢃ

ꢀꢁ

ꢀꢀ

ꢀꢁ

ꢀ

ꢀ ꢁꢂ

ꢀꢁꢂꢃꢂ

ꢀꢁꢂ

ꢀꢁ

ꢀꢁꢂ

ꢀꢁ

ꢀꢁꢂ

ꢀꢁꢂꢃꢁRAꢀꢄRꢁ ꢅꢆꢇꢈ

ꢀꢁꢀꢂ ꢃꢄꢄ

ꢀꢁꢀꢂ ꢃꢄꢅ

Supercapacitor Balancer

Source/Sink Current

Minimum V_SCAPto Maintain

Boost Regulation vs I_SYS

ꢀꢁꢂ

ꢀ

ꢀꢁ

ꢀRꢁꢂRAꢃꢃꢄꢅ ꢆ

ꢀ ꢁꢂ

ꢀ ꢁꢂꢁꢃ

ꢀꢁꢀ

ꢀAꢁꢂꢃꢄ ꢅ ꢆꢇ

ꢀRꢁꢂRAꢃꢃꢄꢅ ꢆ

ꢀꢁꢀ

ꢀꢁ

ꢀ

ꢀꢁꢂ

ꢀꢁꢂꢂ

ꢀꢁꢂꢃ

ꢀꢁꢀꢂꢃ ꢄAꢅꢅꢆꢇꢂ

ꢀ

ꢀ ꢁꢂ

ꢀ ꢁꢂꢃꢄ

ꢀꢁAꢂ

ꢀꢁ

ꢀꢁꢂ

ꢀꢁꢁꢂ

ꢀ

ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁꢁ

ꢀꢁ ꢀꢁꢂ

ꢀ

ꢀAꢁ

ꢀ

ꢀꢁꢀ

ꢀAꢁ ꢀꢁAꢂ

ꢀꢁꢀꢂ ꢃꢄꢅ

ꢀꢁꢀꢂ ꢃꢄꢀ

Rev A

8

For more information www.analog.com

LTC4041

PIN FUNCTIONS

V

(Pins 1, 24): System Voltage Output Pin. This pin is

supercapacitor exceeds 2.7V, this pin is pulled low and

charging is disabled. In backup mode, if the voltage of any

single supercapacitor falls below –20mV, the CAPFLT pin

is pulled low and the backup boost is disabled. To keep

charging or backup enabled under any supercapacitor

fault condition, tie this pin high. The current pull-down

capability of the CAPFLT is 10µA.

SYS

used to provide power to an external load from either the

primary input supply or from the backup supercapacitor

if the primary input supply is not available. In addition to

supplying power to the load, this pin provides power to

charge the supercapacitor when input power is available.

V_SYSshould be bypassed with a low ESR ceramic capaci-

tor of at least 100μF to GND.

BAL (Pin 9): Supercapacitor Balance Point. Connect the

common node of a stack of two supercapacitors to this

pin. An internal supercapacitor balancer drives this node

PROG (Pin 2): Charge Current Program Pin. An external

resistor from the PROG pin to GND programs the full-

scale charge current. At full scale, the PROG pin servos

to 0.8V. The ratio of the SCAP pin current to the PROG

pin current is internally set to 2500.

to a voltage that is half of V

. Leave this pin open if

SCAP

only one supercapacitor is used.

RSTFB (Pin 10): SYSGD Comparator Input. High imped-

ance input to an accurate comparator with a 0.74V falling

threshold and 20mV hysteresis. This pin controls the state

of the SYSGD output pin. An external resistor divider is

IMON (Pin 3): V_SYSCurrent Monitoring Pin. The ratio

between the IMON pin voltage and the differential voltage

between V and CLN is internally set to 32. Charge cur-

IN

rent is reduced when the IMON pin voltage reaches 0.8V.

used between V , RSTFB and GND. It can be the same

SYS

resistor divider as the BSTFB divider to monitor the sys-

tem output voltage V_SYS. See the Applications Information

section.

CHGEN (Pin 4): Disable Pin for the Supercapacitor

Charger. Tie this pin to GND to enable the charger or to

a voltage above 1.2V to disable it. Do not leave this pin

unconnected.

SYSGD (Pin 11): Open-Drain Status Output of the SYSGD

Comparator. This pin is pulled to GND by an internal

N-channel MOSFET whenever the RSTFB pin falls below

0.74V.

BSTEN (Pin 5): Disable Pin for the Backup Boost Converter.

Tie this pin to GND to enable the boost backup or to a volt-

age above 1.2V to disable backup. Do not leave this pin

unconnected.

CAPFB (Pin 12): Supercapacitor (Single or a Stack of

Two) Feedback Pin. An external divider between the

SCAP pin and GND with the center tap connected to the

CAPFB pin programs the final supercapacitor (or stack)

V

(Pin 6): Input Pin. Power can be applied directly to

IN

this pin if the optional overvoltage protection (OVP) fea-

ture is not used. For applications where the OVP feature

is required, connect an external N-channel FET between

voltage(V ). The voltage on this pin nominally servos

CHG

to 0.8V.

the input supply V

and this pin.

PWR

CAPGD (Pin 13): Supercapacitor Power Good Indicator

Pin. The open-drain output is pulled low until CAPFB rises

to 92.5% of its regulation point.

CLN (Pin 7): Negative terminal pin for an external cur-

rent limit sense resistor connected between V and this

IN

pin. This resistor is used to monitor the current from V

IN

to V . The LTC4041 reduces charge current in order

PFO (Pin 14): Open-Drain Power-Fail Status Output. This

pin is pulled to GND by an internal N-channel MOSFET

when the PFI input is below the falling threshold of the

power-fail comparator. Once the PFI input rises above the

rising threshold, this pin becomes high impedance.

SYS

to maintain 25mV across this sense resistor. However,

it does not limit the system current if the drop exceeds

25mV.

CAPFLT (Pin 8): Open-Drain Supercapacitor Fault Status

Output. In charger mode, if the voltage of any single

Rev A

9

For more information www.analog.com

LTC4041

PIN FUNCTIONS

IGATE (Pin 15): Gate Pin for the External N-Channel

FET(s). This pin is driven by an internal charge pump

to develop sufficient overdrive to fully enhance the pass

transistors. The first pass transistor, connected between

PFI (Pin 19): Power-Fail Input. High impedance input to

an accurate comparator (power-fail) with a 1.19V falling

threshold and 40mV hysteresis. PFI controls the state of

the PFO output pin and sets the input voltage threshold

below which the boost backup is initiated. This thresh-

old voltage also represents the minimum voltage above

which the step-down supercapacitor charger is enabled

and power is allowed to flow from the input to the output

through the external pass transistor(s).

the input power supply and V , is a part of the optional

IN

overvoltage protection module. The second pass transis-

tor, connected between V and V , is mandatory and

IN

SYS

is used to disconnect the system from the input supply

during backup mode.

OVSNS (Pin 16): Overvoltage Protection Sense Input. If

the overvoltage feature is used, the OVSNS pin should

be connected through a 6.2k resistor to the input power

supply and the drain of an N-channel MOS pass transistor.

CAPSEL (Pin 20): Supercapacitor Stack Selector Pin. Tie

this pin to a voltage higher than 1.2V if a stack of two

supercapacitors is connected to the SCAP pin or to GND

if a single supercapacitor is connected to the SCAP pin.

Do not leave this pin unconnected.

If not, this pin should be shorted to V . When voltage is

IN

detected on OVSNS, it draws a small amount of current

to power a charge pump which then provides gate drive

to IGATE to energize the external transistor(s). When the

voltage on this pin exceeds 6V (typical), IGATE is pulled

to GND to disable the pass transistor and protect the

LTC4041 from high voltage.

SW (Pins 21, 22): Switch Pins for the Buck Charger and

the Boost Backup Converter. A 1μH to 2.2μH inductor

should be connected from SW to SCAP.

SCAP (Pin 23): Supercapacitor Pin. Connect a single

supercapacitor or the top of a two-supercapacitor stack

to this pin. Depending on the availability of input power,

the supercapacitor (or the stack) will either deliver power

CPF (Pin 17): Minimum Backup Time (t_MIN-BACKUP

)

Program Pin. Connect a capacitor to this pin to set

t_MIN-BACKUP. When backup mode is initiated, the LTC4041’s

to V

via the boost converter or be charged from V

SYS

via the buck charger.

backup boost converter stays on for at least t

MIN-BACKUP

GND (Exposed Pad Pin 25): The exposed pad must

be soldered to the PCB to provide a low electrical and

thermal impedance connection to the printed circuit

board’s ground. A continuous ground plane on the sec-

ond layer of a multilayer printed circuit board is strongly

recommended.

to prevent any unwanted mode switching. The output of

the power-fail comparator is ignored during this time. Do

not tie this pin to GND or leave it unconnected.

BSTFB (Pin 18): Feedback Input for the Backup Boost

Regulator. During backup operation, the voltage on this

pin servos to 0.8V.

Rev A

10

For more information www.analog.com

LTC4041

BLOCK DIAGRAM

R

ꢌ

ꢝꢆꢐ

ꢐꢖ

ꢌꢢꢌꢄꢃꢝ

ꢛꢆꢍꢈꢄ

ꢝꢆꢔ

ꢘ

ꢙ

ꢓ

ꢐ

ꢔꢑ

ꢘꢞꢔꢟ

ꢚ

ꢀꢅꢆ

ꢛꢝꢋꢆ

ꢛꢂAꢄꢃ

ꢚꢌꢢꢌ

ꢛꢆ

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ꢐꢘ

ꢌꢢꢌꢂꢡ

Rꢌꢄꢠꢇ

ꢐꢐ

ꢐꢕ

R

ꢇꢠꢇꢐ

R

ꢇꢠꢇꢔ

ꢘꢚ

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ꢣ ꢓꢔ

ꢕꢞꢙꢑꢚ

ꢎ

ꢏ

A

ꢚ

ꢎ

ꢏ

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ꢏ

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ꢏ

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R

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ꢀꢋꢝꢍARARꢄꢋR

ꢍꢠꢔ

PFO

ꢏ

ꢎ

ꢅꢐ

ꢌꢜ

BSTEN

CHGEN

ꢍꢜꢝ

ꢔꢐ

ꢖ

ꢐꢞꢐꢗꢚ

ꢀ

ꢋꢈꢄ

ꢇꢈꢀꢉꢊꢇꢋꢋꢌꢄ

CAPFLT

ꢒ

ꢑ

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ꢀꢄRꢅ

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ꢇAꢅ

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ꢎ

ꢏ

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ꢔꢓ

ꢗ

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ꢀ

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ꢎ

ꢏ

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ꢔꢞꢙꢚ

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ꢇAꢅ

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ꢀAꢍꢂꢡ

ꢛꢝꢋꢆ ꢕꢞꢒꢚ ꢕꢞꢒꢚ

ꢕꢞꢒꢚ

ꢔꢕ

ꢐꢓ

R

ꢍRꢋꢂ

R

ꢠꢇꢐ

ꢀAꢍꢠꢇ

ꢕꢞꢙꢑꢚ

ꢀAꢍꢠꢇ

ꢎ

ꢏ

ꢐꢔ

ꢠꢇꢔ

ꢂꢆꢡ

ꢔꢖ

ꢑꢕꢑꢐ ꢇꢡ

Rev A

11

For more information www.analog.com

LTC4041

OPERATION

The LTC4041 is a complete supercapacitor backup system

manager for a 2.9V to 5.5V supply rail. The system has

three principal circuit components: a full-featured step-

down (buck) supercapacitor charger, a step-up (boost)

backup converter to deliver power to the system load

when external input power is lost, and a power-fail com-

parator to decide which one to activate. The LTC4041 has

several other auxiliary components: an input current limit

(IMON) amplifier, an optional input overvoltage protec-

tion (OVP) circuit, and a system power good (SYSGD)

comparator.

(2.25MHz) synchronous buck converter used to charge

SCAP from V via the SW pin. It is capable of directly

SYS

charging the supercapacitor to its charge voltage with an

externally programmable charge current up to 2.5A from

an input supply as high as 5.5V. A zero current com-

parator monitors the inductor current and shuts off the

NMOS synchronous rectifier once the current reduces to

approximately 250mA. This prevents the inductor current

from reversing and improves efficiency for low charg-

ing currents. The charger can be disabled by pulling the

CHGEN pin above 1.2V.

The LTC4041 has three modes of operation: normal,

backup and shutdown. If the input supply is above an

externally programmable PFI threshold voltage, the

LTC4041 is considered to be in normal mode. In this

Constant-Current Mode Charging

In constant-current (CC) mode, the average current

delivered to the supercapacitor can reach 2000V/ R

.

PROG

Depending on the external load condition, the superca-

pacitor charger may or may not be able to charge at the

full programmed rate. The external load will always be

prioritized over the supercapacitor charge current. The

charger will charge at the full programmed rate only if

the sum of the external load and the charger input current

normal mode power flows from input to output (V_SYS

)

while the step-down switching regulator charges a super-

capacitor or a stack of supercapacitors to a charge voltage

programmed by an external resistor divider connected at

the CAPFB pin. Refer to the Block Diagram.

The total system load is monitored by the IMON amplifier

is less than or equal to the input current limit set by R .

S

via an external series resistor, R , connected between the

S

If the buck charger is operating at very low duty cycles

(i.e. if the supercapacitor voltage is very low), the actual

average charge current delivered to the supercapacitor

could vary by as much as 50% of the programmed value.

At low duty cycles, the measurement accuracy of the

inductor current sensing circuitry in the CC servo loop is

low. As a result, the average charge current could over-

shoot or undershoot. When the supercapacitor (or a stack

of supercapacitors) is charged from 0V, the low accuracy

of the inductor current sensing causes the buck to operate

in discontinuous mode. As the SCAP voltage increases

the buck will try to servo the average charge current to

the programmed value. When the SCAP voltage is about

1V, the buck exits discontinuous mode and the average

charge current will be at the programmed level. During

V

and CLN pins. This amplifier can reduce the charge

IN

current from its programmed value (set by the PROG

pin external resistor R

) if the external load demand

PROG

increases beyond the level set by R .

S

When the input supply falls below the PFI threshold,

backup mode disconnects the switches (MN1 and MN2)

to isolate the system (V ) from the input, and the boost

SYS

converter powers the system load from the supercapacitor

using the external inductor, L1.

THE SUPERCAPACITOR CHARGER

The LTC4041 includes a full-featured constant-current

(CC)/ constant-voltage (CV) supercapacitor charger with

programmable charge current and charge voltage, auto-

matic recharge, supercapacitor good indicator, superca-

pacitor overvoltage detection, and an internal balancer.

The charger is a high efficiency, constant frequency

this discontinuous mode of operation, the V

voltage

SYS

ripple is still well-controlled despite the large inductor cur

-

rent ripple because the buck is running at a low duty cycle.

Rev A

12

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LTC4041

OPERATION

Figure 1 shows the buck charger operating in discon-

tinuous mode. The supercapacitor voltage is at 0V and

supercapacitor voltage must be below V

for at least

5ms (typical) for the charger to be re-e^Rn^Ea^Cb^Hle^Rd^G.

the charge current is programmed to 500mA. The V

SYS

Supercapacitor Charge Status Indication via the

CAPGD Pin

voltage ripple, which is also shown in the same figure, is

about 14mV in this example.

The CAPGD pin is an open-drain output used to indicate

that the supercapacitor (or the stack) voltage has reached

92.5% of its regulation point. The CAPGD pin is pulled

low until the supercapacitor voltage is above 92.5% of

the final charge voltage at which point the CAPGD pin

becomes high impedance. The supercapacitor voltage has

to fall below 90% of the regulation point to pull the CAPGD

pin low again. The CAPGD pin requires an external pull-up

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pin or to another appropriate

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SYS

power source. When the charger is disabled, the CAPGD

pin is pulled low.

Figure 1. Charge Current Waveform for V_SCAP<1V

Charge Termination

Supercapacitor Balancer

The charge voltage of the supercapacitor (or the stack) is

set by an external resistor divider connected between the

SCAP pin and ground with its midpoint connected to the

CAPFB pin. As the voltage on the supercapacitor reaches

the pre-set charge voltage, the constant-voltage (CV) loop

of the buck charger starts to regulate the supercapacitor

voltage and the charge current decreases naturally. Once

the charge current drops to 12.5% of the programmed

charge current, the buck charger is disabled and no

charge current will be delivered to the supercapacitor. To

enable the buck charger and resume charging, the super-

capacitor voltage has to fall below the automatic recharge

threshold.

The LTC4041 has an internal balancer that servos the mid-

point of a stack of two supercapacitors, i.e. the BAL pin

voltage, to half the stack voltage (V

). To activate the

SCAP

balancer, tie the CAPSEL pin high to indicate that a stack

of two supercapacitors is connected to the SCAP pin with

the midpoint of the stack connected to the BAL pin. The

source/sink capability of the internal balancer is typically

50mA with V

at 5V. The balancer will try to balance

SCAP

the stack of supercapacitors even after charging is com-

pleted. The balancer circuitry is disabled if the charger is

disabled. The balancer is also disabled if the CAPSEL pin

is low. When a single supercapacitor is connected to the

SCAP pin, tie the CAPSEL pin low and float the BAL pin.

Automatic Recharge

Differential Undervoltage Lockout

Once the supercapacitor charger terminates, it remains

off drawing only microamperes of current from the super-

capacitor. To ensure that the supercapacitor is always

topped off, a charge cycle automatically begins when

An undervoltage lockout circuit monitors the differential

voltage between V

and SCAP and shuts off the char-

SYS

ger if the SCAP voltage reaches within 50mV of the V

SYS

voltage. Charging does not resume until this difference

the supercapacitor voltage falls below V

(typically

from

RECHRG

increases to 150mV.

97.5%). To prevent brief excursions below V

enabling/disabling the buck charger unnec^Re^Es^Cs^Ha^Rri^Gly, the

Rev A

13

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LTC4041

OPERATION

Input Current Limit and IMON Monitor

switching regulator with output disconnect and auto-

matic Burst Mode features. The regulator can provide a

maximum load of 2.5A from a supercapacitor (or a stack

of two supercapacitors) and the system output voltage

The LTC4041 contains an input current limit circuit which

monitors the total system current (the external load plus

the charger input current) via an external series resis-

tor, R_S, connected between the V_INand CLN pins. The

LTC4041 does not actually limit the external load but as

the external load demand increases, it reduces charge

current, if necessary, in an attempt to maintain a maxi-

mum of 25mV across the V_INand CLN pins. Refer to

Programming the Input Current Limit and IMON Monitor

section in Applications Information. However, if the exter-

nal load demand exceeds the limit set by R_S, the LTC4041

does not reduce the load current but the charge current

will drop to zero. In all scenarios, the voltage on the

IMON pin will correctly represent the total system cur-

rent. 800mV on the IMON pin represents the full-scale

(V ) can be programmed up to a maximum of 5V via

SYS

the BSTFB pin. See the Applications Information section

for details. The converter can be disabled by pulling the

BSTEN pin high. The boost regulator includes safety fea-

tures like short-circuit current protection, input undervolt-

age lockout, and output overvoltage protection.

Zero Current Comparator

The LTC4041 boost converter includes a zero current

comparator which monitors the inductor current and

shuts off the PMOS synchronous rectifier once the current

drops to approximately 250mA. This prevents the induc-

tor current from reversing in polarity thereby improving

efficiency at light loads.

current set by the external series resistor, R .

S

SUPERCAPACITOR FAULT INDICATION VIA THE

PMOS Synchronous Rectifier

CAPFLT PIN

To prevent the inductor current from running away, the

PMOS synchronous rectifier is only enabled when V

The LTC4041 is equipped with comparators to detect if

the voltage on the supercapacitor (or either supercapacitor

in the stack) has exceeded the overvoltage (OV) thresh-

old (2.7V typical) or has fallen below the undervoltage

(UV) threshold (–20mV typical). Overvoltage detection is

enabled only during charging and undervoltage detection

is enabled only during backup. Undervoltage detection is

also disabled if a single supercapacitor is used (CAPSEL

pin is set to low).

>

SYS

(V

– 200mV). Additionally, if the current through the

SCAP

synchronous FET (PMOS) ever exceeds 8A, the converter

skips the next two clock cycles so that the inductor cur-

rent has a chance to discharge safely below this level.

Short-Circuit Protection

The output disconnect feature enables the LTC4041 boost

converter to survive a short circuit at its output. It incor-

porates internal features such as current limit foldback

and thermal shutdown for protection from excessive

power dissipation during short circuit.

The CAPFLT pin is an open-drain output pin with a 10µA

(typical) pull-down current source. If the supercapacitor

is not under any fault conditions, the CAPFLT pin is high

impedance. If the supercapacitor is in an OV/UV condi-

tion, the CAPFLT pin is pulled low and charging or backup

is disabled. To ignore the fault condition (and continue

charging or backup), tie the CAPFLT pin high.

Max(V ,V

) Undervoltage Lockout

SYS SCAP

The LTC4041 incorporates an undervoltage lockout circuit

which shuts down the boost regulator when max(V

,

SYS

V

) drops below 2.5V. This is to ensure that the boost

SCAP

BACKUP BOOST CONVERTER

regulator has enough supply voltage to function properly.

To supply the system load from the supercapacitor

in backup mode, the LTC4041 contains a 1.125MHz

constant-frequency current-mode synchronous boost

Rev A

14

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LTC4041

OPERATION

Boost Overvoltage Protection

V

SCAP

> V

Operation

SYS

If the BSTFB node were inadvertently shorted to ground,

the boost converter output voltage (V_SYS) would increase

indefinitely with the maximum current that could be

sourced from the supercapacitor. The LTC4041 protects

against this by shutting off both switches if the output

voltage exceeds 5.5V.

The LTC4041 boost converter will maintain voltage regu-

lation even if its input voltage is above the output voltage.

This is achieved by terminating the switching of the syn-

chronous PMOS and applying V

voltage statically on

SCAP

its gate. This ensures that the slope of the inductor current

reverses during the time current is flowing to the output.

Since the PMOS no longer acts as a low impedance switch

in this mode, there will be more power dissipation within

the IC. This will cause a sharp drop in the efficiency. The

maximum output current should be limited in order to

maintain an acceptable junction temperature.

Burst Mode Operation

The LTC4041 boost converter provides automatic Burst

Mode operation which increases the efficiency of power

conversion at very light loads. Burst Mode operation is

initiated if the output load current falls below an internally

set threshold. Once Burst Mode operation is initiated, only

the circuitry required to monitor the output and the super-

capacitor undervoltage comparators (if CAPSEL = H)

are kept alive. This is referred to as the sleep state in

which the backup boost consumes only 75μA (typical,

CAPSEL = H) from the system output and 1μA (typical)

from the supercapacitor(s). When the V_SYSpin voltage

drops by about 1% from its nominal value, the boost con-

verter wakes up and commences normal PWM operation.

The output capacitor recharges and causes the LTC4041

to re-enter the sleep state if the output load remains less

than the Burst Mode threshold. The frequency of this

intermittent PWM or Burst Mode operation depends on

the load current. As the load current drops below the

burst threshold, the boost converter turns on less fre-

quently. When the load current increases above the burst

threshold, the converter seamlessly resumes continuous

PWM operation. Thus, Burst Mode operation maximizes

the efficiency at very light loads by minimizing switching

and quiescent losses. However, the output ripple typically

increases to about 2% peak-to-peak. Burst Mode ripple

can be reduced in some circumstances by placing a small

SYSGD COMPARATOR

The LTC4041 contains a SYSGD comparator which moni-

tors V

under all operating modes via the RSTFB pin

SYS

and reports the status via an open-drain NMOS transistor

on the SYSGD pin. At any time, if V falls 7.5% from its

SYS

programmed value, the SYSGD pin pulls low after a 100µs

(typical) delay. The comparator also waits 100µs (typical)

after V

rises above the threshold before making the

SYS

SYSGD pin high impedance. Refer to Programming the

SYSGD Comparator section in Applications Information.

POWER-FAIL COMPARATOR AND MODE SWITCHING

The LTC4041 contains a fast power-fail comparator which

switches the LTC4041 from normal to backup mode in the

event the input supply voltage falls below an externally

programmed threshold voltage. This threshold voltage

is programmed by an external resistor divider via the PFI

pin. See the Applications Information section for details

on how to choose values for the resistor divider. The out-

put of the power-fail comparator also directly drives the

gate of an open-drain NMOS to report the status of the

availability of input power via the PFO pin. If input power

is available, the PFO pin is high impedance; otherwise,

the pin is pulled down to ground.

phase-lead capacitor (C ) between the V

and BSTFB

PL

SYS

pins. However, this may adversely affect the efficiency and

the quiescent current at light loads. Typical values of C

range from 15pF to 100pF.

PL

Rev A

15

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LTC4041

OPERATION

At the onset of backup mode, the supercapacitor charger

shuts off and the external NMOS pass transistors (MN1

and MN2 in the Block Diagram) are quickly turned off by

discharging the IGATE pin to ground, thereby disconnect-

The optional overvoltage protection (OVP) module con-

sists of two pins. The first, OVSNS, is used to measure the

applied voltage through an external resistor. The second,

IGATE, is an output used to drive the gate pins of two

external N-channel FETs, MN1 and MN2 (Block Diagram).

The voltage at the OVSNS pin will be lower than the OVP

input voltage by about 250mV due to the OVP circuit’s

quiescent current flowing through the OVSNS resistor.

When OVSNS is below 6V, an internal charge pump drives

ing the system output V

from the input and activat-

SYS

ing the backup boost converter to promptly deliver load

from the supercapacitor. Although the power-fail com-

parator has a hysteresis of approximately 40mV, it may

not be able to overcome the input voltage spike resulting

from the sudden collapse of the forward current from the

IGATE to approximately 1.88 • V

. This enhances the

OVSNS

input to V . To prevent repetitive mode switching, the

N-channel FETs providing a low impedance connection to

V_SYSand power to the LTC4041. If OVSNS rises above 6V

due to a fault, IGATE is pulled down to ground, disabling

the external FETs to protect downstream circuitry. At the

same time, the backup boost converter activates to sup-

ply the system load from the supercapacitor. When the

voltage drops below 6V again, the external FETs are re-

enabled. If the OVP feature is not desired, remove MN1,

SYS

backup boost stays on for at least the minimum backup

time (t ) once activated. The minimum backup

MIN-BACKUP

time is programmed by connecting an external capacitor

between the CPF pin and ground. Refer to Programming

the Minimum Backup Time section in the Applications

Information. During this time, the power-fail comparator

output is ignored and an internal switch of approximately

270Ω pulls down the OVSNS pin to help discharge the

input. After the minimum backup time has elapsed, if the

power-fail comparator output indicates that power is still

not available, the backup boost continues to deliver the

load but the pull-down on the OVSNS pin is released.

When the power-fail comparator detects that input power

is available, the OVP charge pump starts to charge up

the IGATE pin but the backup boost converter continues

to deliver system load until IGATE is approximately 8V.

This ensures that the forward conduction path through

the external NMOS pass transistors has been established.

At this point, the backup boost gets deactivated and the

charger turns back on to charge the supercapacitor while

the system load gets delivered directly from the input to

short OVSNS to V , and apply external power directly

IN

to V .

IN

SHUTDOWN MODE OPERATION

The LTC4041 can be shutdown almost entirely by pulling

both CHGEN and BSTEN pin above 1.2V. In this mode,

the internal charge pump is shutdown and IGATE is pulled

to ground disconnecting the forward path from input to

output via the external FETs. Only the internal OVP shunt

regulator remains active to monitor the input supply for

any possible overvoltage condition and consuming about

25μA via the OVSNS pin. Total current draw from the

SCAP pin drops to below 1μA (V_SCAP= 2.5V) in shutdown.

V

through the pass transistors.

SYS

Overtemperature (OT) Protection

When the LTC4041 die temperature exceeds 160°C (typi-

cal), the buck charger and backup boost are shut down

to prevent any thermal damage and remain in shutdown

until the die temperature falls to 145°C (typical). In OT,

OPTIONAL INPUT OVERVOLTAGE PROTECTION (OVP)

The LTC4041 can protect itself from the inadvertent appli-

cation of excessive voltage with just two external com-

ponents: an N-channel FET (MN1) and a 6.2k resistor as

shown in the Block Diagram. The maximum safe overvolt-

age magnitude is determined by the choice of external

NMOS and its associated drain breakdown voltage.

the forward path from V to V

is disconnected by

IN

SYS

pulling the gate voltage of the external FET(s) to ground.

Rev A

16

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LTC4041

APPLICATIONS INFORMATION

Programming the Supercapacitor Charge Voltage

below the nominal input supply voltage so that supply

transients do not trip the comparator. On the other hand,

it should be set high enough so that the V_SYSvoltage

does not drop enough to trip the SYSGD comparator dur-

ing the transition to backup mode. For applications using

the overvoltage protection (OVP) module, select a value

The charge voltage for a supercapacitor or a stack of

supercapacitors is set by an external resistor divider as

shown in Figure 2. The charge voltage is given by the

following equation:

⎛

⎞

R

FB1

⎜

⎟

greater than 35k for R

.

PF1

V

= 0.8V • 1+

CHG

⎜

⎟

R

FB2

⎝

⎠

Programming the Supercapacitor Charge Current

where 0.8V is the typical CAPFB pin servo voltage

(V_CAPFB). Typical values for R_FB1and R_FB2are in the range

of 40k to 2MΩ. Small resistor values result in higher leak-

age current that will discharge the supercapacitor. If the

resistor values are too large, the parasitic capacitance on

the CAPFB pin could create an additional pole and cause

loop instability.

Supercapacitor charge current is programmed using a

single resistor from the PROG pin to ground. To set a

charge current of I , the PROG pin resistor value can

CHG

be determined using the following equation:

0.8V 2000V

R

= 2500 •

=

PROG

I

CHG

where 0.8V is the typical PROG pin servo voltage (V_PROG).

For example, to set the charge current to 1A, the value

of the PROG pin resistor should be 2k. The minimum

recommended charge current is 500mA, below which the

accuracy of the charge current suffers. This corresponds

to a maximum R_PROGresistor of 4k. The maximum charge

current is 2.5A.

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Figure 2. Programming the Charge Voltage

Programming the Input Current Limit and IMON

Monitor

Programming the Input Voltage Threshold for the

Power-Fail Comparator

The input current limit is programmed by connecting a

series resistor between the V and CLN pins. To limit the

IN

SYSLIM

The input voltage threshold below which the power-fail

status pin PFO indicates a power-fail condition and the

LTC4041 activates the backup boost operation can be

programmed by using a resistor divider from the supply

to GND via the PFI pin such that:

total system current to I

, the value of the required

resistor can be calculated using the following equation:

25mV

R =

S

I

SYSLIM

⎛

⎞

For example, to set the current limit to 2A, the series

resistor should be 12.5mΩ. As discussed in the Operation

section, the LTC4041 does not limit the system current

but reduces the charge current to zero in the event the

system load exceeds this limit.

R

PF1

⎜

⎟

V

= 1.19V • 1+

IN(PF)

⎜

⎟

PF2

⎝

⎠

where 1.19V is the typical power fail threshold voltage

(V ). See Block Diagram. The power fail threshold volt-

PFI

age should be set to a level between 200mV to 300mV

Rev A

17

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LTC4041

APPLICATIONS INFORMATION

The voltage on the IMON pin always represents the total

R

and R

are in the range of 40k to 2M. In most

BFB2

BFB1

system current I_SYSthrough the external series resis-

applications, the BSTFB and RSTFB pins can be shorted

tance, R . A voltage of 800mV on IMON represents the

together and only one resistor divider between V

GND is needed to set the V_SYSvoltage during ^Sb^Ya^Sckup

mode and the SYSGD threshold 7.5% below the V

programmed voltage.

and

S

full-scale current set by R . The system current can be

calculated from the IMON^Spin voltage by using the fol

lowing equation:

-

SYS

V

IMON

I

=

Programming the Minimum Backup Time

SYS

32 • R

S

The minimum backup time can be programmed by con-

necting an external capacitor between the CPF pin and

CPF MIN-BACKUP

calculated by the following equation:

For example, if the IMON pin voltage is 600mV and R is

S

12.5mΩ, then the total system current is 1.5A. As shown

in the block diagram, the IMON pin is not buffered inter-

nally, so it is important to isolate this pin before connect-

ing to an ADC or any other monitoring device. Failure to

do so can degrade the accuracy of this circuit.

ground. For a given capacitor (C ), t

can be

t

(ms)=2.2 • C (nF)

MIN-BACKUP

CPF

It is recommended to set t

in the range of 1ms

to 0.5s. If t

is ^Mto^INo^-Bs^Ah^Co^Kr^Ut,^Pthe LTC4041 could

Programming the Boost Output Voltage

oscillate be^Mtw^INe^-e^Bn^ACc^Kh^Ua^Prging and backup unnecessarily.

If the minimum backup time is too long, the amount of

energy drained from the supercapacitor on any single

backup event may be more than necessary.

The boost converter output voltage in backup mode can

be programmed for any voltage from 2.7V to 5V by using

a resistor divider from the V

pin such that:

pin to GND via the BSTFB

SYS

Note: When the LTC4041 is powered on, the C_CPFcapaci-

tor is pre-charged by the internal circuitry to 1V (typical)

with a 1µA current source. The time taken for the initial

pre-charge is given by:

⎛

⎞

R

BFB1

⎜

⎟

V

= 0.8V • 1+

SYS

⎜

⎟

R

BFB2

⎝

⎠

where 0.8V is the typical BSTFB pin servo voltage (V_BSTFB).

t

(ms) = 1 • C (nF)

CPF

PRE-CHARGE

See the Block Diagram. Typical values for R

and R

BFB2

are in the range of 40k to 2M. Too small a r^Be^Fs^Bis¹tor results

in a large quiescent current whereas too large a resistor

coupled with any parasitic BSTFB pin capacitance creates

an additional pole and may cause loop instability.

If a backup event occurs during this pre-charge time, the

total minimum backup duration will be longer than the

programmed value.

Choosing the External Resistor for the Overvoltage

Protection (OVP) Module

Programming the SYSGD Comparator

When overvoltage protection is activated, the OVSNS pin

is clamped at 6V. The external 6.2k resistor must be sized

appropriately to dissipate the resultant power. For example,

a 1/8W, 6.2k resistor can have at most √P_MAX• 6.2kΩ =

28V applied across its terminals. With 6V at OVSNS, the

maximum overvoltage magnitude that this resistor can with-

stand is 34V. A 0.25W, 6.2k resistor raises the value to 45V.

The OVSNS pin’s absolute maximum current rating of 10mA

imposes an upper limit of 68V protection.

The threshold for the SYSGD comparator can be pro-

grammed by using a resistor divider from the V

to GND via the RSTFB pin such that:

SYS

⎛

⎞

R

BFB1

⎜

⎟

V

= 0.74V • 1+

SYS(SYSGD)

⎜

⎟

R

BFB2

⎝

⎠

where 0.74V is the typical SYSGD pin (falling) threshold

voltage (V_RSTFB). See the Block Diagram. Typical value for

Rev A

18

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LTC4041

APPLICATIONS INFORMATION

Choosing the External Transistors (MN1 and MN2) for

the OVP Module and the Input-to-Output Disconnect

Switch

above equation to be 0.5μH. To account for inaccuracies

in the system and component values, the practical lower

limit should be 1μH. Since the backup boost operates

at half the frequency (1.125MHz), the inductor current

ripple with a 1μH inductor using the same equation will

be approximately 1A in backup mode. If this is excessive,

inductors up to 2.2μH can be used to lower the inductor

current ripple.

The LTC4041 uses a weak internal charge pump to pump

IGATE above the input voltage so that the N-channel exter-

nal FETs can be used as pass transistors. However, these

transistors should be carefully chosen so that they are

fully enhanced with a V of 3V. Since one of these pass

GS

transistors is the OVP FET, its breakdown voltage (BV_DSS

)

The other considerations when choosing an inductor are

the maximum DC current (IDC) and the maximum DC

resistance (DCR) rating as shown in Table 2. The chosen

inductor should have a max IDC rating which is greater

than the current limit specification of the LTC4041 in

order to prevent an inductor current runaway situation.

For the LTC4041, the maximum current that the inductor

can experience is approximately 8A in backup mode. It is

also important to keep the max DCR as low as possible

in order to minimize conduction loss to and help improve

the converter’s efficiency.

determines the maximum voltage the LTC4041 can with-

stand at its input. Also, care must be taken to avoid any

leakage on the IGATE pin, as it may adversely affect the

FET operation. See Table 1 for a list of recommended

transistors.

Table 1. Recommended NMOS FETs for Overvoltage Protection

and Disconnect Switch

NMOS FET

BVDSS

20V

R

ON

SIR424DP (Vishay)

SiS488DN (Vishay)

SiS424DN (Vishay)

7.4mΩ

7.5mΩ

8.9mΩ

40V

20V

Table 2. Recommended Inductors for the LTC4041

MAX MAX

PART

NUMBER

L

IDC DCR

SIZE IN mm

(L × W × H)

Choosing the Inductor for the Switching Regulators

(μH) (A) (mΩ)

MANUFACTURER

Since the same inductor is used to charge the superca-

pacitor in normal mode and to deliver the system load in

backup mode, its inductance should be low enough so

that the inductor current can reverse quickly as soon as

backup mode is initiated. On the other hand, the induc-

tance should not be so low that the inductor current is

discontinuous at the lowest charge current setting since

charge current accuracy suffers greatly if the inductor

XAL-5020-122 1.2 8.3 20.5 5.68 × 5.68 × 2 Coilcraft

www.coilcraft.com

XAL-6030-122 1.2 10.8 7.5 6.76 × 6.76 × 3.1 Coilcraft

www.coilcraft.com

XAL-6020-132 1.3

9

15.4 6.76 × 6.76 × 2.1 Coilcraft

www.coilcraft.com

XAL-6030-182 1.8 14 10.52 6.76 × 6.76 × 3.1 Coilcraft

www.coilcraft.com

XAL-5030-222 2.2 9.2 14.5 5.3 × 5.5 × 3.1

Coilcraft

www.coilcraft.com

current is discontinuous. Inductor current ripple (ΔI ) can

L

be computed using the following equation:

XAL-6030-222 2.2 15.9 13.97 6.38 × 6.58 × 3.1 Coilcraft

www.coilcraft.com

⎛

⎞

V

1

⎜

⎟

SCAP

831532200

2.2 14 15.3 6.5 × 7 × 3

Wurth Electronics

www.we-online.

com

ΔI = V

•

1–

•

⎜

⎟

L

SCAP

V

L • f

OSC

SYS

⎝

⎠

Since the lowest recommended charge current set-

ting is 500mA, inductor current will be discontinuous if

the ripple is more than twice that amount, i.e, 1A. For

Choosing the V

Capacitor

SYS

The worst-case delay for the backup boost converter to

meet the system load demand occurs when the PFI input

falls below the externally set threshold at a time when

the buck charger is charging at the highest setting of

V

= 5V, V

= 3.2V, f

= 2.25MHz (buck mode),

SYS

SCAP

OSC

and ΔI = 1A, the theoretical minimum inductor size to

L

avoid discontinuous operation can be computed using the

Rev A

19

For more information www.analog.com

LTC4041

APPLICATIONS INFORMATION

2.5A and the system load is also very high, e.g., 2.5A.

Under this scenario, as soon as the LTC4041 initiates

backup mode, the inductor current has to reverse from

2.5A (from SW to SCAP) to as high as the boost current

limit of approximately 6.5A (from SCAP to SW). That is a

Choosing a Supercapacitor

The backup energy requirement is the main consider-

ation when selecting a supercapacitor. The capacitance

per cell and the number of cells (maximum of two) needed

depends on the system load (I_SYS), system voltage (V_SYS),

backup boost efficiency (η), supercapacitor charge volt-

9A current change in the inductor with a slope of V

/L.

SCAP

At a low supercapacitor voltage of 3.2V, this would take

age (V ) and the duration of the backup (t

). The

BACKUP

CHG

almost 3μs even with a 1μH inductor. During this transi-

following equation can be used to estimate the amount

tion, C , the capacitor on the V

pin, has to deliver

SYS

of capacitance required for a given backup application:

the shortfall until the inductor current catches up with

the system load demand, and the capacitor will deplete

according to the following equation:

V

•I

• t

SYS SYS BACKUP

2

C

=

SCAP

η • (V

)

CHG

Δt

Another factor to be considered is the current rating of

the supercapacitor. With the LTC4041, the supercapacitor

could be charged with a current as high as 2.5A. During a

backup event, the supercapacitor could be discharged at a

current level as high as 7.5A. It is also important to select

a supercapacitor with low ESR to minimize power losses

in the supercapacitor during charging or backup. Other

factors to be considered are the lifetime of the superca-

pacitor at the charge voltage, and the capacitance degra-

dation over time.

C

= I

•

SYS

LOAD

ΔV

The size of the capacitor should be big enough to hold

the system voltage, V , up above the SYSGD threshold

during this transition. For a system load I

SYS

= 2.5A and

LOAD

transition time Δt = 3μs, if the maximum droop ΔV allowed

in the system output is 100mV, the required capacitance

at the V

pin should be at least 75μF. The other consid-

SYS

eration for choosing the V

capacitor size is the maxi-

SYS

mum acceptable output voltage ripple during steady-state

The internal balancer of the LTC4041 is designed to bal-

ance supercapacitors with capacitances greater than

100mF per cell. For lower capacitances, the balancer

servo loop could be unstable.

backup boost operation. For a given duty cycle D and

load I

, the output ripple V of a boost converter is

RIP

LOAD

calculated using the following equation:

I

1

LOAD

V

=

• D •

RIP

A list of supercapacitor suppliers is provided in Table 4.

C

f

OSC

SYS

Table 4. Supercapacitor Suppliers

If the maximum allowable ripple is 20mV under 2.5A

steady-state load while boosting from 3.2V to 5V

(D = 36%), the required capacitance at V_SYSis calculated to

be at least 40μF using the above equation. Refer to Table 3

for recommended ceramic capacitor manufacturers.

AVX

www.avx.com

Bussman

CAP-XX

www.cooperbussman.com

www.cap-xx.com

www.illcap.com

Illinois Capacitor

Maxwell

www.maxwell.com

www.murata.com

www.nesscap.com

www.tecategroup.com

Table 3. Recommended Ceramic Capacitor Manufacturers

Murata

AVX

www.avx.com

NESS CAP

Tecate Group

Murata

www.murata.com

www.t-yuden.com

www.vishay.com

www.tdk.com

Taiyo Yuden

Vishay Siliconix

TDK

Rev A

20

For more information www.analog.com

LTC4041

APPLICATIONS INFORMATION

Supercapacitor Charger Stability Considerations

size should not exceed 2.2μH because of the RHP zero

consideration. Also, too much resistance between the

supercapacitor and the SCAP pin can lower the effective

input voltage of the boost converter causing the RHP zero

to shift lower in frequency and thus causing instability.

This is why it is important to minimize the lead resistance

and place the supercapacitor as close to the SCAP pin as

possible.

The LTC4041’s switching supercapacitor charger contains

three control loops: constant-voltage, constant-current,

and input current limit loop, all of which are internally

compensated. However, various external variables like

load and component values may interfere with the inter-

nal compensation and cause instability.

In constant-current mode, the PROG pin is in the feedback

loop rather than the SCAP pin. Because of the additional

pole created by any PROG pin capacitance, capacitance on

this pin must be kept to a minimum. For the constant-cur-

rent loop to be stable, the pole frequency at the PROG pin

should be kept above 1MHz. Therefore, if the PROG pin

PCB Layout Considerations

Since the LTC4041 includes a high-current high-frequency

switching converter, the following guidelines should be

followed in the printed circuit board (PCB) layout in order

to achieve optimum performance and minimum electro-

magnetic interference (EMI).

has a parasitic capacitance, C

, the following equa-

PROG

tion should be used to calculate the maximum resistance

1. Even though the converter can operate in both step-

down (buck) and step-up (boost) mode, there is only

one hot-loop containing high-frequency switching

currents. The simplified diagram in Figure 3 can be

used to explain the hot-loop in the LTC4041 switch-

ing converter. Current follows the blue loop when the

switch S2 (NMOS) is closed and the red loop when

switch S1 (PMOS) is closed. So it is evident that the

value for R

:

PROG

1

R

≤

PROG

2π • 1MHz • C

PROG

Alternatively, for R

= 4k (500mA setting), the maxi-

PROG

mum allowable capacitance on the PROG pin is 40pF. If

any measuring device is attached to the PROG pin for

monitoring the charge current, a 1M isolation resistor

should be inserted between the PROG pin and the device.

current in the C

capacitor is continuous whereas

SCAP

the C

current is discontinuous forming a hot loop

SYS

with the V_SYSpins and GND as indicated by the green

loop. Since the amount of EMI is directly proportional

Backup Boost Stability Considerations

The LTC4041’s backup boost converter is internally com-

pensated. However, system capacitance less than 100µF

or over 1000μF will adversely affect the phase margin and

hence the stability of the converter. Also, if the right-half-

plane (RHP) zero moves down in frequency due to exter-

nal load conditions or the choice of the inductor value,

the phase margin may be reduced to a point which causes

to the area of this loop, the V

capacitor, prioritized

SYS

over all else, should be placed as close to the V

SYS

pins as possible and the ground side of the capacitor

should return to the ground plane through an array

of vias.

ꢀ

ꢁꢍꢁ

ꢁꢊ

instability. If the output power is P , inductor value is

OUT

ꢇꢊ

ꢀ

ꢁꢂAꢃ

L, efficiency is η, and the input to the boost converter

ꢂ

ꢄꢅꢆ ꢇꢅꢅꢃ

ꢁꢍꢁ

is V

, the RHP zero frequency can be expressed as

SCAP

follows:

ꢁꢎ

ꢂ

ꢁꢂAꢃ

2

ꢈꢉꢈꢊ ꢋꢉꢌ

V

(

)

SCAP

f

=

• η

RHP

2 • π • L • P

OUT

Figure 3. Hot-Loop Illustration for

the LTC4041 Switching Converter

For the LTC4041’s backup boost to be able to supply

12.5W of output power (2.5A at 5V) from a stack of

supercapacitors charged to 3.2V, the maximum inductor

Rev A

21

For more information www.analog.com

LTC4041

APPLICATIONS INFORMATION

2. To minimize parasitic inductance, the ground plane

should be as close as possible to the top plane of

the PC board (Layer 2). High frequency currents in

the hot loop tend to flow along a mirror path on the

ground plane which is directly beneath the incident

path on the top plane of the board as illustrated in

Figure 4. If there are slits or cuts or drill-holes in this

mirror path on the ground plane due to other traces,

the current will be forced to go around the slits. When

high frequency currents are not allowed to flow back

through their natural least-area path, excessive volt-

age will build up and radiated emissions will occur.

So every effort should be made to keep the hot-loop

current path as unbroken as possible.

3. The other important components that need to be

placed close to the pins are the supercapacitor (con-

nected to the SCAP pin) and the inductor L1. Even

though the current through these components is

continuous, they can change very abruptly due to

a sudden change in load demand. Also, their traces

should be wide enough to handle currents as high as

the NMOS current limit (typical 6.5A) in backup boost

mode.

4. Locate the V

dividers for BSTFB and RSTFB near

the IC but a^Sw^Ya^Sy from the switching components.

Kelvin the top of the resistor dividers to the positive

terminal of C . The bottom of the resistor dividers

SYS

should return to the ground plane away from the hot-

loop current path. The same is true for the PFI divider

and the CAPFB divider.

5. The exposed pad on the backside of the LTC4041

package must be securely soldered to the PC board

ground and also must have a group of vias con-

necting it to the ground plane for optimum thermal

performance. Also this is the only ground pin in the

package, and it serves as the return path for both the

control circuitry and the switching converter.

ꢀꢁꢀꢂ ꢃꢁꢀ

6. The IGATE pin for controlling the gates of the external

pass transistors has extremely limited drive current.

Care must be taken to minimize leakage to adjacent

PC board traces. To minimize leakage, the trace can

be guarded on the PC board by surrounding it with

Figure 4. High Frequency Ground Currents Follow

Their Incident Path. Slices in the Ground Plane

Cause High Voltage and Increased EMI

V

connected metal.

SYS

Rev A

22

For more information www.analog.com

LTC4041

TYPICAL APPLICATIONS

3.3V Backup System with 12V Buck for Automotive Application

(Charge Current Setting: 1A, Input Current Limit Setting: 2A)

V

IN

V

BST

IN

12V

EN/UV

4.7µF

10nF

0.1µF

V

PG

SYNC

TR/SS

LT8610

OUT

2.2µH

MN2

12mΩ

3.3V

SYSTEM

LOAD

SW

BIAS

47µF

100µF

1.07M

1.02M

10pF

1µF

FB

V

CLN

IGATE

V

SYS

BSTFB

RSTFB

INTV

IN

340k

CC

121k

75k

OVSNS

PFI

RT PGND GND

2.2µH

18.2k

422k

SW

SUPERCAP

50F

PFO

SCAP

LTC4041

SYSGD

CAPGD

IMON

698k

BAL

CAPFB

CAPFLT

348k

CHGEN BSTEN GND CAPSEL CPF PROG

1nF

2k

L1: COILCRAFT XAL-5030-222

MN2: VISHAY/SILICONIX SiS488DN

4041 TA02

5V Backup Application with Non-Backed Up 3.3V Load Option

(Charge Current Setting: 2.5A, Input Current Limit Setting: 2.5A)

V

SYS

MN1

10mΩ

4.7V TO 5V

INPUT SUPPLY

TO BACKED UP

SYSTEM OUTPUT

2.2µF

100µF

1050k

V

CLN

IGATE

V

SYS

BSTFB

RSTFB

IN

200k

OVSNS

PFI

113k

TO NON-BACKED UP

2.2µH

3.3V SYSTEM OUTPUT

SW

38.3k

PFO

SCAP

SUPERCAP

LTC4041

SYSGD

CAPGD

IMON

10F

BAL

1070k

SUPERCAP

10F

CAPFLT

CAPFB

CHGEN BSTEN GND CAPSEL

CPF PROG

340k

V

SYS

V

IN

V

SYS

1nF

806Ω

LDO

1M

2.5V OUTPUT

EN

V

OUT

GND

L1: COILCRAFT XAL-5030-222

MN2: VISHAY/SILICONIX SiS488DN

4041 TA02a

Rev A

23

For more information www.analog.com

LTC4041

PACKAGE DESCRIPTION

UFD Package

24-Lead Plastic QFN (4mm × 5mm)

ꢄReꢩeꢪeꢫꢬe ꢙꢎꢖ ꢈꢐꢑ ꢭ ꢂꢋꢚꢂꢮꢚꢃꢣꢯꢣ Rev Aꢊ

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ꢌꢍꢎꢉꢏ

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ꢋꢁ ꢉꢜꢒꢍꢆꢉꢈ ꢒAꢈ ꢆꢟAꢙꢙ ꢓꢉ ꢆꢍꢙꢈꢉR ꢒꢙAꢎꢉꢈ

ꢣꢁ ꢆꢟAꢈꢉꢈ ARꢉA ꢇꢆ ꢍꢌꢙꢢ A RꢉꢞꢉRꢉꢌꢖꢉ ꢞꢍR ꢒꢇꢌ ꢃ ꢙꢍꢖAꢎꢇꢍꢌ

ꢍꢌ ꢎꢟꢉ ꢎꢍꢒ Aꢌꢈ ꢓꢍꢎꢎꢍꢔ ꢍꢞ ꢒAꢖꢗAꢑꢉ

Rev A

24

For more information www.analog.com

LTC4041

REVISION HISTORY

REV

DATE

DESCRIPTION

PAGE NUMBER

A

01/19 Add Condition to I

spec

4

BSTFB

Modified Block Diagram pin numbering

11

21

Modified Backup Boost Stability Considerations section

Rev A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog

Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications

25

subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

For more information www.analog.com

LTC4041

TYPICAL APPLICATION

5V Backup Application with OVP Protection and Non-Backed Up Load Option

(Charge Current Setting: 2.5A, Input Current Limit Setting: 4A)

TO NON-BACKED-UP

OUTPUT

V

SYS

4.7V TO 5V

INPUT SUPPLY

(PROTECTED

TO 40V)

MN1

V

PWR

6mΩ

MN2

4.7V TO 5V

TO BACKED-UP

SYSTEM OUTPUT

2.2µF

6.2k 1/4W

OVP OPT

1.05M

100µF

V

CLN

IGATE

V

SYS

BSTFB

RSTFB

IN

200k

OVSNS

PFI

2.2µH

113k

SW

SCAP

BAL

38.3k

SUPERCAP

25F

PFO

LTC4041

SYSGD

CAPGD

IMON

SUPERCAP

25F

1.18M

255k

CAPFLT

CAPFB

CHGEN BSTEN GND CAPSEL CPF PROG

L1: COILCRAFT XAL-5030-222

MN1: VISHAY/SILICONIX SiS488DN

MN2: VISHAY/SILICONIX SiS488DN

V

1nF 806Ω

SYS

4041 TA03

RELATED PARTS

PART NUMBER

DESCRIPTION

COMMENTS

LTC3226

2-Cell Supercapacitor Charger with Backup

PowerPath™ Controller

1×/2× Multimode Charge Pump Supercapacitor Charger, Internal 2A LDO Backup

Supply, PowerPath, Automatic Main/Backup Switchover, Automatic Cell Balancing,

Input Voltage Range: 2.5V-5V, 16-Lead 3mm × 3mm QFN Package.

LTC3350/LTC3351 High Current Supercapacitor Backup Controller High Efficiency Synchronous Step-Down CC-CV Charging of 1-4 Series

and System Monitor

Supercapacitors, 14-Bit ADC for Monitoring System Voltage/Currents, Capacitance

and ESR, Programmable Input Current Limit, V : 4.5V to 35V, 38-Lead 5mm ×

IN

7mm QFN Package. LTC3351 is Also a Hot Swap Controller.

LTC3355

LTC4040

LTC4089

20V, 1A Buck DC/DC with Integrated SCAP

Charger and Backup Regulator

1A Main Buck Regulator, 5A Boost Backup Regulator Powered from Single

Supercapacitor, Overvoltage Protection, V : 3V to 20V, V : 2.7V to 5V,

IN

OUT

20-Lead 4mm × 4mm QFN Package.

2.5A Battery Backup Power Manager

3.5V to 5.5V Supply Rail Battery Backup System, 2.5A Backup from 3.2V Battery,

Input Current Limit Prioritizer, Pin Selectable Battery, 24-Lead 4mm × 5mm QFN

Package.

USB Power Manager with High Voltage

Switching Charger

1.2A Charger for Li-Ion from 6V to 86V Supply , Seamless Transition Between

Power Sources, Load Dependent Charging from USB Input, 215mΩ Internal Ideal

Diode plus Optional External Ideal Diode Controller, Thermal Regulation, 22-Lead

6mm × 3mm DFN Package

LTC4090

LTC4110

USB Power Manager with 2A High Voltage

Bat-Track™ Buck Regulator

Full Featured Li-Ion Battery Charger, 1.5A Maximum Charge Current with Thermal

Limiting, NTC Thermistor Input for Temperature Qualified Charging, 22-Lead

3mm × 6mm DFN Package.

Battery Backup System Manager

Complete Manager for Li-Ion/Polymer, Lead Acid, NiMH/NiCd Batteries and

Supercapacitors, Input Supply Range: 4.5V to 19V, Programmable Charge Current

up to 3A, 38-Lead 5mm × 7mm QFN Package.

LTC4155/LTC4156 Dual Input Power Manager/3.5A Li-Ion Battery 3.5A Charge Current for Li-Ion/Polymer, LTC4156 for LiFePO4 Batteries, Dual Input

2

Charger with I C Control and USB OTG

Overvoltage Protection Controller, Instant-On Operation with Low Battery, Priority

Multiplexing for Multiple Outputs, 28-Lead 4mm × 5mm QFN Package

LTC4160

Switching Power Manager with USB On-The-Go USB-OTG 5V Output, Overvoltage Protection, Maximizes Available Power from

and Overvoltage Protection

USB Port, Bat-Track, Instant-On Operation, 1.2A Max Charge Current with Thermal

Limiting, 1.2A Max Input Current Limit, 20-Lead 3mm × 4mm QFN Package

Rev A

D16901-0-2/19(A)

www.analog.com

26

 ANALOG DEVICES, INC. 2018 to 2019

For more information www.analog.com


型号：	LTC3350
厂家：	ADI
描述：	2.5A Supercapacitor Backup Power Manager
文件：	总26页 (文件大小：965K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC3350 [ADI]

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