LTC3350EUHF#PBF [Linear]
LTC3350 - High Current Supercapacitor Backup Controller and System Monitor; Package: QFN; Pins: 38; Temperature Range: -40°C to 85°C;
| 型号： | LTC3350EUHF#PBF |
| 厂家： | 
Linear |
| 描述： | LTC3350 - High Current Supercapacitor Backup Controller and System Monitor; Package: QFN; Pins: 38; Temperature Range: -40°C to 85°C |
| 文件： | 总46页 (文件大小：731K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC3350
High Current Supercapacitor
Backup Controller and
System Monitor
FeaTures
DescripTion
TheLTC®3350isabackuppowercontrollerthatcancharge
and monitor a series stack of one to four supercapacitors.
The LTC3350’s synchronous step-down controller drives
N-channelMOSFETsforconstantcurrent/constantvoltage
n
High Efficiency Synchronous Step-Down CC/CV
Charging of One to Four Series Supercapacitors
n
Step-Up Mode in Backup Provides Greater
Utilization of Stored Energy in Supercapacitors
n
14-Bit ADC for Monitoring System Voltages/Currents, chargingwithprogrammableinputcurrentlimit.Inaddition,
Capacitance and ESR
the step-down converter can run in reverse as a step-up
converter to deliver power from the supercapacitor stack
to the backup supply rail. Internal balancers eliminate the
need for external balance resistors and each capacitor has
a shunt regulator for overvoltage protection.
n
n
n
Active Overvoltage Protection Shunts
Internal Active Balancers—No Balance Resistors
V : 4.5V to 35V, V
: Up to 5V per Capacitor,
CAP(n)
IN
Charge/Backup Current: 10+A
n
Programmable Input Current Limit Prioritizes System
Load Over Capacitor Charge Current
The LTC3350 monitors system voltages, currents, stack
capacitance and stack ESR which can all be read over
n
n
n
Dual Ideal Diode PowerPath™ Controller
All N-FET Charger Controller and PowerPath Controller
Compact 38-Lead 5mm × 7mm QFN Package
2
the I C/SMBus. The dual ideal diode controller uses
N-channel MOSFETs for low loss power paths from the
input and supercapacitors to the backup system supply.
The LTC3350 is available in a low profile 38-lead 5mm ×
7mm × 0.75mm QFN surface mount package.
applicaTions
n
High Current 12V Ride-Through UPS
Servers/Mass Storage/High Availability Systems
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
PowerPath are trademarks of Linear Technology Corporation. All other trademarks are the
property of their respective owners. Patents pending.
n
Typical applicaTion
High Current Supercapacitor Charger and Backup Supply
I
(STEP-DOWN)
I
BACKUP
CHG
V
OUT
V
IN
Backup Operation
INFET VOUTSP VOUTSN
P
= 25W
BACKUP
PFI
OUTFB
V
> V
OUT
V
CAP
(DIRECT
CONNECT)
OUT
2V/DIV
OUTFET
TGATE
V
< V
OUT
CAP
(STEP-UP)
V
OUT
V
CAP
2V/DIV
SW
V
CAP
V
IN
BGATE
2V/DIV
LTC3350
V
IN
ICAP
VCAP
CAP4
0V
2
V
CAP
I C
10F
10F
10F
10F
3350 TA01a
400ms/DIV
BACK PAGE APPLICATION CIRCUIT
CAP3
CAP2
CAP1
CAPRTN
3350 TA01a
CAPFB
3350fc
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For more information www.linear.com/LTC3350
LTC3350
Table oF conTenTs
Features..................................................... 1
Applications ................................................ 1
Typical Application ........................................ 1
Description.................................................. 1
Absolute Maximum Ratings.............................. 3
Order Information.......................................... 3
Pin Configuration .......................................... 3
Electrical Characteristics................................. 4
Typical Performance Characteristics ................... 7
Pin Functions..............................................10
Block Diagram.............................................13
Timing Diagram...........................................14
Operation...................................................14
Introduction............................................................ 14
Bidirectional Switching Controller—Step-Down
Applications Information ................................21
Digital Configuration...............................................21
Capacitor Configuration..........................................21
Capacitor Shunt Regulator Programming ...............21
Setting Input and Charge Currents .........................21
Low Current Charging and High Current Backup ....22
Setting V
Voltage...............................................22
CAP
Power-Fail Comparator Input Voltage Threshold ...22
Setting V Voltage in Backup Mode....................23
OUT
Compensation.........................................................24
Minimum V Voltage in Backup Mode.................24
CAP
Optimizing Supercapacitor Energy Storage Capacity..
25
Capacitor Selection Procedure ...............................26
Inductor Selection...................................................26
Mode ...................................................................... 14
Bidirectional Switching Controller—Step-Up Mode 15
Ideal Diodes............................................................ 16
C
OUT
and C
Capacitance....................................27
CAP
Power MOSFET Selection .......................................28
Schottky Diode Selection........................................28
Gate Drive Supply (DRV ) .................................... 17
Top MOSFET Driver Supply (C , D ).......................29
B B
CC
Undervoltage Lockout (UVLO) ............................... 17
RT Oscillator and Switching Frequency .................. 17
Input Overvoltage Protection ................................. 17
INTV /DRV and IC Power Dissipation ...............29
CC CC
Minimum On-Time Considerations..........................30
Ideal Diode MOSFET Selection ...............................30
PCB Layout Considerations ....................................30
Register Map ..............................................32
Register Descriptions ....................................33
Typical Applications......................................39
Package Description .....................................44
Revision History ..........................................45
Typical Application .......................................46
Related Parts..............................................46
V
CAP
DAC ............................................................... 17
Power-Fail (PF) Comparator.................................... 17
Charge Status Indication......................................... 17
Capacitor Voltage Balancer .................................... 17
Capacitor Shunt Regulators.................................... 18
2
I C/SMBus and SMBALERT.................................... 18
Analog-to-Digital Converter .................................... 18
Capacitance and ESR Measurement ...................... 18
Monitor Status Register.......................................... 19
Charge Status Register...........................................20
Limit Checking and Alarms.....................................20
Die Temperature Sensor .........................................20
General Purpose Input............................................20
3350fc
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For more information www.linear.com/LTC3350
LTC3350
absoluTe MaxiMuM raTings
(Note 1)
pin conFiguraTion
V , VOUTSP, VOUTSN............................... –0.3V to 40V
IN
VCAP.......................................................... –0.3V to 22V
TOP VIEW
CAP4-CAP3, CAP3-CAP2, CAP2-CAP1,
CAP1-CAPRTN.......................................... –0.3V to 5.5V
DRV , OUTFB, CAPFB, SMBALERT, CAPGD,
CC
38 37 36 35 34 33 32
PFO, GPI, SDA, SCL .................................. –0.3V to 5.5V
BST......................................................... –0.3V to 45.5V
PFI ............................................................. –0.3V to 20V
CAP_SLCT0, CAP_SLCT1................................–0.3 to 3V
BST to SW ................................................ –0.3V to 5.5V
VOUTSP to VOUTSN, ICAP to VCAP ......... –0.3V to 0.3V
SCL
SDA
1
2
3
4
5
6
7
8
9
31 VOUTSP
30 VOUTSN
SMBALERT
CAPGD
VC
INTV
DRV
29
28
CC
CC
27 BGATE
BST
CAPFB
OUTFB
SGND
RT
26
39
PGND
25 TGATE
24 SW
I
.................................................................100mA
INTVCC
I
, I
, I
............................................ 600mA
.........................................10mA
CAP(1,2,3,4) CAPRTN
23 VCC2P5
22 ICAP
21 VCAP
I
, I
GPI 10
ITST 11
CAPGD PFO SMBALERT
Operating Junction Temperature Range
20
CAPRTN 12
OUTFET
(Notes 2, 3)..............................................–40°C to 125°C
Storage Temperature Range .................. –65°C to 150°C
13 14 15 16 17 18 19
UHF PACKAGE
38-LEAD (5mm × 7mm) PLASTIC QFN
T
JMAX
= 125°C, θ = 34°C/W
JA
EXPOSED PAD (PIN 39) IS PGND, MUST BE SOLDERED TO PCB
orDer inForMaTion
LEAD FREE FINISH
LTC3350EUHF#PBF
LTC3350IUHF#PBF
TAPE AND REEL
PART MARKING*
3350
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC3350EUHF#TRPBF
LTC3350IUHF#TRPBF
–40°C to 125°C
–40°C to 125°C
38-Lead (5mm × 7mm) Plastic QFN
38-Lead (5mm × 7mm) Plastic QFN
3350
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on nonstandard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
3350fc
3
For more information www.linear.com/LTC3350
LTC3350
elecTrical characTerisTics The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = VOUT = 12V, VDRVCC = VINTVCC unless otherwise
noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Switching Regulator
l
l
V
Input Supply Voltage
4.5
35
V
IN
I
Input Quiescent Current (Note 4)
4
mA
Q
V
Maximum Regulated V
Feedback Voltage
V
Full Scale (1111b)
Zero Scale (0000b)
1.188
1.176
1.200
1.200
1.212
1.224
V
V
CAPFBHI
CAP
CAPDAC
CAPDAC
V
Minimum Regulated V
Feedback Voltage
V
V
0.628
–50
0.638
0.647
50
V
CAPFBLO
CAPFB
CAP
l
l
I
CAPFB Input Leakage Current
Regulated V Feedback Voltage
= 1.2V
nA
CAPFB
V
1.188
1.176
1.200
1.200
1.212
1.224
V
V
OUTFB
OUT
V
OUTFET Turn-Off Threshold
OUTFB Input Leakage Current
Falling Threshold
1.27
–50
4.5
1.3
1.33
50
V
nA
V
OUTFB(TH)
OUTFB
l
l
I
V = 1.2V
OUTFB
V
V
V
Voltage in Step-Up Mode
V = 0V
IN
35
OUTBST
UVLO
OUT
l
l
INTV Undervoltage Lockout
Rising Threshold
Falling Threshold
4.3
4
4.45
V
V
CC
3.85
l
l
V
V
V
V
DRV Undervoltage Lockout
Rising Threshold
Falling Threshold
4.2
3.9
4.35
V
V
DRVUVLO
DUVLO
OVLO
CC
3.75
l
l
V
V
– V
Differential Undervoltage Lockout
Rising Threshold
Falling Threshold
145
55
185
90
225
125
mV
mV
IN
IN
CAP
l
l
Overvoltage Lockout
Rising Threshold
Falling Threshold
37.7
36.3
38.6
37.2
39.5
38.1
V
V
Charge Pump Output Voltage
Relative to V , 0V ≤ V ≤ 20V
CAP
5
V
VCAPP5
CAP
Input Current Sense Amplifier
V
Regulated Input Current Sense Voltage
(VOUTSP – VOUTSN)
31.36
31.04
32.00
32.00
32.64
32.96
mV
mV
SNSI
l
l
Charge Current Sense Amplifier
V
Regulated Charge Current Sense Voltage
(ICAP – VCAP)
V
CAP
= 10V
31.36
31.04
32.00
32.00
32.64
32.96
mV
mV
SNSC
V
V
V
Common Mode Range (ICAP, VCAP)
Peak Inductor Current Sense Voltage
Reverse Inductor Current Sense Voltage
ICAP Pin Current
0
20
65
10
V
mV
mV
CMC
PEAK
REV
l
l
51
58
7
Step-Down Mode
3.867
I
Step-Down Mode, V
= 32mV
30
135
µA
µA
ICAP
SNSC
Step-Up Mode, V
= 32mV
SNSC
Error Amplifier
g
g
g
g
V
Voltage Loop Transconductance
CAP
1
mmho
μmho
μmho
μmho
MV
MC
MI
Charge Current Loop Transconductance
Input Current Loop Transconductance
64
64
V
Voltage Loop Transconductance
OUT
400
MO
Oscillator
f
Switching Frequency
R = 107k
T
495
490
500
500
505
510
kHz
kHz
SW
l
Maximum Programmable Frequency
Minimum Programmable Frequency
R = 53.6k
1
MHz
kHz
T
R = 267k
T
200
3350fc
4
For more information www.linear.com/LTC3350
LTC3350
elecTrical characTerisTics The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = VOUT = 12V, VDRVCC = VINTVCC unless otherwise
noted.
SYMBOL
DC
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Maximum Duty Cycle
Step-Down Mode
Step-Up Mode
97
87
98
93
99.5
%
%
MAX
Gate Drivers
R
R
R
R
TGATE Pull-Up On-Resistance
TGATE Pull-Down On-Resistance
BGATE Pull-Up On-Resistance
BGATE Pull-Down On-Resistance
TGATE 10% to 90% Rise Time
TGATE 10% to 90% Fall Time
BGATE 10% to 90% Rise Time
BGATE 10% to 90% Fall Time
Non-Overlap Time
2
0.6
2
Ω
Ω
UP-TG
DOWN-TG
UP-BG
DOWN-BG
r-TG
Ω
0.6
18
8
Ω
t
t
t
t
t
t
C
LOAD
C
LOAD
C
LOAD
C
LOAD
= 3.3nF
= 3.3nF
= 3.3nF
= 3.3nF
25
15
25
15
ns
ns
ns
ns
ns
ns
f-TG
18
8
r-BG
f-BG
50
85
NO
ON(MIN)
INTV Linear Regulator
CC
V
Internal V Voltage
5.2V ≤ V ≤ 35V
5
V
INTVCC
CC
IN
Load Regulation
I
= 50mA
–1.5
–2.5
%
∆V
INTVCC
INTVCC
PowerPath/Ideal Diodes
V
V
V
Forward Turn-On Voltage
Forward Regulation
Reverse Turn Off
65
30
mV
mV
mV
µs
FTO
FR
–30
560
1.5
RTO
t
t
t
t
INFET Rise Time
INFET – V > 3V, C
= 3.3nF
= 3.3nF
IF(ON)
IF(OFF)
OF(ON)
OF(OFF)
IN
INFET
INFET Fall Time
INFET – V < 1V, C
µs
IN
INFET
OUTFET Rise Time
OUTFET Fall Time
OUTFET – V
OUTFET – V
> 3V, C
< 1V, C
= 3.3nF
0.13
0.26
µs
CAP
CAP
OUTFET
OUTFET
= 3.3nF
µs
Power-Fail Comparator
l
l
l
V
V
PFI Input Threshold (Falling Edge)
PFI Hysteresis
1.147
–50
1.17
30
1.193
50
V
mV
nA
mV
μA
ns
PFI(TH)
PFI(HYS)
I
PFI
PFI Input Leakage Current
PFO Output Low Voltage
PFO High-Z Leakage Current
PFI Falling to PFO Low Delay
PFI Rising to PFO High Delay
V
= 0.5V
= 5mA
= 5V
PFI
V
I
200
PFO
PFO
SINK
I
V
PFO
1
85
0.4
μs
CAPGD
l
V
V
V
CAPGD Rising Threshold as % of Regulated V
Feedback Voltage
V
V
= Full Scale (1111b)
= Full Scale (1111b)
90
92
94
1
%
%
CAPFB(TH)
CAP
capfb_dac
CAPGD Hysteresis at CAPFB as a % of Regulated
Feedback Voltage
1.25
200
CAPFB(HYS)
capfb_dac
V
CAP
CAPGD Output Low Voltage
I
= 5mA
mV
μA
CAPGD
CAPGD
SINK
l
I
CAPGD High-Z Leakage Current
V
= 5V
CAPGD
3350fc
5
For more information www.linear.com/LTC3350
LTC3350
elecTrical characTerisTics The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = VOUT = 12V, VDRVCC = VINTVCC unless otherwise
noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Analog-to-Digital Converter
V
V
Measurement Resolution
16
Bits
RES
General Purpose Input Voltage Range
Unbuffered
Buffered
0
0
5
3.5
V
V
GPI
I
General Purpose Input Pin Leakage Current
GPI Pin Resistance
Buffered Input
Buffer Disabled
1
μA
GPI
R
2.5
MΩ
GPI
Measurement System Error
Measurement Error (Note 5)
V
ERR
V
IN
V
IN
= 0V
= 30V
100
1.5
mV
%
V
V
= 5V
= 30V
100
1.5
mV
%
OUTSP
OUTSP
V
CAP
V
CAP
= 0V
= 10V
100
1.5
mV
%
V
V
= 0V, Unbuffered
= 3.5V, Unbuffered
2
1
mV
%
GPI
GPI
V
CAP1
V
CAP1
= 0V
= 2V
2
1
mV
%
V
CAP2
V
CAP2
= 0V
= 2V
2
1
mV
%
V
CAP3
V
CAP3
= 0V
= 2V
2
1
mV
%
V
CAP4
V
CAP4
= 0V
= 2V
2
1
mV
%
V
V
= 0mV
= 32mV
200
2
µV
%
SNSI
SNSI
V
SNSC
V
SNSC
= 0mV
= 32mV
200
2
µV
%
CAP1 to CAP4
R
Shunt Resistance
Maximum Capacitor Voltage with Shunts Enabled 2 or More Capacitors in Stack
Programming Pins
ITST Voltage
I C/SMBus – SDA, SCL, SMBALERT
0.5
Ω
V
SHNT
DV
3.6
CAPMAX
V
ITST
R
TST
= 121Ω
1.185
1.197
1.209
V
2
I
I
Input Leakage Low
–1
–1
1
1
µA
µA
V
IL,SDA,SCL
IH,SDA,SCL
Input Leakage High
V
V
Input High Threshold
1.5
IH
Input Low Threshold
0.8
V
IL
f
t
t
t
t
t
SCL Clock Frequency
400
kHz
µs
µs
µs
µs
µs
SCL
Low Period of SCL Clock
1.3
0.6
1.3
0.6
0.6
LOW
HIGH
BUF
High Period of SCL Clock
Bus Free Time Between Start and Stop Conditions
Hold Time, After (Repeated) Start Condition
Setup Time After a Repeated Start Condition
HD,STA
SU,STA
3350fc
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For more information www.linear.com/LTC3350
LTC3350
elecTrical characTerisTics The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = VOUT = 12V, VDRVCC = VINTVCC unless otherwise
noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
0.6
0
TYP
MAX
UNITS
µs
t
t
t
t
t
Stop Condition Set-Up Time
Output Data Hold Time
SU,STO
HD,DATO
HD,DATI
SU,DAT
SP
900
ns
Input Data Hold Time
0
ns
Data Set-Up Time
100
ns
Input Spike Suppression Pulse Width
SMBALERT Output Low Voltage
SMBALERT High-Z Leakage Current
50
1
ns
V
I
= 1mA
200
mV
μA
SMBALERT
SMBALERT
SINK
l
I
V
= 5V
SMBALERT
Note 3: The LTC3350 includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 125˚C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC3350 is tested under pulsed load conditions such that
Note 4: Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency. See the Applications Information
section.
T ≈ T . The LTC3350E is guaranteed to meet specifications from
J
A
0°C to 125°C junction temperature. Specifications over the –40°C to
125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LTC3350I is guaranteed over the –40°C to 125°C operating junction
temperature range. Note that the maximum ambient temperature
consistent with these specifications is determined by specific operating
conditions in conjunction with board layout, the rated package thermal
impedance and other environmental factors. The junction temperature
Note 5: Measurement error is the magnitude of the difference between the
actual measured value and the ideal value. V
VOUTSP and VOUTSN, representing input current. V
is the voltage between
SNSI
is the voltage
SNSC
between ICAP and VCAP, representing charge current. Error for V
and
SNSI
V
is expressed in μV, a conversion to an equivalent current may be
SNSC
made by dividing by the sense resistors, R
and R , respectively.
SNSC
SNSI
(T , in °C) is calculated from the ambient temperature (T , in °C) and
J
A
power dissipation (P , in Watts) according to the formula:
D
T = T + (P • θ )
JA
J
A
D
where θ = 34°C/W for the UHF package.
JA
Typical perForMance characTerisTics
TA = 25°C, Application Circuit 4 unless otherwise noted.
Supercapacitor Backup Operation HV Electrolytic Backup Operation
Shunt Operation Using VCAP2
5
4
3
2
V
= 2.7V
P
= 25W
P
= 25W
SHUNT
BACKUP
BACKUP
V
OUT
V
CAP
2V/DIV
5V/DIV
V
CAP
I
2V/DIV
CHARGE
V
OUT
5V/DIV
V
IN
V
2V/DIV
IN
5V/DIV
0V
1
0
0V
I
CAP2
3350 G01
3350 G02
400ms/DIV
BACK PAGE APPLICATION CIRCUIT
20ms/DIV
APPLICATION CIRCUIT 6
–1
2.68
2.70 2.71
3350 G03
2.64 2.65 2.66 2.67
2.69
V
(V)
CAP2
3350fc
7
For more information www.linear.com/LTC3350
LTC3350
Typical perForMance characTerisTics
TA = 25°C, Application Circuit 4 unless otherwise noted.
IIN and ICHARGE vs VIN
ICHARGE vs VCAP
ICHARGE vs VCAP
4.1
3.5
2.9
2.3
1.7
5.00
3.75
2.50
1.25
0
5.00
3.75
2.50
1.25
0
I
= 1A
= 6V
OUT
CAP
V
125°C
25°C
–40°C
I
CHARGE
I
I
= 2A
I
I
= 2A
IN(MAX)
OUT
IN(MAX)
OUT
= 1A
= 0A
V
= 12V
= 24V
= 35V
V
= 12V
= 24V
= 35V
IN
IN
IN
I
IN
IN
IN
IN
V
V
V
V
21
26
(V)
31
4
11
36
0
6
8
16
2
4
6
0
8
2
V
V
CAP
(V)
V
(V)
IN
CAP
3350 G04
3350 G06
3350 G05
IIN and ICHARGE vs IOUT
Charger Efficiency vs VCAP
VCAP vs vcapfb_dac
5.00
3.75
2.50
1.25
0
8.00
6.75
5.50
4.25
3.00
100
75
50
25
0
I
= 2A
I
= 2A
CHARGE
IN(MAX)
V
= 12V
= 24V
= 35V
IN
IN
IN
V
V
I
CHARGE
I
IN
I
I
= 2A
IN(MAX)
OUT
= 0A
V
V
V
= 12V
IN
IN
IN
= 24V
= 35V
1.50
(A)
2.25
0
3.00
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
0.75
3.6
(V)
0
5.4
7.2
1.8
I
vcapfb_dac (CODE)
V
OUT
CAP
3350 G07
3350 G09
3350 G08
VCAP vs Temperature
Efficiency in Boost Mode
Load Regulation in Boost Mode
7.210
7.205
7.200
7.195
7.190
7.185
100
75
5.000
4.994
4.988
50
V
V
V
= 2V
= 3V
= 4V
V
CAP
V
CAP
V
CAP
= 2V
= 3V
= 4V
25
0
CAP
CAP
CAP
4.981
4.975
capfb_dac = 15
I
= 2A
APPLICATION CIRCUIT 5
APPLICATION CIRCUIT 5
CHARGE
–3
–2
–1
0
1
–3
–2
–1
0
1
28
TEMPERATURE (°C)
62
96
–40
130
–6
10
10
10
10
10
10
10
10
10
10
I
(A)
I
(A)
OUT
OUT
3350 G11
3350 G12
3350 G10
3350fc
8
For more information www.linear.com/LTC3350
LTC3350
Typical perForMance characTerisTics
TA = 25°C, Application Circuit 4 unless otherwise noted.
DRVCC Current vs Boost Inductor
Current
IQ vs VIN, Pulse Skipping GPI Code vs Temperature
4.90
4.75
4.60
4.45
4.30
5480
5475
5470
5465
5460
5455
10.0
7.5
5.0
2.5
0
V
= 1V
GPI
V
CAP
= 4V
125°C
25°C
–40°C
125°C
25°C
–40°C
APPLICATION CIRCUIT 5
25
30
28
62
96
3
4.5
10
35
–40
130
0
6
15
20
–6
1.5
V
(V)
TEMPERATURE (°C)
I
L
(A)
IN
3350 G13
3350 G14
3350 G15
INTVCC vs Charge Current
INTVCC vs Temperature
5.000
4.938
4.875
4.813
4.750
5.000
V
IN
= 12V
4.938
4.875
4.813
4.750
125°C
25°C
–40°C
2
3
0
4
1
28
62
96
–40
130
–6
I
(A)
TEMPERATURE (°C)
CHARGE
3350 G16
3350 G17
3350fc
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For more information www.linear.com/LTC3350
LTC3350
pin FuncTions
SCL (Pin 1): Clock Pin for the I C/SMBus Serial Port.
2
RT (Pin 9): Timing Resistor. The switching frequency of
the synchronous controller is set by placing a resistor, R ,
2
T
SDA (Pin 2): Bidirectional Data Pin for the I C/SMBus
Serial Port.
from this pin to SGND. This resistor is always required.
If not present the synchronous controller will not start.
SMBALERT (Pin 3): Interrupt Output. This open-drain
output is pulled low when an alarm threshold is exceeded,
andwillremainlowuntiltheacknowledgementofthepart’s
response to an SMBus ARA.
GPI (Pin 10): General Purpose Input. The voltage on this
pin is digitized directly by the ADC. For high impedance
inputs an internal buffer can be selected and used to drive
the ADC. The GPI pin can be connected to a negative
temperature coefficient (NTC) thermistor to monitor the
temperature of the supercapacitor stack. A low drift bias
CAPGD (Pin 4): Capacitor Power Good. This open-drain
output is pulled low when CAPFB is below 92% of its
regulation point.
resistor is required from INTV to GPI and a thermistor
CC
is required from GPI to ground. Connect GPI to SGND if
not used. The digitized voltage on this pin can be read in
the meas_gpi register.
VC (PIN 5): Control Voltage Pin. This is the compensation
node for the charge current, input current, supercapacitor
stack voltage and output voltage control loops. An RC
network is connected between VC and SGND. Nominal
voltage range for this pin is 1V to 3V.
ITST(Pin 11): Programming Pin forCapacitance TestCur-
rent. This current is used to partially discharge the capaci-
tor stack at a precise rate for capacitance measurement.
This pin servos to 1.2V during a capacitor measurement.
CAPFB (Pin 6): Capacitor Stack Feedback Pin. This pin
closes the feedback loop for constant voltage regulation.
An external resistor divider between VCAP and SGND with
the center tap connected to CAPFB programs the final
supercapacitor stack voltage. This pin is nominally equal
A resistor, R , from this pin to SGND programs the test
TST
current. R must be at least 121Ω.
TST
CAPRTN (Pin 12): Capacitor Stack Shunt Return Pin. This
pin is connected to the grounded bottom plate of the first
super capacitor in the stack through a shunt resistor.
to the output of the V
DAC when the synchronous
CAP
controller is in constant voltage mode while charging.
OUTFB (Pin 7): Step-Up Mode Feedback Pin. This pin
CAP1 (Pin 13): First Supercapacitor Pin. The top plate of
the first supercapacitor and the bottom plate of the second
supercapacitor are connected to this pin through a shunt
resistor.CAP1andCAPRTNareusedtomeasurethevoltage
acrossthefirstsupercapacitorandtoshuntcurrentaround
thecapacitortoprovidebalancingandpreventovervoltage.
The voltage between this pin and CAPRTN is digitized and
can be read in the meas_vcap1 register.
closes the feedback loop for voltage regulation of V
OUT
duringinputpowerfailureusingthesynchronouscontroller
in step-up mode. An external resistor divider between
V
OUT
and SGND with the center tap connected to OUTFB
programs the minimum backup supply rail voltage when
inputpowerisunavailable.Thispinisnominally1.2Vwhen
in backup and the synchronous controller is not in current
limit. To disable step-up mode tie OUTFB to INTV .
CC
CAP2 (Pin 14): Second Supercapacitor Pin. The top plate
of the second supercapacitor and the bottom plate of the
third supercapacitor are connected to this pin through a
shunt resistor. CAP2 and CAP1 are used to measure the
voltage across the second supercapacitor and to shunt
SGND (Pin 8): Signal Ground. All small-signal and com-
pensation components should be connected to this pin,
which in turn connects to PGND at one point. This pin
shouldalsoKelvintothebottomplateofthecapacitorstack.
3350fc
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For more information www.linear.com/LTC3350
LTC3350
pin FuncTions
current around the capacitor to provide balancing and
prevent overvoltage. If not used this pin should be shorted
toCAP1.ThevoltagebetweenthispinandCAP1isdigitized
and can be read in the meas_vcap2 register.
VCAP (Pin 21): Supercapacitor Stack Voltage and Charge
Current Sense Amplifier Negative Input. Connect this pin
to the top of the supercapacitor stack. The voltage at this
pin is digitized and can be read in the meas_vcap register.
CAP3 (Pin 15): Third Supercapacitor Pin. The top plate of
the third supercapacitor and the bottom plate of the fourth
supercapacitor are connected to this pin through a shunt
resistor. CAP3 and CAP2 are used to measure the voltage
acrossthethirdsupercapacitorandtoshuntcurrentaround
thecapacitortoprovidebalancingandpreventovervoltage.
IfnotusedthispinshouldbeshortedtoCAP2. Thevoltage
between this pin and CAP2 is digitized and can be read in
the meas_vcap3 register.
ICAP (Pin 22): Charge Current Sense Amplifier Positive
Input.TheICAPandVCAPpinsmeasurethevoltageacross
the sense resistor, R
, to provide instantaneous cur-
SNSC
rent signals for the control loops and ESR measurement
system. The maximum charge current is 32mV/R
.
SNSC
VCC2P5 (Pin 23): Internal 2.5V Regulator Output. This
regulator provides power to the internal logic circuitry.
Decouple this pin to ground with a minimum 1μF low ESR
tantalum or ceramic capacitor.
CAP4(Pin16):FourthSupercapacitorPin. Thetopplateof
the fourth supercapacitor is connected to this pin through
a shunt resistor. CAP4 and CAP3 are used to measure
the voltage on the capacitor and to shunt current around
the supercapacitor to provide balancing and prevent
overvoltage.IfnotusedthispinshouldbeshortedtoCAP3.
The voltage between this pin and CAP3 is digitized and
can be read in the meas_vcap4 register. The capacitance
test current set by the ITST pin is pulled from this pin.
SW (Pin 24): Switch Node Connection to the Inductor.
The negative terminal of the boot-strap capacitor, C , is
B
connected to this pin. The voltage on this pin is also used
as the source reference for the top side N-channel MOS-
FET gate drive. In step-down mode, the voltage swing on
this pin is from a diode (external) forward voltage below
groundtoV .Instep-upmodethevoltageswingisfrom
OUT
ground to a diode forward voltage above V
.
OUT
TGATE (Pin 25): Top Gate Driver Output. This pin is the
outputofafloatinggatedriverforthetopexternalN-channel
CFP (Pin 17): VCAPP5 Charge Pump Flying Capacitor
Positive Terminal. Place a 0.1μF between CFP and CFN.
MOSFET. The voltage swing at this pin is ground to V
OUT
CFN (Pin 18): VCAPP5 Charge Pump Flying Capacitor
Negative Terminal. Place a 0.1μF between CFP and CFN.
+ DRV .
CC
BST (Pin 26): TGATE Driver Supply Input. The positive
VCAPP5 (Pin 19): Charge Pump Output. The internal
terminal of the boot-strap capacitor, C , is connected to
B
charge pump drives this pin to VCAP + INTV which is
this pin. This pin swings from a diode voltage drop below
CC
used as the high side rail for the OUTFET gate drive and
charge current sense amplifier. Connect a 0.1μF capacitor
from VCAPP5 to VCAP.
DRV up to V
+ DRV .
OUT CC
CC
BGATE (Pin 27): Bottom Gate Driver Output. This pin
drives the bottom external N-channel MOSFET between
OUTFET (Pin 20): Output Ideal Diode Gate Drive Out-
PGND and DRV .
CC
put. This pin controls the gate of an external N-channel
DRV (Pin 28): Power Rail for Bottom Gate Driver. Con-
CC
MOSFET used as an ideal diode between V
and V
.
OUT
CAP
nect to INTV or to an external supply. Decouple this pin
CC
The gate drive receives power from the internal charge
pump output VCAPP5. The source of the N-channel
MOSFETshouldbeconnectedtoVCAPandthedrainshould
beconnectedtoVOUTSN.IftheoutputidealdiodeMOSFET
is not used, OUTFET should be left floating.
to ground with a minimum 2.2μF low ESR tantalum or
ceramic capacitor. Do not exceed 5.5V on this pin.
3350fc
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For more information www.linear.com/LTC3350
LTC3350
pin FuncTions
INTV (Pin29):Internal5VRegulatorOutput.Thecontrol
INFET (Pin 33): Input Ideal Diode Gate Drive Output. This
CC
circuits and gate drivers (when connected to DRV ) are
pin controls the gate of an external N-channel MOSFET
CC
powered from this supply. If not connected to DRV ,
used as an ideal diode between V and V . The gate
CC
IN OUT
decouple this pin to ground with a minimum 1μF low ESR
drive receives power from an internal charge pump. The
source of the N-channel MOSFET should be connected
tantalum or ceramic capacitor.
to V and the drain should be connected to VOUTSP. If
IN
VOUTSN (Pin 30): Input Current Limiting Amplifier Nega-
tive Input. A sense resistor, R
the input ideal diode MOSFET is not used, INFET should
, between VOUTSP and
SNSI
be left floating.
VOUTSN sets the input current limit. The maximum input
current is 32mV/R . An RC network across the sense
V (Pin 34): External DC Power Source Input. Decouple
SNSI
IN
resistor can be used to modify loop compensation. To
disable input current limit, connect this pin to VOUTSP.
this pin with at least 0.1μF to ground. The voltage at this
pin is digitized and can be read in the meas_vin register.
VOUTSP (Pin 31): Backup System Supply Voltage and
InputCurrentLimitingAmplifierPositiveInput.Thevoltage
acrosstheVOUTSPandVOUTSNpinsareusedtoregulate
input current. This pin also serves as the power supply
for the IC. The voltage at this pin is digitized and can be
read in the meas_vout register.
CAP_SLCT0, CAP_SLCT1 (Pins 35, 36): CAP_SLCT0 and
CAP_SLCT1 set the number of super-capacitors used.
Refer to Table 1 in the Applications Information section.
PFI (Pin 37): Power-Fail Comparator Input. When the
voltage at this pin drops below 1.17V, PFO is pulled low
and step-up mode is enabled.
VOUTM5 (Pin 32): V
– 5V Regulator. This pin is regu-
OUT
OUT
PFO (Pin 38): Power-Fail Status Output. This open-drain
output is pulled low when a power fault has occurred.
lated to 5V below V
or to ground if V
< 5V. This
OUT
rail provides power to the input current sense amplifier.
PGND(ExposedPadPin39):PowerGround.Theexposed
pad must be connected to a continuous ground plane on
thesecondlayeroftheprintedcircuitboardbyseveralvias
directlyundertheLTC3350forratedthermalperformance.
It must be tied to the SGND pin.
Decouple this pin with at least 1μF to V
.
OUT
3350fc
12
For more information www.linear.com/LTC3350
LTC3350
block DiagraM
34
33
INFET
31
VOUTSP
32
VOUTM5
30
VOUTSN
20
OUTFET
17
CFP
18
CFM
V
IN
VCAPP5
19
INTV
+
+
–
CC
–
CHARGE
PUMP
+
–5V LDO
–
30mV
+
30mV
–
V
+
–
–
x37.5
+
REF
–
+
VCAP
21
x37.5
I
IN
22
ICAP
V
Vcapfb_dac
REF
+
–
D/A
vcapfb_dac[3:0]
CAPFB
+ I
REF
BST
26
6
–
V
+
–
REF
OUTFB
VC
TGATE
25
I
CHG
7
5
SW
24
BIDIRECTIONAL
SWITCHING
DRV
CC
RT
CONTROLLER
28
27
9
OSC
BGATE
CAP4
INTV
CC
29
V
5V LDO
OUTSP
16
15
VCC2P5
CAPGD
23
4
2.5V LDO
V
REF
BANDGAP
INTV
CC
SHUNT
BALANCER
BALANCER
BALANCER
BALANCER
+
–
Vcapfb_dac
CAPFB
CONTROLLER
CAP3
CAP2
CAP1
INTV
CC
SHUNT
I
IN
CONTROLLER
ICHG
VCAP
OUT
+
–
V
REF
PFI
V
REF
14
13
37
38
V
V
IN
PFO
CAP4
CAP3
CAP2
CAP1
CAPRTN
DTEMP
A/D
SHUNT
CONTROLLER
LOGIC
CAP_SLCT0
CAP_SLCT1
SMBALERT
SDA
35
36
3
SHUNT
CONTROLLER
CAPRTN
ITST
12
11
+
–
V
REF
2
SCL
1
–
+
GPI
10
8
GPIBUF
SGND
PGND
39
3350 BD
3350fc
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For more information www.linear.com/LTC3350
LTC3350
TiMing DiagraM
Definition of Timing for F/S Mode Devices on the I2C Bus
SDA
t
t
SU(DAT)
t
t
BUF
r
LOW
HD(SDA)
t
f
t
f
t
SP
t
t
r
SCL
t
t
t
SU(STO)
HD(SDA)
SU(STA)
t
t
HIGH
HD(DAT)
S
Sr
P
S
3350 TD
S = START, Sr = REPEATED START, P = STOP
operaTion
Introduction
The LTC3350 monitors system voltages, currents, and
die temperature. A general purpose input (GPI) pin is
provided to measure an additional system parameter or
implement a thermistor measurement. In addition, the
LTC3350canmeasurethecapacitanceandresistanceofthe
supercapacitorstack.Thisprovidesindicationofthehealth
TheLTC3350isahighlyintegratedbackuppowercontroller
and system monitor. It features a bidirectional switching
controller, input and output ideal diodes, supercapacitor
shunts/balancers, a power-fail comparator, a 14-bit ADC
2
and I C/SMBus programmability with status reporting.
of the supercapacitors and, along with the V
voltage
CAP
If V is above an externally programmable PFI threshold
measurement, provides information on the total energy
stored and the maximum power that can be delivered.
IN
voltage,thesynchronouscontrolleroperatesinstep-down
mode and charges a stack of supercapacitors. A program-
mable input current limit ensures that the supercapacitors
willautomaticallybechargedatthehighestpossiblecharge
Bidirectional Switching Controller—Step-Down Mode
Thebidirectionalswitchingcontrollerisdesignedtocharge
a series stack of supercapacitors (Figure 1). Charging
proceeds at a constant current until the supercapacitors
reach their maximum charge voltage determined by the
current that the input can support. If V is below the PFI
IN
threshold, then the synchronous controller will run in
reverse as a step-up converter to deliver power from the
supercapacitor stack to V
.
OUT
CAPFBservovoltageandtheresistordividerbetweenV
CAP
The two ideal diode controllers drive external MOSFETs to
provide low loss power paths from V and V to V
and CAPFB. The maximum charge current is determined
.
by the value of the sense resistor, R , used in series
IN
CAP
OUT
SNSC
The ideal diodes work seamlessly with the bidirectional
with the inductor. The charge current loop servos the
voltageacrossthesenseresistorto32mV.Whencharging
begins, aninternalsoft-start ramp willincrease the charge
controller to provide power from the supercapacitors to
V
without backdriving V .
IN
OUT
current from zero to full current in 2ms. The V
voltage
CAP
The LTC3350 provides balancing and overvoltage protec-
tion to a series stack of one to four supercapacitors. The
internal capacitor voltage balancers eliminate the need
for external balance resistors. Overvoltage protection is
provided by shunt regulators that use an internal switch
and an external resistor across each supercapacitor.
and charge current can be read from the meas_vcap and
meas_ichrg registers, respectively.
3350fc
14
For more information www.linear.com/LTC3350
LTC3350
operaTion
V
OUT
V
IN
(TO SYSTEM)
R
SNSI
V
INFET
VOUTSP VOUTSN
IN
LTC3350
+ –
+
30mV
–
INPUT
CURRENT
CONTROLLER
V
+
–
REF
+
–
I
IN
TGATE
BGATE
BIDIRECTIONAL
SWITCHING
CONTROLLER
STEP-DOWN MODE
CHARGE
CURRENT
CONTROLLER
I
+
REF
ICAP
+
–
–
37.5
R
SNSC
I
CHG
VCAP
CAPACITOR
VOLTAGE
CONTROLLER
+
V
REF
D/A
vcapfb_dac[3:0]
CAPFB
+
–
+
+
+
VC
3350 F01
Figure 1. Power Path Block Diagram—Power Available from VIN
Bidirectional Switching Controller—Step-Up Mode
TheLTC3350providesconstantpowercharging(forafixed
IN
V ) by limiting the input current drawn by the switching
The bidirectional switching controller acts as a step-up
converter to provide power from the supercapacitors to
controller in step-down mode. The input current limit will
reduce charge current to limit the voltage across the input
V
when input power is unavailable (Figure 2). The PFI
OUT
sense resistor, R , to 32mV. If the combined system
SNSI
comparator enables step-up mode. V
regulation is set
OUT
loadplussupercapacitorchargecurrentislargeenoughto
cause the switching controller to reach the programmed
input current limit, the input current limit loop will reduce
the charge current by precisely the amount necessary
to enable the external load to be satisfied. Even if the
charge current is programmed to exceed the allowable
input current, the input current will not be violated; the
supercapacitor charger will reduce its current as needed.
Note that the part’s quiescent and gate drive currents are
not included in the input current measurement.The input
current can be read from the meas_iin register.
by a resistor divider between V
and OUTFB. To disable
OUT
step-up mode tie OUTFB to INTV .
CC
Step-up mode can be used in conjunction with the output
ideal diode. The V
regulation voltage can be set below
OUT
the capacitor stack voltage. Upon removal of input power,
power to V will be provided from the supercapacitor
OUT
stack via the output ideal diode. V
and V
will fall as
CAP
OUT
the load current discharges the supercapacitor stack. The
output ideal diode will shut off when the voltage on OUTFB
falls below 1.3V and V
will fall a PN diode (~700mV)
OUT
below V . If OUTFB falls below 1.2V when the output
CAP
3350fc
15
For more information www.linear.com/LTC3350
LTC3350
operaTion
V
< V
OUT
CAP
V
OUT
(TO SYSTEM)
LTC3350
OUTFB
VOUTSN
OUTPUT
VOLTAGE
CONTROLLER
V
> V
OUT
CAP
–
+
V
REF
–
+
OUTFET
+
30mV
–
TGATE
BGATE
BIDIRECTIONAL
SWITCHING
R
SNSC
CONTROLLER
+
+
+
+
STEP-UP MODE
ICAP
VCAP
3350 F02
VC
Figure 2. Power Path Block Diagram—Power Backup
ideal diode shuts off, the synchronous controller will turn
on immediately. If OUTFB is above 1.2V when the output
ideal diode shuts off, the load current will flow through the
bodydiodeoftheoutputidealdiodeN-channelMOSFETfor
aperiodoftimeuntilOUTFBfallsto1.2V.Thesynchronous
controller will regulate OUTFB to 1.2V when it turns on,
30mV (V ) below the voltage at V or V . Within
FWD IN CAP
the amplifier’s linear range, the small-signal resistance
of the ideal diode will be quite low, keeping the forward
drop near 30mV. At higher current levels, the MOSFETs
will be in full conduction.
The input ideal diode prevents the supercapacitors from
holding up V
ground.
while the supercapacitors discharge to
OUT
back driving V during backup mode. A Fast-Off com-
IN
parator shuts off the N-channel MOSFET if V falls 30mV
IN
The synchronous controller in step-up mode will run
nonsynchronously when V is less than 100mV below
belowV .ThePFIcomparatoralsoshutsofftheMOSFET
OUT
during power failure.
CAP
V
. It will run synchronously when V
falls 200mV
OUT
below V
CAP
Theoutputidealdiodeprovidesapathforthesupercapaci-
.
OUT
torstopowerV
whenV isunavailable. Inadditiontoa
OUT
IN
Fast-Offcomparator,theoutputidealdiodealsohasaFast-
Ideal Diodes
On comparator that turns on the external MOSFET when
The LTC3350 has two ideal diode controllers that drive
external N-channel MOSFETs. The ideal diodes consist of
a precision amplifier that drives the gates of N-channel
V
drops 65mV below V . The output ideal diode will
CAP
OUT
shut off when OUTFB is just above regulation allowing the
synchronous controller to power V in step-up mode.
OUT
MOSFETs whenever the voltage at V
is approximately
OUT
3350fc
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For more information www.linear.com/LTC3350
LTC3350
operaTion
Gate Drive Supply (DRV )
defaults to full scale (1.2V) and is programmed via the
vcapfb_dac register.
CC
The bottom gate driver is powered from the DRV pin. It
is normally connected to the INTV pin. An external LDO
can also be used to power the gate drivers to minimize
power dissipation inside the IC. See the Applications
Information section for details.
CC
Supercapacitors lose capacitance as they age. By initially
CC
setting the V
DAC to a low setting, the final charge
CAP
voltage on the supercapacitors can be increased as they
age to maintain a constant level of stored backup energy
throughout the lifetime of the supercapacitors.
Undervoltage Lockout (UVLO)
Power-Fail (PF) Comparator
Internal undervoltage lockout circuits monitor both the
INTV and DRV pins. The switching controller is kept
The LTC3350 contains a fast power-fail (PF) comparator
which switches the part from charging to backup mode in
CC
CC
off until INTV rises above 4.3V and DRV rises above
CC
CC
4.2V. Hysteresis on the UVLOs turn off the controller if
either INTV falls below 4V or DRV falls below 3.9V.
the event the input voltage, V , falls below an externally
IN
programmedthresholdvoltage.Inbackupmode,theinput
idealdiodeshutsoffandthesupercapacitorspowertheload
either directly through the output ideal diode or through
the synchronous controller in step-up mode.
CC
CC
ChargingisnotenableduntilVOUTSNis185mVabovethe
supercapacitor voltage and V is above the PFI threshold.
IN
ChargingisdisabledwhenVOUTSNfallstowithin90mVof
thesupercapacitorvoltageorV isbelowthePFIthreshold.
The PF comparator threshold voltage is programmed by
an external resistor divider via the PFI pin. The output of
the PF comparator also drives the gate of an open-drain
NMOStransistortoreportthestatusviathePFOpin.When
input power is available the PFO pin is high impedance.
IN
RT Oscillator and Switching Frequency
The RT pin is used to program the switching frequency.
A resistor, R , from this pin to ground sets the switching
T
When V falls below the PF comparator threshold, PFO
IN
frequency according to:
is pulled down to ground.
53.5
fSW MHz =
(
)
The output of the PF comparator may also be read from
the chrg_pfo bit in the chrg_status register.
R kΩ
(
)
T
R alsosetsthescalefactorforthecapacitormeasurement
T
Charge Status Indication
value reported in the meas_cap register, described in the
Capacitance and ESR Measurement section of this data
sheet.
The LTC3350 includes a comparator to report the status
of the supercapacitors via an open-drain NMOS transistor
on the CAPGD pin. This pin is pulled to ground until the
Input Overvoltage Protection
CAPFB pin voltage rises to within 8% of the V
DAC
CAP
setting. Once the CAPFB pin is above this threshold, the
CAPGD pin goes high impedance.
The LTC3350 has overvoltage protection on its input. If
IN
V exceeds 38.6V, the switching controller will hold the
switchingMOSFETsoff.Thecontrollerwillresumeswitch-
The output of this comparator may also be read from the
chrg_cappg bit in the chrg_status register.
ing if V falls below 37.2V. The input ideal diode MOSFET
IN
remains on during input overvoltage.
Capacitor Voltage Balancer
V
CAP
DAC
The LTC3350 has an integrated active stack balancer. This
balancer slowly balances all of the capacitor voltages to
within about 10mV of each other. This maximizes the life
of the supercapacitors by keeping the voltage on each as
low as possible to achieve the needed total stack voltage.
3350fc
The feedback reference for the CAPFB servo point can
be programmed using an internal 4-bit digital-to-analog
converter(DAC).Thereferencevoltagecanbeprogrammed
from 0.6375V to 1.2V in 37.5mV increments. The DAC
17
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LTC3350
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When the difference between any two capacitor volt-
ages exceeds about 10mV, the capacitor with the largest
voltage is discharged with a resistive balancer at about
10mA until all capacitor voltages are within 10mV. The
balancers are disabled in backup mode.
happens (see Limit Check and Alarms and Monitor Status
Register). The LTC3350 will deassert the SMBALERT
pin only after responding to an SMBus alert response
address (ARA), an SMBus protocol used to respond to a
SMBALERT. ThehostwillreadfromtheARA(0b0001100)
and each part asserting SMBALERT will begin to respond
with its address. The responding parts arbitrate in such a
way that only the part with the lowest address responds.
Only when a part has responded with its address does it
release the SMBALERT signal. If multiple parts are as-
serting the SMBALERT signal then multiple reads from
the ARA are needed. For more information refer to the
SMBus specification.
Capacitor Shunt Regulators
In addition to balancing, there is a need to protect each
capacitorfromovervoltageduringcharging.Thecapacitors
in the stack will not have exactly the same capacitance due
to manufacturing tolerances or uneven aging. This will
cause the capacitor voltages to increase at different rates
with the same charge current. If this mismatch is severe
enough or if the capacitors are being charged to near their
maximum voltage, it becomes necessary to limit the volt-
age increase on some capacitors while still charging the
other capacitors. Up to 500mA of current may be shunted
around a capacitor whose voltage is approaching the pro-
grammable shunt voltage. This shunt current reduces the
chargerateofthatcapacitorrelativetotheothercapacitors.
If a capacitor continues to approach its shunt voltage, the
charge current is reduced. This protects the capacitor
from overvoltage while still charging the other capacitors,
although at a reduced rate of charge. The shunt voltage is
programmable in the vshunt register. Shunt voltages up
to 3.6V may be programmed in 183.5µV increments. The
shunt regulators can be disabled by programming vshunt
to zero (0x0000). The default value is 0x3999, resulting
in a shunt voltage of 2.7V.
Details on the registers accessible through this interface
areavailableintheRegisterMapandRegisterDescriptions
sections of this data sheet.
Analog-to-Digital Converter
TheLTC3350hasanintegrated14-bitsigma-deltaanalog-
to-digital converter (ADC). This converter is automatically
multiplexed between all of the measured channels and
2
its results are stored in registers accessible via the I C/
SMBus port. There are 11 channels measured by the ADC,
each of which takes approximately 1.6ms to measure. In
addition to providing status information about the system
voltages and currents, some of these measurements are
used by the LTC3350 to balance, protect, and measure
the capacitors in the stack.
The result of the analog-to-digital conversion is stored in
a 16-bit register as a signed, two’s complement number.
The lower two bits of this number are sub-bits. These bits
are ADC outputs which are too noisy to be reliably used
on any single conversion, however, they may be included
if multiple samples are averaged.
2
I C/SMBus and SMBALERT
2
TheLTC3350containsanI C/SMBusport.Thisportallows
communication with the LTC3350 for configuration and
readingbacktelemetrydata.TheportsupportstwoSMBus
formats, read word and write word. Refer to the SMBus
specification for details of these formats. The registers
accessible via this port are organized on an 8-bit address
busandeachregisteris16bitswide.The“commandcode”
(or sub-address) of the SMBus read/write word formats is
the 8-bit address of each of these registers. The address
of the LTC3350 is 0b0001001.
The measurements from the ADC are directly stored in the
meas_vcap1, meas_vcap2, meas_vcap3, meas_vcap4,
meas_gpi, meas_vin, meas_vcap, meas_vout, meas_iin,
meas_ichg and meas_dtemp registers.
Capacitance and ESR Measurement
The LTC3350 has the ability to measure the capacitance
andequivalentseriesresistance(ESR)ofitssupercapacitor
The SMBALERT pin is asserted (pulled low) whenever an
enabled limit is exceeded or when an enabled status event
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stack.Thismeasurementisperformedwithminimalimpact
to the system, and can be done while the supercapacitor
backup system is online. This measurement discharges
the capacitor stack by a small amount (200mV). If input
power fails during this test, the part will go into backup
mode and the test will terminate.
The capacitance and capacitor ESR measurements do not
automatically run as the other measurements do. They
must be initiated by setting the ctl_strt_capesr bit in the
ctl_reg register. This bit will automatically clear once the
measurement begins. If the cap_esr_per register is set to
a non-zero value, the measurement will be repeated after
the time programmed in the cap_esr_per register. Each
LSB in the cap_esr_per register represents 10 seconds.
The capacitance test is performed only once the
supercapacitors have finished charging. The test
temporarily disables the charger, then discharges the
supercapacitors by 200mV with a precision current.
The discharge time is measured and used to calculate
the capacitance with the result of this measurement
stored in the meas_cap register. The number reported is
proportional to the capacitance of the entire stack. Two
different scales can be set using the ctl_cap_scale bit in
the ctl_reg register. If ctl_cap_scale is set to 0 (for large
value capacitor stacks), use the following equation to
convert the meas_cap value to Farads:
The capacitance and ESR measurements may fail to
complete for several reasons, in which case the respective
mon_cap_failed or mon_esr_failed bit will be set. The ca-
pacitancetestmayfailduetoapowerfailureorifthe200mV
dischargetripstheCAPGDcomparator.TheESRtestwillalso
failifthecapacitancetestfails.TheESRtestusesthecharger
to supply a current and then measures the supercapacitor
stack voltage with and without that current. If the ESR is
greater than 1024 times R , the ESR measurement will
SNSC
fail.TheESRmeasurementisadaptive;itusesknowledgeof
the ESR from previous measurements to program the test
current. The capacitance and ESR tests should initially be
run several times when first powering up to get the most
accuracy out of the system. It is possible for the first few
measurementstogivelowqualityresultsorfailtocomplete
and after running several times will complete with a quality
result. The leakage on supercapacitors is initially very high
after being charged. Many supercapacitor manufacturers
specifytheleakagecurrentafterbeingchargedfor72hours.
Itisexpectedthatcapacitormeasurementsconductedprior
to this time will read low.
RT
RTST
CSTACK
=
•336µF •meas_cap
Ifctl_cap_scaleissetto1(forsmallvaluecapactorstacks),
use the following equation to convert the meas_cap value
to Farads:
RT
RTST
CSTACK
=
•3.36µF •meas_cap
In the two previous equations R is the resistor on the RT
T
pin and R is the resistor on the ITST pin.
TST
Monitor Status Register
The ESR test is performed immediately following the
capacitance test. The switching controller is switched on
and off several times. The changes in charge current and
stack voltage are measured. These measurements are
used to calculate the ESR relative to the charge current
sense resistor. The result of this measurement is stored
in the meas_esr register. The value reported in meas_esr
can be converted to ohms using the following equation:
The LTC3350 has a monitor status register (mon_status)
which contains status bits indicating the state of the ca-
pacitance and ESR monitoring system. These bits are set
and cleared by the capacitor monitor upon certain events
during a capacitor and ESR measurement, as described
in the Capacitance and ESR Measurement section.
Thereisacorrespondingmsk_mon_statusregister.Writing
a one to any of these bits will cause the SMBALERT pin to
pull low when the corresponding bit in the msk_mon_sta-
tus register has a rising edge. This allows reduced polling
of the LTC3350 when waiting for a capacitance or ESR
measurement to complete.
RSNSC
64
RESR
=
•meas_esr
where R
is the charge current sense resistor in series
SNSC
with the inductor.
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Details of the mon_status and msk_mon_status registers
can be found in the Register Descriptions section of this
data sheet.
Alloftheindividualmeasuredvoltageshaveacorresponding
undervoltage (uv) and overvoltage (ov) alarm level. All of
theindividualcapacitorvoltagesarecomparedtothesame
alarmlevels,setinthecap_ov_lvlandcap_uv_lvlregisters.
The input current measurement has an overcurrent (oc)
alarm programmed in the iin_oc_lvl register. The charge
current has an undercurrent alarm programmed in the
ichg_uc_lvl register.
Charge Status Register
TheLTC3350chargerstatusregister(chrg_status)contains
data about the state of the charger, switcher, shunts, and
balancers. Details of this register may be found in the
Register Description sections of this data sheet.
Die Temperature Sensor
Limit Checking and Alarms
The LTC3350 has an integrated die temperature sensor
monitored by the ADC and digitized to the meas_dtemp
register. An alarm may be set on die temperature by
settingthedtemp_cold_lvland/ordtemp_hot_lvlregisters
and enabling their respective alarms in the msk_alarms
register. To convert the code in the meas_dtemp register
to degrees Celsius use the following:
The LTC3350 has a limit checking function that will check
each measured value against I C/SMBus programmable
limits. This feature is optional, and all the limits are dis-
abled by default. The limit checking is designed to simplify
system monitoring, eliminating the need to continuously
poll the LTC3350 for measurement data.
2
T
(°C) = 0.028 • meas_dtemp – 251.4
DIE
If a measured parameter goes outside of the programmed
levelofanenabledlimit,theassociatedbitinthealarm_reg
register is set high and the SMBALERT pin is pulled low.
General Purpose Input
2
Thegeneralpurposeinput(GPI)pincanbeusedtomeasure
an additional system parameter. The voltage on this pin is
directly digitized by the ADC. For high impedance inputs,
an internal buffer may be selected and used to drive the
ADC.Thisbufferisenabledbysettingthectl_gpi_buffer_en
bit in the ctl_reg register. With this buffer, the input range
is limited from 0V to 3.5V. If this buffer is not used, the
range is from 0V to 5V, however, the input stage of the
ADC will draw about 0.4µA per volt from this pin. The ADC
input is a switched capacitor amplifier running at about
1MHz, so this current draw will be at that frequency. The
pin current can be eliminated at the cost of reduced range
and increased offset by enabling the buffer.
ThisinformstheI C/SMBushostalimithasbeenexceeded.
The alarms register may then be read to determine exactly
which programmed limits have been exceeded.
AsingleADCissharedbetweenthe11channelswithabout
18ms between consecutive measurements of the same
channel. In a transient condition, it is possible for these
parameters to exceed their programmed levels in between
consecutiveADCmeasurementswithoutsettingthealarm.
Once the LTC3350 has responded to an SMBus ARA the
SMBALERT pin is released. The part will not pull the pin
low again until another limit is exceeded. To reset a limit
that has been exceeded, it must be cleared by writing a
one to the respective bit in the clr_alarms register.
Alarms are available for this pin voltage with levels
programmedusingthegpi_uv_lvlandgpi_ov_lvlregisters.
These alarms are enabled using the msk_gpi_uv and
msk_gpi_ov bits in the msk_alarms register.
A number of the LTC3350’s registers are used for limit
checking. Individual limits are enabled or disabled in the
msk_alarmsregisters.Onceanenabledalarm’smeasured
valueexceedstheprogrammedlevelforthatalarmthealarm
is set. That alarm may be cleared by writing a one to the
appropriate bit of the clr_alarms register or by writing a
zero to the appropriate bit to the msk_alarms register. All
alarms that have been set and have not yet been cleared
may be read in the alarm_reg register.
To monitor the temperature of the supercapacitor stack,
the GPI pin can be connected to a negative temperature
coefficient (NTC) thermistor. A low drift bias resistor is
required from INTV to GPI and a thermistor is required
CC
from GPI to ground. Connect GPI to SGND if not used.
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Digital Configuration
V . CAPRTN, CAP1, CAP2, CAP3 and CAP4 must be
SHUNT
connected to the supercapacitors through resistors which
serve as ballasts for the internal shunts. The shunt cur-
Although the LTC3350 has extensive digital features, only
a few are required for basic use. The shunt voltage should
be programmed via the vshunt register if a value other
than the default 2.7V is required. The capacitor voltage
feedback reference defaults to 1.2V; it may be changed
in the vcapfb_dac register.
rent is approximately V
divided by twice the shunt
SHUNT
resistance value. For a V
of 2.7V, 2.7Ω resistors
SHUNT
should be used for 500mA of shunt current. The shunts
have a duty cycle of up to 75%. The power dissipated in
a single shunt resistor is approximately:
All other digital features are optional and used for moni-
toring. The ADC automatically runs and stores conver-
sionstoregisters(e.g.,meas_vcap).CapacitanceandESR
measurements only run if requested, however, they may
bescheduledtorepeatifdesired(ctl_strt_capesrandcap_
esr_per). Each measured parameter has programmable
limits (e.g., vcap_uv_lvl and vcap_ov_lvl) which may
trigger an alarm and SMBALERT when enabled. These
alarms are disabled by default.
3VS2HUNT
16RSHUNT
PSHUNT
≈
andtheresistorsshouldbesizedaccordingly.Iftheshunts
are disabled, make R 100Ω.
SHUNT
Since the shunt current is less than what the switcher can
supply, the on-chip logic will automatically reduce the
chargingcurrenttoallowtheshunttoprotectthecapacitor.
This greatly reduces the charge rate once any one shunt is
Capacitor Configuration
activated. For this reason, V
should be programmed
SHUNT
The LTC3350 may be used with one to four supercapaci-
tors. If less than four capacitors are used, the capacitors
mustbepopulatedfromCAPRTNtoCAP4, andtheunused
CAP pins must be tied to the highest used CAP pin. For
example, if three capacitors are used, CAP4 should be tied
to CAP3. If only two capacitors are used, both CAP4 and
CAP3 should be tied to CAP2. The number of capacitors
used must be programmed on the CAP_SLCT0 and
CAP_SLCT1 pins by tying the pins to VCC2P5 for a one
and ground for a zero as shown in Table 1. The value
programmed on these pins may be read back from the
as high as possible to reduce the likelihood of it activating
during a charge cycle. Ideally, V would be set high
SHUNT
enough so that any likely capacitor mismatches would not
causetheshuntstoturnon.Thiskeepsthechargeroperat-
ing at the highest possible charge current and reduces the
charge time. If the shunts never turn on, the charge cycle
completes quickly and the balancers eventually equalize
the voltage on the capacitors. The shunt setting may also
be used to discharge the capacitors for testing, storage
or other purposes.
2
Setting Input and Charge Currents
num_caps register via I C/SMBus.
The maximum input current is determined by the resis-
Table 1
tance across the VOUTSP and VOUTSN pins, R
. The
SNSI
num_caps
NUMBER OF
CAPACITORS
CAP_SLCT1 CAP_SLCT0 REGISTER VALUE
maximum charge current is determined by the value of
the sense resistor, R , used in series with the induc-
0
0
1
1
0
1
0
1
0
1
2
3
1
2
3
4
SNSC
tor. The input and charge current loops servo the voltage
across their respective sense resistor to 32mV. Therefore,
the maximum input and charge currents are:
32mV
RSNSI
Capacitor Shunt Regulator Programming
I
=
IN(MAX)
2
V
is programmed via the I C/SMBus interface and
SHUNT
32mV
RSNSC
defaults to 2.7V at initial power-up. V
the voltage on any individual capacitor by turning on a
serves to limit
SHUNT
ICHG(MAX)
=
shunt around that capacitor as the voltage approaches
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The peak inductor current limit, I
, is 80% higher than
PEAK
The following equation can be used to determine charging
input current as a function of system load current:
the maximum charge current and is equal to:
58mV
RSNSC
32mV
SNSI1+RSNSI2
RSNSI1
SNSI1+RSNSI2
IPEAK
=
IINCHG
=
–
•ILOAD
R
R
Note that the input current limit does not include the part’s
quiescent and gate drive currents. The total current drawn
ThecontactresistanceofthenegativeterminalofR
and
SNSI1
the positive terminal of R
as well as the resistance of
SNSI2
by the part will be I
+ I + I , where I is the non-
IN(MAX)
Q G Q
thetraceconnectingthemwillcausevariabilityintheinput
currentlimit.To minimizetheerror,placebothinputcurrent
sense resistors close together with a large PCB pad area
betweenthemasthesystemloadcurrentispulledfromthe
trace connecting the two sense resistors.
switchingquiescentcurrentandI isthegatedrivecurrent.
G
Low Current Charging and High Current Backup
The LTC3350 can accommodate applications requiring
low charge currents and high backup currents. In these
applications, program the desired charge current using
Note that the backup current will flow through R
SNSI2
power dissipation.
. The
SNSI2
R
package should be sized accordingly to handle the
R
. The higher current needed during backup can be
SNSI
set using R
. The input current limit will override the
SNSC
V
(TO SYSTEM)
chargecurrentlimitwhenthesupercapacitorsarecharging
while the charge current limit provides sufficient current
capability for backup operation.
OUT
I
LOAD
V
IN
R
R
SNSI1 SNSI2
I
INCHG
The charge current will be limited to I
at low
CHG(MAX)
rises, the switching
V
IN
INFET VOUTSP
LTC3350
VOUTSN
TGATE
V
(i.e., low duty cycles). As V
CAP
CAP
controller’s input current will increase until it reaches
I
. The input current will be maintained at I
IN(MAX)
IN(MAX)
rises further.
BGATE
and the charge current will decrease as V
CAP
3350 F03
Some applications may want to use only a portion of the
inputcurrentlimittochargethesupercapacitors.Two input
current sense resistors placed in series can be used to
accomplish this as shown in Figure 3. VOUTSP is kelvin
Figure 3
Setting V
Voltage
CAP
The LTC3350 V
voltage is set by an external feedback
connected to the positive terminal of R
and VOUTSN
CAP
SNSI1
resistordivider,asshowninFigure4.Theregulatedoutput
is kelvin connected to the negative terminal of R
.
SNSI2
voltage is determined by:
The load current is pulled across R
while the input
SNSI1
SNSI1
current to the charger is pulled across R
The input current limit is:
and R
.
SNSI2
⎛
⎞
RFBC1
RFBC2
VCAP = 1+
CAPFBREF
⎜
⎟
⎝
⎠
32mV = R
• I
+ (R
+ R ) • I
SNSI2 INCHG
SNSI1 LOAD
SNSI1
where CAPFBREF is the output of the V
DAC, pro-
CAP
For example, suppose that only 2A of input current is de-
sired to charge the supercapacitors but the system load
and charger combined can pull a total of up to 4A from the
grammed in the vcapfb_dac register. Great care should
be taken to route the CAPFB line away from noise sources,
such as the SW line.
supply. Setting R
= R
= 8mΩ will set a 4A cur-
SNSI1
SNSI2
rent limit for the load + charger while setting a 2A limit for
the charger. With no system load, the charger can pull up
to 2A of input current. As the load pulls 0A to 4A of current
thecharger’sinputcurrentwillreducefrom2Adownto0A.
Power-Fail Comparator Input Voltage Threshold
The input voltage threshold below which the power-fail
status pin, PFO, indicates a power-fail condition and the
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V
V
IN
CAP
R
LTC3350
CAPFB
R
R
FBC1
PF1
PF2
PFI
V
DD
R
FBC2
LTC3350
PFO
R
PF3
3350 F04
MP1
Figure 4. VCAP Voltage Feedback Divider
MN1
LTC3350bidirectionalcontrollerswitchestostep-upmode
is programmed using a resistor divider from the V pin
IN
3350 F06
to SGND via the PFI pin such that:
Figure 6. PFI Threshold Divider with Added Hystersis
⎛
⎞
RPF1
RPF2
V = 1+
VPFI(TH)
MN1 and MP1 can be implemented with a single pack-
age N-channel and P-channel MOSFET pair such as the
Si1555DLorSi1016CX. ThedrainleakagecurrentofMN1,
when its gate voltage is at ground, can introduce an offset
in the threshold. To minimize the effect of this leakage cur-
IN
⎜
⎟
⎝
⎠
where V
is 1.17V. Typical values for R and R
PF1 PF2
PFI(TH)
are in the range of 40k to 1M. See Figure 5.
The input voltage above which the power-fail status pin
PFO is high impedance and the bidirectional controller
switches to step-down mode is:
rent R , R and R should be between 1k and 100k.
PF1 PF2
PF3
Setting V
Voltage in Backup Mode
OUT
⎛
⎞
RPF1
RPF2
The output voltage for the controller in step-up mode is
set by an external feedback resistor divider, as shown in
Figure 7. The regulated output voltage is determined by:
V = 1+
VPFI(TH) + VPFI(HYS)
(
)
IN
⎜
⎟
⎝
⎠
where V
is the hysteresis of the PFI comparator
PFI(HYS)
and is equal to 30mV.
⎛
⎞
⎟
RFBO1
RFBO2
V
OUT = 1+
1.2V
⎜
V
IN
⎝
⎠
R
R
LTC3350
PFI
PF1
Great care should be taken to route the OUTFB line away
from noise sources, such as the SW line.
PF2
3350 F05
V
OUT
R
Figure 5. PFI Threshold Voltage Divider
LTC3350
OUTFB
C
FBO1
R
FO
FBO1
FBO2
Additional hysteresis can be added by switching in an
(OPT)
additional resistor, R , in parallel with R
when the
PF3
PF2
C
FO
R
voltage at PFI falls below 1.17V as shown in Figure 6. The
(OPT)
–
+
VC
falling V threshold is the same as before but the rising
IN
R
V
C
REF
(OPT)
V threshold becomes:
IN
C
C
3350 F07
⎛
⎞
RPF1 RPF1
+
V = 1+
VPFI(TH) + VPFI(HYST)
(
)
IN
⎜
⎟
RRP2 RPF3
⎝
⎠
Figure 7. VOUT Voltage Divider and Compensation Network
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Compensation
The output ideal diode provides a low loss power path
from the supercapacitors to V . The minimum internal
OUT
The input current, charge current, V
voltage, and V
OUT
CAP
(open-circuit) supercapacitor voltage will be equal to
voltage loops all require a 1nF to 10nF capacitor from the
VC node to ground. When using the output ideal diode and
backing up to low voltages (<8V) use 8.2nF to 10nF on
VC. When not using the output ideal diode 4.7nF to 10nF
on VC is recommended. For very high backup voltages
(>15V) 1nF to 4.7nF is recommended.
the minimum V
necessary for the system to operate
OUT
plus the voltage drops due to the output ideal diode and
equivalent series resistance, R , of each supercapacitor
in the stack.
SC
Example: System needs 5V to run and draws 1A during
backup. There are four supercapacitors in the stack, each
In addition to the VC node capacitor, the V
voltage loop
OUT
with an R of 45mΩ. The output ideal diode forward
SC
requires a phase-lead capacitor, C
, for stability and
FBO1
regulation voltage is 30mV (OUTFET R
The minimum open-circuit supercapacitor voltage is:
< 30mΩ).
DS(ON)
improved transient response during input power failure
(Figure 7). The product of the top divider resistor and the
phase-lead capacitor should be used to create a zero at
approximately 2kHz:
V
= 5V + 0.030V + (1A • 4 • 45mΩ) = 5.21V
CAP(MIN)
Using the synchronous controller in step-up mode allows
the supercapacitors to be discharged to a voltage much
1
RFBO1 • CFBO1
≈
lower than the minimum V
needed to run the system.
OUT
2π 2kHz
(
)
The amount of power that the supercapacitor stack can
deliveratitsminimuminternal(open-circuit)voltageshould
be greater than what is needed to power the output and
the step-up converter.
Choose an R
such that C
is ≥ 100pF to minimize
FBO1
FBO1
theeffectsofparasiticpincapacitance.Becausethephase-
lead capacitor introduces a larger ripple at the input of
the V
transconductance amplifier, an additional RC
According to the maximum power transfer rule:
OUT
lowpass filter from the V
divider to the OUTFB pin may
OUT
2
VCAP(MIN)
P
BACKUP
beneededtoeliminatevoltageripplespikes. Thefiltertime
constant should be located at the switching frequency of
the synchronous controller:
PCAP(MIN)
=
>
4•n•RSC
η
In the equation above η is the efficiency of the synchro-
nous controller in step-up mode and n is the number of
supercapacitors in the stack.
1
RFO •CFO =
2πfSW
Example: System needs 5V to run and draws 1A during
backup.Therearefoursupercapacitorsinthestack(n=4),
with C > 10pF to minimize the effects of parasitic pin
FO
capacitance. For back up applications where the V
OUT
each with an R of 45mΩ. The converter efficiency is
SC
regulation voltage is low (~5V to 6V), an additional 1k to
90%.Theminimumopen-circuitsupercapacitorvoltageis:
3kresistor,R ,inserieswiththeVCcapacitorcanimprove
C
4•4•45mΩ •5V •1A
stability and transient response.
VCAP(MIN)
=
= 2.0V
0.9
Minimum V
Voltage in Backup Mode
CAP
In this case, the voltage seen at the terminals of the ca-
pacitor stack is half this voltage, or 1V, according to the
maximum power transfer rule.
In backup mode, power is provided to the output from the
supercapacitors either through the output ideal diode or
the synchronous controller operating in step-up mode.
3350fc
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LTC3350
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Note the minimum V
voltage can also be limited by the
where:
γMAX =1+ 1–
CAP
peakinductorcurrentlimit(180%ofmaximumchargecur-
rent)andthemaximumdutycycleinstep-upmode(~90%).
4RSC •P
BACKUP
and,
2
n
VCELL(MAX)
Optimizing Supercapacitor Energy Storage Capacity
4RSC •P
BACKUP
In most systems the supercapacitors will provide backup
powertooneormoreDC/DCconverters.ADC/DCconverter
presentsaconstantpowerloadtothesupercapacitor.When
the supercapacitors are near their maximum voltage, the
loads will draw little current. As the capacitors discharge,
the current drawn from supercapacitors will increase to
maintainconstantpowertotheload.Theamountofenergy
required in back up mode is the product of this constant
γMin =1+ 1–
2
n
VCELL(MIN)
R
is the equivalent series resistance (ESR) of a single
supercapacitorinthestack. Notethatthemaximumpower
transfer rule limits the minimum cell voltage to:
SC
VCAP(MIN)
4RSC •P
BACKUP
n
VCELL(MIN)
=
≥
n
backup power, P
, and the backup time, t
.
BACKUP
BACKUP
To minimize the size of the capacitance for a given amount
of backup energy, the maximum voltage on the stack,
CELL(MAX)
limited to a maximum of 2.7V and this may lead to an
unacceptably low capacitor lifetime.
The energy stored in a stack of n supercapacitors available
for backup is:
V
, can be increased. However, the voltage is
1
2
V2
VCELL(MIN)
2
nCSC
–
(
)
CELL(MAX)
whereC , V
andV
arethecapacitance,
SC CELL(MAX)
CELL(MIN)
An alternative option would be to keep V
at a
CELL(MAX)
maximum voltage and minimum voltage of a single ca-
pacitor in the stack, respectively. The maximum voltage
voltage that leads to reasonably long lifetime and increase
the capacitor utilization ratio of the supercapacitor stack.
on the stack is V
= n • V
CAP(MIN)
. The minimum
CELL(MIN)
CAP(MAX)
voltage on the stack is V
CELL(MAX)
= n • V
The capacitor utilization ratio, α , can be defined as:
B
.
2
2
–
VCELL(MAX) VCELL(MIN)
Some of this energy will be dissipated as conduction loss
in the ESR of the supercapacitor stack. A higher backup
power requirement leads to a higher conduction loss for
a given stack ESR.
αB =
VC2ELL(MAX)
Ifthesynchronouscontrollerinstep-upmodeisusedthen
thesupercapacitorscanberundowntoavoltagesetbythe
Theamountofcapacitanceneededcanbefoundbysolving
the following equation for C :
SC
⎡
⎤
⎥
⎦
⎛
⎞
γMAX •VCELL(MAX)
1
4
4RSC •P
BACKUP ln
2
2
P
BACKUP •tBACKUP = nCSC
γ
•
– γMIN
•
–
VCELL(MIN)
⎢
VCELL(MAX)
MAX
⎜
⎟
n
γMIN •VCELL(MIN)
⎝
⎠
⎢
⎥
⎣
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LTC3350
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maximum power transfer rule to maximize the utilization
ratio. The minimum voltage in this case is:
7. Ifasuitablecapacitorisnotavailable,iteratebychoosing
morecapacitance,ahighercellvoltage,morecapacitors
in the stack and/or a lower utilization ratio.
4RSC •P
BACKUP
VCELL(MIN)
=
8. Make sure to take into account the lifetime degrada-
tion of ESR and capacitance, as well as the maximum
discharge current rating of the supercapacitor. A list of
supercapacitor suppliers is provided in Table 2.
nη
where η is the efficiency of the boost converter
(~90% to 96%). For the backup equation, γ and γ
,
MAX
MIN
Table 2. Supercapacitor Suppliers
substitute P
/η for P
. In this case the energy
needed for backup is governed by the following equation:
BACKUP
BACKUP
AVX
www.avx.com
Bussman
CAP-XX
www.cooperbussman.com
www.cap-xx.com
www.illcap.com
P
1
2
BACKUP
2
tBACKUP ≤ nC •
•
VCELL(MAX)
SC
η
Illinois Capacitor
Maxwell
www.maxwell.com
www.murata.com
www.nesscap.com
www.tecategroup.com
⎡
⎢
⎢
⎣
⎤
⎥
⎦
⎛
⎞
⎟
αB + αB
1+ αB
1–α
B ln
Murata
–
⎜
2
2
1–αB ⎥
⎝
⎠
NESS CAP
Tecate Group
Once a capacitance is found using the above equation the
maximum ESR allowed needs to be checked:
Inductor Selection
2
The switching frequency and inductor selection are inter-
related. Higher switching frequencies allow the use of
smallerinductorandcapacitorvalues,butgenerallyresults
inlowerefficiencyduetoMOSFETswitchingandgatecharge
losses. In addition, the effect of inductor value on ripple
current must also be considered. The inductor ripple cur-
rent decreases with higher inductance or higher frequency
η 1–α n
(
)
VCELL(MAX)
B
RSC ≤
4P
BACKUP
Capacitor Selection Procedure
1. Determine backup requirements P
and t
.
BACKUP
BACKUP
2. Determine maximum cell voltage that provides accept-
able capacitor lifetime.
and increases with higher V . Accepting larger values of
IN
ripple current allows the use of low inductances but results
in higher output voltage ripple and greater core losses.
3. Choose number of capacitors in the stack.
4. Choose a desired utilization ratio, α , for the superca-
For the LTC3350, the best overall performance will be
attained if the inductor is chosen to be:
B
pacitor (e.g., 80%).
5. Solve for capacitance, C :
V
SC
IN(MAX)
L =
2PBACKUP •tBACKUP
ICHG(MAX) •fSW
CSC ≥
•
2
nη
VCELL(MAX)
for V
≤ 2V
and:
IN(MAX)
CAP
–1
⎡
⎤
⎥
⎛
⎞
⎟
1+ α
αB + αB
(
)
1–α
⎛
⎞
B
VCAP
VCAP
0.25•ICHG(MAX) •fSW
⎢
–
B ln
⎜
L = 1–
⎜
⎟
⎜
⎝
⎟
⎠
2
2
1–αB
⎢
⎥
V
⎝
⎠
IN(MAX)
⎣
⎦
6. FindsupercapacitorwithsufficientcapacitanceC and
SC
for V
≥ 2V , where V
is the final supercapaci-
CAP
IN(MAX)
tor stack voltage, V
CAP
minimum R :
SC
is the maximum input voltage,
IN(MAX)
I
f
is the maximum regulated charge current, and
2
CHG(MAX)
η 1–α n
(
)
VCELL(MAX)
B
is the switching frequency. Using these equations, the
SW
RSC ≤
4P
inductor ripple will be at most 25% of I
.
BACKUP
CHG(MAX)
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Using the above equation, the inductor may be too large
to provide a fast enough transient response to hold up
Maximum ripple occurs at the lowest V that can supply
CAP
OUT(BACKUP)
high frequency filtering.
I
. Multilayer ceramics are recommended for
V
when input power goes away. This occurs in cases
OUT
where the maximum V can be high (e.g. 25V) and the
IN
If step-up mode is unused, then the specification for
backup voltage low (e.g. 6V). In these situations it would
C
will be determined by the desired ripple voltage in
OUT
be best to choose an inductor that is smaller resulting in
step-down mode:
maximumpeak-to-peakrippleashighas40%ofI
.
CHG(MAX)
∆VOUT
=
Once the value for L is known, the type of inductor core
must be selected. Ferrite cores are recommended for their
very low core loss. Selection criteria should concentrate
on minimizing copper loss and preventing saturation.
Ferrite core material saturates “hard,” which means that
inductancecollapsesabruptlywhenthepeakdesigncurrent
is exceeded. This causes an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate. The saturation current
for the inductor should be at least 80% higher than the
I
⎛
⎞
VCAP
VOUT
VCAP
VOUT
CHG(MAX)
1–
+ICHG(MAX) •RESR
⎜
⎟
C
OUT •fSW
⎝
⎠
In continuous conduction mode, the source current of the
top MOSFET is a square wave of duty cycle V /V
.
CAP OUT
To prevent large voltage transients, a low ESR capacitor
sized for the maximum RMS current must be used. The
maximum RMS capacitor current is given by:
VCAP VOUT
VOUT VCAP
maximum regulated current, I
. A list of inductor
CHG(MAX)
suppliers is provided in Table 3.
IRMS ≅ICHG(MAX)
–1
Table 3. Inductor Vendors
This formula has a maximum at V
= 2V , where
OUT
CAP
VENDOR
Coilcraft
Murata
URL
I
= I
/2. This simple worst-case condition is
RMS
CHG(MAX)
www.coilcraft.com
www.murata.com
www.sumida.com
www.tdk.com
commonlyusedfordesignbecauseevensignificantdevia-
tions do not offer much relief.
Sumida
TDK
Mediumvoltage(20Vto35V)ceramic,tantalum,OS-CON,
and switcher-rated electrolytic capacitors can be used as
inputcapacitors.SanyoOS-CONSVP,SVPDseries,Sanyo
POSCAP TQC series, or aluminum electrolytic capacitors
from Panasonic WA series or Cornel Dublilier SPV series
in parallel with a couple of high performance ceramic
capacitors can be used as an effective means of achieving
low ESR and high bulk capacitance.
Toko
www.toko.com
Vishay
www.vishay.com
www.we-online.com
Würth Electronic
C
OUT
and C
Capacitance
CAP
V
serves as the input to the synchronous controller in
OUT
step-down mode and as the output in step-up (backup)
mode. If step-up mode is used, place 100µF of bulk
(aluminum electrolytic, OS-CON, POSCAP) capacitance
for every 2A of backup current desired. For 5V system
applications, 100µF per 1A of backup current is recom-
mended. In addition, a certain amount of high frequency
bypass capacitance is needed to minimize voltage ripple.
The voltage ripple in step-up mode is:
V
serves as the input to the controller in step-up mode
CAP
and as the output in step-down mode. The purpose of the
V
CAP
V
CAP
capacitor is to filter the inductor current ripple. The
ripple (∆V ) is approximated by:
CAP
⎛
⎞
1
∆VCAP ≈ ∆IPP
+RESR
⎜
⎟
8CCAP •fSW
⎝
⎠
where f
is the switching frequency, C
is the ca-
∆VOUT
=
SW
CAP
pacitance on V
and ∆I is the ripple current in the
CAP
PP
⎡
⎢
⎣
⎤
⎥
⎦
⎛
⎞
VCAP
VOUT
1
VOUT
OUT •fSW VCAP
inductor. The output ripple is highest at maximum input
voltage since ∆I increases with input voltage.
1–
+
•RESR
I
OUT(BACKUP)
⎜
⎟
C
⎝
⎠
PP
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Because supercapacitors have low series resistance, it is
Both MOSFET switches have conduction loss. However,
transition loss occurs only in the top MOSFET in step-
important that C
be sized properly so that the bulk of
CAP
down mode and only in the bottom MOSFET in step-up
the inductor current ripple flows through the filter capaci-
2
mode. These losses are proportional to V
and can
tor and not the supercapacitor. It is recommended that:
OUT
be considerably large in high voltage applications (V
> 20V). The maximum transition loss is:
OUT
⎛
⎞
1
n•RSC
+RESR
≤
⎜
⎟
8CCAP •fSW
5
⎝
⎠
k
2
P
TRAN ≈ VOUT2 •ICHG(MAX) •CRSS •fSW
where n is the number of supercapacitors in the stack and
is the ESR of each supercapacitor. The capacitance
R
SC
where k is related to the drive current during the Miller
plateau and is approximately equal to one.
on VCAP can be a combination of bulk and high frequency
capacitors. Aluminum electrolytic, OS-CON and POSCAP
capacitorsaresuitableforbulkcapacitancewhilemultilayer
ceramics are recommended for high frequency filtering.
Thesynchronouscontrollercanoperateinbothstep-down
and step-up mode with different voltages on V
in each
OUT
mode. If V
is 12V in step-down mode (input power
OUT
available) and 10V in step-up mode (backup mode) then
Power MOSFET Selection
bothMOSFETscanbesizedtominimizeconductionloss.If
Two external power MOSFETs must be selected for
the LTC3350’s synchronous controller: one N-channel
MOSFET for the top switch and one N-channel MOSFET
for the bottom switch. The selection criteria of the external
N-channelpowerMOSFETsincludemaximumdrain-source
V
canbeashighas25VwhilechargingandV
isheld
OUT
OUT
to 6V in backup mode, then the MOSFETs should be sized
to minimize losses during backup mode. This may lead to
choosing a high side MOSFET with significant transition
loss which may be tolerable when input power is avail-
able so long as thermal issues do not become a limiting
factor. The bottom MOSFET can be chosen to minimize
conductionloss.Ifstep-upmodeisunused,thenchoosing
voltage(V ),thresholdvoltage,on-resistance(R
),
G
DSS
DS(ON)
reversetransfercapacitance(C ),totalgatecharge(Q ),
RSS
and maximum continuous drain current.
V
of both MOSFETs should be selected to be higher
a high side MOSFET that that has a higher R
device
DSS
DS(ON)
than the maximum input supply voltage (including
and lower C
would minimize overall losses.
RSS
transient). The peak-to-peak drive levels are set by the
AnotherpowerlossrelatedtoswitchingMOSFETselection
isthepowerlosttodrivingthegates.Thetotalgatecharge,
DRV voltage. Logic-level threshold MOSFETs should
CC
be used because DRV is powered from either INTV
CC
CC
Q ,mustbechargedanddischargedeachswitchingcycle.
G
(5V) or an external LDO whose output voltage must be
ThepowerislosttotheinternalLDOandgatedriverswithin
the LTC3350. The power lost due to charging the gates is:
less than 5.5V.
MOSFET power losses are determined by R
, C
DS(ON) RSS
P ≈ (Q
+ Q ) • f • V
GBOT SW OUT
G
GTOP
and Q . The conduction loss at maximum charge current
G
where Q
is the top MOSFET gate charge and Q
GBOT
for the top and bottom MOSFET switches are:
GTOP
is the bottom MOSFET gate charge. Whenever possible,
utilizeMOSFETswitchesthatminimizethetotalgatecharge
to limit the internal power dissipation of the LTC3350.
VCAP
VOUT
PCOND(TOP)
=
ICHG(MAX)2 •RDS(ON) 1+δ∆T
(
)
⎛
⎞
VCAP
VOUT
P
COND(BOT) = 1–
ICHG(MAX)2 •RDS(ON) 1+δ∆T
Schottky Diode Selection
(
)
⎜
⎟
⎝
⎠
Optional Schottky diodes can be placed in parallel with the
top and bottom MOSFET switches. These diodes clamp
SW during the non-overlap times between conduction of
the top and bottom MOSFET switches. This prevents the
The term (1+ δ∆T) is generally given for a MOSFET in the
form of a normalized R
vs Temperature curve, but
DS(ON)
δ = 0.005/°C can be used as an approximation for low
voltage MOSFETs.
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body diodes of the MOSFET switches from turning on,
storing charge during the non-overlap time and requiring
a reverse recovery period that could cost as much as 3%
INTV /DRV and IC Power Dissipation
CC CC
The LTC3350 features a low dropout linear regulator
(LDO) that supplies power to INTV from the V sup-
CC
OUT
in efficiency at high V . One or both diodes can be omit-
IN
ply. INTV powers the gate drivers (when connected to
CC
ted if the efficiency loss can be tolerated. The diode can
be rated for about one-third to one-fifth of the full load
current since it is on for only a fraction of the duty cycle.
Larger diodes result in additional switching losses due to
their larger junction capacitance. In order for the diodes
to be effective, the inductance between them and the top
and bottom MOSFETs must be as small as possible. This
mandates that these components be placed next to each
other on the same layer of the PC board.
DRV ) and much of the LTC3350’s internal circuitry. The
CC
LDO regulates the voltage at the INTV pin to 5V. The
CC
LDO can supply a maximum current of 50mA and must
be bypassed to ground with a minimum of 1μF when not
connected to DRV . DRV should have at least a 2.2μF
CC
CC
ceramic or low ESR electrolytic capacitor. No matter what
type of bulk capacitor is used on DRV , an additional
CC
0.1μF ceramic capacitor placed directly adjacent to the
DRV pin is highly recommended. Good bypassing is
CC
needed to supply the high transient currents required by
Top MOSFET Driver Supply (C , D )
B
B
the MOSFET gate drivers.
An external bootstrap capacitor, C , connected to the BST
B
High input voltage applications in which large MOSFETs
are being driven at high frequencies may cause the maxi-
mum junction temperature rating for the LTC3350 to be
pin supplies the gate drive voltage for the top MOSFET.
Capacitor C , in Figure 8, is charged though an external
B
diode, D , from DRV when the SW pin is low. The value
B
CC
exceeded. The INTV current, which is dominated by the
CC
of the bootstrap capacitor, C , needs to be 20 times that
B
gate charge current, is supplied by the 5V LDO.
of the total input capacitance of the top MOSFET.
Power dissipation for the IC in this case is highest and is
With the top MOSFET on, the BST voltage is above the
system supply rail:
approximately equal to (V ) • (I + I ), where I is the
OUT
Q
G
Q
non-switching quiescent current of ~4mA and I is gate
G
V
BST
= V + V
OUT DRVCC
chargecurrent.Thejunctiontemperaturecanbeestimated
by using the equations given in Note 2 of the Electrical
The reverse break down of the external diode, D , must
B
Characteristics.Forexample,theI suppliedbytheINTV
G
CC
be greater than V
+ V
.
OUT(MAX)
DRVCC(MAX)
LDO is limited to less than 42mA from a 35V supply in the
The step-up converter can briefly run nonsynchronously
when used in conjunction with the output ideal diode. Dur-
ingthistimetheBSTtoSWvoltagecanpumpuptovoltages
QFN package at a 70°C ambient temperature:
T = 70°C + (35V)(4mA + 42mA)(34°C/W) = 125°C
J
exceeding5.5VifD isaSchottkydiode.FastswitchingPN
To prevent the maximum junction temperature from being
B
diodesarerecommendedduetotheirlowleakageandjunc-
tioncapacitance.ASchottkydiodecanbeusedifthestep-up
converter runs synchronous throughout backup mode.
exceeded, the INTV LDO current must be checked while
CC
operating in continuous conduction mode at maximum
V
OUT
.
The power dissipation in the IC is drastically reduced if
BST
DRV is powered from an external LDO. In this case the
CC
C
B
LTC3350
power dissipation in the IC is equal to power dissipation
D
B
SW
due to I and the power dissipated in the gate drivers,
Q
DRV
CC
CC
(V
) • (I ). Assuming the external DRV LDO output
DRVCC
G CC
0.1µF
>2.2µF
is 5V and is supplying 42mA to the gate drivers, the junc-
INTV
3350 F07
tion temperature rises to only 82°C:
1µF
OPT
T = 70°C + [(35V)(4mA)+(5V)(42mA)](34°C/W) = 82°C
J
Figure 8. Bootstrap Capacitor/Diode and DRVCC Connections
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LTC3350
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The external LDO should be powered from V . It must
Achievingforwardregulationwillminimizepowerlossand
heat dissipation, but it is not a necessity. If a forward volt-
age drop of more than 30mV is acceptable, then a smaller
MOSFET can be used but must be sized compatible with
the higher power dissipation. Care should be taken to
ensure that the power dissipated is never allowed to rise
above the manufacturer’s recommended maximum level.
OUT
be enabled after the INTV LDO has powered up and its
CC
output must be less than 5.5V. INTV should no longer
CC
be tied to DRV .
CC
Minimum On-Time Considerations
Minimum on-time, t
, is the smallest time dura-
ON(MIN)
tion that the LTC3350 is capable of turning on the top
MOSFET in step-down mode. It is determined by internal
timing delays and the gate charge required to turn on the
top MOSFET. The minimum on-time for the LTC3350 is
approximately 85ns. Low duty cycle applications may
approach this minimum on-time limit and care should be
taken to ensure that:
During backup mode, the output ideal diode shuts off
when the voltage on OUTFB falls below 1.3V. For high
V
backup voltages (>8.4V), the output ideal diode will
OUT
shut off when V
above the V
is more than a diode drop (~700mV)
CAP
regulation point (i.e., OUTFB > 1.2V). The
OUT
body diode of the output ideal diode N-channel MOSFET
will carry the load current until V drops to within a
CAP
diode drop of the V
regulation voltage at which point
OUT
VCAP
VOUT •fSW
tON(MIN)
<
the synchronous controller takes over. During this period
the power dissipation in the output ideal diode MOSFET
increases significantly. Diode conduction time is small
comparedtotheoverallbackuptimebutcanbesignificant
whendischargingverylargesupercapacitors(>600F).Care
should be taken to properly heat sink the MOSFET to limit
the temperature rise.
If the duty cycle falls below what can be accommodated
by the minimum on-time, the controller will begin to skip
cycles.ThechargecurrentandV voltagewillcontinueto
CAP
beregulated,buttheripplevoltageandcurrentwillincrease.
Ideal Diode MOSFET Selection
PCB Layout Considerations
AnexternalN-channelMOSFETisrequiredfortheinputand
outputidealdiodes.Importantparametersfortheselection
oftheseMOSFETsarethemaximumdrain-sourcevoltage,
When laying out the printed circuit board, the following
guidelines should be used to ensure proper operation of
the IC. Check the following in your layout:
V
DSS
, gate threshold voltage and on-resistance (R
).
DS(ON)
1. Keep MN1, MN2, D1, D2 and C
close together.
The high di/dt loop formed by the MOSFETs, Schottky
diodes and the V capacitance, shown in Figure 9,
should have short, wide traces to minimize high
frequency noise and voltage stress from inductive
ringing. Surface mount components are preferred to
reduce parasitic inductances from component leads.
D1
Whentheinputisgrounded,eitherthesupercapacitorstack
voltageorthestep-upcontroller’sbackupvoltageisapplied
OUT
acrosstheinputidealdiodeMOSFET.Therefore,theV of
OUT
DSS
theinputidealdiodeMOSFETmustwithstandthemaximum
voltage on V
in backup mode. When the supercapaci-
OUT
torsareat0V,theinputvoltageisappliedacrosstheoutput
idealdiodeMOSFET.Therefore,theV oftheoutputideal
diode MOSFET must withstand the highest voltage on V .
DSS
IN
The gate drive for both ideal diodes is 5V. This allows the
use of logic-level threshold N-channel MOSFETs.
R
L1
MN1
SNSC
V
CAP
V
OUT
+
As a general rule, select MOSFETs with a low enough
+
+
+
HIGH
FREQUENCY
CIRCULATING
PATH
C
OUT
C
CAP
R
to obtain the desired V while operating at full
DS(ON)
DS
MN2
D2
loadcurrent.TheLTC3350willregulatetheforwardvoltage
drop across the input and output ideal diode MOSFETs to
3350 F09
30mVifR
islowenough.TherequiredR
canbe
DS(ON)
DS(ON)
Figure 9. High Speed Switching Path
calculated by dividing 0.030V by the load current in amps.
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For more information www.linear.com/LTC3350
LTC3350
applicaTions inForMaTion
DIRECTION OF SENSED CURRENT
Connect the drain of the top MOSFET and cathode of
the top diode directly to the positive terminal of C
.
OUT
R
Connect the source of the bottom MOSFET and anode
of the bottom diode directly to the negative terminal
SNSC
OR
R
SNSI
of C . This capacitor provides the AC current to the
OUT
3350 F10
MOSFETs.
TO VCAP
OR
VOUTSN
TO ICAP
OR
VOUTSP
2. Ground is referenced to the negative terminal of the
V
decoupling capacitor in step-down mode and to
CAP
Figure 10. Kelvin Current Sensing
thenegativeterminaloftheV
decouplingcapacitor
OUT
instep-upmode.ThenegativeterminalofC
should
7. Locate the DRV and BST decoupling capacitors in
OUT
CC
be as close as possible to the negative terminal of
by placing the capacitors next to each other and
close proximity to the IC. These capacitors carry the
C
MOSFETdrivers’highpeakcurrents.Anadditional0.1μF
CAP
away from the switching loop described above. The
combined IC SGND pin/PGND paddle and the ground
ceramiccapacitorplacedimmediatelynexttotheDRV
CC
pin can help improve noise performance substantially.
returnsofC
andC
mustreturntothecom-
INTVCC
DRVCC
8. Locate the small-signal components away from high
frequencyswitchingnodes(BST,SW,TG,andBG).All
ofthesenodeshaveverylargeandfastmovingsignals
and should be kept on the output side of the LTC3350.
bined negative terminal of C
and C
.
OUT
CAP
3. Effectivegroundingtechniquesarecriticalforsuccess-
fulDC/DCconverterlayouts.Orientpowercomponents
such that switching current paths in the ground plane
do not cross through the SGND pin and exposed pad
on the backside of the LTC3350 IC. Switching path
currents can be controlled by orienting the MOSFET
9. The input ideal diode senses the voltage between V
IN
andVOUTSP.V shouldbeconnectednearthesource
IN
of the input ideal diode MOSFET. VOUTSP is used for
Kelvin sensing the input current. Place the input cur-
switches,Schottkydiodes,theinductor,andV
CAP
other.
and
OUT
rent sense resistor, R
, near the input ideal diode
SNSI
V
decoupling capacitors in close proximity to each
MOSFETwithashort,widetracetominimizeresistance
betweenthedrainoftheidealdiodeMOSFETandR
.
SNSI
4. Locate V
and V
dividers near the part and away
CAP
OUT
10. The output ideal diode senses the voltage between
VOUTSN and VCAP. VCAP is used for Kelvin sensing
the charge current. Place the output ideal diode near
from switching components. Kelvin the top of resistor
dividers to the positive terminals of C and C
,
OUT
CAP
respectively.Thebottomoftheresistivedividersshould
go back to the SGND pin. The feedback resistor con-
nectionsshouldnotberunalongthehighcurrentfeeds
thechargecurrentsenseresistor, R
, withashort,
SNSC
wide trace to minimize resistance between the source
of the ideal diode MOSFET and R
.
SNSC
from the C
capacitor.
OUT
11. TheINFETandOUTFETpinsfortheexternalidealdiode
controllers have extremely limited drive current. Care
mustbetakentominimizeleakagetoadjacentPCboard
traces.100nAofleakagefromthesepinswillintroduce
anadditionaloffsettotheidealdiodesofapproximately
10mV. To minimize leakage, the INFET trace can be
guarded on the PC board by surrounding it with VOUT
connectedmetal.Similarly,theOUTFETtraceshouldbe
guardedbysurroundingitwithVCAPconnectedmetal.
5. RouteICAPandVCAPsenselinestogether, keepthem
short. Same with VOUTSP and VOUTSN. Filter com-
ponents should be placed near the part and not near
the sense resistors. Ensure accurate current sensing
with Kelvin connections at the sense resistors. See
Figure 10.
6. Thetracefromthepositiveterminaloftheinputcurrent
sense resistor, R
, to the VOUTSP pin carries the
SNSI
part’s quiescent and gate drive currents. To maintain
accurate measurement of the input current keep this
12. TheVCC2P5bypasscapacitorshouldreturntoground
away from switching and gate drive current paths.
3350fc
trace short and wide by placing R
near the part.
SNSI
31
For more information www.linear.com/LTC3350
LTC3350
regisTer Map
REGISTER
clr_alarms
msk_alarms
msk_mon_status
cap_esr_per
vcapfb_dac
vshunt
SUB ADDR
0x00
0x01
0x02
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
BITS
15:0
15:0
9:0
DESCRIPTION
DEFAULT
0x0000
0x0000
0x0000
0x0000
0xF
PAGE
33
33
34
34
34
34
34
34
34
34
35
35
35
35
35
35
35
35
35
35
35
35
36
36
36
37
37
38
38
38
38
38
38
38
38
38
38
38
38
38
Clear alarms register
Enable/mask alarms register
Enable/mask monitor status alerts
Capacitance/ESR measurement period
15:0
3:0
V
voltage reference DAC setting
CAP
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
3:0
Capacitor shunt voltage setting
Capacitor undervoltage alarm level
Capacitor overvoltage alarm level
GPI undervoltage alarm level
GPI overvoltage alarm level
0x3999
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0b0000
–
cap_uv_lvl
cap_ov_lvl
gpi_uv_lvl
gpi_ov_lvl
vin_uv_lvl
vin_ov_lvl
vcap_uv_lvl
vcap_ov_lvl
vout_uv_lvl
vout_ov_lvl
iin_oc_lvl
V
V
V
V
V
V
undervoltage alarm level
overvoltage alarm level
IN
IN
undervoltage alarm level
overvoltage alarm level
undervoltage alarm level
overvoltage alarm level
CAP
CAP
OUT
OUT
I
I
overcurrent alarm level
IN
ichg_uc_lvl
dtemp_cold_lvl
dtemp_hot_lvl
esr_hi_lvl
undercurrent alarm level
CHG
Die temperature cold alarm level
Die temperature hot alarm level
ESR high alarm level
cap_lo_lvl
ctl_reg
Capacitance low alarm level
Control register
num_caps
chrg_status
mon_status
alarm_reg
meas_cap
meas_esr
1:0
Number of capacitors configured
Charger status register
R
11:0
9:0
–
R
Monitor status register
–
R
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
Active alarms register
0x0000
–
R
Measured capacitance value
Measured ESR value
R
–
meas_vcap1
meas_vcap2
meas_vcap3
meas_vcap4
meas_gpi
R
Measured capacitor one voltage
Measured capacitor two voltage
Measured capacitor three voltage
Measured capacitor four voltage
Measured GPI pin voltage
–
R
–
R
–
R
–
R
–
meas_vin
R
Measured V voltage
–
IN
meas_vcap
meas_vout
meas_iin
R
Measured V
Measured V
voltage
voltage
–
CAP
OUT
R
–
R
Measured I current
–
IN
meas_ichg
meas_dtemp
R
Measured I
current
–
CHG
R
Measured die temperature
–
Registers at sub address 0x03, 0x18, 0x19, 0x2B-0xFF are unused.
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For more information www.linear.com/LTC3350
LTC3350
regisTer DescripTions
clr_alarms (0x00)
Clear Alarms Register: This register is used to clear alarms caused by exceeding a programmed limit. Writing a one to any bit in this register will cause its
respective alarm to be cleared. The one written to this register is automatically cleared when its respective alarm is cleared.
BIT(S)
0
BIT NAME
DESCRIPTION
clr_cap_uv
clr_cap_ov
clr_gpi_uv
clr_gpi_ov
clr_vin_uv
clr_vin_ov
clr_vcap_uv
clr_vcap_ov
clr_vout_uv
clr_vout_ov
clr_iin_oc
Clear capacitor undervoltage alarm
Clear capacitor overvoltage alarm
Clear GPI undervoltage alarm
Clear GPI overvoltage alarm
1
2
3
4
Clear V undervoltage alarm
IN
5
Clear V overvoltage alarm
IN
6
Clear V
Clear V
Clear V
Clear V
undervoltage alarm
overvoltage alarm
undervoltage alarm
overvoltage alarm
CAP
CAP
OUT
OUT
7
8
9
10
11
12
13
14
15
Clear input overcurrent alarm
Clear charge undercurrent alarm
Clear die temperature cold alarm
Clear die temperature hot alarm
Clear ESR high alarm
clr_ichg_uc
clr_dtemp_cold
clr_dtemp_hot
clr_esr_hi
clr_cap_lo
Clear capacitance low alarm
msk_alarms (0x01)
Mask Alarms Register: Writing a one to any bit in the Mask Alarms Register enables its respective alarm to trigger an SMBALERT.
BIT(S)
0
BIT NAME
DESCRIPTION
msk_cap_uv
msk_cap_ov
msk_gpi_uv
msk_gpi_ov
msk_vin_uv
msk_vin_ov
msk_vcap_uv
msk_vcap_ov
msk_vout_uv
msk_vout_ov
msk_iin_oc
Enable capacitor undervoltage alarm
Enable capacitor overvoltage alarm
Enable GPI undervoltage alarm
Enable GPI overvoltage alarm
1
2
3
4
Enable V undervoltage alarm
IN
5
Enable V overvoltage alarm
IN
6
Enable V
Enable V
Enable V
Enable V
undervoltage alarm
overvoltage alarm
undervoltage alarm
overvoltage alarm
CAP
CAP
OUT
OUT
7
8
9
10
11
12
13
14
15
Enable input overcurrent alarm
Enable charge undercurrent alarm
Enable die temperature cold alarm
Enable die temperature hot alarm
Enable ESR high alarm
msk_ichg_uc
msk_dtemp_cold
msk_dtemp_hot
msk_esr_hi
msk_cap_lo
Enable capacitance low alarm
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For more information www.linear.com/LTC3350
LTC3350
regisTer DescripTions
msk_mon_status (0x02)
Mask Monitor Status Register: Writing a one to any bit in this register enables a rising edge of its respective bit in the mon_status register to trigger an
SMBALERT.
BIT(S)
BIT NAME
DESCRIPTION
0
msk_mon_capesr_active
msk_mon_capesr_scheduled
msk_mon_capesr_pending
msk_mon_cap_done
msk_mon_esr_done
msk_mon_cap_failed
msk_mon_esr_failed
–
Set the SMBALERT when there is a rising edge on mon_capesr_active
Set the SMBALERT when there is a rising edge on mon_capesr_scheduled
Set the SMBALERT when there is a rising edge on mon_capesr_pending
Set the SMBALERT when there is a rising edge on mon_cap_done
Set the SMBALERT when there is a rising edge on mon_esr_done
Set the SMBALERT when there is a rising edge on mon_cap_failed
Set the SMBALERT when there is a rising edge on mon_esr_failed
Reserved, write to 0
1
2
3
4
5
6
7
8
msk_mon_power_failed
msk_mon_power_returned
–
Set the SMBALERT when there is a rising edge on mon_power_failed
Set the SMBALERT when there is a rising edge on mon_power_returned
Reserved, write to 0
9
15:10
cap_esr_per (0x04)
10 seconds per LSB
Capacitance and ESR Measurement Period: This register sets the period of repeated capacitance and ESR measurements. Each LSB represents 10
seconds. Capacitance and ESR measurements will not repeat if this register is zero.
vcapfb_dac (0x05)
CAPFBREF = 37.5mV • vcapfb_dac + 637.5mV
V
CAP
Regulation Reference: This register is used to program the capacitor voltage feedback loop’s reference voltage. Only bits 3:0 are active.
vshunt (0x06)
183.5µV per LSB
Shunt Voltage Register: This register programs the shunt voltage for each capacitor in the stack. The charger will limit current and the active shunts will
shunt current to prevent this voltage from being exceeded. As a capacitor voltage nears this level, the charge current will be reduced. This should be
programmed higher than the intended final balanced individual capacitor voltage. Setting this register to 0x0000 disables the shunt.
cap_uv_lvl (0x07)
183.5µV per LSB
Capacitor Undervoltage Level: This is an alarm threshold for each individual capacitor voltage in the stack. If enabled, any capacitor voltage falling below
this level will trigger an alarm and an SMBALERT.
cap_ov_lvl (0x08)
183.5µV per LSB
Capacitor Overvoltage Level: This is an alarm threshold for each individual capacitor in the stack. If enabled, any capacitor voltage rising above this level
will trigger an alarm and an SMBALERT.
gpi_uv_lvl (0x09)
183.5µV per LSB
General Purpose Input Undervoltage Level: This is an alarm threshold for the GPI pin. If enabled, the voltage falling below this level will trigger an alarm
and an SMBALERT.
gpi_ov_lvl (0x0A)
183.5µV per LSB
General Purpose Input Overvoltage Level: This is an alarm threshold for the GPI pin. If enabled, the voltage rising above this level will trigger an alarm and
an SMBALERT.
3350fc
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For more information www.linear.com/LTC3350
LTC3350
regisTer DescripTions
vin_uv_lvl (0x0B)
2.21mV per LSB
2.21mV per LSB
1.476mV per LSB
V
Undervoltage Level: This is an alarm threshold for the input voltage. If enabled, the voltage falling below this level will trigger an alarm and an
IN
SMBALERT.
vin_ov_lvl (0x0C)
V
Overvoltage Level: This is an alarm threshold for the input voltage. If enabled, the voltage rising above this level will trigger an alarm and an
IN
SMBALERT.
vcap_uv_lvl (0x0D)
V
Undervoltage Level: This is an alarm threshold for the capacitor stack voltage. If enabled, the voltage falling below this level will trigger an alarm and
CAP
an SMBALERT.
vcap_ov_lvl (0x0E)
1.476mV per LSB
V
Overvoltage Level: This is an alarm threshold for the capacitor stack voltage. If enabled, the voltage rising above this level will trigger an alarm and
CAP
an SMBALERT.
vout_uv_lvl (0x0F)
2.21mV per LSB
V
Undervoltage Level: This is an alarm threshold for the output voltage. If enabled, the voltage falling below this level will trigger an alarm and an
OUT
SMBALERT.
vout_ov_lvl (0x10)
2.21mV per LSB
V
Overvoltage Level: This is an alarm threshold for the output voltage. If enabled, the voltage rising above this level will trigger an alarm and an
OUT
SMBALERT.
iin_oc_lvl (0x11)
1.983µV/R
per LSB
SNSI
Input Overcurrent Level: This is an alarm threshold for the input current. If enabled, the current rising above this level will trigger an alarm and an
SMBALERT.
ichg_uc_lvl (0x12)
1.983µV/R
SNSC
per LSB
Charge Undercurrent Level: This is an alarm threshold for the charge current. If enabled, the current falling below this level will trigger an alarm and an
SMBALERT.
dtemp_cold_lvl (0x13)
Temperature = 0.028°C per LSB – 251.4°C
Die Temperature Cold Level: This is an alarm threshold for the die temperature. If enabled, the die temperature falling below this level will trigger an alarm
and an SMBALERT.
dtemp_hot_lvl (0x14)
Temperature = 0.028°C per LSB – 251.4°C
Die Temperature Hot Level: This is an alarm threshold for the die temperature. If enabled, the die temperature rising above this level will trigger an alarm
and an SMBALERT.
esr_hi_lvl (0x15)
R /64 per LSB
SNSC
ESR High Level: This is an alarm threshold for the measured stack ESR. If enabled, a measurement of stack ESR exceeding this level will trigger an alarm
and an SMBALERT.
cap_lo_lvl (0x16)
336µF • R /R per LSB
T TST
Capacitance Low Level: This is an alarm threshold for the measured stack capacitance. If enabled, if the measured stack capacitance is less than this level
it will trigger an alarm and an SMBALERT. When ctl_cap_scale is set to one the constant is 3.36 • R /R
.
T
TST
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For more information www.linear.com/LTC3350
LTC3350
regisTer DescripTions
ctl_reg (0x17)
Control Register: Several Control Functions are grouped into this register.
BIT(S)
BIT NAME
DESCRIPTION
0
ctl_strt_capesr
Begin a capacitance and ESR measurement when possible; this bit clears itself
once a cycle begins.
1
ctl_gpi_buffer_en
A one in this bit location enables the input buffer on the GPI pin. With a zero in this
location the GPI pin is measured without the buffer.
2
3
ctl_stop_capesr
ctl_cap_scale
Stops an active capacitance/ESR measurement.
Increases capacitor measurement resolution by 100x, this is used when measuring
smaller capacitors.
15:4
–
Reserved
num_caps (0x1A)
Number of Capacitors: This register shows the state of the CAP_SLCT1, CAP_SLCT0 pins. The value read in this register is the number of capacitors
programmed minus one.
VALUE
0b00
0b01
0b10
0b11
CAPACITORS
1 Capacitor Selected
2 Capacitors Selected
3 Capacitors Selected
4 Capacitors Selected
chrg_status (0x1B)
Charger Status Register: This register provides real time status information about the state of the charger system. Each bit is active high.
BIT(S)
BIT NAME
chrg_stepdown
chrg_stepup
chrg_cv
DESCRIPTION
0
1
The synchronous controller is in step-down mode (charging)
The synchronous controller is in step-up mode (backup)
The charger is in constant voltage mode
The charger is in undervoltage lockout
The charger is in input current limit
The capacitor voltage is above power good threshold
The capacitor manager is shunting
The capacitor manager is balancing
The charger is temporarily disabled for capacitance measurement
The charger is in constant current mode
Reserved
2
3
chrg_uvlo
chrg_input_ilim
chrg_cappg
chrg_shnt
chrg_bal
chrg_dis
chrg_ci
4
5
6
7
8
9
10
11
15:12
–
chrg_pfo
–
Input voltage is below PFI threshold
Reserved
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LTC3350
regisTer DescripTions
mon_status (0x1C)
Monitor Status: This register provides real time status information about the state of the monitoring system. Each bit is active high.
BIT(S)
BIT NAME
DESCRIPTION
0
1
2
3
4
5
6
7
8
mon_capesr_active
mon_capesr_scheduled
mon_capesr_pending
mon_cap_done
mon_esr_done
mon_cap_failed
mon_esr_failed
–
Capacitance/ESR measurement is in progress
Waiting programmed time to begin a capacitance/ESR measurement
Waiting for satisfactory conditions to begin a capacitance/ESR measurement
Capacitance measurement has completed
ESR Measurement has completed
The last attempted capacitance measurement was unable to complete
The last attempted ESR measurement was unable to complete
Reserved
mon_power_failed
This bit is set when V falls below the PFI threshold or the charger is unable to
IN
charge. It is cleared only when power returns and the charger is able to charge.
9
mon_power_returned
–
This bit is set when the input is above the PFI threshold and the charger is able to
charge. It is cleared only when mon_power_failed is set.
15:10
Reserved
alarm_reg (0x1D)
Alarms Register: A one in any bit in the register indicates its respective alarm has triggered. All bits are active high.
BIT(S)
0
BIT NAME
DESCRIPTION
alarm_cap_uv
alarm_cap_ov
alarm_gpi_uv
alarm_gpi_ov
alarm_vin_uv
alarm_vin_ov
alarm_vcap_uv
alarm_vcap_ov
alarm_vout_uv
alarm_vout_ov
alarm_iin_oc
alarm_ichg_uc
alarm_dtemp_cold
alarm_dtemp_hot
alarm_esr_hi
alarm_cap_lo
Capacitor undervoltage alarm
Capacitor overvoltage alarm
GPI undervoltage alarm
GPI overvoltage alarm
1
2
3
4
V
V
V
V
V
V
undervoltage alarm
overvoltage alarm
IN
5
IN
6
undervoltage alarm
overvoltage alarm
undervoltage alarm
overvoltage alarm
CAP
CAP
OUT
OUT
7
8
9
10
11
12
13
14
15
Input overcurrent alarm
Charge undercurrent alarm
Die temperature cold alarm
Die temperature hot alarm
ESR high alarm
Capacitance low alarm
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For more information www.linear.com/LTC3350
LTC3350
regisTer DescripTions
meas_cap (0x1E)
336µF • R /R per LSB
T
TST
Measured capacitor stack capacitance value. When ctl_cap_scale is set to one the constant is 3.36µF • R /R
.
T
TST
meas_esr (0x1F)
R /64 per LSB
SNSC
Measured capacitor stack equivalent series resistance (ESR) value
meas_vcap1 (0x20)
183.5µV per LSB
183.5µV per LSB
183.5µV per LSB
183.5µV per LSB
183.5µV per LSB
2.21mV per LSB
1.476mV per LSB
2.21mV per LSB
Measured voltage between the CAP1 and CAPRTN pins.
meas_vcap2 (0x21)
Measured voltage between the CAP2 and CAP1 pins.
meas_vcap3 (0x22)
Measured voltage between the CAP3 and CAP2 pins.
meas_vcap4 (0x23)
Measured voltage between the CAP4 and CAP3 pins.
meas_gpi (0x24)
Measurement of GPI pin voltage.
meas_vin (0x25)
Measured Input Voltage.
meas_vcap (0x26)
Measured Capacitor Stack Voltage.
meas_vout (0x27)
Measured Output Voltage.
meas_iin (0x28)
1.983µV/R
per LSB
per LSB
SNSI
Measured Input Current.
meas_ichg (0x29)
1.983µV/R
SNSC
Measured Charge Current.
meas_dtemp (0x2A)
Temperature = 0.028°C per LSB – 251.4°C
Measured die temperature.
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For more information www.linear.com/LTC3350
LTC3350
Typical applicaTions
Application Circuit 1. 25V to 35V, 6.4A Supercapacitor Charger with 2A Input Current Limit and 28V, 50W Backup Mode
R
MN1
SiS434DN
SNSI
0.016Ω
V
OUT
V
IN
28V
25V TO 35V
50W IN BACKUP
C2
1µF
C1
0.1µF
25V RISING THRESHOLD
22V FALLING THRESHOLD
R
PF1
80.6k
V
IN
INFET VOUTM5VOUTSP VOUTSN OUTFET
PFI
R
R
PF3
39.2k
PF2
4.53k
C
OUT2
V
+
DD
C
10µF
FBO1
R
C
Si1555DL
FBO1
665k
OUT1
82µF
120pF
×2
R1
10k
R2
10k
R3
10k
OUTFB
R
29.4k
DRV
FBO2
CC
R7
10k
INTV
CC
C3
C4
0.1µF
D
B
4.7µF
B0540WS
BST
PFO
CAPGD
SMBALERT
SCL
PFO
C
B
0.1µF
MN2
SiS434DN
CAPGD
SMBALERT
SCL
TGATE
L1
6.8µH
R
SNSC
0.005Ω
SDA
SDA
SW
MN3
SiS434DN
C
CAP
47µF
BGATE
VCC2P5
LTC3350
R4
100k
CAP_SLCT0
CAP_SLCT1
ICAP
VCAP
CFP
R
R
R
R
2.7Ω
CAP4
CAP3
CAP2
CAP1
C5
1µF
C
C
CP5
0.1µF
GPI
VC
F
+
0.1µF
2.7Ω
2.7Ω
2.7Ω
CFN
VCAPP5
CAP4 5F
R
FBC1
866k
+
+
+
CAP3 5F
RT
R
T1
100k
CAP4
CAP3
CAP2
CAP1
T
R
FBC2
ITST
CAP2 5F
CAP1 5F
118k
C
C
R5
R6
1.2nF 107k 121Ω
R
2.7Ω
CAPRTN
SGND
PGND
CAPRTN
CAPFB
3350 TA02
CAP1-4: NESSCAP ESHSR-0005C0-002R7
L1: COILCRAFT XAL7070-682ME
3350fc
39
For more information www.linear.com/LTC3350
LTC3350
Typical applicaTions
Application Circuit 2. 11V to 20V, 16A Supercapacitor Charger with 6.4A Input Current Limit and 10V, 60W Backup Mode
R
MN1
SiR422DP
SNSI
0.005Ω
V
OUT
V
IN
11V TO 20V
10V
60W IN BACKUP
C2
1µF
C1
0.1µF
C
+
C
OUT2
OUT1
C
R
FBO1
R
PF1
FBO1
619k
22µF
82µF
V
INFET VOUTM5VOUTSP VOUTSN OUTFET
OUTFB
120pF
IN
806k
×4
×4
V
PFI
DD
R
89.5k
R
DRV
FBO2
PF2
CC
100k
INTV
CC
R1
10k
R2
10k
R3
10k
C3
C4
0.1µF
D
B
4.7µF
B0540WS
BST
PFO
CAPGD
SMBALERT
SCL
PFO
C
B
0.47µF
MN2
CAPGD
SMBALERT
SCL
BSC026N02KS
TGATE
L1
2.2µH
R
SNSC
0.002Ω
SDA
SDA
SW
MN3
C
CAP
BSC046N02KS ×2
47µF
BGATE
VCC2P5
LTC3350
R4
100k
CAP_SLCT0
CAP_SLCT1
ICAP
VCAP
CFP
R
R
R
R
2.7Ω
CAP4
CAP3
CAP2
CAP1
C5
1µF
C
C
CP5
0.1µF
GPI
VC
F
+
0.1µF
2.7Ω
2.7Ω
2.7Ω
CFN
VCAPP5
CAP4 360F
CAP3 360F
CAP2 360F
CAP1 360F
R
FBC1
845k
+
+
+
RT
R
T1
100k
CAP4
CAP3
CAP2
CAP1
T
R
FBC2
ITST
150k
C
C
10nF
R5
R6
133k 121Ω
R
2.7Ω
CAPRTN
SGND
PGND
CAPRTN
CAPFB
3350 TA03
CAP1-4: NESSCAP ESHSR-0360CO-002R7
L1: VISHAY IHLP5050FDER2R2MO1
Application Circuit 3. 11V to 20V, 5.3A LiFePO4 Battery Charger with 4.6A Input Current Limit and 12V, 48W Backup Mode
R
MN1
SiS438DN
SNSI
0.007Ω
V
OUT
V
IN
11V TO 20V
12V
48W IN BACKUP
C2
1µF
C1
0.1µF
C
C
OUT2
OUT1
C
R
FBO1
R
PF1
FBO1
649k
47µF
2.2µF
V
INFET VOUTM5VOUTSP VOUTSN OUTFET
OUTFB
120pF
IN
806k
×2
×2
V
PFI
DD
R
71.5k
R
DRV
FBO2
PF2
CC
100k
INTV
CC
R1
10k
R2
10k
R3
10k
C3
C4
0.1µF
D
B
4.7µF
B0540WS
BST
PFO
CAPGD
SMBALERT
SCL
PFO
C
B
0.1µF
MN2
BSZ060NE2LS
CAPGD
SMBALERT
SCL
TGATE
L1
3.3µH
R
SNSC
0.006Ω
SDA
SDA
SW
C
MN3
BSZ060NE2LS
CAP
22µF
BGATE
VCC2P5
×4
LTC3350
R4
100k
CAP_SLCT1
CAP_SLCT0
ICAP
VCAP
CFP
C5
1µF
C
C
CP5
0.1µF
GPI
VC
F
0.1µF
R
R
R
3.6Ω
CAP3
CAP2
CAP1
CFN
VCAPP5
+
+
+
3.6Ω
3.6Ω
RT
R
T1
100k
CAP4
CAP3
CAP2
CAP1
T
R
FBC1
909k
ITST
C
C
R5
R6
4.7nF 71.5k 10M
R
118k
FBC2
R
3.6Ω
CAPRTN
SGND
PGND
CAPRTN
CAPFB
3350 TA04
V
= 3.6V
SHUNT
L1: COILCRAFT XAL7070-332ME
3350fc
40
For more information www.linear.com/LTC3350
LTC3350
Typical applicaTions
Application Circuit 4. 11V to 35V, 4A Supercapacitor Charger with 2A Input Current Limit and 10V, 1A Backup Mode
R
MN1
SiR426DP
SNSI
0.016Ω
V
OUT
V
IN
11V TO 35V
10V
10W IN BACKUP
C2
1µF
C1
0.1µF
C
OUT2
+
C
R
10µF
FBO1
R
C
PF1
806k
FBO1
665k
OUT1
82µF
V
INFET VOUTM5VOUTSP VOUTSN OUTFET
OUTFB
100pF
IN
×2
V
PFI
DD
R
90.9k
R
DRV
INTV
CC
FBO2
PF2
100k
CC
R1
10k
R2
R3
10k
C3
C4
0.1µF
D
B
10k
4.7µF
1N4448HWT
BST
PFO
CAPGD
SMBALERT
SCL
PFO
C
B
0.1µF
MN2
SiR426DP
CAPGD
SMBALERT
SCL
D1
DFLS240
TGATE
L1
R
SNSC
0.008Ω
4.7µH
SDA
SDA
SW
MN3
SiR426DP
C
CAP
D2
DFLS240
47µF
BGATE
VCC2P5
LTC3350
R4
100k
CAP_SLCT0
ICAP
C6
220pF
CAP_SLCT1
VCAP
CFP
C5
1µF
R
R
R
R
2.7Ω
CAP4
CAP3
CAP2
CAP1
C
C
CP5
0.1µF
GPI
VC
F
+
0.1µF
2.7Ω
2.7Ω
2.7Ω
CFN
VCAPP5
CAP4 10F
R
+
+
+
FBC1
590k
CAP3 10F
CAP2 10F
CAP1 10F
RT
R
T1
100k
CAP4
CAP3
CAP2
CAP1
T
R
FBC2
ITST
118k
C
C
R5
R6
121Ω
10nF 107k
R
2.7Ω
CAPRTN
SGND
PGND
CAPRTN
CAPFB
3350 TA05
CAP1-4: NESSCAP ESHSR-0010C0-002R7
L1: VISHAY IHLP5050FDER47MO1
Application Circuit 5. 11V to 20V, 4A Supercapacitor Charger with 2A Input Current Limit and 5V, 2A Backup Mode
R
MN1
SiR412DP
SNSI
0.016Ω
V
OUT
5V
V
IN
11V TO 20V
10W IN BACKUP
C2
MN4
SiR412DP
1µF
C1
0.1µF
C
OUT2
+
C
R
10µF
FBO1
R
C
PF1
806k
FBO1
665k
OUT1
82µF
V
INFET VOUTM5VOUTSP VOUTSN OUTFET
OUTFB
100pF
IN
×2
V
PFI
DD
R
R
DRV
INTV
CC
FBO2
210k
PF2
100k
CC
R1
10k
R2
R3
10k
C3
4.7µF
C4
0.1µF
D
B
10k
1N4448HWT
BST
PFO
CAPGD
SMBALERT
SCL
PFO
C
B
0.1µF
MN2
SiR426DP
CAPGD
SMBALERT
SCL
D1
DFLS240
TGATE
L1
R
SNSC
0.008Ω
4.7µH
SDA
SDA
SW
MN3
SiR426DP
C
CAP
D2
DFLS240
47µF
BGATE
VCC2P5
LTC3350
R4
100k
CAP_SLCT0
ICAP
C6
220pF
CAP_SLCT1
VCAP
CFP
C5
1µF
R
R
R
R
2.7Ω
CAP4
CAP3
CAP2
CAP1
C
C
CP5
0.1µF
GPI
VC
F
+
0.1µF
2.7Ω
2.7Ω
2.7Ω
CFN
VCAPP5
CAP4 10F
R
+
+
+
FBC1
590k
CAP3 10F
CAP2 10F
CAP1 10F
RT
R
T1
100k
CAP4
CAP3
CAP2
CAP1
T
R
FBC2
ITST
118k
C
C
R5
R6
121Ω
10nF 107k
R
2.7Ω
CAPRTN
SGND
PGND
CAPRTN
CAPFB
3350 TA06
CAP1-4: NESSCAP ESHSR-0010C0-002R7
L1: VISHAY IHLP5050FDER47MO1
3350fc
41
For more information www.linear.com/LTC3350
LTC3350
Typical applicaTions
Application Circuit 6. 11V to 15V, 2.3A Zeta-SEPIC High Voltage Capacitor Charger with 2A Input Current Limit and 10V, 25W Backup Mode
R
MN1
FDMC7660S
SNSI
0.016Ω
V
OUT
V
IN
11V TO 15V
10V
25W IN BACKUP
C2
1µF
C1
0.1µF
C
OUT
R
22µF
R
PF1
158k
FBO1
V
INFET VOUTM5VOUTSP VOUTSN OUTFET
OUTFB
IN
×5
768k
PFI
R
100k
R
DRV
INTV
CC
FBO2
PF2
20k
CC
V
DD
C3
4.7µF
C4
0.1µF
R1
10k
R2
10k
R3
10k
Q1
Si1555DL
L1
4.7µH
BST
PFO
CAPGD
SMBALERT
SCL
PFO
C
C
B2
4.7µF
CAPGD
SMBALERT
SCL
B
0.1µF
10µF
1Ω
TGATE
MP1
Si7415DN
SDA
SDA
L2
4.7µH
10µF
VCC2P5
SW
LTC3350
CAP
2200µF
35V
R
+
FBC3
C7
MN2
FDMC86520L
604k
FBC
BGATE
10µF
CAP_SLCT0
CAP_SLCT1
C
CFP
CFN
ICAP
×2
820pF
C5
1µF
R
CAPTOP
255k
R
GPI
VC
FBC1
C6
470pF
R
787k
SNSC
0.014Ω
R
CAPBOT
24.3k
R
FBC2
28k
VCAP
VCAPP5
RT
CAP4
CAP3
CAP2
CAP1
CAPRTN
CAPFB
ITST
C
R5
R6
C
22nF
107k 10M
SGND
PGND
3350 TA07
CAP: NICHICON UHW1V222MHD
L1, L2: COILCRAFT XAL4030-472ME
SET ctl_cap_scale TO 1
In a Zeta-SEPIC application there are several differences
in the monitoring features due to differences in how the
LTC3350isconfigured. Thecapacitorvoltageismeasured
differently, it is no longer measured in the meas_vcap
register, but in the meas_vcap1 register. The scale factor
for meas_vcap1 must be adjusted for the resistor divider
connected to the CAP1 pin. Also in this configuration
the precision current load (ITST) for the capacitance test
cannotbeused. Theloadonthecapacitorsaretheexternal
dividers only. A capacitance measurement may still be
done. The results in the meas_cap_register will have an
LSB in Farads of:
where R is the total resistance to ground in parallel with
L
the capacitor, R
is the top divider resistor from
CAPTOP
the capacitor to CAP1 and R
is the bottom divider
CAPBOT
resistor from CAP1 to ground. The above equation is for
whenthectl_cap_scalebitissettoone.ESRmeasurements
may be possible with large capacitors with larger ESR’s.
However, the accuracy of the ESR measurement in this
applicationissignificantlyreduced.TheESRmeasurement
in the meas_esr register must be scaled up by the resistor
divider ratio. The voltage at the CAP1 pin should be kept
below the V
setting.
SHUNT
The voltage at the CAP1 pin will be above the default shunt
value (2.7V) when V is greater than 31V. In order to
–5.6•10–7
RT
CAP
CLSB
=
continue charging to 35V, the shunts should be disabled
by setting vshunt to zero (0x0000).
R
⎡
⎤
⎥
⎦
⎛
⎞ ⎛
⎟ ⎜
⎞
0.2
RCAPTOP
L
In 1–
1+
⎢
⎜
⎟
V
RCAPBOT
⎝
CAP ⎠ ⎝
⎠
⎣
3350fc
42
For more information www.linear.com/LTC3350
LTC3350
Typical applicaTions
Application Circuit 7. 4.8V to 12V, 10A Supercapacitor Charger with 6.4A Input Current Limit and 5V, 30W Backup Mode
R
MN1
SiS452DN
SNSI
0.005Ω
V
OUT
V
IN
4.8V TO 12V
5V
30W IN BACKUP
C2
1µF
50µs FALLING
EDGE FILTER
C1
0.1µF
C
C
OUT1
OUT2
C
R
FBO1
R
PF1
FBO1
665k
100µF
2.2µF
V
INFET VOUTM5VOUTSP VOUTSN OUTFET
OUTFB
100pF
IN
30.1k
1M
×6
×2
V
PFI
DD
R
FBO2
210k
R
10pF
DRV
PF2
CC
10k
INTV
CC
R1
10k
R2
10k
R3
1k
C3
10µF
C4
0.1µF
D
B
MN4
Si1062X
B0540WS
BST
PFO
CAPGD
SMBALERT
SCL
PFO
C
B
0.1µF
MN2
SiS452DN
CAPGD
SMBALERT
SCL
TGATE
L1
1µH
R
SNSC
0.003Ω
SDA
SDA
SW
MN3
SiS452DN
C
CAP
47µF
BGATE
VCC2P5
LTC3350
R4
100k
CAP_SLCT0
CAP_SLCT1
ICAP
VCAP
CFP
C5
1µF
C
C
CP5
0.1µF
GPI
VC
F
0.1µF
CFN
VCAPP5
R
R
2.7Ω
CAP2
R
R
RT
CAP4
CAP3
CAP2
CAP1
T1
C
T
100k
2k
+
R
FBC1
732k
ITST
2.7Ω
2.7Ω
CAP1
CAP2 50F
C
R5
R6
C
+
4.7nF 88.7k 121Ω
R
FBC2
R
CAPRTN
CAP1 50F
SGND
PGND
274k
CAPRTN
CAPFB
3350 TA08
CAP1-2: NESSCAP ESHSR-0050C0-002R7
L1: COILCRAFT XAL7030-102ME
3350fc
43
For more information www.linear.com/LTC3350
LTC3350
package DescripTion
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
UHF Package
38-Lead Plastic QFN (5mm × 7mm)
(Reference LTC DWG # 05-08-ꢀ70ꢀ Rev C)
0.70 0.05
5.50 0.05
5.ꢀ5 0.05
4.ꢀ0 0.05
3.ꢀ5 0.05
3.00 REF
PACKAGE
OUTLINE
0.25 0.05
0.50 BSC
5.5 REF
6.ꢀ0 0.05
7.50 0.05
RECOMMENDED SOLDER PAD LAYOUT
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
PIN ꢀ NOTCH
R = 0.30 TYP OR
0.35 × 45° CHAMFER
0.75 0.05
0.00 – 0.05
3.00 REF
5.00 0.ꢀ0
37
38
0.40 0.ꢀ0
PIN ꢀ
TOP MARK
ꢀ
2
(SEE NOTE 6)
5.ꢀ5 0.ꢀ0
5.50 REF
7.00 0.ꢀ0
3.ꢀ5 0.ꢀ0
(UH) QFN REF C ꢀꢀ07
0.200 REF 0.25 0.05
0.50 BSC
R = 0.ꢀ25
TYP
R = 0.ꢀ0
TYP
BOTTOM VIEW—EXPOSED PAD
NOTE:
ꢀ. DRAWING CONFORMS TO JEDEC PACKAGE
OUTLINE M0-220 VARIATION WHKD
2. DRAWING NOT TO SCALE
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN ꢀ LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
3. ALL DIMENSIONS ARE IN MILLIMETERS
3350fc
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
44
LTC3350
revision hisTory
REV
DATE
DESCRIPTION
PAGE NUMBER
A
09/14 Modified I
equations in C
and C Capacitance section
CAP
27
28
32
42
4
RMS
OUT
Changed 5V to 6V in back-up mode under the Power MOSFET Selection section
Changed V voltage reference DAC setting
CAP
Modified Application Circuit
B
01/15 Remove V
Common Mode Range from Electrical Characteristics
CMI
Remove Conditions on I
Falling and Rising
5
PFO
Change Analog-to-Digital Converter section
Change range in the General Purpose Input section to 0V to 5V
Change MN1 to MP1 just below Figure 6
18
20
23
30
32
38
42
3
Change M1, M2 to MN1, MN2 in the PCB Layout Considerations section
Increase page numbers to all entries on the Register Map
For meas_vcap change µV to mV
Change name to Application Circuit 6
C
08/15 Modified Order Information Table for temperature grade identified by label on shipping container
Modified Input Overvoltage Protection Section
17
18
19
20
22
26
31
35
38
42
Add sentence at the end of the first paragraph
Add three sentences to the end of the Capacitance and ESR Measurements section
Replace sentence in the Limit Checking and Alarms section
Modified Figure 3
Add new supplier to Table 2, Supercapacitor Suppliers
Add Note 12 in the PCB Considerations Layout section
Change reference from R /R to R /R on cap_lo_lvl description
TST
T
T
TST
Change reference from R /R to R /R on meas_cap description
TST
T
T
TST
Change value of R
to 24.3k from 20k. Also add two sentences to the end of the text
CAPBOT
3350fc
45
For more information www.linear.com/LTC3350
LTC3350
Typical applicaTion
12V PCle Backup Controller
R
MN1
SiS438DN
SNSI
0.016Ω
V
OUT
V
IN
11V TO 20V
6V
25W IN BACKUP
C2
1µF
MN4
SiS438DN
C1
0.1µF
C
C
OUT2
OUT1
C
R
FBO1
R
PF1
FBO1
649k
47µF
2.2µF
V
INFET VOUTM5VOUTSP VOUTSN OUTFET
OUTFB
120pF
IN
806k
×2
×2
V
PFI
DD
R
R
PF2
DRV
FBO2
162k
CC
100k
INTV
CC
R1
10k
R2
10k
R3
10k
C3
4.7µF
C4
0.1µF
D
B
1N4448HWT
BST
PFO
CAPGD
SMBALERT
SCL
PFO
C
B
0.1µF
MN2
BSZ060NE2LS
CAPGD
SMBALERT
SCL
TGATE
L1
3.3µH
R
SNSC
0.006Ω
SDA
SDA
SW
MN3
BSZ060NE2LS
C
CAP
22µF
BGATE
VCC2P5
×4
LTC3350
R4
100k
CAP_SLCT0
CAP_SLCT1
ICAP
VCAP
CFP
R
R
R
R
2.7Ω
CAP4
CAP3
CAP2
CAP1
C5
1µF
C
C
CP5
0.1µF
GPI
VC
F
+
0.1µF
2.7Ω
2.7Ω
2.7Ω
CFN
VCAPP5
CAP4 10F
CAP3 10F
CAP2 10F
CAP1 10F
R
+
+
+
FBC1
866k
RT
R
T1
100k
CAP4
CAP3
CAP2
CAP1
T
R
FBC2
ITST
118k
C
C
10nF
R5
R6
71.5k 121Ω
R
2.7Ω
CAPRTN
GND
PGND
CAPRTN
CAPFB
3350 TA09
CAP1-4: NESSCAP ESHSR-0010C0-002R7
L1: COILCRAFT XAL7030-332ME
relaTeD parTs
PART NUMBER
DESCRIPTION
COMMENTS
Power Management
LTC3128
3A Monolithic Buck-Boost Supercapacitor Charger
and Balancer with Accurate Input Current Limit
2% Accurate Average Input Current Limit Programmable to 3A, Active Charge
Balancing, Charges 1 or 2 Capacitors, V Range: 1.73V to 5.5V, V
Range:
IN
OUT
1.8V to 5.5V, 20-Lead (4mm × 5mm × 0.75mm) QFN and 24-Lead TSSOP
Packages
LTC3226
LTC3355
LTC3625
LTC4110
LTC4425
2-Cell Supercapacitor Charger with Backup
PowerPath Controller
1x/2x Multimode Charge Pump Supercapacitor Charger, Automatic Cell
Balancing, PowerPath, 2A LDO Backup Supply, Automatic Main/Backup
Switchover, 2.5V to 5.5V, 16-Lead 3mm × 3mm QFN Package
20V, 1A Buck DC/DC with Integrated SCAP Charger V : 3V to 20V, V : 2.7V to 5V, 1A Main Buck Regulator, 5A Boost Backup
and Backup Regulator
IN
OUT
Regulator Powered from Single Supercapacitor, Overvoltage Protection, 20-
Lead 4mm × 4mm QFN Package.
1A High Efficiency 2-Cell Supercapacitor Charger
with Automatic Cell Balancing
High Efficiency Step-Up/Step-Down Charging of Two Series Supercapacitors.
Automatic Cell Balancing. Programmable Charging Current to 500mA (Single
Inductor), 1A (Dual Inductor). 12-Lead 3mm × 4mm DFN Package
Battery Backup System Manager
Complete Backup Battery Manager for Li-Ion/Polymer, Lead Acid, NiMH/
NiCd Batteries and Supercapacitors. Input Supply Range: 4.5V to 19V,
Programmable Charge Current Up to 3A, 38-Lead 5mm × 7mm QFN Package.
Linear SuperCap Charger with Current-Limited Ideal Constant-Current/Constant-Voltage Linear Charger for 2-Cell Series
Diode and V/I Monitor
Supercapacitor Stack. V : Li-Ion/Polymer Battery, a USB Port, or a 2.7V to
IN
5.5V Current-Limited Supply. 2A Charge Current, Automatic Cell Balancing,
Shutdown Current <2μA. 12-Pin 3mm × 3mm DFN or 12-Lead MSOP Package
3350fc
LT 0815 REV C• PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
46
(408)432-1900 FAX: (408) 434-0507 www.linear.com/LTC3350
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LINEAR TECHNOLOGY CORPORATION 2014
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