LTC3370_技术文档

LTC3372

60V Low I Buck Controller

Q

Plus 4-Channel 8A Configurable Buck DC/DCs

FEATURES

DESCRIPTION

n

HV Buck Controller: V = 4.5V to 60V, V

= 5V/3.3V

OUT

TheLTC^®3372isahighlyflexiblemultioutputpowersupply

IC. The device includes a high-performance, high voltage

(HV)step-downDC/DCswitchingregulatorcontrollerthat

drives an all N-channel synchronous power FET stage

from a 4.5V to 60V input.

IN

n

LV Buck Regulators: V

OUT1-4

= 2.25V to 5.5V,

INA-H

V

≥ 0.8V

n

8×1A LV Buck Integrated Power Stages, Configurable

as 2, 3 or 4 Output Channels

n

8 Unique Output Configurations (1A to 4A Per Channel)

The LTC3372 also includes four low voltage (LV) synchro-

nous buck regulators that can be programmed by the

C1-C3 pins to share eight 1A integrated power stages in

one of eight possible configurations. Each power stage is

poweredfromindependentinputswhichmaybeconnected

Low Total No-Load Input Supply Current (I )

Q

n

15µA HV Controller Only (5V

)

OUT

n

23μA HV Controller Only (3.3V

)

OUT

33μA HV Controller (3.3V ) Plus One LV Regulator

9μA Per Additional LV Regulator Channel

OUT

to the HV buck’s V

or to other 2.25V to 5.5V supplies.

OUT

n

1MHz to 3MHz Operation (HV Runs at 1/6 Frequency)

Programmable or Synchronizable to External Clock

Programmable Watchdog and Power-On Reset Delay

IC Die Temperature Monitor Output

The CT pin programs timing parameters of the watchdog

timer and LV outputs’ Power-On Reset (RST). Precision

enable thresholds facilitate reliable power-up sequencing.

Thermally Enhanced 48-Pin 7mm × 7mm QFN Package

The LTC3372 is available in a 48-pin 7mm × 7mm

QFN package.

APPLICATIONS

All registered trademarks and trademarks are the property of their respective owners.

n

Automotive and Industrial Always-On Systems

General Purpose Multi-Channel Power Supplies

n

LV Efficiency vs Output Current

TYPICAL APPLICATION

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5mΩ

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Low Voltage Buck Regulator Configurations

C3 C2 C1 BUCK1 BUCK2 BUCK3 BUCK4

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0

1

0

1

0

1

0

1

0

1

0

1

0

1

2A

3A

4A

3A

4A

2A

1A

2A

–

2A

1A

–

2A

1A

–

2A

3A

2A

3A

2A

3A

4A

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ꢀA

ꢀꢁꢂ

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Rꢀ

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Rꢀꢁꢂ

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–

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A

RR

ꢀꢀꢁꢂ ꢃAꢄꢅꢆ

RR

R

Rev. A

1

Document Feedback

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LTC3372

TABLE OF CONTENTS

Features............................................................................................................................ 1

Applications ....................................................................................................................... 1

Typical Application ............................................................................................................... 1

Description......................................................................................................................... 1

Absolute Maximum Ratings..................................................................................................... 3

Order Information................................................................................................................. 4

Electrical Characteristics........................................................................................................ 4

Typical Performance Characteristics .......................................................................................... 8

Pin Functions.....................................................................................................................14

Block Diagram....................................................................................................................17

Operation..........................................................................................................................18

Low Voltage Regulators........................................................................................................................................ 20

Applications Information .......................................................................................................23

High Voltage Buck Controller................................................................................................................................ 23

Low Voltage Buck Regulators............................................................................................................................... 33

Printed Circuit Board PCB Layout Considerations................................................................................................. 35

Typical Applications.............................................................................................................37

Package Description ............................................................................................................42

Revision History .................................................................................................................43

Typical Application ..............................................................................................................44

Related Parts.....................................................................................................................44

Rev. A

2

For more information www.analog.com

LTC3372

ABSOLUTE MAXIMUM RATINGS ^{(Note 1)}

Input Supply (V ) Voltage......................... –0.3V to 65V

TG, BG ............................................................. (Note 11)

IN

Topside Driver (BOOST) Voltage.................–0.3V to 71V

Switch (SW) Voltage..................................... –5V to 65V

(BOOST-SW) Voltage................................... –0.3V to 6V

RUN Voltage............................................... –0.3V to 65V

ITH, V

, CT,

OUTPRG

TEMP Voltages........................–0.3V to (INTV + 0.3V)

CC

I

, I

................................................................5mA

RST WDO

Operating Junction Temperature Range

+

–

TRACK/SS, V /EXTV , SENSE , SENSE , PGOOD,

(Notes 2, 3)............................................ –40°C to 150°C

Storage Temperature Range .................. –65°C to 150°C

OUT

CC

RT, PLL/MODE, FB1-4, EN1-4, C1-3, WDI,

WDO, RST, V Voltages.......................... –0.3V to 6V

INA-H

PIN CONFIGURATION

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RST

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ꢝ

ꢥ

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ꢞ

ꢦ

ꢓ

ꢏ

ꢈ

ꢢꢦ ꢤꢉ

ꢢꢞ ꢄꢊꢀꢃ

ꢢꢇ ꢅꢊꢇ

ꢢꢢ ꢘꢤꢇ

ꢎꢎ

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ꢢꢝ ꢖꢆꢧ

ꢢꢟ ꢖꢆꢉ

ꢇꢈ

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ꢥꢏ ꢃ

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ꢝꢥ

ꢥꢞ ꢃ

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ꢇꢏꢐꢑꢅAꢋ ꢒꢓꢔꢔ × ꢓꢔꢔꢕ ꢂꢑAꢖꢀꢄꢎ ꢗꢘꢊ

ꢀ

ꢜ ꢝꢞꢟꢠꢎꢡ θ ꢜ ꢢꢇꢠꢎꢣꢆ

ꢙA

ꢙꢚAꢛ

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Rev. A

3

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LTC3372

ORDER INFORMATION

LEAD FREE FINISH

LTC3372EUK#PBF

LTC3372IUK#PBF

LTC3372HUK#PBF

TAPE AND REEL

PART MARKING*

LTC3372UK

PACKAGE DESCRIPTION

TEMPERATURE RANGE

–40°C to 125°C

LTC3372EUK#TRPBF

LTC3372IUK#TRPBF

LTC3372HUK#TRPBF

48-Lead (7mm × 7mm) Plastic QFN

LTC3372UK

–40°C to 125°C

LTC3372UK

–40°C to 150°C

Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the specified operating

junction temperature range, otherwise specifications are at T_A= 25°C (Note 2), V_IN= 12V, V_RUN= 5V, V_OUT= V_INA-H= 3.3V unless

otherwise noted.

SYMBOL

PARAMETER

Pin Operating Voltage Range

CONDITIONS

MIN

TYP

MAX UNITS

V

4.5

60

V

IN

I (Forced

No-Load V Pin DC Current

PLL/MODE =INTV or INTV /2

V

OUTPRG

=

7

µA

Q

IN

CC

–

Continuous/ No-Load V /EXTV Pin + SENSE Pin

Run = V

INTV

1450

OUT

DC Current

CC

IN

CC

Pulse-

Skipping

Mode)

EN1-4 = GND

(5V V

)

OUT

No-Load V Pin DC Current

V

=

1300

130

µA

IN

OUTPRG

–

No-Load V /EXTV Pin + SENSE Pin

GND

OUT

DC Current

CC

(3.3V V

)

OUT

l

I (Burst

No-Load V Pin DC Current

PLL/MODE = GND

(Burst Mode)

V

OUTPRG

=

)

4

10

µA

Q

IN

Mode)

No-Load V /EXTV Pin DC Current

INTV

OUT

CC

HV Controller On Only

(5V V

20

52

46

74

+39

+12

µA

OUT

HV Controller and One LV Regulator On

V

= 12V, V

= V

(LV

OUT

IN

INA-H

Additional I , per LV Regulator On

+26

+7

Q

Regulators Powered from HV

Additional I , Watchdog On (Float CT Pin)

Q

Regulator’s Output), No Load on

V

Additional I , TEMP On (Float TEMP Pin)

+15

0.5

Q

or V

.

OUT

OUT1-4

–

l

No-Load SENSE Pin DC Current

2

No-Load V Pin DC Current

V

=

IN

OUTPRG

CT = TEMP = INTV (Watchdog

and TEMP Monitor Off, Unless

Otherwise Specified)

CC

HV Controller On Only

GND

22

23

+1

+2

42

33

+4.2

µA

HV Controller and LV Regulator On

(3.3V V

)

OUT

Additional I , Watchdog On (Float CT Pin)

Q

Additional I , TEMP On (Float TEMP Pin)

Q

No-Load V /EXTV Pin DC Current

OUT

CC

l

HV Controller On Only

4

29

8.5

39

+33

+8

µA

HV Controller and One LV Regulator On

Additional I , per LV Regulator On

+23

+6

Q

Additional I , Watchdog On (Float CT Pin)

Q

Additional I , TEMP On (Float TEMP Pin)

+13

Q

I

Total No-Load Input Supply Current

HV Controller On Only

PLL/MODE = GND

V

=

)

Q

OUTPRG

(Note 4)

(Burst

INTV

15

31

35

45

+20

+6

µA

CC

HV Controller and One LV Regulator On

V

= 12V, V

= V

(LV

(5V V

OUT

IN

INA-H

OUT

Mode)

Additional I , per LV Regulator On

Regulators Powered from HV

+14

+4

Q

Additional I , Watchdog On (Float CT Pin) Regulator’s Output), No Load on

Q

Additional I , TEMP On (Float TEMP Pin)

V

or V

OUT1-4

+8

Q

OUT

Total No-Load Input Supply Current

HV Controller On Only

V

=

OUTPRG

GND

23

33

+9

+3

+7

46

+12

+7

µA

CT = TEMP = INTV (Watchdog

and TEMP Monitor Off, unless

otherwise specified)

CC

HV Controller and One LV Regulator On

(3.3V V

)

OUT

Additional I , per LV Regulator On

Q

Additional I , Watchdog On (Float CT Pin)

Q

Additional I , TEMP On (Float TEMP Pin)

Q

I

V

Pin Current in Shutdown

IN

RUN = EN1-4 = GND

3.5

8

μA

SD

Rev. A

4

For more information www.analog.com

LTC3372

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the specified operating

junction temperature range, otherwise specifications are at T_A= 25°C (Note 2), V_IN= 12V, V_RUN= 5V, V_OUT= V_INA-H= 3.3V unless

otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX UNITS

High Voltage Buck Controller

V

Regulated Output Voltage

(Note 5) I = 0.7V to 2V

OUT

TH

l

V

= INTV

V = 6V to 60V

4.875

3.217

5.000 5.125

3.300 3.383

V

OUTPRG

CC, IN

IN

= GND, V = 4.5V to 60V

RUN Pin Controller Enable Threshold

RUN Pin Voltage Rising

Hysteresis

1.17

1.22

50

1.27

V

mV

RUN

I

RUN Pin Pull-Up Current

RUN = 0V

0.5

2

μA

mS

μA

mV

%

RUN

g

Error Amplifier Transconductance

Soft-Start Charge Current

(Note 5) ITH = 1.2V, Sink/Source 5μA

TRACK/SS = 0V

m

I

7

10

14

1

TRACK/SS

+

SENSE Pin Current

SENSE

–

l

V

Maximum Current Sense Threshold

Maximum Duty Cycle In Dropout

SENSE = 3.3V

68

75

98

82

SENSE(MAX)

D

R

RT

= 400k

97.5

MAX(HV)

TG

Top Gate Pull-Up On-Resistance

Top Gate Pull-Down On-Resistance

2.3

1.5

Ω

BG

Bottom Gate Pull-Up On-Resistance

Bottom Gate Pull-Down On-Resistance

2.4

1.1

Ω

t

Delay Time, Top Gate Off to Bottom Gate On (Note 6)

Delay Time, Bottom Gate Off to Top Gate On (Note 6)

40

18

60

0.2

ns

D(TG/BG)

D(BG/TG)

ON(MIN)

Minimum On-Time (Top Gate)

(Note 7)

PGOOD

PGOOD Pin Voltage When Low

PGOOD Pin Leakage Current When High

I

= 2mA

0.4

1

V

μA

PGOOD

PGOOD = 5V

UV

V

/EXTV Pin Undervoltage Threshold

Falling, Relative to Regulated V

Hysteresis

–5

+5

–7.5

2.5

–10

%

OUT

CC

OUT

OV

/EXTV Pin Overvoltage Threshold

Rising, Relative to Regulated V

Hysteresis

+7.5

2.5

+10

%

CC

–

SENSE Pin Overvoltage Threshold

Rising, Relative to Regulated V

Hysteresis

+15

2.5

%

t

PGOOD Delay for Reporting OV/UV Fault

PGOOD High to Low

40

μs

PGOOD

INTV

No Load Internal V Regulated Voltage

6V < V < 60V

INTVCC

V

= 3.3V

= 5V

4.9

5.1

–1

5.3

–2

V

CC

IN

OUT

INTV Voltage Load Regulation

I

= 0mA to 50mA

%

CC

5

–2.5

V

Ω

No Load Internal V Voltage

CC

Source Resistance

I

= 0mA to 50mA

INTVCC

V

Threshold for INTV Switchover from

OUT

V Rising

OUT

4.5

3.6

4.7

4.9

V

OUT

IN

CC

to V

Hysteresis

0.25

l

Undervoltage Lockout (UVLO) Threshold on INTV Voltage Rising

INTV

4.0

3.8

4.25

4.0

V

CC

INTV Voltage Falling

CC

Internal Bias Start Up Time

Oscillator and Phase-Locked Loop

V

OUT

= 0V

1.2

ms

f

Frequency of Internal Oscillator

(LV Regulators’ Switching Frequency)

V

= INTV

1.9

1.75

1.85

2

2.1

2.25

2.15

MHz

OSC

RT

CC

l

R

= 400k

f

HV Controller Switching Frequency

Synchronization Frequency Range

1/6•f

kHz

SW

OSC

l

t , t > 60ns

LOW HIGH

1

3

MHz

PLL/MODE

l

V

PLL/MODE Level High

PLL/MODE Level Low

For Synchronization

1.3

V

PLL/MODE

0.25

825

l

V

RT Servo Voltage

R

RT

= 400k

770

800

mV

RT

Rev. A

5

For more information www.analog.com

LTC3372

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the specified operating

junction temperature range, otherwise specifications are at T_A= 25°C (Note 2), V_IN= 12V, V_RUN= 5V, V_OUT= V_INA-H= 3.3V unless

otherwise noted.

SYMBOL

Temperature Monitor

TEMP Voltage at 25°C

PARAMETER

CONDITIONS

MIN

TYP

MAX UNITS

V

200

220

7

240

mV

mV/°C

°C

TEMP(ROOM)

∆V

OT

/°C

TEMP

V

Slope

TEMP

Overtemperature Shutdown

Overtemperature Hysteresis

170

10

OT Hyst

°C

Low Voltage (LV) Buck Regulators

l

V

Input Operating Voltage

2.25

0.8

5.5

V

INA-H

Regulated Output Voltage Set Point

Undervoltage Lockout Threshold on V

V

INA-H

OUT1-4

l

UVLO

V

Falling

Rising

1.95

2.05

2.15

2.25

V

INA-H

I

Quiescent Current into V

Pins, Per

Burst Mode, FB1-4 = 0.82V

Forced Continuous Mode, FB1-4 = 0V

25

35

µA

Q(VINA-H)

INA-H

Enabled LV Regulator (Note 8)

400

550

Shutdown Current into V

Pins

INA-H

0

1

µA

mV

SD(VINA-H)

l

V

Regulated Feedback Voltage for Regulator 1

792

780

800

808

820

FB1

Regulated Feedback Voltage for Regulators

2-4

FB2-4

I

Feedback Leakage Current

Maximum Duty Cycle

PMOS On-Resistance

NMOS On-Resistance

PMOS Leakage Current

NMOS Leakage Current

Soft-Start Time

FB1-4 = 0.85V

FB1-4 = 0V

–50

100

50

nA

%

FB1-4

l

D

R

MAX

PMOS

NMOS

LEAKP

LEAKN

SS

I

SW

I

SW

= 100mA, 1A – Per Power Stage

= –100mA, 1A – Per Power Stage

290

180

mΩ

µA

I

t

EN1-4 = GND

(Note 10)

–1

1

µA

0.25

–4

1.5

3

ms

l

UV

Rising Undervoltage RST Threshold

Regulator 1

% Relative to Regulated V

Hysteresis

–2

1

–1

%

FB

Rising RST Undervoltage Threshold

Regulators 2-4

% Relative to Regulated V

Hysteresis

–7

+5

–5

1

–3

+10

2.2

%

OV

RST Overvoltage Threshold of Regulators

1-4

% Relative to Regulated V

Hysteresis

+7.5

–3

%

I

PMOS Current Limit

1 Buck with 1 Power Stage (Note 9)

1 Buck with 2 Power Stages (Note 9)

1 Buck with 3 Power Stages (Note 9)

1 Buck with 4 Power Stages (Note 9)

1.4

1.8

3.6

5.4

7.2

A

LIM

Interface Logic Pins (RST, WDO, WDI, CT, C1, C2, C3)

I

Output High Leakage Current

Output Low Voltage

RST, WDO 5.5V at Pin

RST, WDO 3mA at Pin

1

µA

V

OH

V

0.1

0.4

OL

IH

l

WDI Input High Threshold

CT, C1, C2, C3 Input High Threshold

WDI, C1, C2, C3 Input Low Threshold

WDI Pulse Width

1.2

V

INTV – 0.4

V

CC

V

0.4

V

IL

t

80

ns

WDI(WIDTH)

Rev. A

6

For more information www.analog.com

LTC3372

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the specified operating

junction temperature range, otherwise specifications are at T_A= 25°C (Note 2), V_IN= 12V, V_RUN= 5V, V_OUT= V_INA-H= 3.3V unless

otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX UNITS

Interface Logic Pins (EN1, EN2, EN3, EN4)

l

V

Enable Rising Threshold

Enable Falling Threshold

Enable Pin Leakage Current

All LV Regulators Disabled

400

380

290

730

400

315

1200

420

340

1

mV

µA

EN

At Least One LV Regulator Enabled

I

EN = 3.3V

EN

CT Timing Parameters; C = 10nF

T

t

Time from WDO Low Until Next WDO Low

Time from Last WDI Until Next WDO Low

WDO Low Time Absent a Transition at WDI

RST Assertion Delay

C = 10nF

9.7

1.22

160

38

12.9

1.62

202

16.1

2.03

280

63

s

WDIO

WDI

T

C = 10nF

T

C = 10nF

T

ms

WDO

RST

C = 10nF

T

202

Watchdog Lower Boundary

C = 10nF

T

50.6

WDL

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 4: The I (Total Input Supply Quiescent Current) is the total average

current drawn from the input power supply by a typical application in Burst

Q

Mode with no load currents (from either the HV Controller V

or the LV

OUT

Regulators’ V

).

OUT1-4

Note 2: The LTC3372 is tested under pulsed load conditions such that

Note 5: The HV Controller’s output regulation is tested in a feedback loop

that servos the ITH pin to a specified voltage and measures the resulted

T ≈ T . The LTC3372E is guaranteed to meet specifications from 0°C

J

A

to 85°C operating junction temperature. Specifications over the –40°C

to 125°C operating junction temperature range are assured by design,

characterization and correlation with statistical process controls. The

LTC3372I is guaranteed over the –40°C to 125°C operating junction

temperature range. The LTC3372H is guaranteed over the –40°C to 150°C

operating junction temperature range. High junction temperatures degrade

operating lifetimes; operating lifetime is derated for junction temperatures

greater than 125°C. Note that the maximum ambient temperature

consistent with these specifications is determined by specific operating

conditions in conjunction with board layout, the rated package thermal

voltage at V /EXTV pin.

Note 6: Delays are measured using 50% levels, with TG and BG driving

minimum capacitive load.

Note 7: The minimum on-time conditions is specified for an inductor

peak-to-peak ripple current ≥40% of I

Considerations in the Applications Information section).

OUT CC

(see Minimum On-Time

MAX

Note 8: The I (Quiescent Current into V Pins) are measured

Q(VINA-H)

INA-H

with power switches not switching. Dynamic supply current when

switching may be higher due to the gate charge being delivered.

Note 9: The current limit features are intended to protect the IC from short

term or intermittent fault conditions. Continuous operation above the

maximum specified pin current rating may result in device degradation

over time.

Note 10: The soft-start is the time from the first top switch turn on,

after an enable rising, until the feedback has reached 90% of its nominal

regulation voltage.

Note 11: Do not apply a voltage or current source to these pins. They

must be connected to the gates of the external power MOSFETs, otherwise

permanent damage may occur.

impedance and other environmental factors. The junction temperature (T

J

in °C) is calculated from the ambient temperature (T in °C) and power

A

dissipation (P in Watts) according to the formula:

D

T = T + (P • θ )

JA

J

A

D

where θ (in °C/W) is the package thermal impedance.

JA

Note 3: This IC includes overtemperature protection which protects the

device during momentary overload conditions. Junction temperatures

will exceed 150°C when overtemperature protection is active. Continuous

operation above the specified maximum operating junction temperature

may impair device reliability.

Rev. A

7

For more information www.analog.com

LTC3372

TYPICAL PERFORMANCE CHARACTERISTICS

(HV Controller) T_A= 25°C, unless otherwise noted.

Efficiency and Power Loss

vs Output Current

Efficiency and Power Loss

vs Output Current

ꢀꢁꢁ

ꢀꢁ

ꢀ

ꢀꢁꢁꢁꢁ

ꢀꢁꢁꢁ

ꢀꢁꢁ

ꢀꢁ

ꢀꢁꢁ

ꢀꢁ

ꢀ

ꢀꢁꢁꢁꢁ

ꢀꢁꢁꢁ

ꢀꢁꢁ

ꢀꢁ

ꢀ

ꢀ ꢁꢂꢃ

ꢀꢁꢂ

ꢀ

ꢀ ꢁꢂꢃ

ꢀꢁꢂ

ꢀꢁ

ꢀꢁRꢂꢃ ꢄꢅꢅꢆꢇꢆꢄꢈꢇꢉ

ꢀ ꢁꢂ

ꢀ ꢁ.ꢁꢂ

ꢀꢁꢂ ꢃꢄꢅꢅ

ꢀꢁꢂꢃꢄꢅꢃꢆꢇꢀꢀꢇꢈꢉ

ꢀꢁꢂꢂ

ꢀꢁꢂꢃꢄꢅꢃꢆꢇꢀꢀꢇꢈꢉ

ꢀꢁꢂꢂ

ꢀꢁRꢂꢃ ꢄꢅꢂꢂ

ꢀꢁꢂꢃꢄꢅꢃꢆꢇꢀꢀꢇꢈꢉ

ꢀꢁꢁꢂꢃꢂꢀꢄꢃꢅ

ꢀꢁꢂꢃꢄꢅꢃꢆꢇꢀꢀꢇꢈꢉ

ꢀꢁꢁꢂꢃꢂꢀꢄꢃꢅ

ꢀ

ꢀꢁꢂ ꢃꢀꢀꢄꢁꢄꢃꢅꢁꢆ

ꢀ.ꢀꢁ ꢀ.ꢁ

ꢀꢁꢂ ꢃꢀꢀꢄꢁꢄꢃꢅꢁꢆ

ꢀ.ꢁ

ꢀꢁꢂꢃꢁꢂ ꢄꢁRRꢅꢆꢂ ꢇAꢈ

ꢀ.ꢁ

ꢀ.ꢀꢀꢀꢁ ꢀ.ꢀꢀꢁ

ꢀ.ꢀꢁ

ꢀ

ꢀꢁ

ꢀ.ꢀꢀꢀꢁ ꢀ.ꢀꢀꢁ

ꢀꢁꢂꢃꢁꢂ ꢄꢁRRꢅꢆꢂ ꢇAꢈ

ꢀ

ꢀꢁ

ꢀꢀꢁꢂ ꢃꢄꢅ

ꢀꢀꢁꢂ ꢃꢄꢂ

Burst Mode Quiescent Current

vs V_IN

Burst Mode Quiescent Current

vs Temperature

Efficiency vs V_IN

ꢀꢁꢁ

ꢀꢁ

ꢀꢀ

ꢀꢁ

ꢀ

ꢀ ꢁꢂꢃ

ꢀꢁ

ꢀꢁ ꢂꢃꢄꢅ

ꢀ

ꢀ ꢁ.ꢁꢂ

ꢀꢁꢂ

ꢀꢁ

ꢀ

ꢀꢁ ꢂꢃꢄꢅ

ꢀꢁꢂꢃꢄꢁ

ꢀꢁ ꢂꢃꢄꢅ

ꢀꢁꢂꢃꢄꢁ

ꢀꢁ ꢂꢃꢄꢅ

ꢀꢁꢂꢃꢄꢁ

ꢀ

ꢀ ꢁꢂ

ꢀꢁꢂ

ꢀ

ꢀ ꢁ.ꢁꢂ

ꢀꢁꢂ

ꢀ

ꢀ ꢁꢂ

ꢀꢁꢂ

ꢀ

ꢀ ꢁ.ꢁꢂ

ꢀꢁꢂ

ꢀ

ꢀ ꢁꢁꢁꢂꢃꢄ

ꢀꢁAꢂ

ꢀꢁ

ꢀ

ꢀꢁꢂ

ꢀ ꢁꢂ

ꢀ ꢁA

ꢀ

ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢀ ꢀꢁ

ꢀ

ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢀ ꢀꢁ

ꢀꢁꢂ ꢀꢁꢂ ꢀꢁꢂ

ꢀ

ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁꢁ ꢀꢁꢂ ꢀꢁꢂ

ꢀꢁꢂꢃꢄ ꢅꢆꢇꢄAꢈꢉ ꢊꢅꢋ

ꢀꢁꢂꢃꢁRAꢀꢄRꢁ ꢅꢆꢇꢈ

ꢀꢀꢁꢂ ꢃꢄꢀ

ꢀꢀꢁꢂ ꢃꢄꢅ

Output Voltage vs Temperature

Forced Continuous Mode

Shutdown Current vs V_IN

Shutdown Current vs Temperature

ꢀ.ꢁꢂ

ꢀ.ꢁꢁ

ꢀ.ꢁꢂ

ꢀ.ꢀꢁ

ꢀ.ꢁꢂ

ꢀꢁ

ꢀ

ꢀ.ꢁꢂ

ꢀ.ꢀꢁ

ꢀ.ꢁꢂ

ꢀ.ꢁꢀ

ꢀ.ꢁꢁ

ꢀ.ꢁꢂ

ꢀ

ꢀ ꢁꢂꢃ

ꢀ

ꢀꢁAꢂ

ꢀ ꢁꢂꢃ

ꢀꢁ

ꢀ

ꢀ ꢁꢂꢂꢃA

ꢀ

ꢀ ꢁꢂ

ꢀꢁꢂ

ꢀ

ꢀ ꢁ.ꢁꢂ

ꢀꢁꢂ

ꢀ

ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢀ ꢀꢁ

ꢀꢁꢂ ꢀꢁꢂ ꢀꢁꢂ

ꢀ

ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁꢁ ꢀꢁꢂ ꢀꢁꢂ

ꢀꢁꢂ ꢀꢁꢂ ꢀꢁꢂ

ꢀ

ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁꢁ ꢀꢁꢂ ꢀꢁꢂ

ꢀꢁꢂꢃꢄ ꢅꢆꢇꢄAꢈꢉ ꢊꢅꢋ

ꢀꢁꢂꢃꢁRAꢀꢄRꢁ ꢅꢆꢇꢈ

ꢀꢀꢁꢂ ꢃꢄꢅ

ꢀꢀꢁꢂ ꢃꢄꢁ

ꢀꢀꢁꢂ ꢃꢄꢅ

Rev. A

8

For more information www.analog.com

LTC3372

TYPICAL PERFORMANCE CHARACTERISTICS

(HV Controller) T_A= 25°C, unless otherwise noted.

Output Voltage Line Regulation

Forced Continuous Mode

Maximum Current Sense

Threshold vs Duty Cycle

ꢀ.ꢀꢁꢂ

ꢀ.ꢁꢂꢁ

ꢀ.ꢁꢁꢂ

ꢀ.ꢁꢁꢀ

ꢀ.ꢁꢁꢂ

ꢀꢁ

ꢀꢀ

ꢀꢁ

ꢀ

ꢀ ꢁꢂ

ꢀꢁꢂ

ꢀ

ꢀ ꢁ.ꢁꢂ

ꢀꢁꢂ

ꢀ

ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢀ ꢀꢁ

ꢀ

ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁꢁ

ꢀꢁꢂꢃꢄ ꢅꢆꢇꢄAꢈꢉ ꢊꢅꢋ

ꢀꢁꢂꢃ ꢄꢃꢄꢅꢆ ꢇꢈꢉ

ꢀꢀꢁꢂ ꢃꢄꢅ

Maximum Current Sense Voltage

vs I_THVoltage

INTV_CCVoltage vs Gate Charge

Current V_OUT= 3.3V

SENSE^–Pin Input Bias Current

ꢀꢁꢁ

ꢀ

ꢀꢁ

ꢀ.ꢁꢀ

ꢀ.ꢁꢁ

ꢀ.ꢁꢂ

ꢀ.ꢁꢁ

ꢀ.ꢁꢂ

ꢀꢁRꢂꢃꢄ ꢂꢁꢅꢆꢇꢅꢈꢁꢈꢉ ꢊꢁꢄꢃ

ꢀ

ꢀ ꢁꢂꢃ

ꢀꢁ

ꢀ

ꢀ ꢁꢂꢃ

ꢀꢁꢂ

ꢀꢁ

ꢀ

ꢀꢁ

ꢀ ꢁꢂ

ꢀꢁ ꢀꢁꢂꢃꢄꢅꢃꢆꢇꢀꢀꢇꢈꢉ ꢊꢋꢌꢄ

ꢀꢁꢂꢃꢄ ꢅꢆꢇe

ꢈꢉꢊRAꢋꢌꢈꢍ

ꢀꢁ

ꢀ

ꢀ ꢁ.ꢂꢃ

ꢀꢁ

ꢀ

ꢀꢁꢂ

ꢀꢁRꢂꢃꢄ ꢂꢁꢅꢆꢇꢅꢈꢁꢈꢉ ꢊꢁꢄꢃ

ꢀꢁꢂꢂ

ꢀꢁꢂ

ꢀ

ꢀ.ꢀ ꢀ.ꢁ ꢀ.ꢁ ꢀ.ꢁ ꢀ.ꢁ ꢀ.ꢁ ꢀ.ꢁ ꢀ.ꢁ ꢀ.ꢁ ꢀ.ꢁ

ꢀ

ꢀ.ꢁ ꢀ.ꢁ ꢀ.ꢁ ꢀ.ꢁ ꢀ.ꢁ ꢀ.ꢁ ꢀ.ꢁ

ꢀ

ꢀꢁ

ꢀ

ꢀꢁꢂ

ꢀAꢁꢂ ꢃꢄARꢀꢂ ꢃꢅRRꢂꢆꢁ ꢇꢈAꢉ

ꢀꢁꢂ

ꢀꢁꢂꢀꢁ ꢀꢁꢂꢃAꢄꢅ ꢆꢀꢇ

ꢀꢀꢁꢂ ꢃꢄꢂ

ꢀꢀꢁꢂ ꢃꢄꢄ

ꢀꢀꢁꢂ ꢃꢄꢀ

INTV_CCVoltage vs Gate Charge

Current V_OUT= 5V

INTV_CCLine Regulation in

Dropout

Current Limit in Foldback

ꢀ.ꢁꢀ

ꢀ.ꢁꢂ

ꢀ.ꢁꢀ

ꢀ.ꢁꢂ

ꢀ.ꢁꢀ

ꢀ.ꢁꢁ

ꢀ.ꢁꢂ

ꢀꢁ

ꢀ.ꢀꢁ

ꢀ.ꢁꢀ

ꢀ.ꢁꢁ

ꢀ.ꢁꢂ

ꢀ.ꢁꢁ

ꢀ

ꢀ ꢁ.ꢁꢂ

ꢀꢁꢂ

ꢀAꢁꢂ ꢃꢄARꢀꢂ ꢃꢅRRꢂꢆꢁ ꢇ ꢈꢉꢊA

ꢀ

ꢀꢁ

ꢀ

ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁꢁ

ꢀꢁ RꢂꢃꢄꢅAꢀꢂꢆ ꢇꢁꢅꢀAꢃꢂ RAꢀꢈꢁ ꢉꢊꢋ

ꢀ.ꢁꢂ ꢀ.ꢁꢂ ꢀ.ꢁꢁ ꢀ.ꢁꢀ ꢀ.ꢀꢁ ꢀ.ꢁꢀ ꢀ.ꢁꢁ ꢀ.ꢁꢂ ꢀ.ꢁꢂ

ꢀAꢁꢂ ꢃꢄARꢀꢂ ꢃꢅRRꢂꢆꢁ ꢇꢈAꢉ

ꢀ

ꢀꢁꢂꢃꢄ ꢅꢆꢇꢄAꢈꢉ ꢊꢅꢋ

ꢀꢁꢂ

ꢀꢀꢁꢂ ꢃꢄꢅ

Rev. A

9

For more information www.analog.com

LTC3372

TYPICAL PERFORMANCE CHARACTERISTICS

(HV Controller) T_A= 25°C, unless otherwise noted.

TRACK/SS Pull-Up Current

vs Temperature

Shutdown (RUN) Threshold

vs Temperature

Undervoltage Lockout Threshold

vs Temperature

ꢀꢁ.ꢂ

ꢀꢀ.ꢁ

ꢀꢁ.ꢂ

ꢀꢁ.ꢁ

ꢀ.ꢁ

ꢀ.ꢁꢂ

ꢀ.ꢁꢁ

ꢀ.ꢁꢂ

ꢀ.ꢁꢂꢂ

ꢀ.ꢁꢂꢃ

ꢀ.ꢁꢁꢂ

ꢀ.ꢁꢂꢂ

ꢀ.ꢀꢁꢂ

ꢀ.ꢀꢁꢁ

ꢀ

ꢀꢁ

ꢀ ꢁꢂ

ꢀ

ꢀꢁ

ꢀ ꢁꢂꢃ

Rꢀꢁꢀꢂꢃ

ꢀAꢁꢁꢂꢃꢄ

ꢀ.ꢁ

ꢀAꢁꢁꢂꢃꢄ

ꢀ.ꢁ

ꢀꢁꢂ ꢀꢁꢂ ꢀꢁꢂ

ꢀ

ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁꢁ ꢀꢁꢂ ꢀꢁꢂ

ꢀꢁꢂ ꢀꢁꢂ ꢀꢁꢂ

ꢀ

ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁꢁ ꢀꢁꢂ ꢀꢁꢂ

ꢀꢁꢂ ꢀꢁꢂ ꢀꢁꢂ

ꢀ

ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁꢁ ꢀꢁꢂ ꢀꢁꢂ

ꢀꢁꢂꢃꢁRAꢀꢄRꢁ ꢅꢆꢇꢈ

ꢀꢀꢁꢂ ꢃꢄꢁ

ꢀꢀꢁꢂ ꢃꢄꢅ

Load Step Forced Continuous

Mode

Load Step Burst Mode Operation

Load Step Pulse-Skipping Mode

ꢀ

ꢀꢁAꢂ

ꢀ

ꢀꢁAꢂ

ꢀ

ꢀꢁAꢂ

ꢀAꢁꢂꢃꢄ

ꢀ

ꢀꢁꢂ

ꢀ

ꢀꢁꢂ

ꢀAꢁꢂꢃꢄ

ꢀ

ꢀꢁꢂ

ꢀ

ꢀꢁꢂ

Aꢀꢁꢀꢂꢃꢄꢅꢆꢇ

ꢀꢁꢁꢂꢃꢄꢅꢆꢃ

ꢀꢀꢁꢂ ꢃꢂꢄ

ꢀꢀꢁꢂ ꢃꢂꢂ

ꢀꢁꢁꢂꢃꢄꢅꢆꢇ

ꢀ

ꢀ ꢁꢂꢃ

ꢀꢁꢂ

ꢀꢁ

ꢀ

ꢀ ꢁꢂꢃ

ꢀ

ꢀ ꢁꢂꢃ

ꢀꢁ

ꢀꢁꢂ

ꢀꢁ

ꢀꢁꢂ

ꢀ

ꢀ ꢁ.ꢁꢂ

ꢀ ꢁꢂꢂꢃA ꢄꢅ ꢆA

ꢀ ꢁ.ꢁꢂ

ꢀ

ꢀ ꢁꢂꢂꢃA ꢄꢅ ꢆA

ꢀꢁAꢂ

ꢀ ꢁꢂꢂꢃA ꢄꢅ ꢆA

ꢀꢁAꢂ

Inductor Current at Light Load

Soft Start-Up

ꢀꢁRꢂꢃꢄ

ꢂꢁꢅꢆꢇꢅꢈꢁꢈꢉ

ꢊAꢋꢄꢇꢌ

ꢀ

ꢀꢁ

ꢀꢁꢂꢃꢄꢁ

ꢀꢁRꢂꢃ

ꢄAꢅꢆꢇꢈ

ꢀ

ꢀꢁꢂ

ꢀ ꢁꢂ

ꢀꢁꢂꢃꢄꢅ

ꢃꢆꢇꢀꢀꢇꢈꢉ

ꢊAꢋꢌꢇꢍ

ꢀ

ꢀꢁꢂ

ꢀ ꢁ.ꢁꢂ

ꢀ

ꢀꢁꢂ

ꢀꢁꢂꢃꢄꢁ

ꢀꢀꢁꢂ ꢃꢂꢀ

ꢀꢀꢁꢂ ꢃꢂꢄ

ꢀꢁꢂꢃꢄꢅꢆ

ꢀ

ꢀ ꢁꢂꢃ

ꢀꢁ

ꢀ

ꢀ ꢁ.ꢁꢂ

ꢀꢁꢂ

ꢀ

ꢀ ꢁꢂꢂꢃA

ꢀꢁAꢂ

Rev. A

10

For more information www.analog.com

LTC3372

TYPICAL PERFORMANCE CHARACTERISTICS

(LV Buck Regulator) T_A= 25°C, unless otherwise noted.

2A Buck Efficiency and Power

Loss vs Output Current

2A Buck Efficiency

vs V_INBurst Mode

vs V_INForced Continuous Mode

ꢀꢁꢁ

ꢀꢁ

ꢀꢁꢁ

ꢀꢁ

ꢀ

ꢀꢁꢁꢁꢁ

ꢀꢁꢁꢁ

ꢀꢁꢁ

ꢀꢁ

ꢀꢁꢁ

ꢀꢁ

ꢀ

ꢀꢁRꢂꢃ ꢄꢅꢅꢆꢇꢆꢄꢈꢇꢉ

ꢀ

ꢀꢁ

ꢀ ꢁ.ꢂꢃ

ꢀ

ꢀ ꢁA

ꢀꢁꢂ

ꢀꢁAꢂ

ꢀ

ꢀ ꢁꢂꢃꢄ

ꢀꢁꢂ ꢃꢀꢀꢄꢁꢄꢃꢅꢁꢆ

ꢀ

ꢀ ꢁꢂꢂꢃA

ꢀꢁAꢂ

ꢀꢁꢂ ꢃꢄꢅꢅ

ꢀ

ꢀ ꢁꢂꢃA

ꢀꢁAꢂ

ꢀ

ꢀꢁ

ꢀ ꢁ.ꢂꢃ

ꢀꢁꢂ

ꢀꢁRꢂꢃ ꢄꢅꢂꢂ

ꢀ

ꢀ ꢁꢂA

ꢀ ꢁꢂꢃA

ꢀ ꢁꢂꢂꢃA

ꢀ ꢁA

ꢀ

ꢀ ꢁꢂꢃꢄ

ꢀꢁAꢂ

ꢀ

ꢀ ꢁ.ꢁꢂ

ꢀꢁꢂ

ꢀꢁ

ꢀ

ꢀ ꢁꢂA

ꢀꢁAꢂ

ꢀ ꢁ.ꢂꢃ

ꢀ.ꢁ

ꢀ

ꢀ.ꢁ

ꢀ

ꢀ.ꢁ

ꢀ

ꢀ.ꢁ

ꢀ

ꢀ.ꢀ

ꢀ.ꢀꢀꢀꢁ

ꢀ.ꢀꢀꢁ

ꢀ.ꢀꢁ

ꢀ.ꢁ

ꢀ

ꢀ.ꢁ

ꢀ

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ꢀ

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ꢀꢁꢂꢃꢄ ꢅꢆꢇꢄAꢈꢉ ꢊꢅꢋ

ꢀꢁꢂꢃꢁꢂ ꢄꢁRRꢅꢆꢂ ꢇAꢈ

ꢀꢁꢂꢃꢄ ꢅꢆꢇꢄAꢈꢉ ꢊꢅꢋ

ꢀꢀꢁꢂ ꢃꢂꢁ

ꢀꢀꢁꢂ ꢃꢂꢄ

2A Buck Efficiency

vs V_OUTForced Continuous Mode

2A Buck Efficiency

Efficiency vs Output Current

Burst Mode Operation

vs V_OUTBurst Mode Operation

ꢀꢁꢁ

ꢀꢁ

ꢀ

ꢀꢁꢁ

ꢀꢁ

ꢀꢁꢁ

ꢀꢁ

ꢀ

ꢀꢁ

ꢀ ꢁ.ꢁꢂ

ꢀ ꢁꢂꢃꢄ

ꢀꢁ

ꢀ

ꢀ ꢁA

ꢀꢁAꢂ

ꢀ

ꢀ ꢁꢂꢂꢃA

ꢀꢁAꢂ

ꢀ

ꢀ ꢁꢂꢃA

ꢀꢁAꢂ

ꢀ

ꢀ ꢁꢂA

ꢀ ꢁꢂꢃA

ꢀ ꢁA

ꢀꢁAꢂ

ꢀA ꢁꢂꢃꢄ

ꢀ

ꢀꢁ

ꢀ ꢁ.ꢁꢂ

ꢀ ꢁꢂꢃꢄ

ꢀꢁ

ꢀ

ꢀ ꢁ.ꢁꢂ

ꢀꢁ

ꢀꢁꢂ

ꢀꢁ

ꢀ

ꢀ ꢁ.ꢂꢃ

ꢀ

ꢀ ꢁꢂA

ꢀꢁAꢂ

ꢀ ꢁꢂꢃꢄ

ꢀ.ꢀꢀꢀꢁ

ꢀ.ꢀꢀꢁ

ꢀ.ꢀꢁ

ꢀ.ꢁ

ꢀ

ꢀ.ꢁ ꢀ.ꢁ ꢀ.ꢁ ꢀ.ꢁ ꢀ.ꢁ ꢀ.ꢁ ꢀ.ꢁ ꢀ.ꢀ ꢀ.ꢁ ꢀ.ꢁ ꢀ.ꢁ ꢀ.ꢁ

ꢀꢁꢂꢃꢁꢂ ꢄꢁRRꢅꢆꢂ ꢇꢈꢉ

ꢀꢁꢂꢃꢁꢂ ꢄꢀꢅꢂAꢆꢇ ꢈꢄꢉ

ꢀꢀꢁꢂ ꢃꢀꢄ

ꢀꢀꢁꢂ ꢃꢂꢄ

2A Buck Efficiency vs Output Current

Across Switching Frequency

2A Buck Regulator Feedback

Voltage vs Temperature

1A Buck Load Regulation Across

V_INForced Continuous Mode

ꢀ.ꢁꢂꢂ

ꢀ.ꢁꢂꢃ

ꢀ.ꢁꢁꢂ

ꢀ.ꢁꢂꢃ

ꢀ.ꢁꢀꢂ

ꢀ.ꢁꢂꢂ

ꢀꢁꢂ

ꢀꢁꢁ

ꢀꢁꢂ

ꢀꢁꢁ

ꢀꢁ

ꢀ

ꢀ ꢁ.ꢂꢃ

ꢀꢁꢂ

ꢀ

ꢀ ꢁ.ꢁꢂ

ꢀꢁꢂ

ꢀꢁ

ꢀ ꢁ.ꢂꢃ

ꢀꢁRꢂꢃ ꢄꢅꢆꢇ

ꢀꢁꢂ

ꢀ

ꢀꢁꢂ

ꢀ ꢁ.ꢁꢂ

ꢀꢁ

ꢀ

ꢀ ꢁ.ꢂꢃ

ꢀ

ꢀ ꢁ.ꢁꢂꢃ

ꢀ ꢁ.ꢁꢂ

ꢀ ꢁꢂ

ꢀꢁ

ꢀ

ꢀ ꢁꢂꢃꢄ

ꢀꢁ

ꢀ.ꢀꢀꢁ

ꢀ.ꢀꢁ

ꢀ.ꢁ

ꢀ

ꢀꢁꢂ ꢀꢁꢂ ꢀꢁꢂ

ꢀ

ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁꢁ ꢀꢁꢂ ꢀꢁꢂ

ꢀ.ꢀꢀꢀꢁ

ꢀ.ꢀꢀꢁ

ꢀ.ꢀꢁ

ꢀ.ꢁ

ꢀ

ꢀꢁꢂꢃꢁꢂ ꢄꢁRRꢅꢆꢂ ꢇAꢈ

ꢀꢁꢂꢃꢁRAꢀꢄRꢁ ꢅꢆꢇꢈ

ꢀꢁꢂꢃꢁꢂ ꢄꢁRRꢅꢆꢂ ꢇAꢈ

ꢀꢀꢁꢂ ꢃꢀꢀ

ꢀꢀꢁꢂ ꢃꢀꢂ

ꢀꢀꢁꢂ ꢃꢀꢄ

Rev. A

11

For more information www.analog.com

LTC3372

TYPICAL PERFORMANCE CHARACTERISTICS

(LV Buck Regulator) T_A= 25°C, unless otherwise noted.

2A Buck Regulated Feedback

Voltage vs V_INA-H

1A Buck PMOS Current Limit

vs Temperature

4A Buck Output Voltage

vs Output Current

ꢀ.ꢁꢂ

ꢀ.ꢁꢁ

ꢀ.ꢁꢂ

ꢀ.ꢁꢂꢃ

ꢀ.ꢁꢂꢂ

ꢀ.ꢁꢂꢃ

ꢀ.ꢁꢂꢂ

ꢀꢁꢀ

ꢀꢁꢂ

ꢀꢁꢁ

ꢀꢁꢂ

ꢀ

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ꢀꢁRꢂꢃꢄ ꢂꢁꢅꢆꢇꢅꢈꢁꢈꢉ ꢊꢁꢄꢃ

ꢀ

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ꢀꢁꢂ

ꢀꢁ

ꢀ

ꢀ ꢁ.ꢂꢃ

ꢀꢁꢂ

ꢀ

ꢀꢁꢂ

ꢀ

ꢀ ꢁ.ꢁꢂꢃ

ꢀ ꢁ.ꢁꢂ

ꢀ ꢁꢂ

ꢀꢁ

ꢀ

ꢀ ꢁꢂꢃA

ꢀ ꢁA

ꢀ

ꢀ ꢁ.ꢁꢂ

ꢀ ꢁꢂ

ꢀꢁAꢂ

ꢀꢁ

ꢀ

ꢀꢁAꢂ

ꢀꢁꢂ ꢀꢁꢂ ꢀꢁꢂ

ꢀ

ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁꢁ ꢀꢁꢂ ꢀꢁꢂ

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ꢀꢁꢂꢃꢁꢂ ꢄꢁRRꢅꢆꢂ ꢇAꢈ

ꢀꢁꢂꢃꢄ ꢅꢆꢇꢄAꢈꢉ ꢊꢅꢋ

ꢀꢀꢁꢂ ꢃꢀꢄ

1A Buck NMOS and PMOS R_DS(ON)

vs Temperature Across V_IN

R_TProgrammed Oscillator

Frequency vs Temperature

Oscillator Frequency vs R_T

ꢀ.ꢁ

ꢀ

ꢀꢁꢁ

ꢀꢁꢂ

ꢀꢁꢁ

ꢀꢁꢂ

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ꢀꢁꢂ

ꢀꢁꢁ

ꢀꢁꢂ

ꢀꢁꢁ

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ꢀ.ꢁꢀ

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ꢀ.ꢁꢂ

ꢀ ꢀ ꢁ.ꢁꢂ

ꢀꢁ

R

ꢀꢁAꢂꢃ

= 402kΩ

ꢀ

ꢀ ꢁꢂ

ꢀ ꢁ.ꢁꢂ

ꢀ ꢁ.ꢁꢂꢃ

ꢀ

ꢀꢁ

ꢀ

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ꢀꢁꢂ ꢀꢁꢁ ꢀꢁꢂ ꢀꢁꢁ ꢀꢁꢂ ꢀꢁꢁ ꢀꢀꢁ ꢀꢁꢁ ꢀꢁꢂ ꢀꢁꢁ ꢀꢁꢂ ꢀꢁꢁ

(kΩ)

ꢀꢁꢂ ꢀꢁꢂ ꢀꢁꢂ

ꢀ

ꢀꢁꢂ ꢀꢁꢂ ꢀꢁꢂ

ꢀ

ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁꢁ ꢀꢁꢂ ꢀꢁꢂ

R

ꢀ

ꢀꢁꢂꢃꢁRAꢀꢄRꢁ ꢅꢆꢇꢈ

ꢀꢀꢁꢂ ꢃꢀꢄ

ꢀꢀꢁꢂ ꢃꢀꢁ

ꢀꢀꢁꢂ ꢃꢀꢄ

Default Oscillator Frequency

vs Temperature

V_TEMPvs Temperature

Enable Threshold vs Temperature

ꢀ.ꢁꢂ

ꢀ.ꢁꢀ

ꢀ.ꢁꢁ

ꢀ.ꢁꢂ

ꢀꢁꢁ

ꢀꢁꢂꢂ

ꢀꢁꢁꢁ

ꢀꢁꢁ

ꢀ

ꢀ ꢁ.ꢁꢂ

ꢀ

ꢀ ꢁ.ꢁꢂ

ꢀꢁAꢂꢃ

ꢀꢁ

Rꢀꢁꢀꢂꢃ

ꢀAꢁꢁꢂꢃꢄ

ꢀꢁꢂꢂ

ꢀꢁꢂ ꢀꢁꢂ ꢀꢁꢂ

ꢀ

ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁꢁ ꢀꢁꢂ ꢀꢁꢂ

ꢀꢁꢂ ꢀꢁꢂ ꢀꢁꢂ

ꢀ

ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁꢁ ꢀꢁꢂ ꢀꢁꢂ

ꢀ

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ꢀꢁꢂꢃꢁRAꢀꢄRꢁ ꢅꢆꢇꢈ

ꢀꢀꢁꢂ ꢃꢄꢅ

ꢀꢀꢁꢂ ꢃꢄꢂ

ꢀꢀꢁꢂ ꢃꢄꢅ

Rev. A

12

For more information www.analog.com

LTC3372

TYPICAL PERFORMANCE CHARACTERISTICS

(LV Buck Regulator) T_A= 25°C, unless otherwise noted.

Precise Enable Threshold

vs Temperature

V_INA-HUVLO Threshold

vs Temperature

2A Buck Load Step Burst Mode

ꢀꢁꢂ

ꢀꢁꢁ

ꢀꢁꢂ

ꢀꢀꢁ

ꢀꢁꢂ

ꢀ.ꢁꢂ

ꢀ.ꢀꢁ

ꢀ.ꢁꢂ

ꢀ.ꢁꢁ

ꢀ.ꢁꢂ

ꢀ

ꢀꢁ

ꢀ ꢁ.ꢁꢂ

ꢀ

ꢀꢁAꢂ

Rꢀꢁꢀꢂꢃ

ꢀAꢁꢂꢃꢄ

ꢀ

ꢀꢁꢂ

Rꢀꢁꢀꢂꢃ

ꢀAꢁꢂꢃꢄ

ꢀ

ꢀꢁꢂ

Aꢀꢁꢀꢂꢃꢄꢅꢆꢇ

ꢀꢁꢂꢃꢄꢅꢆꢃ

ꢀAꢁꢁꢂꢃꢄ

ꢀꢀꢁꢂ ꢃꢄꢅ

ꢀAꢁꢁꢂꢃꢄ

ꢀꢁꢁꢂꢃꢄꢅꢆꢇ

ꢀ

ꢀ ꢁ.ꢁꢂ

ꢀꢁꢂ

ꢀꢁ

ꢀ

ꢀ ꢁ.ꢂꢃ

ꢀ

ꢀ ꢁꢂꢂꢃA ꢄꢅ ꢁ.ꢆA

ꢀꢁAꢂ

ꢀꢁꢂ ꢀꢁꢂ ꢀꢁꢂ

ꢀ

ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁꢁ ꢀꢁꢂ ꢀꢁꢂ

ꢀꢁꢂ ꢀꢁꢂ ꢀꢁꢂ

ꢀ

ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁꢁ ꢀꢁꢂ ꢀꢁꢂ

ꢀꢁꢂꢃꢁRAꢀꢄRꢁ ꢅꢆꢇꢈ

ꢀꢀꢁꢂ ꢃꢄꢀ

ꢀꢀꢁꢂ ꢃꢄꢄ

2A Buck Load Step Forced

Continuous Mode

2A Buck Start-Up

ꢀ

ꢀꢁAꢂ

ꢀAꢁꢂꢃꢄ

ꢀ

ꢀꢁ

ꢀꢁꢂꢃꢄꢁ

ꢀ

ꢀꢁꢂ

ꢀAꢁꢂꢃꢄ

ꢀ

ꢀꢁꢂ

ꢀ

Aꢀꢁꢀꢂꢃꢄꢅꢆꢇ

ꢀꢁꢂ

ꢀꢁꢂꢃꢄꢁ

ꢀꢁꢂAꢃꢄꢅꢆ

ꢀꢀꢁꢂ ꢃꢄꢅ

ꢀꢀꢁꢂ ꢃꢄꢁ

ꢀꢁꢁꢂꢃꢄꢅꢆꢇ

ꢀꢁꢂꢃꢄꢅꢆ

ꢀ

ꢀ ꢁ.ꢁꢂ

ꢀꢁꢂ

ꢀꢁ

ꢀ

ꢀ ꢁ.ꢁꢂ

ꢀꢁꢂ

ꢀꢁ

ꢀ

ꢀ ꢁ.ꢂꢃ

ꢀ

ꢀ ꢁꢂꢂꢃA ꢄꢅ ꢁ.ꢆA

ꢀꢁAꢂ

Rev. A

13

For more information www.analog.com

LTC3372

PIN FUNCTIONS

RST (Pin 1): LV Regulator Reset Logic Output. This pin is

pulled low when the feedback pin (FB1-4) voltage of any

enabled LV regulator is outside of its power good window.

The window is –2% to +7.5% (typical) for regulator 1,

and –5% to +7.5% (typical) for regulators 2-4, around

the regulated 0.8V level. This pin is pulled low when all

LV regulators are disabled. Assertion (the pin goes high)

FB2 (Pin 13): LV Buck Regulator 2 Feedback Pin. Receives

feedbackbyaresistordividerconnectedacrosstheoutput.

In configurations where LV Regulator 2 is not used, FB2

should be tied to ground.

EN2 (Pin 14): LV Buck Regulator 2 Enable Input. Active

high. In configurations where LV Regulator 2 is not used,

tie EN2 to ground. Do not float.

delay is scaled by the C capacitor.

T

C1 (Pin 15): LV Regulator Configuration Control Input Bit.

With C2 and C3, C1 configures the buck output current

power stage combinations. C1 should either be tied to

TEMP (Pin 2): Temperature Indication Pin. TEMP outputs

a voltage of 220mV (typical) at 25°C. The TEMP voltage

will increase by 7mV/°C (typical) at higher temperatures

giving an external indication of the IC’s internal die tem-

perature. The temperature monitor can be shut down by

tying the TEMP pin to INTV to reduce quiescent current.

If all LV regulators are disabled, the temperature monitor

shuts down and the TEMP pin becomes high impedance.

INTV or ground. Do not float.

CC

C2 (Pin 16): LV Regulator Configuration Control Input Bit.

With C1 and C3, C2 configures the buck output current

power stage combinations. C2 should either be tied to

CC

INTV or ground. Do not float.

CC

C3 (Pin 17): LV Regulator Configuration Control Input Bit.

With C1 and C2, C3 configures the buck output control

power stage combinations. C3 should either be tied to

EN1 (Pin 3): LV Buck Regulator 1 Enable Input. Active

high. Do not float.

FB1 (Pin 4): LV Buck Regulator 1 Feedback Pin. Receives

feedbackbyaresistordividerconnectedacrosstheoutput.

INTV or ground. Do not float.

CC

RT (Pin 18): Oscillator Frequency Pin. This pin provides

twomodesofsettingtheswitchingfrequency.Connectinga

resistorfromRTtogroundwillsettheswitchingfrequency

V

(Pin 5): LV Power Stage A Input Supply. Bypass to

INA

GND with a 10µF or larger ceramic capacitor.

SWA (Pin 6): LV Power Stage A Switch Node. External

inductor connects to this pin.

based on the resistor value. If RT is tied to INTV the

CC

internal 2MHz oscillator will be used. Do not float.

SWB (Pin 7): LV Power Stage B Switch Node. External

PLL/MODE (Pin 19): Oscillator Synchronization Input and

Mode Select Pin. Driving this pin with an external clock

signal synchronizes the internal oscillator to the applied

clock.TheLVbuckssynchronizetotheoscillatorfrequency

and HV buck synchronizes to 1/6th frequency when in

forced continuous mode. When no external clock is ap-

plied the oscillator frequency is programmed by the RT

pin. Whennotsynchronizingtoanexternalclockthisinput

determines how the controller and regulators operate at

lightload.FloatingorgroundingthispinselectsBurstMode

inductor connects to this pin.

V

(Pin 8): LV Power Stage B Input Supply. Bypass to

INB

GND with a 10µF or larger ceramic capacitor.

V

(Pin 9): LV Power Stage C Input Supply. Bypass to

INC

GND with a 10µF or larger ceramic capacitor.

SWC (Pin 10): LV Power Stage C Switch Node. External

inductor connects to this pin.

SWD (Pin 11): LV Power Stage D Switch Node. External

inductor connects to this pin.

operation, and tying this pin to INTV forces continuous

CC

inductor current mode operation for all the converters and

the controller. Tying this pin to a voltage greater than 1.2V

V

(Pin 12): LV Power Stage D Input Supply. Bypass to

IND

and less than INTV –1.3V selects pulse-skipping mode

GND with a 10µF or larger ceramic capacitor.

CC

operation for the controller, but Burst Mode operation for

the low voltage converters. This pin has a 100k internal

resistor to ground.

Rev. A

14

For more information www.analog.com

LTC3372

PIN FUNCTIONS

WDI (Pin 20): Watchdog Timer Input. The WDI pin must

be toggled either low to high or high to low every 1.62

seconds. Failure to toggle WDI results in the WDO pin

being pulled low for 202ms. All times correspond to a

10nF capacitor on the CT pin.

V

(Pin 32): LV Power Stage H Input Supply. Bypass to

INH

GND with a 10μF or larger ceramic capacitor.

FB4 (Pin 33): LV Buck Regulator 4 Feedback Pin. Receives

feedbackbyaresistordividerconnectedacrosstheoutput.

EN4 (Pin 34): LV Buck Regulator 4 Enable Input. Active

high. Do not float.

WDO (Pin 21): Watchdog Timer. Open-drain output. WDO

ispulledlowfor202msduringawatchdogtimeoutperiod.

The WDO pin pulls low if the WDI input does not transition

in less than 1.62 seconds since its last transition or 12.9

seconds after a watchdog timeout period. An UVLO event

resets the watchdog timer and WDO asserts itself low for

the202mswatchdogtimeoutperiod.Alltimescorrespond

to a 10nF capacitor on the CT pin.

INTV (Pin 35): Internal V Pin. Output of an internal

CC

linearlow-dropout(LDO)regulatorpoweredfromV .The

IN

HV buck gate drive and control circuits are powered from

this voltage source when V

is < 4.7V. When V

>

OUT

4.7V the bias connects to Vout and the LDO is shutdown.

Must be de-coupled to GND pin with a minimum of 4.7μF

low ESR (ceramic) capacitor.

CT (Pin 22): Timing Capacitor Pin. A capacitor connected

BG (Pin 36): HV Controller High Current Gate Drive for

to GND sets a time constant which is scaled for use by

Bottom(Synchronous)N-channelMOSFET.Voltageswing

the WDI, WDO, and RST pins. Tying the CT pin to INTV

CC

at this pin is from ground to INTV .

disables the watchdog timer to reduce quiescent current.

CC

TG (Pin 37): HV Controller High Current Gate Drive for Top

EN3 (Pin 23): LV Buck Regulator 3 Enable Input. Active

high. In configurations where LV Regulator 3 is not used,

tie EN3 to ground. Do not float.

N-channel MOSFET. This is the output of floating driver

with a voltage swing equal to INTV superimposed on

CC

the switch node voltage SW.

FB3 (Pin 24): LV Buck Regulator 3 Feedback Pin. Receives

feedbackbyaresistordividerconnectedacrosstheoutput.

In configurations where LV Regulator 3 is not used, FB3

should be tied to ground.

SW (Pin 38): HV Controller Switch Node Connection to

Inductor.

BOOST(Pin39):HVControllerBootstrappedSupplytothe

Topside Floating Driver. A capacitor should be connected

between the BOOST and SW pin and a Schottky diode

V

(Pin 25): LV Power Stage E Input Supply. Bypass to

INE

GND with a 10μF or larger ceramic capacitor.

should be connected between the BOOST and INTV

CC

SWE (Pin 26): LV Power Stage E Switch Node. External

inductor connects to this pin.

pins. Voltage swing at the BOOST pin is from INTV to

CC

(V + INTV ).

IN

CC

SWF (Pin 27): LV Power Stage F Switch Node. External

inductor connects to this pin.

RUN (Pin 40): HV Controller Enable Input. Forcing this

pin above 1.2V turns on the HV controller. This pin has a

0.5µA internal pull-up current from ground to around 4V,

and can be forced up to 65V (absolute maximum).

V

(Pin 28): LV Power Stage F Input Supply. Bypass to

INF

GND with a 10μF or larger ceramic capacitor.

V

(Pin 29): LV Power Stage G Input Supply. Bypass to

V

(Pin 41): HV Input Supply Pin. A bypass capacitor

IN

ING

GND with a 10μF or larger ceramic capacitor.

should be tied between this pin and the GND pin.

SWG (Pin 30): LV Power Stage G Switch Node. External

TRACK/SS (Pin 42): HV Controller External Tracking and

inductor connects to this pin.

Soft-StartInput.Whenthispinisabove1.2V,thecontroller

regulates the output voltage V

to the programed 5V or

OUT

SWH (Pin 31): LV Power Stage H Switch Node. External

inductor connects to this pin.

3.3V level. When this pin is below 1.2V, the output voltage

Rev. A

15

For more information www.analog.com

LTC3372

PIN FUNCTIONS

+

is regulated proportionally lower. An internal 10μA pull-

up current source is connected to this pin. A capacitor to

ground at this pin sets the ramp time to the final regulated

output voltage. Alternatively, a resistor divider on another

voltagesupplyconnectedtothispinallowsthecontroller’s

output to track another supply during start-up.

SENSE (Pin 45): HV Controller Positive (+) Input to

Differential Current Comparator. The ITH pin voltage and

–

+

controlled offsets between the SENSE and SENSE pins

set the current trip threshold. The current comparator

can be used for either inductor DCR sensing or traditional

current sensing resistor (R

) sensing.

SENSE

V

/EXTV (Pin 43): HV Controller Output Voltage

ITH (Pin 46): HV Controller Error Amplifier Output and

Compensation Point. The current comparator threshold

increases with this control voltage.

OUT

CC

Sensing and External V Power Input. Connect this pin

CC

to the HV controller’s regulated output voltage. The HV

controller V

internal resistor divider selected by the V

pin is also provides an external V connection and sup-

plies internal bias voltages from V

performance and reduce power loss.

is regulated to either 3.3V or 5V by an

OUT

V

(Pin 47): HV ControllerOutput Voltage Program-

OUTPRG

pin. This

PROG

ming Pin. When this pin is tied to INTV , the output volt-

CC

OUT

age is regulated to 5V. When tied to ground, the output

voltage is regulated to 3.3V.

to improve low I

Q

PGOOD (Pin 48): HV Controller Power Good Open-Drain

LogicOutput. Thispinispulledlowwhenthevoltageatthe

–

SENSE (Pin 44): HV Controller Negative (–) Input to

Differential Current Comparator. This SENSE pin also

–

V

/EXTV pin is outside of the 7.5% window around

OUT

CC

functions as the output voltage sense pin for a secondary

15% overvoltage protection in addition to the 7.5% over-

–

the regulated level, or voltage at SENSE pin is more than

15% above the regulated level of V

.

OUT

voltage protection at the V /EXTV pin. In the situation

OUT

CC

–

GND (Exposed Pad Pin 49): Ground. The exposed pad

must be soldered to a continuous printed circuit board

ground plane directly under the IC package for rated ther-

mal performance. The exposed pad is a shared ground for

signal grounds, driver ground and power stage grounds

of all HV and LV buck regulators.

that SENSE pin is separated from V /EXTV pin to

OUT

CC

–

achievepoint-of-load(POL)regulation, SENSE canbegin

–

drawinga>500µAcurrentwhenSENSE is200mVgreater

than V

(V

= 5V) or INTV (V

= 3.3V). When

CC

OUT

CC

OUT

–

voltage on SENSE pin is close to INTV , SENSE can

begin drawing >500µA current. Do not connect a filtering

–

resistor in series with SENSE pin unless SENSE stays

close to ground in the application.

Rev. A

16

For more information www.analog.com

LTC3372

BLOCK DIAGRAM

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Rev. A

17

For more information www.analog.com

LTC3372

OPERATION

The LTC3372 is a single IC that combines a high voltage

(HV) buck (step-down) DC/DC switching regulator con-

troller and a total of four configurable low voltage (LV)

buck regulators.

to V , the loop may enter dropout and attempt to turn

OUT

on the top MOSFET continuously. The dropout detector

detects this and forces the top MOSFET off for a short

time every tenth cycle to allow C to recharge, resulting

B

in an effective duty cycle of 98%.

Main Control Loop of HV Buck Controller

Shutdown and Start-Up (RUN, TRACK/SS Pins)

TheHVcontrollerusesaconstantfrequency,currentmode

buck (step-down) architecture. During normal operation,

the external top MOSFET is turned on when the clock sets

the RS latch, and is turned off when the main current

comparator, ICMP, resets the RS latch. The peak inductor

current at which ICMP trips and resets the latch is con-

trolled by the voltage on the ITH pin, which is the output

of the error amplifier, EA. The error amplifier compares

an internal 1.2V reference voltage to the feedback voltage

generated by an internal resistor divider connected to the

Ittypicallytakes1.2msfortheinternalbiascircuits(includ-

ing INTV ) to be ready after the first time either the RUN

CC

pin or any of the EN1-4 pins rises above 730mV. During

the 1ms internal bias circuit startup time, neither the HV

or LV regulators are enabled. The HV controller is enabled

when the RUN pin is pulled above 1.2V and the internal

bias is enabled. Pulling RUN pin below 1.16V disables

the HV controller.

The RUN pin has an internal 0.5μA current that pulls up

the pin to enable the HV controller. Alternatively, the RUN

pin may be externally pulled up or driven by logic. The

RUN pin can tolerate up to 65V (absolute maximum), so

V

/EXTV pin. The divider can be selected to program

OUT

CC

an output of either 3.3V to 5V. When the load current

increases, it causes a slight decrease in V relative to

FB

the reference, which causes the EA to increase the ITH

voltage until the average inductor current matches the

new load current.

it can be conveniently tied to V in an always-on applica-

IN

tion in which the controller is enabled continuously and

never shut down.

After the top MOSFET is turned off each cycle, the bottom

MOSFET is turned on until either the beginning of the next

clock cycle, or the inductor current starts to reverse, as

indicated by the reverse current comparator IREV (at light

load in pulse-skipping mode or Burst Mode).

The RUN pin can also be used as an undervoltage lockout

(UVLO) by connecting it to the midpoint of an external re-

sistordividernetworkofV (seeApplicationsInformation

IN

section).

The start-up of the controller’s output voltage V

is

OUT

INTV Power

controlled by the voltage on the TRACK/SS pin. When the

voltage on the TRACK/SS pin is less than the 1.2V internal

CC

Power for the top and bottom MOSFET drivers and some

reference,theHVcontrollerregulatestheV voltagetothe

FB

otherinternalcircuitryisderivedfromtheINTV pin.When

CC

TRACK/SS pin voltage instead of the 1.2V reference. This

allowstheTRACK/SSpintobeusedtoprogramasoft-start

by connecting an external capacitor from the TRACK/SS

pin to GND. An internal 10μA pull-up current charges this

capacitorcreatingavoltagerampontheTRACK/SSpin.As

the TRACK/SS voltage rises linearly from 0V to 1.2V and

the V /EXTV pin is tied to a voltage less than 4.7V,

OUT

CC

the V LDO (low dropout linear regulator) supplies 5.1V

IN

from V to INTV . If V /EXTV is taken above 4.7V,

IN

CC

OUT

CC

the V LDO is turned off and an internal PMOS switch

IN

connectsV /EXTV toINTV . UsingtheV /EXTV

OUT

CC

OUT

CC

pin allows the INTV power to be derived from the high

CC

beyond, the output voltage V

rises smoothly from zero

OUT

efficiency HV buck regulator output.

to its final value. Alternatively the TRACK/SS pin can be

used to cause the start-up of V to track that of another

ThetopMOSFETdriverisbiasedfromthefloatingbootstrap

OUT

capacitor, C , which normally recharges during each cycle

supply. Typically, this requires connecting to the TRACK/

SS pin an external resistor divider from the other supply

to ground (see the Applications Information section).

B

throughanexternaldiode,D ,whenthetopMOSFETturns

B

off. If the input voltage, V , decreases to a voltage close

IN

Rev. A

18

For more information www.analog.com

LTC3372

OPERATION

Output Overvoltage Protection

The LTC3372’s PLL/MODE pin selects the light load

operation modes for both the HV controller and LV

buck regulators. To select Burst Mode operation, tie the

PLL/MODE pin to SGND. To select forced continuous

Overvoltage comparators guard against transient over-

shoots as well as other more serious conditions that may

overvoltage the output.

mode operation, tie the PLL/MODE pin to INTV . When

CC

When the V /EXTV pin voltage rises by more than

PLL/MODE pin is connected to an external clock, both HV

controller and the LV buck regulators are synchronized to

the external clock in forced continuous mode operation.

To select pulse-skipping mode for the HV controller, tie the

PLL/MODE pin to a DC voltage greater than 1.2V but less

OUT

CC

7.5%aboveitsregulationsetpoint,thetoppowerMOSFET

gate(TG)isturnedoffandthebottompowerMOSFETgate

(BG)isturnedonuntiltheovervoltageconditioniscleared.

–

The SENSE pin functions as the output voltage sense pin

than INTV – 3.3V. The LV buck regulators will operate

CC

for a secondary +15% overvoltage protection in addition

in Burst Mode operation.

to the +7.5% overvoltage protection at V /EXTV pin.

OUT

CC

When voltage at this pin is over 15% higher than the

regulated output voltage set point, the HV controller will

turn TG off and BG on. This provides an additional layer of

protectionwhenpoint-of-load(POL)regulationisdesired.

When the controller is enabled for Burst Mode operation, the

minimum peak current in the inductor is set to approximately

25% of the maximum sense voltage even though the voltage

on the ITH pin indicates a lower value. If the average inductor

current is higher than the load current, the error amplifier,

EA, will decrease the voltage on the ITH pin. When the ITH

voltage drops below 0.425V, the internal sleep signal goes

high (enabling sleep mode) and both external MOSFETs are

turned off. The ITH pin is then disconnected from the output

of the EA and parked at 0.450V.

Power Good Indicator (PGOOD) Pin

The PGOOD pin is connected to the open drain of an

internal N-channel MOSFET. The MOSFET turns on and

pulls the PGOOD pin low when the V /EXTV voltage

OUT

CC

is outside of the 7.5% window around the regulated

level. The PGOOD pin is also pulled low when the RUN

In sleep, much of the internal circuitry is turned off, re-

ducing the quiescent currents that the controllers draws.

The load current is supplied by the output capacitor. As

the output voltage decreases, the EA’s output begins to

rise. When the output voltage drops enough, the ITH pin

is reconnected to the output of the EA, the sleep signal

goes low, and the controller resumes normal operation

by turning on the top external MOSFET on the next cycle

of the internal oscillator.

pin is low (shut down). When the V /EXTV voltage is

OUT

CC

within the 7.5% window, the MOSFET is turned off and

the pin is allowed to be pulled up by an external resistor

to a source no greater than 6V.

Foldback Current Limit

When the output voltage falls to less than 70% of its nominal

level, foldback current limiting is activated. Foldback progres-

sively lowers the peak current limit as the output drops in a

sustainedovercurrentorshort-circuitcondition.Foldbackcur-

rent limiting is disabled during the soft-start interval (as long

When the controller is enabled for Burst Mode operation,

the inductor current is not allowed to reverse. The reverse

current comparator, I , turns off the bottom external

REV

as the V voltage is keeping up with the TRACK/SS voltage).

FB

MOSFET just before the inductor current reaches zero,

preventing it from reversing and going negative. Thus, the

controller operates in discontinuous operation.

Light Load Current Operation

The HV buck controller can be enabled to enter one of

the three modes at light load current: (a) high efficiency

Burst Mode, (b) forced continuous conduction mode, or

(c) pulse-skipping mode operations at light load currents.

In forced continuous operation, the inductor current is

allowed to reverse at light loads or under large transient

conditions. The peak inductor current is determined by

the voltage on the ITH pin, just as in normal operation.

In this mode, the efficiency at light loads is lower than in

Rev. A

19

For more information www.analog.com

LTC3372

OPERATION

Burst Mode operation. However, continuous operation

has the advantage of lower output voltage ripple and less

interference to other circuitry. In forced continuous mode,

the output ripple is independent of load current. Clock-

ing the LTC3372 from an external source enables forced

continuous mode (see the Programming the Operating

Frequency section.)

be used to provide event based sequencing via feedback

from other previously enabled regulators.

It typically takes 1ms for the internal bias circuits (in-

cluding INTV ) to be ready after the first time RUN or

CC

any EN pin rises above 0.73V. All regulators are disabled

during internal circuit start-up time. When a LV regulator

is enabled there is an additional 150μs delay before the

soft start ramp begins. All LV regulators have soft start

and forward and reverse current limiting to control inrush

currentduringstart-upandtoprovideshort-circuitprotec-

tion in normal operation.

When the PLL/MODE pin is connected for pulse-skipping

mode, the HV controller operates in PWM pulse-skipping

mode at light loads. In this mode, constant frequency

operation is maintained down to approximately 1% of

designed maximum output current. At very light loads,

the current comparator, ICMP, may remain tripped for

several cycles and force the external top MOSFET to stay

off for the same number of cycles (i.e., skipping pulses).

The inductor current is not allowed to reverse (discon-

tinuous operation). This mode, like forced continuous

operation, exhibits low output ripple as well as low noise

and reduced RF interference as compared to Burst Mode

operation. It provides higher low current efficiency than

forced continuous mode, but not nearly as high as Burst

Mode operation.

The LV buck switching regulators are phased in 90° steps

toreducenoiseandinputripple.Thephasestepdetermines

the fixed edge of the switching sequence, which is when

the PMOS turns on. The PMOS off (NMOS on) phase is

subject to the duty cycle demanded by the regulator. Buck

1 is set to 0°, Buck 2 is set to 90°, Buck 3 is set to 270°,

and Buck 4 is set to 180°. In shutdown all SW nodes are

high impedance. The buck regulator enable pins may be

tiedtoV

voltagesthrougharesistordivider,toprogram

OUT

power-up sequencing.

LV Buck Regulators with Combined Power Stages

LOW VOLTAGE REGULATORS

Up to four adjacent LV buck regulators may be combined

inamaster-slaveconfigurationbysettingtheconfiguration

via the C1, C2, and C3 pins. These pins should either be

Low Voltage Buck Switching Regulator

The LTC3372 contains eight low voltage (LV) monolithic

1Asynchronousbuckswitchingpowerstages.Eachpower

stage contains an integrated PMOS top-side switch and

a NMOS bottom-side switch. The eight power stages are

controlled by up to four constant frequency peak current

mode controllers. All of the switching regulators are

internally compensated and need only external feedback

resistors to set their output voltages.

tiedtogroundorpinstrappedtoINTV inaccordancewith

CC

the desired configuration code (Table 1). Any combined

SW pins must be tied together, as must any of the com-

bined V pins. EN1 and FB1 are utilized by Buck 1, EN2

IN

and FB2 by Buck 2, EN3 and FB3 by Buck 3, and EN4 and

FB4 by Buck 4. If any buck is not used or is not available

in the desired configuration, then the associated FB and

EN pins must be tied to ground.

Each LV buck switching regulator can operate with an

independent input voltage and has its own FB and EN

pins to maximize flexibility. The enable pins have two

different enable thresholds that depend on the operating

state of the other LV regulators. When all of the LV regu-

lators are disabled, the EN pin threshold is 0.73V . Once

any LV regulator is enabled, the EN pin thresholds of the

remaining LV regulators are set to a precision internal-

reference-based 400mV. This precision EN threshold may

Any available combination of 2, 3, or 4 adjacent buck

regulators serves to provide up to either 2A, 3A, or 4A

of average output load current. For example, code 110

(C3C2C1) configures Buck 1 to operate as a 4A regulator

through V

/SWA-H pairs A, B, C, and D, while Buck

INA-H

2 is disabled, Buck 3 operates as a 1A regulator through

/SWA-H pair E, and Buck 4 operates as a 3A regula-

V

INA-H

tor through V

/SWA-H pairs F, G, and H.

INA-H

Rev. A

20

For more information www.analog.com

LTC3372

OPERATION

Table 1. Master Slave Program Combinations (Each Letter

Corresponds to a Low Voltage Power Stage)

Thetemperaturemaybereadbackbytheuserbysampling

theTEMPpinanalogvoltage.Thetemperature,T,indicated

by the TEMP pin voltage is given by:

PROGRAM

CODE

V

− 45mV

C3C2C1

BUCK 1

AB

BUCK 2

BUCK 3

BUCK 4

GH

TEMP

T =

• 1°C

000

CD

EF

7mV

001

ABC

D

EF

GH

To reduce quiescent current (I ), if all the LV buck regula-

Q

010

ABC

E

FGH

FG

tors are shut down, the temperature monitor also shuts

down and the TEMP pin becomes high impedance. The

temperature monitor can be disabled by tying the TEMP

011

ABCH

ABC

D

E

Not Used

EF

100

DE

FGH

GH

101

ABCD

Not Used

pin to INTV to save I .

CC

Q

110

E

FGH

EFGH

111

Not Used

Programming the Operating Frequency

Selectionoftheoperatingfrequencyisatrade-offbetween

efficiency and component size. High frequency operation

allows the use of smaller inductor and capacitor values.

Operation at lower frequencies improves efficiency by

reducing internal gate charge losses but requires larger

inductance values and/or capacitance to maintain low

output voltage ripple.

Power Failure Reporting via RST Pin

Power failure conditions of all LV buck regulators are

reported by the single RST pin. Each LV regulator has an

internal power good signal. If LV Buck 1 output voltage

fallsbelow98%, oranyoftheBuck2-4outputsfallsbelow

95%, of its programmed value, or if any LV regulator’s

output rises above 107.5% of its programmed value, its

internal power good signal is pulled low. If any internal

power good signal stays low for greater than 100μs, then

the RST pin is pulled low. The RST low signal indicates to

a microprocessor that a power failure fault has occurred.

The 100μs filter time prevents a false fault indication low

due to a output/load transient.

The frequency of the internal oscillator (system clock)

is determined by an external resistor that is connected

between the RT pin and ground. The operating frequency

can be calculated using the following equation:

11

8 • 10 • ΩHz

f

=

OSC

R

T

The internal power good comparators have hysteresis, so

the regulated output voltage of an enabled regulator has

to move back into the power good window by more than

the hysteresis for its power good signal to transition high.

Once all enabled LV regulator outputs are power good for

The oscillator is designed to function with operating fre-

quencies between 1MHz and 3MHz, it has safety clamps

that prevent the oscillator from running faster than 4MHz

(typical) or slower than 250kHz (typical). Tying the RT pin

202ms (typical, C = 10nF), the RST output goes high

T

to INTV sets the oscillator to the default internal operat-

CC

impedance (pulled high by external resistor/current). If

ing frequency of 2MHz (typical).

all LV buck regulators are disabled, RST pulls low.

The internal oscillator can be synchronized through an

internal PLL circuit to an external frequency by applying

a square wave clock signal to the PLL/MODE pin. During

synchronization,thetopMOSFETturn-onofLVbuckregu-

lator 1 is phase-locked to the rising edge of the external

frequency source. All other LV regulators are locked to

the appropriate phase of the external frequency source.

Temperature Monitoring and Overtemperature

Protection

To prevent thermal damage to the IC and its surrounding

components, the LV regulators have an overtemperature

(OT)function.WhentheLTC3372dietemperaturereaches

170°C (typical) all LV buck switching regulators are shut

down and remain in shutdown until the die temperature

falls to 160°C (typical).

Rev. A

21

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LTC3372

OPERATION

The synchronization frequency range is 1MHz to 3MHz.

A synchronization signal on the PLL/MODE pin will force

all low voltage (LV) active buck switching regulators to

operate in forced continuous mode PWM.

Choosing the C Capacitor

T

The watchdog timeout period is adjustable and can be

optimized for software execution. The watchdog timeout

period is adjusted by connecting a capacitor between CT

and ground. Given a specified watchdog timeout period,

the capacitor is determined by:

The LV regulators switch directly off the internal oscillator

in 90-degree phase increments. The LTC3372 HV control-

ler switches at one-sixth (1/6) of the internal oscillator

frequency with a range of between 166kHz to 500kHz.

C = t

• 49.39 [nF/s]

T

WDO

For example, using a standard capacitor value of 10nF

givesa202mswatchdogtimeoutperiod.Further,theother

watchdog timing periods scale with t

Windowed Watchdog Timer

. The watchdog

WDO

A standard watchdog function is used to ensure that the

system is in a valid state by continuously monitoring the

microprocessor’sactivity.Themicroprocessormusttoggle

the logic state of the WDI pin periodically in order to clear

the watchdog timer. The WDI pin reset is read only on a

WDI falling edge, such that a single reset signal may be

asserted by pulsing the WDI pin for a time greater than

the minimum pulse width. If timeout occurs, a WDO low

is asserted for the reset timeout period, issuing a system

reset. Once the reset timeout completes, WDO is released

to go high and the watchdog timer starts again.

lower boundary time (t

WDO

previous WDI pulse scales as eight times that of t

) scales as precisely 1/4 of

WDL

t

, the watchdog upper boundary time following the

, and

WDO

the watchdog upper boundary time following a watchdog

timeout scales as 64 times that of t . Finally the RST

assertion delay will scale to the same time as t

WDO

.

WDO

These timing periods are illustrated inFigure 1. Each WDO

low period is equal to the time period t -t (202ms for a

2 1

10nF C capacitor, typical). If a WDI falling edge occurs

T

before the watchdog lower boundary, indicated by t -t

3 2

(50.6ms for a 10nF C capacitor, typical), then another

T

During power-up, the watchdog timer initiates in the

timeout state with WDO asserted low. As soon as the

reset timer times out, WDO goes high and the watchdog

timer is started.

watchdog timeout period occurs. If a WDI falling edge

occurs after the watchdog lower boundary (t ), then the

4

watchdog counter resets, beginning with another watch-

dog lower boundary period. In the case where a WDI low

transition is not detected by the specified time another

watchdogtimeoutperiodisinitiated. Thistimeisindicated

A windowed watchdog function is implemented by add-

ing a lower boundary condition to the standard watchdog

function. If the WDI input receives a falling edge prior to

the watchdog lower boundary, the part considers this a

watchdog failure, and asserts WDO low (releasing again

aftertheresettimeoutperiodasdescribedabove).Thiswill

again be followed by another lower boundary time period.

by t -t (1.62s for a 10nF C capacitor, typical). If a WDI

5 4

T

low transition is not detected within the specified time fol-

lowingawatchdogtimeoutperiod,thenanotherwatchdog

timeout period is initiated. This time is indicated by t -t

7 6

(12.9s for a 10nF C capacitor, typical).

T

The watchdog timer shuts down when RUN and EN1-4

are off (all HV and LV regulators are shut down). Tying the

CT pin to INTV disables the watchdog timer regardless

CC

ꢀꢁꢂ

ꢀꢁꢃ

of the RUN and EN1-4 pins (HV and LV regulators either

on or off).

ꢇꢇꢋꢆ ꢌꢍꢅ

ꢄ

ꢅ

ꢄ

ꢋ

ꢆ

ꢇ

ꢈ

ꢉ

ꢊ

Figure 1. WDO Timing Parameters

Rev. A

22

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LTC3372

APPLICATIONS INFORMATION ^{High Voltage Buck Controller}

HIGH VOLTAGE BUCK CONTROLLER

programmed current limit unpredictable. If inductor DCR

sensing is used (Figure 3b), resistor R1 should be placed

closetotheswitchingnode,topreventnoisefromcoupling

into sensitive small-signal nodes.

The Typical Application on the first page is a basic applica-

tioncircuit.TheHVcontrollerinductorcurrentsensingcan

be configured to use either DCR (inductor resistance) or a

low value sense resistor. The choice between the two cur-

rentsensingschemesislargelyadesigntrade-offbetween

cost, power consumption and accuracy. DCR sensing

has become popular because it saves expensive current

sensing resistors and is more power efficient, especially

in high current applications. However, current sensing

resistors provide the most accurate current limits for the

controller. Other external component selection is driven

by the load requirement, and begins with the selection of

ꢃꢁ ꢄꢅꢆꢄꢅ ꢇꢈꢉꢃꢅRꢊ

ꢆꢅꢋꢃ ꢃꢁ ꢃꢌꢅ ꢀꢁꢆꢃRꢁꢉꢉꢅR

ꢀ

ꢁꢂꢃ

ꢎꢎꢏꢐ ꢇꢑꢐ

ꢈꢆꢍꢂꢀꢃꢁR ꢁR R

ꢄꢅꢆꢄꢅ

Figure 2. Sense Lines Placement with Inductor or Sense Resistor

ꢀ

ꢁꢂ

R

(if R

is used) and inductor value. Next, the

ꢁꢂ

SENSE

ꢁꢂꢅꢀ

ꢆꢆ

power MOSFETs. Finally, input and output capacitors are

selected.

ꢇꢈꢈꢃꢅ

ꢅꢉ

R

ꢃꢄꢂꢃꢄ

+

–

ꢃꢊ

ꢀ

ꢈꢓꢅ

Current Sense Pins (SENSE and SENSE )

ꢌꢅꢆꢐꢐꢑꢒ

+

–

ꢇꢉ

The SENSE and SENSE pins are the inputs to the cur-

rent comparators. The common mode voltage range on

these pins is 0V to 6V (abs max), allowing margin for

tolerances and transients for the HV regulator’s regulated

5V or 3.3V output.

Rꢘꢗ

ꢍ

ꢃꢄꢂꢃꢄ

ꢋꢌAꢆꢄ ꢆAꢋAꢆꢁꢅꢈR ꢂꢄAR

ꢃꢄꢂꢃꢄ ꢋꢁꢂꢃ

ꢆꢘꢗ

ꢎ

ꢃꢄꢂꢃꢄ

ꢉꢂꢏ

ꢐꢐꢑꢒ ꢔꢕꢐꢖ

+

ꢗRꢘ Aꢂꢏ ꢆꢘ ARꢄ ꢈꢋꢅꢁꢈꢂAꢌ

The SENSE pin is high impedance over the full common

mode range, drawing at most 1μA. This high impedance

allows the current comparators to be used in inductor

DCR sensing.

(3a) Using a Resistor to Sense Current

ꢀ

ꢁꢂꢃꢀ

ꢀ

ꢁꢂ

ꢄꢄ

–

Connect the SENSE pin directly to the sense point at the

ꢁꢂꢏꢐꢄꢃꢆR

ꢏꢄR

ꢅꢆꢆꢇꢃ

ꢃꢈ

V

side of the inductor (in DCR sensing) or the current

OUT

senseresistor(R

), withoutaddinganyresistorinse-

ꢌ

SENSE

ꢇꢉ

ꢀ

ꢆꢐꢃ

–

ries.TheimpedanceoftheSENSE pinchangesdepending

ꢌꢃꢄꢓꢓꢔꢕ

–

ꢅꢈ

on its voltage. When SENSE is less than INTV – 0.5V,

CC

a small current of less than 1μA flows out of the pin. As

Rꢎ

ꢄꢎꢊ Rꢕ

ꢑ

ꢇꢍꢂꢇꢍ

–

SENSE approachesINTV ,thecurrenttransitionshigher

CC

to close to 1mA.

ꢒ

ꢇꢍꢂꢇꢍ

ꢈꢂꢏ

Filter components mutual to the sense lines should be

placed close to the IC, and the sense lines should run

close together to a Kelvin connection underneath the

current sense element (shown in Figure 2). Sensing cur-

rent elsewhere can effectively add parasitic inductance

and capacitance to the current sense element, degrading

the information at the sense terminals and making the

Rꢕ

Rꢎ ꢑ Rꢕ

ꢌ

ꢏꢄR

ꢚꢚ

ꢙRꢎ Rꢕꢛ ꢜ ꢄꢎ ꢝ

ꢊꢋꢌAꢄꢍ ꢄꢎ ꢂꢍAR

ꢇꢍꢂꢇꢍ ꢋꢁꢂꢇ

R

ꢝ ꢏꢄR

ꢇꢍꢂꢇꢍꢙꢍꢞꢛ

ꢓꢓꢔꢕ ꢖꢗꢓꢘ

(3b) Using the Inductor DCR to Sense Current

Figure 3. Current Sensing Methods

Rev. A

23

For more information www.analog.com

LTC3372

APPLICATIONS INFORMATION ^{High Voltage Buck Controller}

Resistor Current Sensing

If the external (R1||R2) • C1 time constant is chosen to be

exactly equal to the L/DCR time constant, the voltage drop

across the external capacitor is equal to the drop across

theinductorDCRmultipliedbyR2/(R1+R2).R2scalesthe

voltage across the sense terminals for applications where

the DCR is greater than the target sense resistor value.

To properly dimension the external filter components, the

DCR of the inductor must be known. It can be measured

using a good RLC meter, but the DCR tolerance is not

always the same and varies with temperature; consult

the manufacturers’ data sheets for detailed information.

A typical sensing circuit using a discrete resistor is shown

in Figure 3a. R

output current.

is chosen based on the required

SENSE

This LTC3372’s current comparator has a fixed maximum

current limit threshold of 75mV (typical). The current

comparator threshold voltage sets the peak of the induc-

tor current, yielding a maximum average output current,

I

, equal to the peak value less half the peak-to-peak

MAX

ripple current, ∆I . To calculate the sense resistor value,

L

use the equation:

Using the inductor ripple current value from the Inductor

ValueCalculationsection,thetargetsenseresistorvalueis:

V

SENSE(MAX)

R

=

SENSE

ΔI

L

V

I

+

SENSE(MAX)

MAX

R

=

2

SENSE(EQUIV)

ΔI

L

I

+

MAX

2

To ensure that the application will deliver full load current

over the full operating temperature range, choose the

minimum value (68mV) for the Maximum Current Sense

To ensure that the application will deliver full load current

over the full operating temperature range, choose the

minimum value (68mV) for the Maximum Current Sense

Threshold (V

table.

) in the Electrical Characteristics

SENSE(MAX)

Threshold (V

table.

) in the Electrical Characteristics

SENSE(MAX)

When using the controller in very low dropout conditions,

the maximum output current level will be reduced due

to the internal compensation required to meet stability

criterion for buck regulators operating at greater than

50% duty factor. The maximum current sense threshold

vs duty cycle curve is provided in the Typical Performance

Characteristics section to estimate this reduction in peak

inductorcurrentdependingupontheoperatingdutyfactor.

Next, determine the DCR of the inductor. When provided,

use the manufacturer’s maximum value, usually given at

20°C. Increase this value to account for the temperature

coefficient of copper resistance, which is approximately

0.4%/°C. A conservative value for T

is 100°C.

L(MAX)

To scale the maximum inductor DCR to the desired sense

resistor value, use the divider ratio (R ):

D

Inductor DCR Current Sensing

R

SENSE(EQUIV)

R =

Forapplicationsrequiringthehighestpossibleefficiencyat

highloadcurrents, theLTC3372’sHVcontrolleriscapable

of sensing the voltage drop across the inductor DCR, as

showninFigure3b.TheDCRoftheinductorrepresentsthe

small amount of DC resistance of the copper wire, which

can be less than 1mΩ for today’s low value, high current

inductors. In a high current application requiring such

an inductor, power loss through a sense resistor would

cost several points of efficiency compared to inductor

DCR sensing.

D

DCR

at T

L(MAX)

MAX

C1isusuallyselectedtobeintherangeof0.1μFto0.47μF.

ThisforcesR1||R2toaround2k,reducingerrorthatmight

+

have been caused by the SENSE pin’s 1μA current.

The equivalent resistance R1 || R2 is scaled to the room

temperature inductance and maximum DCR:

L

R1||R2 =

(DCR at 20°C) • C1

Rev. A

24

For more information www.analog.com

LTC3372

APPLICATIONS INFORMATION ^{High Voltage Buck Controller}

The sense resistor values are:

The inductor value also has secondary effects. The tran-

sition to Burst Mode operation begins when the average

inductor current required results in a peak current below

R1||R2 R1• R

D

R1=

; R2 =

R

1−R

D

25% of the current limit determined by R

. Lower

SENSE

inductor values (higher ∆I ) will cause this to occur at

L

The maximum power loss in R1 is related to duty cycle,

and will occur in continuous mode at the maximum input

voltage:

lower load currents, which can cause a dip in efficiency in

the upper range of low current operation. In Burst Mode

operation, lower inductance values will cause the burst

frequency to decrease.

(V

− V

) • V

IN(MAX)

OUT OUT

P

R1=

LOSS

R1

Inductor Core Selection

Ensure that R1 has a power rating higher than this value.

If high efficiency is necessary at light loads, consider this

power loss when deciding whether to use DCR sensing or

sense resistors. Light load power loss can be modestly

higher with a DCR network than with a sense resistor, due

totheextraswitchinglossesincurredthroughR1.However,

DCR sensing eliminates a sense resistor, reduces conduc-

tion losses and provides higher efficiency at heavy loads.

Peak efficiency is about the same with either method.

Once the value for L is known, the type of inductor must

be selected. High efficiency converters generally cannot

affordthecorelossfoundinlowcostpowderedironcores,

forcingtheuseofmoreexpensiveferriteormolypermalloy

cores. Actual core loss is independent of core size for a

fixedinductorvalue,butitisverydependentoninductance

value selected. As inductance increases, core losses go

down. Unfortunately, increased inductance requires more

turns of wire and therefore copper losses will increase.

Inductor Value Calculation

Ferrite designs have very low core loss and are preferred

for high switching frequencies, so design goals can con-

centrate on copper loss and preventing saturation. Ferrite

core material saturates hard, which means that induc-

tance collapses abruptly when the peak design current is

exceeded. This results in an abrupt increase in inductor

ripple current and consequent output voltage ripple. Do

not allow the core to saturate!

The operating frequency and inductor selection are inter-

related in that higher operating frequencies allow the use

of smaller inductor and capacitor values. So why would

anyone ever choose to operate at lower frequencies with

larger components? The answer is efficiency. A higher

frequency generally results in lower efficiency because of

MOSFET switching and gate charge losses. In addition to

this basic trade-off, the effect of inductor value on ripple

currentandlowcurrentoperationmustalsobeconsidered.

Power MOSFET and Schottky Diode (Optional)

Selection

Theinductorvaluehasadirecteffectonripplecurrent.The

Two external power MOSFETs must be selected for the

HV controller: one N-channel MOSFET for the top (main)

switch, and one N-channel MOSFET for the bottom (syn-

chronous) switch.

inductor ripple current, ∆I , decreases with higher induc-

L

tance or higher frequency and increases with higher V :

IN

⎛

⎜

⎝

⎞

⎟

⎠

1

V

OUT

ΔI =

V

1−

L

OUT

(f)(L)

V

IN

Thepeak-to-peakdrivelevelsaresetbytheINTV voltage.

CC

This voltage is typically 5.1V during start-up (see V

OUT

Accepting larger values of ∆I allows the use of low in-

Connection).Consequently,logic-levelthresholdMOSFETs

L

ductances, but results in higher output voltage ripple and

must be used in most applications. Pay close attention to

greater core losses. A reasonable starting point for setting

the BV

specification for the MOSFETs as well.

DSS

ripple current is ∆I = 0.3(I

). The maximum ∆I occurs

L

MAX

Selection criteria for the power MOSFETs include the on-

at the maximum input voltage.

resistance, R , Miller capacitance, C , input

DS(ON) MILLER

Rev. A

25

For more information www.analog.com

LTC3372

APPLICATIONS INFORMATION ^{High Voltage Buck Controller}

voltage and maximum output current. Miller capacitance,

MILLER

a short-circuit when the synchronous switch is on close

to 100% of the period.

C

, can be approximated from the gate charge curve

usually provided on the MOSFET manufacturers’ data

sheet. C is equal to the increase in gate charge

The term (1+ δ) is generally given for a MOSFET in the

MILLER

form of a normalized R

vs Temperature curve, but

DS(ON)

along the horizontal axis while the curve is approximately

δ = 0.005/°C can be used as an approximation for low

voltage MOSFETs.

flat divided by the specified change in V . This result is

DS

then multiplied by the ratio of the application applied V

DS

A Schottky diode can be placed in parallel with the bot-

tom MOSFET to conduct during the dead-time between

the conduction of the two power MOSFETs. This prevents

the body diode of the bottom MOSFET from turning on,

storing charge during the dead-time and requiring a re-

verse recovery period that could cost as much as 3% in

to the gate charge curve specified V . When the IC is

DS

operating in continuous mode the duty cycles for the top

and bottom MOSFETs are given by:

V

OUT

Main Switch Duty Cycle =

V

IN

efficiency at high V . A 1A to 3A Schottky is generally a

V − V

IN

OUT

Synchronous Switch Duty Cycle =

good compromise for both regions of operation due to

the relatively small average current. Larger diodes result

in additional transition losses due to their larger junction

capacitance.

V

IN

The MOSFET power dissipations at maximum output

current are given by:

Another consideration is the losses due to the gate charge

of the MOSFETs. Each cycle, the bottom FET gate driver

V

2

OUT

P

=

(I

) (1+ δ)R

+

DS(ON)

MAIN

MAX

V

IN

drawsapulseofcurrentfromtheINTV pinwhenturning

CC

⎛

⎜

⎝

⎞

I

2

MAX

on the bottom FET gate. Another pulse of current is drawn

by the boost capacitor as the bottom FET turns on. This

energy is used by the floating high side driver to turn on

(V )

(R )(C

) •

MILLER

⎟

IN

DR

⎠

2

⎡

⎢

⎣

⎤

1

+

(f)

⎥

thetopMOSFET.TheINTV decouplingcapacitorsmooths

CC

V

− V

V

THMIN

⎦

THMIN

INTVCC

the current flowing through the LDO. The resulting DC

V − V

current can be estimated as:

2

IN

OUT

P

=

(I ) (1+ δ)R

MAX

DS(ON)

SYNC

V

IN

I

GQ

= f(Q + Q )

GT GB

The LDO losses will then become:

= (V – V ) • I

where δ is the temperature dependency of R

DR

and

DS(ON)

R

(approximately 2Ω) is the effective driver resistance

P

LDO

IN

INTVCC

GQ

at the MOSFET’s Miller threshold voltage. V

is the

THMIN

To avoid the LDO losses, program V

for 5V with the

CC

with an internal

OUT

typical MOSFET minimum threshold voltage.

VOUTPRG pin. With this setting, the INTV LDO is shut

2

BothMOSFETshaveI RlosseswhilethetopsideN-channel

equation includes an additional term for transition losses,

down and the INTV pin is tied to V

CC

OUT

switch. This will provide significant power loss reductions

which are highest at high input voltages. For V < 20V

IN

for high input voltages.

the high current efficiency generally improves with larger

ThelossesinthegatedriverarealsoaffectedbytheMOSFET

gatecharge.Aconservativeestimateofthetheselossesis:

MOSFETs, while for V > 20V the transition losses rapidly

IN

increasetothepointthattheuseofahigherR

device

DS(ON)

withlowerC

actuallyprovideshigherefficiency.The

P

= I • V

GQ INTVCC

MILLER

GATE_DRIVE

synchronous MOSFET losses are greatest at high input

voltage when the top switch duty factor is low or during

Rev. A

26

For more information www.analog.com

LTC3372

APPLICATIONS INFORMATION ^{High Voltage Buck Controller}

C and C

Selection

Setting Output Voltage (HV Controller)

IN

OUT

The selection of C is usually based off the worst-case

The HV controller output voltage is set by the V

IN

OUTPRG

RMSinputcurrent.Thehighest(V )(I )productneeds

pin through an internal resistor voltage divider. When

OUT OUT

to be used in the formula to determine the maximum RMS

capacitor current requirement.

the V pin is tied to INTV , the output voltage is

OUTPRG

CC

regulated to 5V. When tied to ground, the output voltage

is regulated to 3.3V.

Incontinuousmode,thesourcecurrentofthetopMOSFET

is a square wave of duty cycle (V )/(V ). To prevent

OUT

IN

RUN Pin

large voltage transients, a low ESR capacitor sized for the

The HV controller is enabled using the RUN pin. It has a

rising threshold of 1.2V with 50mV of hysteresis. Pulling

the RUN pin below 1.15V shuts down the main control

loop.Pullingitbelow0.7Vdisablesthecontrollerandmost

maximumRMScurrentmustbeused.ThemaximumRMS

capacitor current is given by:

I

1/2

MAX

C Required I

≈

(V

)(V − V

)

[

]

IN

RMS

OUT

internal circuits, including the INTV LDOs.

CC

V

IN

Releasing the RUN pin allows a 0.5μA internal current to

pull up the pin to enable the controller. The RUN pin may

be externally pulled up to up to 60V (65V Abs Max).

This formula has a maximum at V = 2V , where I

IN

OUT

RMS

= I /2. This simple worst-case condition is commonly

OUT

used for design because even significant deviations do

not offer much relief. Note that capacitor manufacturers’

ripple current ratings are often based on only 2000 hours

of life. This makes it advisable to further derate the capaci-

tor, or to choose a capacitor rated at a higher temperature

than size or height requirements in the design. Due to the

high operating frequency, ceramic capacitors can also be

The RUN pin can be implemented as a UVLO by connect-

ing it to the output of an external resistor divider network

off V , as shown in Figure 4.

IN

TherisingandfallingUVLOthresholdsarecalculatedusing

the RUN pin thresholds:

⎛

⎞

⎟

⎠

R

used for C . Always consult the manufacturer if there is

B

A

IN

V

= 1.2V 1+

⎜

UVLO(RISING)

any question.

⎝

A small (0.1µF to 1µF) bypass capacitor between the

⎛

⎞

⎟

⎠

R

B

A

V

= 1.15V 1+

⎜

UVLO(FALLING)

chip V pin and ground, placed close to the IC, is also

IN

R

⎝

suggested. A small (<10Ω) resistor placed between C

IN

(C1) and the V pin provides further isolation.

IN

The resistor values should be carefully chosen such that

the absolute maximum ratings of the RUN pin do not get

violated over the entire V voltage range.

The selection of C

is driven by the effective series

OUT

resistance (ESR). Typically, once the ESR requirement

is satisfied, the capacitance is adequate for filtering. The

IN

ꢈ

ꢉꢇ

output ripple (V ) is approximated by:

OUT

R

ꢀꢁꢂꢃꢃꢄꢅ

Rꢆꢇ

ꢊ

⎛

⎜

⎝

⎞

⎟

⎠

1

ΔV

≈ ΔI ESR +

L

OUT

8 • f • C

A

OUT

ꢃꢃꢄꢅ ꢋꢌꢍ

where f is the operating frequency, C

is the output

OUT

capacitance and ∆I is the ripple current in the inductor.

Figure 4. Using the RUN Pin as a UVLO

L

The output ripple is highest at maximum input voltage

since ∆I increases with input voltage.

L

Rev. A

27

For more information www.analog.com

LTC3372

APPLICATIONS INFORMATION ^{High Voltage Buck Controller}

Tracking and Soft-Start (TRACK/SS Pin)

ꢀꢁꢂꢃꢃꢄꢅ

ꢁRAꢂꢆꢇꢈꢈ

The start-up of V

is controlled by the voltage on the

OUT

ꢂ

ꢈꢈ

TRACK/SS pin. When the voltage on the TRACK/SS pin

is less than the internal 1.2V reference, it regulates the

ꢈꢉꢊꢋ

ꢃꢃꢄꢅ ꢌꢍꢎ

internal V voltage to the voltage on the TRACK/SS pin

FB

Figure 5. Using the TRACK/SS Pin to Program Soft-Start

insteadof1.2V.TheTRACK/SSpincanbeusedtoprogram

an external soft-start function or to allow V

another supply during start-up.

to track

OUT

ꢄ

ꢅꢆꢂAꢇꢀꢃRꢈ

Soft-start is enabled by simply connecting a capacitor

from the TRACK/SS pin to ground, as shown in Figure 5.

An internal 10μA current source charges the capacitor,

providing a linear ramping voltage at the TRACK/SS pin.

ꢄ

ꢉꢊꢀꢆꢇꢋAꢄꢃꢈ

The HV controller will regulate the V (and hence V

)

FB

OUT

according to the voltage on the TRACK/SS pin, allowing

V

/EXTV torisesmoothlyfrom0Vtoitsfinalregulated

OUT

CC

value. The total soft-start time will be approximately:

ꢎꢎꢏꢐ ꢑꢒꢓꢔ

ꢀꢁꢂꢃ

1.2V

t

= C

•

SS

(6a) Coincident Tracking

10µA

ꢋ

Alternatively,theTRACK/SSpincanbeusedtotrackanother

supplyduringstart-up,asshownqualitativelyinFigures6a

and 6b. To do this, a resistor divider should be connected

ꢌꢍꢂAꢎꢀꢃRꢏ

ꢐꢑꢀꢍꢎꢒAꢋꢃꢏ

from the master supply (V ) to the TRACK/SS pin of the

X

ꢋ

slave supply (V /EXTV ) as shown in Figure 7. During

OUT

CC

start-up V /EXTV will track V according to the ratio

OUT

CC

X

set by the resistor divider:

V

1.2V

R

+R

TRACKB

X

TRACKA

ꢄꢄꢅꢆ ꢇꢈꢉꢊ

=

•

ꢀꢁꢂꢃ

V

R

TRACKA

OUT

OUT(REG)

(6b) Ratiometric Tracking

V

is the programmed output regulation voltage.

OUT(REG)

Figure 6. Two Different Modes of Output Voltage Tracking

If the V

pin it tied to INTV pin, V

= 5V.

OUTPRG

CC

OUT(REG)

pin is tied to ground, V

= 3.3V.

OUT(REG)

ꢆ

ꢉꢊꢋꢁꢆ

ꢇꢈꢁ

ꢂꢂ

INTV Regulation

CC

ꢇꢈꢁ

INTV powers the gate drivers and much of the internal

CC

ꢆ

ꢌ

ꢀꢁꢂꢃꢃꢄꢅ

circuitry. Power to the INTV pin is supplied either from

CC

theV pinthroughaninternallowdropoutlinearregulator

IN

R

ꢁRAꢂꢍꢑ

(LDO), or from the V /EXTV pin through an internal

OUT

CC

ꢁRAꢂꢍꢉꢎꢎ

switch, depending on the voltage at V /EXTV . The V

ꢃꢃꢄꢅ ꢏꢐꢄ

OUT

CC

IN

ꢁRAꢂꢍA

LDO regulates INTV to 5.1V. The INTV can supply a

CC

peak current of at least 50mA and must be bypassed to

ground with a minimum of 4.7μF ceramic capacitor. Good

Figure 7. Using the TRACK/SS Pin for Tracking

Rev. A

28

For more information www.analog.com

LTC3372

APPLICATIONS INFORMATION ^{High Voltage Buck Controller}

bypassing is needed to supply the high transient currents

required by the MOSFET gate drivers and to prevent in-

teraction between the channels.

Topside MOSFET Driver Supply (C , D )

B

An external bootstrap capacitor, C , connected to the

B

BOOST pin supplies the gate drive voltage for the topside

The INTV load current (I

) is dominated by the

MOSFET. Capacitor C in the Block Diagram is charged

CC

INTVCC

B

gate charge current and may be supplied by either the

V LDO or the V /EXTV pin. The gate charge current

though external diode D from INTV when the SW pin

B CC

is low. When the topside MOSFET is to be turned on, the

IN

OUT

CC

is dependent on operating frequency and NMOS size as

discussed in the Efficiency Considerations section.

driver places the C voltage across the gate-source of

B

the MOSFET. This enhances the top MOSFET switch and

turns it on. The switch node voltage, SW, rises to V and

IN

When the V /EXTV regulation is set to 3.3V, the V

OUT

CC

IN

the BOOST pin follows. With the topside MOSFET on, the

LDO is always enabled as the voltage on the V /EXTV

OUT

CC

boost voltage is above the input supply: V

= V +

BOOST

B

IN

pinisneverabovethe4.7Vthreshold.Powerdissipationfor

the IC in this case is highest and is equal to V • I

V

. The value of the boost capacitor, C , needs to be

INTVCC

.

IN INTVCC

100 times that of the total input capacitance of the top-

High input voltage applications in which large power

MOSFETs are being driven at high frequencies may cause

the maximum junction temperature rating for the IC to be

side MOSFET(s). The reverse breakdown of the external

Schottky diode must be greater than V

.

IN(MAX)

exceeded. For example, a 30mA INTV current from a

Fault Conditions: Current Limit and Current Foldback

CC

48V input supply will result in a junction temperature (T )

J

The HV controller includes current foldback to help limit

load current when the output is shorted to ground. If the

output voltage falls below 70% of its nominal output level,

then the maximum sense voltage is progressively lowered

from 100% to 45% of its maximum selected value. Under

short-circuit conditions with very low duty cycles, cycle

skippingwillbegininordertolimittheshort-circuitcurrent.

In this situation the bottom MOSFET will be dissipating

most of the power. The short-circuit ripple current is de-

increase (rise) of:

∆T = (30mA)(48V)(34°C/W for QFN) = 48°C

J

The power dissipation due to I

from V should be

IN

INTVCC

checked at the maximum V of the application operating

IN

in forced continuous mode.

When the V

regulation is set to 5V and V

rises

OUT

through an

above 4.7V, INTV is connected to V

CC

OUT

internal switch. Significant efficiency and thermal gains

terminedbytheminimumon-time, t

(seeElectrical

ON(MIN)

can be realized by powering INTV from the output, since

Characteristics), the input voltage and inductor value:

CC

the input supply current resulting from INTV current is

CC

⎛

⎜

⎝

⎞

⎟

⎠

V

IN

scaled by a factor of (V /V )/(efficiency). In this case,

OUT IN

ΔI

= t

L(SC) ON(MIN)

L

power dissipation in the LTC3372 due to the INTV cur-

CC

rent is V

• I

, and the junction temperature (T )

INTVCC INTVCC J

increase (rise) of:

The resulting average short-circuit current is:

1

∆T = (30mA)(5V)(34°C/W for QFN) = 5°C

I

= 45% •I

− ΔI

J

LIM(MAX)

SC

L(SC)

2

The LTC3372 junction temperature (T ) can be estimated

J

fromambienttemperature(T )andtotalpowerdissipation

A

Fault Conditions: Overvoltage Protection (Crowbar)

(P ) using the equations given in Note 2 of the Electrical

D

The overvoltage crowbar is designed to blow a system

input fuse when the output voltage of the regulator rises

muchhigherthannominallevels.Thecrowbarcauseshuge

currents to flow, that blow the fuse to protect against a

shorted top MOSFET if the short occurs while the control-

ler is operating.

Characteristics. To prevent the maximum junction tem-

peraturefrombeingexceeded,allpowerdissipationsfrom

the HV controller’s INTV current and the LV buck power

CC

stages must be considered.

Rev. A

29

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LTC3372

APPLICATIONS INFORMATION ^{High Voltage Buck Controller}

–

Both the V

and SENSE pins are monitored for over-

produce the most improvement. Percent efficiency can

OUT

voltage conditions. An overvoltage condition is detected

when either pin is 7.5% above the nominal output volt-

age. When this condition is sensed, the top MOSFET is

turned off and the bottom MOSFET is turned on until the

overvoltage condition is cleared. The bottom MOSFET

remains on continuously for as long as the overvoltage

be expressed as:

%Efficiency = 100% – (L1 + L2 + L3 + ...)

where L1, L2, etc. are the individual losses as a percent-

age of input power.

Although all dissipative elements in the circuit produce

losses, four main sources usually account for most of

condition persists; if V

returns to a safe level, normal

operation automatically resumes.

OUT

the losses in HV regulator: 1) IC V current, 2) INTV

IN

CC

2

regulator current, 3) I R losses, 4) topside MOSFET

AshortedtopMOSFETwillresultinahighcurrentcondition

which will open the system fuse. The switching regulator

will regulate properly with a leaky top MOSFET by altering

the duty cycle to accommodate the leakage.

transition losses.

1. The V current is the DC supply current given in the

IN

Electrical Characteristics table, which excludes MOS-

FET driver and control currents. V current typically

IN

Minimum On-Time Considerations

results in a small (<0.1%) loss.

The minimum on-time, t

, is the smallest time dura-

ON(MIN)

2. INTV current is the sum of the MOSFET driver and

CC

tion that the HV controller is capable of turning on the top

MOSFET. It is determined by internal timing delays and the

gate charge required to turn on the top MOSFET. Low duty

cycle applications may approach this minimum on-time

limit and care should be taken to ensure that:

control currents. The MOSFET driver current results

from switching the gate capacitance of the power

MOSFETs. Each time a MOSFET gate is switched

from low to high to low again, a packet of charge, dQ,

moves from INTV to ground. The resulting dQ/dt is

CC

V

a current out of INTV that is typically much larger

CC

OUT

t

<

ON(MIN)

than the control circuit current. In continuous mode,

V (f)

IN

I

= f(Q + Q ), where Q and Q are the gate

GATECHG

T B T B

charges of the topside and bottom side MOSFETs.

InapplicationswhenV /EXTV issetto5V,INTV

CC

If the duty cycle falls below what can be accommodated

by the minimum on-time, the controller will begin to skip

cycles. The output voltage will continue to be regulated,

but the ripple voltage and current will increase.

OUT

CC

is supplied through V /EXTV . This scales the V

OUT

CC

IN

current required for the driver and control circuits by

a factor of (Duty Cycle)/(Efficiency). For example, in a

The minimum on-time of top FET is typically 60ns. How-

ever, as the peak sense voltage decreases the minimum

on-time gradually increases. This is of particular concern

in forced continuous applications with low ripple current

at light loads. If the duty cycle drops below the minimum

on-timelimitinthissituation, asignificantamountofcycle

skipping can occur with correspondingly larger current

and voltage ripple.

20V to5V application, 10mA of INTV current results

CC

in approximately 2.5mA of V current. This reduces

IN

the midcurrent loss from 10% or more (if the driver

was powered directly from V ) to only a few percent.

IN

2

3. I RlossesarepredictedfromtheDCresistancesofthe

fuse (if used), MOSFET, inductor, current sense resis-

tor and input and output capacitor ESR. In continuous

mode the average output current flows through L and

Efficiency Considerations

R , but is chopped between the topside MOSFET

SENSE

The percent efficiency of a switching regulator is equal to

the output power divided by the input power times 100%.

It is often useful to analyze individual losses to determine

what is limiting the efficiency and which change would

and the synchronous MOSFET. If the two MOSFETs

have approximately the same R , then the re-

DS(ON)

sistance of one MOSFET can simply be summed with

the resistances of L, R

and ESR to obtain I2R

SENSE

Rev. A

30

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LTC3372

APPLICATIONS INFORMATION ^{High Voltage Buck Controller}

losses. For example, if each R

= 30mΩ, R =

ringing, which would indicate a stability problem. OPTI-

LOOP compensation allows the transient response to be

optimized over a wide range of output capacitance and

ESR values. The availability of the ITH pin not only allows

optimization of control loop behavior, but it also provides

a DC coupled and AC filtered closed-loop response test

point. The DC step, rise time and settling at this test

point truly reflects the closed-loop response. Assuming

a predominantly second order system, phase margin and/

or damping factor can be estimated using the percentage

of overshoot seen at this pin. The bandwidth can also be

estimated by examining the rise time at the pin. The ITH

external components in Typical Applications will provide

an adequate starting point for most applications.

DS(ON)

L

50mΩ,R

=10mΩandR =40mΩ(sumofboth

SENSE

ESR

input and output capacitance losses), then the total

resistance is 130mΩ. This results in losses ranging

from 3% to 13% as the output current increases from

1A to 5A for a 5V output, or a 4% to 20% loss for a

3.3V output. Efficiency varies as the inverse square

of V

for the same external components and output

OUT

power level. The combined effects of increasingly

lower output voltages and higher currents required

by high performance digital systems is not doubling

but quadrupling the importance of loss terms in the

switching regulator system!

4. TransitionlossesapplyonlytothetopsideMOSFET(s),

and become significant only when operating at high

input voltages (typically 15V or greater). Transition

losses can be estimated from:

The ITH series RC-CC filter sets the dominant pole-zero

loop compensation. The values can be modified slightly

to optimize transient response once the final PC layout is

done and the particular output capacitor type and value

have been determined. The output capacitors need to be

selected because the various types and values determine

the loop gain and phase. An output current pulse of 20%

to 80% of full-load current having a rise time of 1μs to

10μs will produce output voltage and ITH pin waveforms

that will give a sense of the overall loop stability without

breaking the feedback loop.

Transition Loss = (1.7) • V • 2 • I

• C

• f

RSS

IN

O(MAX)

Other hidden losses such as copper trace and internal

battery resistances can account for an additional 5%

to 10% efficiency degradation in portable systems. It

is very important to include these system level losses

during the design phase. The internal battery and fuse

resistancelossescanbeminimizedbymakingsurethat

C has adequate charge storage and very low ESR at

IN

Placing a power MOSFET directly across the output ca-

pacitor and driving the gate with an appropriate signal

generator is a practical way to produce a realistic load step

condition. The initial output voltage step resulting from

the step change in output current may not be within the

bandwidth of the feedback loop, so this signal cannot be

used to determine phase margin. This is why it is better

to look at the ITH pin signal which is in the feedback loop

andisthefilteredandcompensatedcontrolloopresponse.

the switching frequency. A 25W supply will typically

require a minimum of 20μF to 40μF of capacitance

having a maximum of 20mΩ to 50mΩ of ESR. Other

lossesincludingbodydiodeconductionlossesduring

dead-time and inductor core losses generally account

for less than 2% total additional loss.

Checking Transient Response

The regulator loop response can be checked by looking at

the load current transient response. Switching regulators

take several cycles to respond to a step in DC (resistive)

The gain of the loop will be increased by increasing RC

and the bandwidth of the loop will be increased by de-

creasing CC. If RC is increased by the same factor that

CC is decreased, the zero frequency will be kept the same,

thereby keeping the phase shift the same in the most

critical frequency range of the feedback loop. The output

voltage settling behavior is related to the stability of the

closed-loopsystemandwilldemonstratetheactualoverall

supply performance.

load current. When a load step occurs, V

shifts by an

OUT

amount equal to ∆I

(ESR), where ESR is the effective

LOAD

series resistance of C . ∆I

also begins to charge or

OUT

LOAD

discharge C

generating the feedback error signal that

OUT

forces the regulator to adapt to the current change and

return V to its steady-state value. During this recovery

OUT

time V

can be monitored for excessive overshoot or

OUT

Rev. A

31

For more information www.analog.com

LTC3372

APPLICATIONS INFORMATION ^{High Voltage Buck Controller}

A second, more severe transient is caused by switching

in loads with large (>1μF) supply bypass capacitors. The

discharged bypass capacitors are effectively put in paral-

Rounding down to the next standard value yields a sense

resistor value of 5mΩ.

Fora3.3V/10A333kHzconverteroperatingwithanominal

12V input and a 60V surge rating, a reasonable MOSFET

selection is:

lel with C , causing a rapid drop in V /EXTV . No

OUT

CC

regulator can alter its delivery of current quickly enough

to prevent this sudden step change in output voltage if

the load switch resistance is low and it is driven quickly. If

Top: RJK0651DPB

the ratio of C

to C

is greater than 1:50, the switch

LOAD

OUT

R

= 0.018Ω, Q = 15nC,

G

DS(ON)

MILLER

rise time should be controlled so that the load rise time is

limited to approximately 25 • C . Thus a 10μF capaci-

C

= 148pF, V

= 1.2V, V

= 60V

THMIN

DSS

LOAD

tor would require a 250μs rise time, limiting the charging

current to about 200mA.

Bottom: RJK0652DPB

= 0.009Ω, Q = 29nC, V = 60V

DSS

R

DS(ON)

G

Design Example

Atthenominalinputvoltageof12VwithT(estimated)=50°C,

the losses become:

As a design example, assume V = 12V (nominal),

IN

V

MAX

= 60V (max) for transient voltages, V

= 3.3V,

3.3V

12V

2

IN

OUT

P

=

(10A)

1 + (0.005)(50°C – 25°C)

[

](0.018Ω)

MAIN

I

= 10A, V

= 75mV and f = 333kHz. The

SENSE(MAX)

inductance value is chosen first based on a 30% ripple

current assumption. The highest value of ripple current

10A

2

+(12V)

(2Ω)(148pF) •

occurs at the maximum input voltage. Tie the R pin to

T

⎡

⎢

⎣

⎤

⎥

⎦

1

INTV (for better frequency accuracy over temperature,

CC

(333kHz)

+

5.1V − 1.2V 1.2V

use an external R = 400k to ground), generating 333kHz

T

operation for LTC3372’s HV controller (1/6 of f

at

= 557mW + 77mW

= 643mW

OSC

2MHz). The maximum ripple current is:

⎛

⎞

ꢂ

ꢃꢄꢅ

12V − 3.3V

ꢃꢄꢅ

2

⎜

⎟

Δꢀ =

ꢉ−

P

=

(10A) •

ꢁ

⎜

⎟

SYNC

ꢆꢇꢈꢆꢁꢈ

ꢂ

ꢀꢊꢆꢋAꢌꢈ

12V

1+(0.005)(50°C − 25°C) (0.009Ω)

⎝

⎠

[

]

A 2.2μH inductor will produce 43% ripple current which

is sufficiently close. The peak inductor current will be the

maximum DC value plus one half the ripple current, or

12.1A. Increasing the ripple current will also help ensure

that the minimum on-time of 60ns is not violated. The

= 734mW

Other losses include the gate drive and INTV LDO

CC

losses. These can be estimated from the gate charge and

switching frequency:

minimum on-time occurs at maximum V :

IN

I

GQ

= 333kHz (15nC + 29nC)

= 14.7mA

ꢇ

ꢌ.ꢌꢇ

ꢃꢋꢆ ꢍꢎꢇꢃꢌꢌꢌꢏꢐꢑꢆ

ꢁꢈꢉ

ꢅꢂꢃꢄAꢊꢆ

ꢀ

=

= ꢒꢍꢓꢔꢕ

ꢁꢂꢃꢄꢅꢂꢆ

ꢇ

P

= (12V – 5.1V) 14.7mA

= 101mW

LDO

The equivalent R

using the minimum value for the maximum current sense

threshold (68mV):

resistor value can be calculated by

SENSE

P

= 5.1V • 14.7mA

GATE_DRIVE

= 75mW

ꢃꢄꢅꢆ

R

≤

≈ ꢉ.ꢃꢅΩ

ꢀꢁꢂꢀꢁ

ꢇꢈ.ꢇA

Rev. A

32

For more information www.analog.com

LTC3372

APPLICATIONS INFORMATION ^{Low Voltage Buck Regulators}

With the input voltage at a sustained 60V and full load on

the output, the estimated power losses in the main FET

will be 2.0W and the LDO losses inside the chip will be

0.8W. Airflow will likely be required. A lower switching

regulatortransientresponsemayimprovewithanoptional

capacitor, C , that helps cancel the pole created by the

FF

feedback resistors and the input capacitance of the FB pin.

Experimentation with capacitor values between 2.2pF and

22pF may improve transient response.

frequency will reduce these losses and setting V

5V will avoid the LDO losses.

to

OUT

Input and Output Decoupling Capacitor Selection

A short-circuit to ground will result in a folded back cur-

rent of:

TheLTC3372buckregulatorshaveindividualinputsupply

pins for each buck power stage. Each of these pins must

be decoupled with low ESR capacitors to GND. These ca-

pacitors must be placed as close to the pins as possible.

Ceramic dielectric capacitors are a good compromise

between high dielectric constant and stability versus

temperature and DC bias. Note that the capacitance of a

capacitor deteriorates at higher DC bias. It is important

to consult manufacturer data sheets and obtain the true

capacitance of a capacitor at the DC bias voltage that it

will be operated at. For this reason, avoid the use of Y5V

dielectric capacitors. The X5R/X7R dielectric capacitors

offer good overall performance.

⎛

⎞

0.45(75mV) 1 60ns(22V)

I

=

−

= 6.6A

⎜

⎟

SC

0.005Ω

2

2.2µH

⎝

⎠

with a maximum value of R

and = (0.005/°C)(25°C)

DS(ON)

= 0.125. The resulting power dissipated in the bottom

MOSFET is:

ꢈ

ꢀ

= ꢅꢆ.ꢆAꢇ ꢅꢉ.ꢉꢈꢊꢇꢅꢋ.ꢋꢋꢌΩꢇ

= ꢍꢍꢉꢎꢏ

ꢁꢂꢃꢄ

whichislessthanunderfull-loadconditions.C ischosen

IN

for an RMS current rating of at least 5A at temperature

Each low voltage input power supply voltage V

Pins

IN,A-H

assuming only this channel is on. C

is chosen with an

OUT

5, 8, 9, 12, 25, 28, 29 and 32 all need to be de-coupled

withatleast10μFcapacitors.Ifpowerstagesarecombined

the supplies should be shorted with as short of a trace

as possible. Additionally, all LV buck regulator outputs

should be bypassed with a capacitor to ground of at least

22µF for 1A, 47µF for 2A, 68µF for 3A and 100µF for 4A

configurations.

ESR of 0.01Ω for low output ripple. The output ripple in

continuousmodewillbehighestatthemaximuminputvolt-

age.TheoutputvoltagerippleduetoESRisapproximately:

V

= R (∆I ) = 0.1Ω(4.3A) = 43mV

ESR L P-P

ORIPPLE

LOW VOLTAGE BUCK REGULATORS

Output Voltage and Feedback Network

Combined Buck Power Stages

The LTC3372 has eight powerstages thatcanhandle aver-

age load currents of 1A each. These power stages may be

combined in any one of eight possible combinations, via

the C1, C2, and C3 pins (see Table 1). Table 3, Table 4, and

Table 5 show recommended inductors for the combined

power stage configurations.

The output voltage of each LV buck switching regulators

is programmed by a resistor divider connected from the

switching regulator’s output to its feedback pin and is

given by V

= V (1 + R2/R1) as shown in Figure 8.

OUT

FB

Typical values for R1 range from 40k to 1M. The buck

ꢂ

ꢐꢎꢑꢊꢂ

ꢅꢅ

Fora2Acombinedbuckregulator, the inputsupplyshould

bede-coupledwitha22μFcapacitorwhiletheoutputshould

be de-coupled with a 47μF capacitor. Similarly, for 3A and

4A configurations the input and output capacitance must

be scaled up to account for the increased load.

ꢏꢄꢊ

ꢀ

ꢁꢂ ꢃꢄꢅꢆ

ꢅ

ꢏꢄꢊ

ꢒꢒ

ꢇꢈꢉꢊꢅꢋꢉꢌꢍ

RꢎꢍꢄꢁAꢊꢏR

Rꢖ

Rꢓ

ꢔꢔꢕꢖ ꢒꢗꢘ

ꢒꢃn

ꢏꢙꢊꢉꢏꢌAꢁ

Figure 8. Feedback Components

Rev. A

33

For more information www.analog.com

LTC3372

APPLICATIONS INFORMATION ^{Low Voltage Buck Regulators}

Table 2. Recommended Inductors for 1A Buck Regulators

f

PART NUMBER

XFL4020-472ME

74408943047

L (µH)

4.7

MAX I (A)

MAX DCR (mΩ)

SIZE IN mm (L × W × H) MANUFACTURER

OSC

DC

2.7

2.2

3.7

2.2

3

57.4

52

4 × 4 × 2.1

4.8 × 4.8 × 3.8

4 × 4 × 2.1

CoilCraft

1MHz

4.7

Wurth Elektronik

CoilCraft

XFL4020-222ME

2.2

23.5

84

2MHz DFE252012P-2R2M

IHLP1212BZER2R2M-11

2.2

2.5 × 2.0 × 1.2

3 × 3.65 × 2.0

3 × 3 × 2

Toko

2.2

46

Vishay

74438336015

3MHz

1.5

3.7

2.7

39

Wurth Elektronik

Toko

DFE252012F-1R5M

1.5

58

2.5 × 2 ×1.2

Table 3. Recommended Inductors for 2A Buck Regulators

f

PART NUMBER

XEL4020-222ME

74438356022

L (µH)

2.2

1

MAX I (A)

MAX DCR (mΩ)

SIZE IN mm (L × W × H) MANUFACTURER

OSC

DC

5.5

4.7

5.4

4.5

5.6

4.5

5.4

38.7

35

4 × 4 × 2.1

4.1 × 4.1 × 2.1

4 × 4 × 2.1

CoilCraft

1MHz

Wurth Elektronik

CoilCraft

XFL4020-102ME

11.9

24

2MHz IHLP1212BZER1R0M-11

SPM4020T-1R0M-LR

1

3 × 3.65 × 2.0

4.1 × 4.4 × 2

3 × 3 × 2

Vishay

1

28.1

27

TDK

744383360068

3MHz

0.68

Wurth Elektronik

Vishay

IHLP1212AEERR68M-11

22

3 × 3.65 × 1.5

Table 4. Recommended Inductors for 3A Buck Regulators

f

PART NUMBER

L (µH)

1.5

MAX I (A)

MAX DCR (mΩ)

SIZE IN mm (L × W × H) MANUFACTURER

OSC

DC

XEL4020-152ME

IHLP2020CZER1R5M11

XEL4020-821ME

7.4

7

23.6

18.5

13

4 × 4 × 2.1

5.18 × 5.49 × 3

4 × 4 × 2

CoilCraft

Vishay

1MHz

1.5

0.82

0.75

0.68

0.47

10.2

9.7

8.2

6.8

6.7

CoilCraft

Toko

2MHz FDV0530-H-R75M

744383560068

7.6

9

6.2 × 5.8 × 3

4.1 × 4.1 × 2.1

4.2 × 4.2 × 2

3 × 3.65 × 1.5

Wurth Elektronik

Toko

FDSD0420D-R47M

3MHz

18

IHLP1212AEERR47M-11

15

Vishay

Table 5. Recommended Inductors for 4A Buck Regulators

f

PART NUMBER

XEL4020-102ME

744316100

L (µH)

1

MAX I (A)

MAX DCR (mΩ)

SIZE IN mm (L × W × H) MANUFACTURER

OSC

DC

9

14.6

5.225

8.8

4 × 4 × 2.1

5.3 × 5.5 × 4.0

4 × 4 × 2.1

CoilCraft

1MHz

1

11.5

11.3

11.1

8.7

9

Wurth Elektronik

CoilCraft

XEL4020-561ME

0.56

0.47

0.33

2MHz FDV0530-H-R56M

SPM4020T-R47M-LR

6.3

6.2 × 5.8 × 3

4.1 × 4.4 × 2

4 × 4 × 1.4

Toko

11.8

12

TDK

XEL4014-331ME

3MHz

CoilCraft

744383560033

9.6

7.2

4.1 × 4.1 × 2.1

Wurth Elektronik

Rev. A

34

For more information www.analog.com

LTC3372

APPLICATIONS INFORMATION

Efficiency can be increased by combining more power

stages than are required to meet output current require-

ments. Conduction loss will decrease by adding power

stages. The overall efficiency will improve provided the

switching loss of the added power stage does not exceed

the reduction in conduction loss. For example, a buck

running at 900mA load may have a higher efficiency when

two power stages are combined to make a 2A buck. In this

example, the 900mA load is closer to the peak efficiency

power of the 2A buck this it is for a 1A buck. In addition

toefficiencyconcerns,combiningadditionalpowerstages

provides increased margin and transient capability. It is

therefore a good idea to explore combining any unused

power stages with active bucks in any given application.

Otherwise, any unused buck regulator should have it’s

possible to the IC. Ensure accurate current sensing

with Kelvin connections at the current sense resistor.

Don’t connect the current sensing leads backwards!

The output voltage may still be maintained but the

current mode control will not be realized.

4. Place the INTV decoupling capacitor close to the

CC

IC, between the INTV pin and power ground plane.

CC

This capacitor carries the MOSFET drivers’ current

peaks. A ceramic capacitor placed immediately next

totheINTV pincanhelpimprovenoiseperformance

CC

substantially.

5. Kelvin connect the return of the ITH network to an iso-

lated shape (ground copper “island”) tied to the GND

pad of the IC (refer to the ground copper “island(s)”

discussed in the Ground Planes section).

FB and EN pins tied to ground. The V pin may be tied to

IN

ground and the SW pin can float.

6. Keep the SW, TG, and BOOST nodes away from sensi-

+

–

tive control signals (I , SENSE , SENSE , RT, etc.).

TH

PRINTED CIRCUIT BOARD PCB LAYOUT

CONSIDERATIONS

These nodes have very large and fast moving signals

and therefore should be kept on the output side of the

HV regulator and occupy minimum PCB trace area.

PCB Layout Considerations for HV Regulator

Debugging HV Buck Controller on PCB

1. The path formed by the top N-channel MOSFET, the

bottom N-channel MOSFET, and the C

capacitor

1. Probeandsynchronizetheoscilloscopetotheswitch-

ing nodes (SW, SWA-H pins). It is helpful to use an

oscilloscope current probe to monitor the currents in

the inductors.

INTVCC

should have short leads and (PCB) trace lengths. The

output capacitor (–) terminals should be connected

as close as possible to the (–) terminals of the input

capacitor by placing the capacitor and kept away from

the loop described above.

2. Checkforproperperformanceovertheoperatingvolt-

age and current range expected in the application. The

frequency of operation should be maintained over the

inputvoltagerangedowntoneardropoutanduntilthe

peak of inductor current drops below the low current

operation threshold—typically 25% of the maximum

designed current level in Burst Mode operation.

For proper operation of the gate drivers, the BG and

TG traces should maintain low impedance. The length

of the BG and TG traces should be 1.0” or less and

the number of via should be kept minimum.

2. Kelvin connect the V /EXTV pin directly to the (+)

OUT

CC

terminal of C , or where the regulation needs to be.

In pulse-skipping mode, the frequency should main-

tain at even lower peak inductor current compared to

Burst Mode until a pulse is skipped to maintain the

regulation. The frequency in forced continuous mode

should not change with load current.

OUT

The connection should not be along the high current

input feeds from the input capacitor(s).

–

+

3. Route the SENSE and SENSE signals together with

minimum PCB trace spacing. The filter capacitor

+

–

between SENSE and SENSE should be as close as

Rev. A

35

For more information www.analog.com

LTC3372

APPLICATIONS INFORMATION

The duty cycle percentage should be maintained

from cycle to cycle in a well-designed, low noise PCB

implementation.

PCB Layout Considerations for LV Regulators

1. Each of the V input supply pins should have a

INA-H

decoupling capacitor. The connections of the decou-

pling capacitors to their respective V pins should

3. Variation in the duty cycle at a subharmonic rate

can suggest noise pickup at the current or voltage

sensing inputs or inadequate loop compensation.

Overcompensation of the loop can be used to tame a

poor PCB layout if regulator bandwidth optimization

is not required.

INA-H

be kept as short as possible. The GND side of these

capacitorsshouldconnectdirectlytothegroundplane

of the part. These capacitors provide the AC current

to the internal power MOSFETs and their drivers. It is

important to minimize inductance from these capaci-

tors to the V pins of the V

pins.

IN

INA-H

4. Reduce V from its nominal level to verify operation

IN

of the regulator in dropout. Check the operation of the

2. The switching power traces connecting SWA-H to the

inductorsshouldbeminimizedtoreduceradiatedEMI

and parasitic coupling. Due to the fast voltage swing

of the switching nodes, high input impedance sensi-

tive nodes, such as the feedback nodes, should be

shielded or kept far away from the switching nodes.

undervoltage lockout circuit by further lowering V

while monitoring the outputs to verify operation.

IN

5. Investigate if any problems exist only at higher output

currents or only at higher input voltages. If problems

coincide with high input voltages and low output cur-

rents,lookforcapacitivecouplingbetweentheBOOST,

SW,TG,andpossiblyBGconnectionsandthesensitive

voltage and current pins.

3. The return (GND side) of the switching regulators’

outputcapacitorsshouldbeconnectedtotheexposed

pad (Pin 49, GND) of the IC through a ground plane.

Minimize the trace length from the output capacitors

to the inductor(s)/pin(s).

If problems are encountered with high current output

loading at lower input voltages, look for inductive

coupling between C , bottom MOSFET, and the top

4. In a multiple power stage buck regulator application,

the trace length of switch nodes to the inductor must

be kept equal to ensure proper operation.

IN

MOSFETcomponentstothesensitivecurrentandvolt-

age sensing traces. In addition, investigate common

groundpathvoltagepickupbetweenthesecomponents

and the exposed ground pad of the IC.

5. Kelvin connect the returns for RT, CT and the feedback

dividerstoanisolatedshape(groundcopper“island”)

tied to the GND pad of the IC.

6. The capacitor placed across the current sensing pins

needs to be placed immediately adjacent to the pins

of the IC. This capacitor helps to minimize the effects

of differential noise injection due to high frequency

capacitive coupling.

Other PCB Layout Considerations

CareshouldbetakentominimizecapacitanceontheTEMP

pin. If the TEMP voltage must drive more than ~30pF,

then the pin should be isolated with a resistor placed

close to the pin of a value between 10k and 100k. Keep

in mind that any load on the isolation resistor will create

a proportional error.

7. If problems are encountered with high current output

loading at lower input voltages, look for inductive

coupling between C , Schottky and the top MOSFET

IN

componentstothesensitivecurrentandvoltagesens-

ing traces. In addition, investigate common ground

path voltage pickup between these components and

the exposed ground pad of the IC.

Rev. A

36

For more information www.analog.com

LTC3372

TYPICAL APPLICATIONS

4.5V to 60V Input 3.3V/3A Output HV Buck Converter Plus Quad 1V/1.2V/1.8V/2.5V LV Regulators

ꢀ

ꢁꢂ

ꢃꢄꢀ ꢅAꢆ

ꢇ.ꢈꢀ ꢅꢁꢂ

ꢀ

ꢄꢅꢆꢇ

ꢈꢉ

ꢀ

ꢁꢂꢃ

ꢃ.ꢃꢄꢅ

ꢆꢃ

ꢁꢂꢃ

ꢀ

ꢀꢁꢂꢃ

ꢄꢄ

ꢁꢂ

Rꢀꢁ

ꢀ.ꢁꢂꢃ

ꢀꢁ

ꢀꢁꢁꢂ

ꢀ.ꢀꢁꢂ

ꢀꢁꢂꢃ

ꢀꢁꢂ

ꢃ.ꢃꢄꢁ

ꢀꢁꢂꢃ

ꢀꢁꢂꢂꢃ

ꢁꢂꢃꢄRꢅ

ꢄꢄ

R

ꢀ

ꢀꢁ

SENSE

ꢀ.ꢁꢂꢃ

5mΩ

ꢀ.ꢁꢂꢃ

ꢀ

ꢄ.ꢄꢀ

ꢄAꢅ

ꢁꢂꢃ

ꢀꢁꢂ

ꢀꢁꢁꢂꢃ

ꢀꢁ

ꢀ

ꢁꢂꢃꢄ

ꢅꢆꢇꢈ

ꢁꢂꢃꢄ

ꢀꢁꢁꢂꢃ

10Ω

ꢄꢅꢆꢇꢈ

ꢉꢊ

ꢀꢁꢂꢃ

ꢀꢁ

ꢀꢁꢂ

ꢀ.ꢀꢁꢂꢃ

ꢀRAꢁꢂꢃꢄꢄ

ꢃ

ꢀꢁꢂꢀꢁ

ꢀꢁꢂ

ꢀꢁꢂꢀꢁ

ꢀ

ꢄꢅꢆꢃꢀ

ꢁꢂꢃ

ꢇꢇ

ꢁꢂꢃ

ꢀ

ꢁꢂꢃ

ꢁꢂA

ꢁꢂꢃ

ꢀꢁꢂꢃ

ꢄꢅ

ꢀꢁꢂꢃ

ꢄꢅ

ꢀꢁ

ꢁꢂꢃ

ꢀꢁ

ꢂꢃꢄ

ꢀꢁꢂꢃꢃꢄꢅ

ꢀ

ꢅ.ꢆꢀ

ꢅA

ꢁꢂꢃꢄ

ꢄꢀ

ꢅA

ꢁꢂꢃꢄ

ꢀꢁA

ꢀꢁꢂ

ꢀꢀꢁꢂ

ꢀꢁꢂꢃ

ꢀꢁꢂ

ꢀꢁꢂꢃ

ꢀ

ꢁꢂꢃ

ꢀ

ꢁꢂꢃ

ꢀꢁꢂꢃ

ꢄꢅ

ꢀꢁꢂꢃ

ꢄꢅ

ꢀꢁ

ꢂꢃꢄ

ꢀ

ꢁꢂꢃꢄ

ꢅ.ꢄꢀ

ꢀ

ꢅ.ꢆꢀ

ꢇA

ꢁꢂꢃꢄ

ꢀꢁꢂ

ꢄA

ꢀꢁꢀꢂ

ꢀꢁꢂꢃ

ꢀꢁꢂ

ꢀꢁꢂꢃꢄ Rꢅꢆꢇꢈꢉꢊꢋꢃꢌ

ꢀꢁꢂꢃꢄ ꢅꢁꢀꢆꢇꢈꢉꢊꢋꢌꢅꢍ

ꢀꢁꢂꢃ ꢄAꢀꢅꢆꢅꢆꢇꢈꢈꢈꢉꢊ

ꢀꢁꢂꢃ

ꢀꢁꢁꢂꢃꢄꢅꢆ

ꢀꢁꢂꢃ

ꢀꢁꢂ

ꢀ

ꢄ ꢅꢆꢇꢈꢇꢉꢊꢋ

ꢁꢂꢃ

Rꢀ

ꢀꢁ

ꢄ ꢅRꢆꢇꢃꢈRꢉꢃAꢃꢃꢊꢋAꢇꢊꢌ

ꢀꢁꢁꢂ

ꢅ ꢃꢆꢇꢈꢉꢄꢆꢊꢋꢈꢈꢌAꢃꢍꢈꢇꢆ

Rꢀꢁꢂ

ꢀꢁꢂꢃ

ꢄꢄ

ꢁꢂꢃꢄ

ꢅ ꢆRꢇꢈꢄꢉRꢊꢋAꢌꢊꢍꢎꢉꢋꢏ

A

RR

ꢀꢁ ꢀꢁ ꢀꢁ

ꢀꢁꢂ ꢀꢃꢄꢅꢁꢁꢆꢆ

ꢀꢁꢂꢃ

A

RR

R

ꢀꢁꢂꢃ

ꢀꢀꢁꢂ ꢃAꢄꢂ

HV Controller Efficiency and

Power Loss vs Output Current

HV Controller Forced Continuous

Mode Load Step

ꢀꢁꢁ

ꢀꢁꢁꢁꢁ

ꢀꢁꢁꢁ

ꢀꢁꢁ

ꢀꢁ

ꢀ

ꢀ ꢁꢂꢃ

ꢀꢁꢂ

ꢀꢁ

ꢀꢁRꢂꢃ ꢄꢅꢅꢆꢇꢆꢄꢈꢇꢉ

ꢀꢁ

ꢀ

ꢀ ꢁ.ꢁꢂ

ꢀ

ꢀꢁꢂ

Aꢀꢁꢀꢂꢃꢄꢅꢆꢇ

ꢀꢁꢂ ꢃꢄꢅꢅ

ꢀꢁꢁꢂꢃꢄꢅꢆꢃ

ꢀꢁꢂꢃꢄꢅꢃꢆꢇꢀꢀꢇꢈꢉ

ꢀꢁꢂꢂ

ꢀꢁRꢂꢃ ꢄꢅꢂꢂ

ꢀ

ꢀꢁAꢂ

ꢀAꢁꢂꢃꢄ

ꢀꢁꢂꢃꢄꢅꢃꢆꢇꢀꢀꢇꢈꢉ

ꢀꢁꢁꢂꢃꢂꢀꢄꢃꢅ

ꢀ

ꢀꢀꢁꢂ ꢃAꢄꢂꢅ

ꢀꢁꢁꢂꢃꢄꢅꢆꢇ

ꢀ

ꢀ ꢁꢂꢃ

ꢀꢁꢂ

ꢀꢁ

ꢀꢁꢂ ꢃꢀꢀꢄꢁꢄꢃꢅꢁꢆ

ꢀ.ꢁ

ꢀꢁꢂꢃꢁꢂ ꢄꢁRRꢅꢆꢂ ꢇAꢈ

ꢀ

ꢀ ꢁ.ꢁꢂ

ꢀ.ꢁ

ꢀ

ꢀ ꢁꢂꢂꢃA ꢄꢅ ꢆA

ꢀꢁAꢂ

ꢀ.ꢀꢀꢀꢁ ꢀ.ꢀꢀꢁ

ꢀ.ꢀꢁ

ꢀ

ꢀꢁ

ꢀꢀꢁꢂ ꢃAꢄꢂꢅ

Rev. A

37

For more information www.analog.com

LTC3372

TYPICAL APPLICATIONS

6V to 60V Input 5V/10A Output HV Buck Converter Plus Quad 1.2V/3A, 1.8V/1A, 2.5V/1A, and 3.3V/3A LV Regulators

ꢀ

ꢁꢂ

ꢃꢄꢀ ꢅAꢆ

ꢃꢀ ꢅꢁꢂ

ꢀ

ꢄꢅꢆꢇ

ꢈꢉ

ꢀ

ꢁꢂꢃ

ꢃ.ꢃꢄꢅ

ꢆꢃ

ꢀ

ꢀꢁꢂꢃ

ꢄꢄ

ꢁꢂ

Rꢀꢁ

ꢀ.ꢁꢂꢃ

ꢀꢁ

ꢀꢁꢁꢂ

ꢀꢁꢂꢃ

ꢀꢁꢂꢂꢃ

ꢀ

ꢄꢄ

ꢀꢁꢂꢃ

R

ꢀꢁ

SENSE

ꢀꢁꢂꢃ

ꢁꢂꢃꢄRꢅ

ꢄꢄ

3mΩ

ꢀ.ꢁꢂꢃ

ꢀ

ꢁꢂꢃ

ꢀ.ꢀꢁꢂ

ꢀꢁꢁꢂꢃ

ꢀꢁ

ꢄꢀ

ꢀ.ꢁꢁꢂ

ꢀꢁꢂ

ꢃ.ꢄꢅꢁ

ꢀꢁꢂꢃ

ꢅꢆAꢇ

ꢀꢁꢂ

ꢀ

ꢁꢂꢃꢄ

ꢀꢁꢁꢂꢃ

10Ω

ꢀꢁꢂ

ꢅꢆꢇꢈ

ꢅꢅꢆꢇꢈ

ꢀꢁ

ꢀ.ꢀꢁꢂꢃ

ꢃ

ꢀRAꢁꢂꢃꢄꢄ

ꢀꢁꢂꢀꢁ

ꢃ

ꢀꢁꢂꢀꢁ

ꢀꢁꢂ

ꢀ

ꢄꢅꢆꢃꢀ

ꢁꢂꢃ

ꢇꢇ

ꢀ

ꢁꢂA

ꢁꢂꢃ

ꢀꢁꢂꢃ

ꢄꢅ

ꢀ

ꢀꢁꢂꢃ

ꢄꢅ

ꢀ

ꢀꢁ

ꢂ.ꢃꢄꢅꢆ

ꢀꢁꢂꢃꢃꢄꢅ

ꢂ.ꢃꢄꢅꢆ

ꢀ

ꢅ.ꢅꢀ

ꢅA

ꢀꢁA

ꢀꢁꢂ

ꢀꢁꢃ

ꢀꢁꢂ

ꢀꢁꢃ

ꢀꢁꢄ

ꢀ

ꢁꢂꢃꢄ

ꢄ.ꢅꢀ

ꢆA

ꢀꢁꢀꢂ

ꢀꢁꢁꢂ

ꢀꢀꢁꢂ

ꢀꢁꢂꢃ

ꢀꢀꢁꢂ

ꢀꢁꢂ

ꢀꢁꢂꢃ

ꢀ

ꢁꢂꢃ

ꢀꢁꢂꢃ

ꢀꢁ

ꢁ.ꢁꢂꢃ

ꢀꢁ

ꢂ.ꢂꢃꢄ

ꢀ

ꢅ.ꢆꢀ

ꢇA

ꢀ

ꢁꢂꢃꢄ

ꢅ.ꢆꢀ

ꢅA

ꢀꢁꢂ

ꢀꢀꢁꢂ

ꢀꢁꢂꢃ

ꢀꢀꢁꢂ

ꢀꢁꢂ

ꢀꢁꢁꢂꢃꢄꢅꢆ

ꢀꢁꢂ

ꢀꢁꢂꢃ

ꢀꢁꢂ

ꢀꢁꢂꢃꢄ ꢅꢁꢀꢆꢇꢈꢉꢊꢋꢌꢅꢍ

ꢀꢁꢂꢃꢄ ꢅꢆꢀꢇꢈꢉꢊꢋꢌꢉꢅꢍ

ꢀꢁꢂꢃꢄAꢀꢅꢆꢅꢆꢇꢅꢈꢉꢊꢋ

ꢀꢁꢂꢃ

ꢀ

ꢄ ꢅꢆꢇꢈꢇꢉꢊꢋ

ꢁꢂꢃ

Rꢀ

ꢀꢁ

ꢀꢁꢂ

ꢀꢁꢁꢂ

ꢄ ꢅRꢆꢇꢃꢈRꢉꢃAꢃꢃꢊꢋAꢇꢊꢌ

Rꢀꢁꢂ

ꢀꢁꢂꢃ

ꢅ ꢆꢃꢇꢈꢉꢉꢊꢋAꢇ

ꢄꢄ

ꢁꢂꢃꢄ

ꢀꢁ ꢀꢁ ꢀꢁ

ꢅ ꢆRꢇꢈꢄꢉRꢊꢋAꢌꢊꢍꢎꢉꢋꢏ

A

RR

ꢀꢀꢁꢂ ꢃAꢄꢀꢅ

ꢀꢁꢂꢃ

A

RR

R

ꢀꢁꢂ ꢀꢃꢄꢅꢁꢁꢆꢆ

ꢀꢁꢂꢃ

ꢄꢄ

HV Controller Efficiency and

Power Loss vs Output Current

HV Controller Forced Continuous

Mode Load Step

ꢀꢁꢁ

ꢀꢁ

ꢀ

ꢀꢁꢁꢁꢁ

ꢀꢁꢁꢁ

ꢀꢁꢁ

ꢀꢁ

ꢀꢁRꢂꢃ ꢄꢅꢅꢆꢇꢆꢄꢈꢇꢉ

ꢀ

ꢀꢁꢂ

Aꢀꢁꢀꢂꢃꢄꢅꢆꢇ

ꢀꢁꢂ ꢃꢄꢅꢅ

ꢀꢁꢁꢂꢃꢄꢅꢆꢃ

ꢀꢁꢂꢃꢄꢅꢃꢆꢇꢀꢀꢇꢈꢉ

ꢀꢁꢂꢂ

ꢀꢁRꢂꢃ ꢄꢅꢂꢂ

ꢀ

ꢀꢁAꢂ

ꢀAꢁꢂꢃꢄ

ꢀꢁꢂꢃꢄꢅꢃꢆꢇꢀꢀꢇꢈꢉ

ꢀꢁꢁꢂꢃꢂꢀꢄꢃꢅ

ꢀ

ꢀꢀꢁꢂ ꢃAꢄꢀꢅ

ꢀꢁꢁꢂꢃꢄꢅꢆꢇ

ꢀ

ꢀ ꢁꢂꢃ

ꢀꢁ

ꢀꢁꢂ ꢃꢀꢀꢄꢁꢄꢃꢅꢁꢆ

ꢀ.ꢀꢁ ꢀ.ꢁ

ꢀ

ꢀ ꢁꢂ

ꢀꢁꢂ

ꢀꢁAꢂ

ꢀ.ꢁ

ꢀ

ꢀ ꢁꢂꢂꢃA ꢄꢅ ꢆꢁA

ꢀ.ꢀꢀꢀꢁ ꢀ.ꢀꢀꢁ

ꢀ

ꢀꢁꢀꢁ

ꢀꢁꢂꢃꢁꢂ ꢄꢁRRꢅꢆꢂ ꢇAꢈ

ꢀꢀꢁꢂ ꢃAꢄꢀꢅ

Rev. A

38

For more information www.analog.com

LTC3372

TYPICAL APPLICATIONS

4.5V to 60V Input 3.3V/10A Output HV Buck Converter Plus Quad 1V/4A, 1.2V/1A, 1.8V/1A and 2.5V/2A LV Regulators

ꢀ

ꢁꢂ

ꢃꢄꢀ ꢅAꢆ

ꢇ.ꢈꢀ ꢅꢁꢂ

ꢀ

ꢄꢅꢆꢇ

ꢈꢉ

ꢀ

ꢁꢂꢃ

ꢃ.ꢃꢄꢅ

ꢆꢃ

ꢁꢂꢃ

ꢀ

ꢀꢁꢂꢃ

ꢄꢄ

ꢁꢂ

Rꢀꢁ

ꢀꢁ

ꢀ.ꢁꢂꢃ

ꢀꢁꢁꢂ

ꢀ.ꢀꢁꢂ

ꢀꢁꢂꢃ

ꢀꢁꢂꢂꢃ

ꢁꢂꢃꢄRꢅ

ꢄꢄ

ꢀꢁꢂꢃ

R

ꢀ

ꢀꢁ

SENSE

3mΩ

ꢀ.ꢁꢂꢃ

ꢀ

ꢁꢂꢃ

ꢀ.ꢁꢂꢃ

ꢀꢁꢂ

ꢀꢁꢁꢂꢃ

ꢀꢁ

ꢄ.ꢄꢀ

ꢀꢁꢂ

ꢃꢄꢁ

ꢀꢁꢂꢃ

ꢅꢆAꢇ

ꢀ

ꢁꢂꢃꢄ

ꢀ

ꢁꢂꢃꢄ

ꢀꢁꢁꢂꢃ

10Ω

ꢄꢅꢆꢇꢈ

ꢉꢊ

ꢅꢆꢇꢈ

ꢀꢁ

ꢀꢁꢂ

ꢀ.ꢀꢁꢂꢃ

ꢀRAꢁꢂꢃꢄꢄ

ꢃ

ꢀꢁꢂꢀꢁ

ꢀꢁꢂ

ꢀꢁꢂꢀꢁ

ꢀ

ꢄꢅꢆꢃꢀ

ꢁꢂꢃ

ꢇꢇ

ꢀ

ꢁꢂꢃ

ꢁꢂA

ꢁꢂꢃ

ꢀꢁꢂꢃ

ꢄꢅ

ꢀꢁꢂꢃ

ꢄꢅ

ꢀꢁ

ꢂ.ꢃꢄꢅ

ꢀꢁ

ꢀꢁꢂꢃꢃꢄꢅ

ꢂ.ꢃꢄꢅ

ꢀ

ꢁꢂꢃꢄ

ꢀ

ꢀꢁA

ꢀꢁꢂ

ꢁꢂꢃꢄ

ꢄꢀ

ꢅA

ꢅ.ꢆꢀ

ꢅA

ꢀꢁꢂ

ꢀꢀꢁꢂ

ꢀꢁꢂꢃ

ꢄꢅ

ꢀꢁꢂꢃ

ꢀꢁꢂ

ꢀꢁꢂꢃ

ꢀ

ꢁꢂꢃ

ꢀ

ꢁꢂꢃ

ꢀꢁꢂꢃ

ꢀꢁ

ꢂ.ꢃꢄꢅ

ꢀꢁ

ꢂ.ꢃꢄꢅ

ꢀ

ꢅ.ꢆꢀ

ꢅA

ꢀ

ꢁꢂꢃꢄ

ꢅ.ꢄꢀ

ꢅA

ꢀꢁꢂ

ꢀꢁꢂꢃ

ꢀꢁꢀꢂ

ꢀꢀꢁꢂ

ꢀꢁꢂ

ꢀꢁꢂꢃ

ꢀꢁꢂ

ꢀꢁꢂꢃꢄ ꢅꢆꢇꢈꢉꢉꢊꢈꢋꢌꢆꢍ

ꢀꢁꢂꢃ

ꢀꢁꢂꢃꢄ ꢁꢅꢆꢇꢈꢉꢊꢇꢈꢋꢅꢌ

ꢀꢁꢂꢃ ꢄAꢀꢅꢆꢅꢆꢇꢅꢆꢈꢉꢊ

ꢀꢁꢁꢂꢃꢄꢅꢆ

Rꢀ

ꢀꢁ

ꢀ

ꢄ ꢅꢆꢇꢈꢇꢉꢊꢋ

ꢁꢂꢃ

ꢀꢁꢁꢂ

ꢄ ꢅRꢆꢇꢃꢈRꢉꢃAꢃꢃꢊꢋAꢇꢊꢌ

Rꢀꢁꢂ

ꢀꢁꢂꢃ

ꢄꢄ

ꢅ ꢃꢆꢇꢈꢉꢄꢆꢊꢋꢈꢈꢌAꢃꢍꢈꢇꢆ

ꢁꢂꢃꢄ

A

RR

ꢅ ꢆRꢇꢈꢄꢉRꢊꢋAꢌꢊꢍꢎꢉꢋꢏ

ꢀꢁ ꢀꢁ ꢀꢁ

ꢀꢁꢂꢃ

ꢀꢁꢁꢂ

A

RR

R

ꢀꢁꢂ ꢀꢃꢄꢅꢁꢁꢆꢆ

ꢀꢀꢁꢂ ꢃAꢄꢅꢆ

ꢄꢄ

HV Controller Efficiency and

Power Loss vs Output Current

HV Controller Forced Continuous

Mode Load Step

ꢀꢁꢁ

ꢀꢁꢁꢁꢁ

ꢀꢁꢁꢁ

ꢀꢁꢁ

ꢀꢁ

ꢀꢁRꢂꢃ ꢄꢅꢅꢆꢇꢆꢄꢈꢇꢉ

ꢀꢁ

ꢀ

ꢀꢁꢂ

Aꢀꢁꢀꢂꢃꢄꢅꢆꢇ

ꢀꢁꢂ ꢃꢄꢅꢅ

ꢀꢁꢁꢂꢃꢄꢅꢆꢃ

ꢀꢁꢂꢃꢄꢅꢃꢆꢇꢀꢀꢇꢈꢉ

ꢀꢁꢂꢂ

ꢀꢁRꢂꢃ ꢄꢅꢂꢂ

ꢀ

ꢀꢁAꢂ

ꢀAꢁꢂꢃꢄ

ꢀꢁꢂꢃꢄꢅꢃꢆꢇꢀꢀꢇꢈꢉ

ꢀꢁꢁꢂꢃꢂꢀꢄꢃꢅ

ꢀ

ꢀꢀꢁꢂ ꢃAꢄꢅꢆ

ꢀꢁꢁꢂꢃꢄꢅꢆꢇ

ꢀ

ꢀ ꢁꢂꢃ

ꢀꢁꢂ

ꢀꢁ

ꢀ

ꢀ ꢁ.ꢁꢂ

ꢀꢁꢂ ꢃꢀꢀꢄꢁꢄꢃꢅꢁꢆ

ꢀ.ꢁ

ꢀ

ꢀ ꢁꢂꢂꢃA ꢄꢅ ꢆꢁA

ꢀꢁAꢂ

ꢀ.ꢀꢀꢀꢁ ꢀ.ꢀꢀꢁ

ꢀ.ꢀꢁ

ꢀ.ꢁ

ꢀ

ꢀꢁꢀꢁ

ꢀꢁꢂꢃꢁꢂ ꢄꢁRRꢅꢆꢂ ꢇAꢈ

ꢀꢀꢁꢂ ꢃAꢄꢅꢆ

Rev. A

39

For more information www.analog.com

LTC3372

TYPICAL APPLICATIONS

4.5V (3V Minimum After Start-Up) to 50V Input HV SEPIC Converter Feeding Dual 3.3V/4A LV Regulators

ꢀ

ꢁꢂ

ꢃ.ꢄꢀ ꢅꢁꢂ

ꢄꢆꢀ ꢅAꢇ

ꢀ

ꢄꢅꢆꢇ

ꢈꢉ

ꢁꢂꢃ

ꢀ

ꢁꢂ

ꢁꢂꢃ

ꢀꢁꢂꢃ

ꢀ.ꢁꢂꢃ

ꢈꢉꢀ ꢅꢁꢂ

ꢀ

ꢄꢅꢆꢇ

ꢁ

ꢀ

ꢀꢁꢂꢃ

ꢄꢄ

AꢊꢋꢌR ꢍꢋARꢋꢎꢏꢐꢑ

ꢁꢂ

ꢂꢃꢄꢅ

ꢀꢁꢂ

Rꢀꢁ

ꢀ.ꢁꢂꢃ

ꢀꢁꢂ

ꢀꢁꢂꢃ

ꢀ

ꢀꢁꢁꢂ

ꢁꢂꢃ

ꢄꢀ

ꢀꢁꢂꢂꢃ

ꢀ

ꢄꢄ

ꢀꢁ

ꢀ

ꢁꢂꢃꢄ

ꢅꢆꢇꢈꢉ

ꢊꢋ

ꢀ

ꢀꢁꢂꢃ

ꢀꢁ

ꢁꢂꢃꢄ

ꢄꢄ

ꢁꢂꢃꢄRꢅ

ꢄꢄꢅꢆꢇ

ꢀ.ꢁꢂꢃ

ꢀꢁꢁꢂꢃ

100Ω

ꢀ.ꢁꢂꢃ

ꢀ

ꢀꢁꢁꢂꢃ

ꢀꢁꢂꢃ

ꢄꢄ

ꢁꢂ

ꢀꢁꢂꢃ

ꢀ.ꢁꢂꢃ

R

ꢀꢁꢂꢀꢁ

ꢀꢁ

ꢀꢁꢂ

100Ω

2mΩ

ꢀ.ꢀꢁꢂꢃ

ꢀꢁ

ꢀRAꢁꢂꢃꢄꢄ

ꢃ

ꢀꢁꢂꢀꢁ

ꢀꢁꢂ

ꢀꢁꢂꢀꢁ

ꢀ

ꢄꢅꢆꢃꢀ

ꢁꢂꢃ

ꢇꢇ

ꢁꢂꢃ

ꢀ

ꢁꢂꢃ

ꢁꢂA

ꢁꢂꢃ

ꢀꢁꢂꢃ

ꢄꢅ

ꢀꢁꢂꢃ

ꢄꢅ

ꢀ

ꢁꢂꢃ ꢀꢁꢂꢃꢃꢄꢅ

ꢁꢂꢃ

ꢀꢁ

ꢂ.ꢃꢃꢄꢅ

ꢀꢁA

ꢀꢁꢂ

ꢂ.ꢃꢃꢄꢅ

ꢀ

ꢅ.ꢅꢀ

ꢄA

ꢁꢂꢃꢄ

ꢅ.ꢅꢀ

ꢆA

ꢁꢂꢃꢄ

ꢀꢁꢂꢃ

ꢄꢅ

ꢀꢁꢁꢂ

ꢀꢁꢂꢃ

ꢄꢅ

ꢀꢁꢂ

ꢀꢁꢂꢃ

ꢀꢁꢂ ꢃꢄꢅꢆRꢇꢇꢈꢄꢉ

ꢀꢁꢂꢃꢄ ꢀꢁꢂꢅꢆ ꢇꢈꢈꢉꢊꢊꢈꢋꢃꢅꢋ

ꢀꢁꢂ

ꢀ

ꢄ ꢅꢆꢇꢈꢇꢉꢊꢋ

ꢁꢂꢃ

ꢁꢂꢃꢄ

ꢀꢁꢂ

ꢄ ꢅRꢆꢇꢃꢈRꢉꢊꢋꢊꢌꢍꢎAꢊꢃꢏ

ꢀꢁꢁꢂꢃꢄꢅꢆ

Rꢀ

ꢀꢁ

ꢀꢁꢂꢃ

ꢀꢁꢂ

ꢅ ꢃꢆꢇꢈꢉꢊꢋꢌꢍꢍꢉRꢍꢍꢎꢏ

ꢅ ꢆRꢇꢈꢄꢉRꢊꢋꢌꢄꢄꢍꢇꢉꢋꢎꢏ

ꢀꢁꢂ ꢃRꢄꢅꢆꢇRꢈꢉꢊꢉꢋꢌꢍAꢉꢆꢎ

ꢀꢁꢁꢂ

ꢀꢁꢂꢃ ꢀꢄꢅꢆꢇꢇꢈꢈ

Rꢀꢁꢂ

ꢀꢁꢂꢃ

ꢄꢄ

ꢀꢁ ꢀꢁ ꢀꢁ

ꢀꢁꢁꢂ

ꢀꢁꢂꢃ

ꢄꢄ

ꢀꢀꢁꢂ ꢃAꢄꢅꢆ

HV Controller Efficiency and

Power Loss vs Output Current

HV Controller V_INStep Response

ꢀꢁꢁ

ꢀꢁ

ꢀ

ꢀꢁꢁꢁꢁ

ꢀ

ꢀꢁꢂ

ꢀꢁRꢂꢃ ꢄꢅꢅꢆꢇꢆꢄꢈꢇꢉ

Aꢀꢁꢀꢂꢃꢄꢅꢆꢇ

ꢀꢁꢁꢁ

ꢀꢁꢁ

ꢀꢁ

ꢀꢁꢁꢂꢃꢄꢅꢆꢃ

ꢀꢁꢂ

ꢀꢁRꢂꢃ ꢄꢅꢂꢂ

ꢀꢁ

ꢀ

ꢀꢁ

ꢀꢁꢂꢃꢄꢅꢃꢆꢇꢀꢀꢇꢈꢉ

ꢀꢁꢁꢂꢃꢂꢀꢄꢃꢅ

ꢀꢁꢂꢃꢄꢁ

ꢀ

ꢀꢀꢁꢂ ꢃAꢄꢅꢆ

ꢀꢁꢁꢂꢃꢄꢅꢆꢇ

ꢀꢁꢂꢃꢄꢅꢃꢆꢇꢀꢀꢇꢈꢉ

ꢀꢁꢂꢂ

ꢀ

ꢀꢁAꢂ

ꢀ ꢁꢂ

ꢀ ꢁ.ꢂA

ꢀꢁꢂ

ꢀ

ꢀ.ꢁ

ꢀ.ꢀꢀꢀꢁ ꢀ.ꢀꢀꢁ

ꢀ.ꢀꢁ

ꢀ.ꢁ

ꢀ

ꢀꢁꢂꢃꢁꢂ ꢄꢁRRꢅꢆꢂ ꢇAꢈ

ꢀꢀꢁꢂ ꢃAꢄꢅꢆ

Rev. A

40

For more information www.analog.com

LTC3372

TYPICAL APPLICATIONS

6V to 60V Input 5V/20A Output HV Buck Converter Plus Triple 3.3V/4A, 1.8V/1A and 1.2V/3A LV Regulators

ꢀ

ꢁꢂ

ꢃꢄꢀ ꢅAꢆ

ꢇꢀ ꢅꢁꢂ

ꢀ

ꢄꢅꢆꢇ

ꢈꢉ

ꢁꢂꢃ

ꢃꢄꢄꢅꢆ

ꢇꢈ

ꢀ

ꢀꢁꢂꢃ

ꢄꢄ

ꢁꢂ

Rꢀꢁ

ꢀꢁ

ꢀ.ꢁꢂꢃ

ꢀꢁꢁꢂ

ꢀꢁꢂꢃ

ꢀꢁꢂꢂꢃ

ꢄꢄ

ꢀꢁꢂꢃ

ꢀꢁꢂ

ꢃꢄꢁ

ꢀ

ꢀꢁ

ꢄꢄ

ꢁꢂꢃꢄRꢅ

ꢀ.ꢁꢁꢂ

ꢀ.ꢁꢂꢃ

ꢀ

ꢁꢂꢃ

ꢀ.ꢁꢂꢃ

ꢀꢁꢂ

ꢀꢁꢁꢂꢃ

ꢀꢁ

ꢄꢀ

ꢅꢆAꢇ

ꢀ

ꢁꢂꢃꢄ

ꢀ.ꢁꢂꢃ

ꢀꢁꢁꢂꢃ

ꢀ

ꢁꢂꢃꢄ

ꢄꢄꢅꢆꢇ

ꢀꢁꢁꢂꢃ

ꢅꢅꢆꢇꢈ

ꢉꢊ

ꢀꢁꢂꢃ

ꢀꢁ

ꢀ.ꢀꢁꢂꢃ

ꢀRAꢁꢂꢃꢄꢄ

ꢃ

ꢀꢁꢂꢀꢁ

ꢀꢁꢂ

ꢀꢁꢂꢀꢁ

ꢀ

ꢄꢅꢆꢃꢀ

ꢁꢂꢃ

ꢇꢇ

ꢁꢂꢃ

ꢀ

ꢁꢂꢃ

ꢁꢂA

ꢁꢂꢃ

ꢀ

ꢀꢁꢂꢃ

ꢄꢅ

ꢀꢁ

ꢂ.ꢃꢄꢅꢆ

ꢀꢁꢂꢃ

ꢄꢅ

ꢀ

ꢁꢂꢃ

ꢀꢁ

ꢂ.ꢃꢄꢅꢆ

ꢀꢁꢂꢃꢃꢄꢅ

ꢀꢁA

ꢀꢁꢂ

ꢀ

ꢅ.ꢆꢀ

ꢇA

ꢀꢁꢂ

ꢁꢂꢃꢄ

ꢅ.ꢅꢀ

ꢆA

ꢁꢂꢃꢄ

ꢀꢁꢂꢃ

ꢄꢅ

ꢀꢁꢁꢂ

ꢀꢁꢂꢃ

ꢀꢁꢀꢂ

ꢀꢁꢂꢃ

ꢀꢀꢁꢂ

ꢀꢁꢂ

ꢀꢁꢀꢂ

ꢀ

ꢁꢂꢃ

ꢀꢁꢂꢃ

ꢀꢁ

ꢂ.ꢂꢃꢄ

ꢀ

ꢅ.ꢆꢀ

ꢅA

ꢁꢂꢃꢄ

ꢀꢁꢂ

ꢀꢁꢂꢃ

ꢀꢀꢁꢂ

ꢀꢁꢂ

ꢀꢁꢂꢃꢄ ꢅꢆꢇꢈꢉꢊꢋꢈꢊꢌꢆꢍ

ꢀꢁꢂꢃꢄ ꢁꢅꢆꢇꢈꢇꢉꢇꢊꢋꢅꢌ

ꢀꢁꢂꢃ ꢄAꢀꢅꢆꢅꢆꢇꢅꢆꢈꢉꢊ

ꢀꢁꢂ

ꢀꢁꢂꢃ

ꢀꢁꢁꢂꢃꢄꢅꢆ

Rꢀ

ꢀꢁ

ꢀꢁꢂꢃ

ꢀꢁꢂ

Rꢀꢁꢂ

ꢀ

ꢄ ꢅꢀꢆꢃꢇꢃꢈꢃꢉꢀꢊꢃꢋꢌ

ꢁꢂꢃ

ꢁꢂꢃꢄ

ꢀꢁꢁꢂ

ꢄ ꢅRꢆꢇꢃꢈRꢉꢊꢋꢊꢌꢍꢎAꢊꢃꢏ

ꢀꢁꢂꢃ

ꢅ ꢆꢃꢇꢈꢉꢉꢊꢋAꢇ

ꢄꢄ

A

RR

ꢅ ꢆRꢇꢈꢄꢉRꢊꢋꢌꢄꢄꢍꢇꢉꢋꢎꢏ

ꢀꢁ ꢀꢁ ꢀꢁ

ꢀꢁꢂꢃ

A

RR

R

ꢀꢁꢂ ꢀꢃꢄꢅꢁꢁꢆꢆ

ꢀꢁꢂꢃ

ꢄꢄ

ꢀꢀꢁꢂ ꢃAꢄꢅꢆ

HV Controller Efficiency and

Power Loss vs Output Current

HV Controller Forced Continuous

Mode Load Step

ꢀꢁꢁ

ꢀꢁ

ꢀꢁꢁꢁꢁ

ꢀꢁRꢂꢃ ꢄꢅꢅꢆꢇꢆꢄꢈꢇꢉ

ꢀ

ꢀꢁꢂ ꢃꢄꢅꢅ

ꢀꢁꢂ

ꢀꢁ

ꢀꢁꢁꢁ

ꢀꢁꢁ

ꢀꢁ

Aꢀꢁꢀꢂꢃꢄꢅꢆꢇ

ꢀꢁꢁꢂꢃꢄꢅꢆꢃ

ꢀꢁ

ꢀꢁꢂꢃꢄꢅꢃꢆꢇꢀꢀꢇꢈꢉ

ꢀꢁ

ꢀ

ꢀꢁꢂꢂ

ꢀꢁRꢂꢃ ꢄꢅꢂꢂ

ꢀ

ꢀꢁAꢂ

ꢀꢁAꢂꢃꢄꢅ

ꢀꢁꢂꢃꢄꢅꢃꢆꢇꢀꢀꢇꢈꢉ

ꢀꢁꢁꢂꢃꢂꢀꢄꢃꢅ

ꢀ

ꢀꢀꢁꢂ ꢃAꢄꢅꢆ

ꢀꢁꢁꢂꢃꢄꢅꢆꢇ

ꢀ

ꢀ ꢁꢂꢃ

ꢀꢁ

ꢀꢁꢂ ꢃꢀꢀꢄꢁꢄꢃꢅꢁꢆ

ꢀ.ꢁ

ꢀꢁꢂꢃꢁꢂ ꢄꢁRRꢅꢆꢂ ꢇAꢈ

ꢀ

ꢀ ꢁꢂ

ꢀꢁꢂ

ꢀꢁAꢂ

ꢀ.ꢁ

ꢀ

ꢀ ꢁꢂꢂꢃA ꢄꢅ ꢁꢂA

ꢀ.ꢀꢀꢀꢁ ꢀ.ꢀꢀꢁ ꢀ.ꢀꢁ

ꢀ

ꢀꢁ ꢀꢁ

ꢀꢀꢁꢂ ꢃAꢄꢅꢆ

Rev. A

41

For more information www.analog.com

LTC3372

PACKAGE DESCRIPTION

UK Package

48-Lead Plastic QFN (7mm × 7mm)

(Reference LTC DWG # 05-08-ꢀ704 Rev C)

0.70 0.05

5.ꢀ5 0.05

5.50 REF

6.ꢀ0 0.05 7.50 0.05

(4 SIDES)

5.ꢀ5 0.05

PACKAGE OUTLINE

0.25 0.05

0.50 BSC

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

0.75 0.05

R = 0.ꢀꢀ5

TYP

7.00 0.ꢀ0

(4 SIDES)

R = 0.ꢀ0

TYP

47 48

0.40 0.ꢀ0

PIN ꢀ TOP MARK

(SEE NOTE 6)

ꢀ

2

PIN ꢀ

CHAMFER

C = 0.35

5.ꢀ5 0.ꢀ0

5.50 REF

(4-SIDES)

5.ꢀ5 0.ꢀ0

(UK48) QFN 0406 REV C

0.200 REF

0.25 0.05

0.50 BSC

BOTTOM VIEW—EXPOSED PAD

0.00 – 0.05

NOTE:

ꢀ. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WKKD-2)

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN ꢀ LOCATION ON THE TOP AND BOTTOM OF PACKAGE

Rev. A

42

For more information www.analog.com

LTC3372

REVISION HISTORY

REV

DATE

DESCRIPTION

PAGE NUMBER

A

03/19 Updated conditions in the Electrical Characteristics tables

4, 6

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog

Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications

43

subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

For more information www.analog.com

LTC3372

TYPICAL APPLICATION

ꢀ

ꢁꢂ

ꢃꢄꢀ ꢅAꢆ

ꢇꢀ ꢅꢁꢂ

ꢀ

ꢄꢅꢆꢇ

ꢈꢉ

ꢁꢂꢃ

ꢃꢄꢄꢅꢆ

ꢇꢈ

ꢀ

ꢀꢁꢂꢃ

ꢄꢄ

ꢁꢂ

Rꢀꢁ

ꢀꢁ

ꢀ.ꢁꢂꢃ

ꢀꢁꢁꢂ

ꢀꢁꢂꢃ

ꢀꢁꢂꢂꢃ

ꢄꢄ

ꢀꢁꢂꢃ

ꢀꢁꢂ

ꢃꢄꢁ

ꢀꢁꢂꢃ

ꢀ

ꢀꢁ

ꢄꢄ

ꢁꢂꢃꢄRꢅ

ꢀ.ꢁꢁꢂ

ꢀ.ꢁꢂꢃ

ꢀ

ꢁꢂꢃ

ꢀꢁꢂ

ꢀꢁꢁꢂꢃ

ꢀꢁ

ꢄꢀ

ꢅꢆAꢇ

ꢀꢁꢁꢂꢃ

ꢀ

ꢁꢂꢃꢄ

ꢀ.ꢁꢂꢃ

ꢀꢁꢁꢂꢃ

ꢀ

ꢁꢂꢃꢄ

ꢄꢄꢅꢆꢇ

ꢅꢅꢆꢇꢈ

ꢉꢊ

ꢀꢁꢂꢃ

ꢀꢁ

ꢀ.ꢀꢁꢂꢃ

ꢀRAꢁꢂꢃꢄꢄ

ꢃ

ꢀꢁꢂꢀꢁ

ꢀꢁꢂ

ꢀꢁꢂꢀꢁ

ꢀ

ꢁꢂꢃ

ꢁꢂA

ꢁꢂꢃ

ꢀ

ꢄꢅꢆꢃꢀ

ꢁꢂꢃ

ꢇꢇ

ꢁꢂꢃ

ꢀꢁꢂꢃ

ꢄꢅ

ꢀꢁ

ꢂ.ꢃꢄꢅꢆ

ꢀ

ꢁꢂꢃ

ꢀ

ꢀꢁꢂꢃ

ꢄꢅ

ꢀ

ꢀꢁ

ꢂ.ꢃꢄꢅꢆ

ꢁꢂꢃ

ꢀꢁA

ꢀꢁꢂ

ꢀ

ꢅ.ꢆꢀ

ꢇA

ꢀꢁꢂ

ꢁꢂꢃꢄ

ꢅ.ꢅꢀ

ꢆA

ꢁꢂꢃꢄ

ꢀꢁꢂꢃꢃꢄꢅ

ꢀꢁꢂꢃ

ꢄꢅ

ꢀꢁꢁꢂ

ꢀꢁꢂꢃ

ꢀꢁꢀꢂ

ꢀꢁꢂꢃ

ꢀꢀꢁꢂ

ꢀꢁꢂ

ꢀꢁ

ꢂ.ꢂꢃꢄ

ꢀ

ꢁꢂꢃꢄ

ꢀꢁꢂ

ꢀ

ꢅ.ꢆꢀ

ꢅA

ꢁꢂꢃ

ꢀꢁꢂꢃꢄ ꢅꢆꢇꢈꢉꢊꢋꢈꢊꢌꢆꢍ

ꢀꢁꢂꢃꢄ ꢁꢅꢆꢇꢈꢇꢉꢇꢊꢋꢅꢌ

ꢀꢁꢂꢃ ꢄAꢀꢅꢆꢅꢆꢇꢅꢆꢈꢉꢊ

ꢀꢁꢂꢃ

ꢀꢀꢁꢂ

ꢀꢁꢂ

ꢀ

ꢄ ꢅꢀꢆꢃꢇꢃꢈꢃꢉꢀꢊꢃꢋꢌ

ꢀꢁꢂꢃ

ꢁꢂꢃ

ꢁꢂꢃꢄ

ꢀꢁꢁꢂꢃꢄꢅꢆ

Rꢀ

ꢀꢁ

ꢀꢁꢂꢃ

ꢀꢁꢂ

ꢄ ꢅRꢆꢇꢃꢈRꢉꢊꢋꢊꢌꢍꢎAꢊꢃꢏ

ꢅ ꢆꢃꢇꢈꢉꢉꢊꢋAꢇ

ꢀꢁꢂ

Rꢀꢁꢂ

A

RR

ꢀꢁꢁꢂ

ꢅ ꢆRꢇꢈꢄꢉRꢊꢋꢌꢄꢄꢍꢇꢉꢋꢎꢏ

ꢀꢁꢂꢃ

A

RR

R

ꢀꢁ ꢀꢁ ꢀꢁ

ꢀꢁꢂ ꢀꢃꢄꢅꢁꢁꢆꢆ

ꢄꢄ

ꢀꢁꢂꢃ

ꢄꢄ

ꢀꢀꢁꢂ ꢃAꢄꢁ

RELATED PARTS

PART NUMBER

DESCRIPTION

COMMENTS

Phase-Lockable Frequency 75kHz to 750kHz, 4V ≤ V ≤ 60V, 0.8V ≤ V

LTC3891/LTC3890/

60V, Low I , Single/Dual

≤ 24V, I =50μA

Q

IN

OUT

LTC3890-1/LTC3890-2/ Synchronous Step-Down DC/

LTC3891: Single Channel; LTC3890/LTC3890-1/LTC3890-2/LTC3890-3

LTC3890-3

DC Controller

LTC3371/LTC3370

4-Channel Configurable DC/DC 4 Synchronous Buck Regulators with 8 × 1A Power Stages. Can Connect Up to Four Power

with 8 × 1A Power Stages

Stages in Parallel, 8 Output Configurations Possible.

LTC3370: Precision PGOODALL Indication, 32-Lead (5mm × 5mm × 0.75mm) QFN Package.

LTC3371: Precision RST Monitoring with Windowed Watchdog Timer (CT Programmable),

38-Lead (5mm × 7mm × 0.75mm) QFN and TSSOP Packages

LTC3892/LTC3892-1/

LTC3892-2

60V, Low I , Dual, 2-Phase

Phase-Lockable Frequency 75kHz to 850kHz, 4.5V ≤ V ≤ 60V, 0.8V ≤ V

Q

≤ 99% V ,

OUT IN

Q

IN

Synchronous Step-Down DC/

DC Controller

I = 29μA, Adjustable 5V to 10V Gate Drive, No External Bootstrap Diode

2

LTC3589

LTC3675

LTC3676

8-Output Regulator with

Triple I C Adjustable High Efficiency Step-Down DC/DC Converters: 1.6A, 1A, 1A. High

Efficiency 1.2A Buck-Boost DC/DC Converter, Triple 250mA LDO Regulators, 40-Lead

(6mm × 6mm × 0.75mm) QFN.

2

Sequencing and I C

7-Channel Configurable High

Power PMIC

Quad Synchronous Buck Regulators (1A, 1A, 500mA, 500mA). Buck DC/DCs Can be Paralleled

to Deliver Up to 2× Current with a Single Inductor. 1A Boost, 1A Buck- Boost, 40V LED Driver.

44-Lead (4mm × 7mm × 0.75mm) QFN Package.

8-Channel Power Management Quad Synchronous Buck Regulators (2.5A, 2.5A, 1.5A, 1.5A). Quad LDO Regulators (300mA,

Solution for Application

Processor

300mA, 300mA, 25mA). 40-Lead (6mm × 6mm × 0.75mm) QFN Package.

LTC3375/LTC3374/

LTC3374A

8-Channel Programmable

Configurable 1A DC/DC

8 × 1A Synchronous Buck Regulators. Can Connect Up to Four Power Stages in Parallel with

a Single Inductor, 15 Output Configurations Possible, 48-Lead (7mm × 7mm × 0.75mm) QFN

Package (LTC3375) 38-Lead (5mm × 7mm × 0.75mm) QFN and TSSOP Packages (LTC3374A)

Rev. A

D16975-0-3/19(A)

www.analog.com

 ANALOG DEVICES, INC. 2018-2019

44

For more information www.analog.com


型号：	LTC3370
厂家：	Linear
描述：	60V Low IQ Buck Controller Plus 4-Channel 8A Configurable Buck DC/DCs
文件：	总44页 (文件大小：5626K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC3370 [Linear]

相关型号：

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LTC3374A

LTC3374EFEPBF

LTC3374EUHFPBF

LTC3374HFEPBF

LTC3374HUHFPBF

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LTC3374IUHFPBF