ISL59830IAZ [INTERSIL]

True Single Supply Video Driver; 真正的单电源视频驱动器
ISL59830IAZ
型号: ISL59830IAZ
厂家: Intersil    Intersil
描述:

True Single Supply Video Driver
真正的单电源视频驱动器

驱动器 商用集成电路 光电二极管 信息通信管理 放大器
文件: 总14页 (文件大小:416K)
中文:  中文翻译
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ISL59830  
®
Data Sheet  
August 15, 2005  
FN7489.2  
True Single Supply Video Driver  
Features  
• Triple single-supply buffer  
The ISL59830 is a revolutionary device that allows true single-  
supply operation of video amplifiers. The device runs off a  
single 3.3V supply and generates the required negative  
voltage internally. This allows for DC-accurate coupling of  
video onto a 75double-terminated line. SInce the buffers  
have an integrated 6dB gain, the only external components  
required are the 75termination resistors. An input reference  
voltage can be supplied to shift the analog video level down  
by an amount equal to the reference (typically 0.6V).  
• Operates from single +3.3V supply  
• No output DC blocking capacitor needed  
• Fixed gain of 2 output buffer  
• Output three-statable  
• Enable/disable functions  
• 50MHz 0.1dB bandwidth  
Ordering Information  
• 300MHz -3dB bandwidth  
TAPE &  
• Pb-free plus anneal available (RoHS compliant)  
PART NUMBER  
ISL59830IA  
PACKAGE  
16 Ld QSOP  
16 Ld QSOP  
REEL  
PKG. DWG.#  
M16.15A  
Applications  
• Driving video  
-
13”  
-
ISL59830IA-T13  
M16.15A  
ISL59830IAZ  
(See Note)  
16 Ld QSOP  
(Pb-Free)  
M16.15A  
Pinout  
ISL59830  
(16 LD QSOP)  
TOP VIEW  
ISL59830IAZ-T13  
(See Note)  
16 Ld QSOP  
(Pb-Free)  
13”  
M16.15A  
NOTE: Intersil Pb-free plus anneal products employ special Pb-free  
material sets; molding compounds/die attach materials and 100%  
matte tin plate termination finish, which are RoHS compliant and  
compatible with both SnPb and Pb-free soldering operations. Intersil  
Pb-free products are MSL classified at Pb-free peak reflow  
temperatures that meet or exceed the Pb-free requirements of  
IPC/JEDEC J STD-020.  
RIN  
GIN  
1
2
3
4
5
6
7
8
16 ROUT  
15 GOUT  
14 BOUT  
13 VCC  
12 EN  
BIN  
REF  
VEE  
GND  
11 VCC  
10 NC  
VEEOUT  
DGND  
9
DVCC  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
1
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.  
Copyright © Intersil Americas Inc. 2005. All Rights Reserved.  
All other trademarks mentioned are the property of their respective owners.  
ISL59830  
Absolute Maximum Ratings (T = 25°C)  
A
V
, Supply Voltage between V and GND5V  
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C  
Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C  
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C  
Lead Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C  
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves  
CC  
S
V
, V  
. . . . . . . . . . . . . . . . . . . . . . . . . . . .VCC+0.3V, VEE-0.3V  
IN REF  
Voltage between V and V  
. . . . . . . . . . . . . . . . . . . . . . . . . .±2V  
REF  
IN  
Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . . 30mA  
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the  
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.  
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests  
are at the specified temperature and are pulsed tests, therefore: T = T = T  
A
J
C
AC Electrical Specifications  
PARAMETER  
V
= DV  
= +3.3V, REF = GND, T = 25°C, R = 150, unless otherwise specified.  
CC A L  
CC  
DESCRIPTION  
3dB Bandwidth  
CONDITIONS  
= 200mV  
MIN  
TYP  
200  
100  
50  
MAX  
UNIT  
MHz  
MHz  
MHz  
V/µs  
%
BW -3dB  
V
V
V
V
OUT  
OUT  
OUT  
OUT  
PP  
= 2V  
= 2V  
= 2V  
PP  
PP  
PP  
BW 0.1dB  
0.1dB Bandwidth  
Slew Rate  
S
500  
R
G
P
d
d
Differential Gain  
Differential Phase  
Hostile Crosstalk  
Input to Output Isolation  
Input Noise Voltage  
.06  
0.1  
-90  
-70  
20  
°
X
I
6MHz  
6MHz  
dB  
T
dB  
V
nV/Hz  
MHz  
mV  
N
CSW Freq  
Load Reg  
Charge Pump Switch Frequency  
168  
12  
I
= 0mA to 10mA  
60  
EE  
V
Ripple Voltage  
30  
mV  
RIPPLE  
DC Electrical Specifications  
V
= D = +3.3V, REF = GND, T = 25°C, R = 150, unless otherwise specified.  
VCC A L  
CC  
PARAMETER  
DESCRIPTION  
CONDITIONS  
MIN  
TYP  
MAX  
3.6  
UNIT  
V
V+  
Supply Range  
Gain Error  
3.0  
V %  
G
R
R
= 150, V = +2.5V to -1V  
1.5  
%
L
IN  
GM  
Gain Matching  
= 150Ω  
0.5  
1.7  
7
%
L
R
Input Resistance  
Output Offset Voltage  
Output Current  
V
V
= 0V to 1.5V  
1.0  
-25  
50  
15  
MΩ  
mV  
mA  
mA  
IN  
IN  
V
= 0  
+25  
OS  
REF  
I
I
R
R
= 10, V = 1.2V  
IN  
OUT +  
OUT -  
L
L
Output Current  
= 10, V = -0.3V  
IN  
-18  
Z
Output Impedance  
Enabled  
1
OUT  
Three-stated  
10  
90  
MΩ  
dB  
mA  
kΩ  
PSRR  
Power Supply Rejection Ratio  
Supply Current  
60  
4
I
Enabled  
150  
6
S
R
Input Reference Resistor  
5
REF  
FN7489.2  
2
August 15, 2005  
ISL59830  
Pin Descriptions  
PIN NUMBER  
PIN NAME  
PIN FUNCTION  
EQUIVALENT CIRCUIT  
1
RIN  
Analog input  
V
CC  
V
EE  
CIRCUIT 1  
2
3
4
GIN  
BIN  
Analog input  
Analog input  
Reference input  
Reference Circuit 1  
Reference Circuit 1  
REF  
R
IN  
IN  
IN  
V
CC  
R
OUT  
G
B
+
-
G
OUT  
OUT  
B
3
REF  
V
EE  
CIRCUIT 2  
5
VEE  
Chip substrate  
V
CC  
V
EE OUT  
-
+
D
GND  
V
EE  
CHARGE  
PUMP  
D
VCC  
CIRCUIT 3  
6
7
GND  
VEE OUT  
DGND  
DVCC  
NC  
Analog ground  
Charge pump output  
Charge pump ground  
Charge pump supply voltage  
Not connected  
Reference Circuit 3  
Reference Circuit 3  
Reference Circuit 3  
8
9
10  
11, 13  
12  
VCC  
Positive power supply  
Chip enable  
EN  
V
CC  
V
EE  
CIRCUIT 4  
FN7489.2  
3
August 15, 2005  
ISL59830  
Pin Descriptions (Continued)  
PIN NUMBER  
PIN NAME  
PIN FUNCTION  
EQUIVALENT CIRCUIT  
14  
BOUT  
Analog output  
V
CC  
V
EE  
CIRCUIT 5  
15  
16  
GOUT  
ROUT  
Analog output  
Analog output  
Reference Circuit 5  
Reference Circuit 5  
Typical Performance Curves  
3
5
A =+2  
A =+2  
V
V
9pF  
C =0pF  
R =500  
L
L
2
1
4.7pF  
2.2pF  
3
1
1kΩ  
0
500Ω  
0pF  
-1  
-3  
-5  
-1  
-2  
-3  
150Ω  
75Ω  
1M  
10M  
100M  
1G  
100K  
1M  
10M  
100M  
1G  
FREQUENCY (Hz)  
FREQUENCY (Hz)  
FIGURE 1. GAIN vs FREQUENCY FOR VARIOUS R  
FIGURE 2. GAIN vs FREQUENCY FOR VARIOUS C  
LOAD  
LOAD  
5
300  
A =+2  
V
A =+2  
V
C =0pF  
L
R =500Ω  
0
-5  
L
-3dB ROLL-OFF  
R =500Ω  
L
240  
180  
120  
60  
-10  
-15  
-20  
-25  
-30  
-35  
-0.1dB ROLL-OFF  
0
1
100  
200  
300  
400  
500  
2.25  
2.8  
3.35  
3.9  
4.45  
5
FREQUENCY (MHz)  
SUPPLY VOLTAGE (V)  
FIGURE 3. V  
PIN OUTPUT FREQUENCY RESPONSE  
FIGURE 4. GAIN ROLL-OFF vs FREQUENCY  
REF  
FN7489.2  
August 15, 2005  
4
ISL59830  
Typical Performance Curves (Continued)  
-30  
-20  
-30  
-40  
-50  
-60  
-70  
-80  
-90  
-100  
A =+2  
V
A =+2  
V
-40  
-50  
R =500Ω  
R =500Ω  
L
L
-60  
ENABLED  
-70  
ENABLED  
-80  
DISABLED  
-90  
DISABLED  
100M  
-100  
-110  
-120  
100K  
1M  
10M  
FREQUENCY (Hz)  
100M  
1G  
100K  
1M  
10M  
1G  
FREQUENCY (Hz)  
FIGURE 5. CROSS TALK CHANNEL TO CHANNEL (TYPICAL)  
FIGURE 6. INPUT TO OUTPUT ISOLATION vs FREQUENCY  
200  
120  
A =+2  
V
-3dB  
R =500Ω  
L
100  
80  
60  
40  
20  
0
160  
A =+2  
V
R =500Ω  
L
120  
80  
40  
0
-0.1dB  
68  
1
1.5  
2
2.5  
3
3.5  
27  
47.5  
88.5  
109  
129.5  
150  
SUPPLY VOLTAGE (V)  
TEMPERATURE (°C)  
FIGURE 7. SUPPLY CURRENT vs SUPPLY VOLTAGE  
FIGURE 8. BANDWIDTH vs TEMPERATURE  
95  
100  
10  
A =+2  
V
R =500Ω  
L
90  
85  
80  
75  
1
0.1  
0.01  
27  
55.6  
84.2  
112.8  
141.4  
170  
10K  
100K  
1M  
10M  
100M  
TEMPERATURE (°C)  
FREQUENCY (Hz)  
FIGURE 9. SUPPLY CURRENT vs TEMPERATURE  
FIGURE 10. OUTPUT IMPEDANCE vs FREQUENCY  
FN7489.2  
August 15, 2005  
5
ISL59830  
Typical Performance Curves (Continued)  
-10  
1K  
100  
10  
-30  
-50  
e
N
PSRR-  
-70  
PSRR+  
I +  
N
1
-90  
I -  
N
-110  
0.1  
1K  
10K  
100K  
1M  
10M  
100M  
10  
100  
1K  
10K  
100K  
1M  
10M  
FREQUENCY (Hz)  
FREQUENCY (Hz)  
FIGURE 11. POWER SUPPLY REJECTION RATIO vs  
FREQUENCY  
FIGURE 12. VOLTAGE AND CURRENT NOISE vs FREQUENCY  
-30  
-40  
-30  
-40  
THD  
-50  
-60  
-50  
THD  
F
=10MHz  
-60  
-70  
-80  
-90  
IN  
-70  
2ND HD  
3RD HD  
10  
-80  
THD  
-90  
F
=1MHz  
IN  
-100  
0
20  
30  
40  
0.5  
1
1.5  
2
2.5  
3
3.5  
FUNDAMENTAL FREQUENCY (MHz)  
OUTPUT VOLTAGE (V  
FIGURE 14.  
)
P-P  
FIGURE 13. HARMONIC DISTORTION vs FREQUENCY  
0
-0.02  
-0.04  
-0.06  
-0.08  
0
-0.02  
-0.04  
-0.06  
-0.08  
IRE  
IRE  
FIGURE 15. DIFFERENTIAL GAIN  
FIGURE 16. DIFFERENTIAL PHASE  
FN7489.2  
August 15, 2005  
6
ISL59830  
Typical Performance Curves (Continued)  
TIME (200ns/DIV)  
TIME (200ns/DIV)  
FIGURE 17. DISABLE TIME  
FIGURE 18. ENABLE TIME  
TIME (10ns/DIV)  
TIME (10ns/DIV)  
FIGURE 19. SMALL SIGNAL RISE & FALL TIME  
FIGURE 20. LARGE SIGNAL RISE & FALL TIMES  
3.25  
3
2.75  
A =+2  
V
C =3.9pF  
L
2.5  
50  
250  
450  
650  
850  
1050  
TIME (20ns/DIV)  
LOAD RESISTANCE ()  
FIGURE 21. CHARGE PUMP OSCILLATION  
FIGURE 22. MAXIMUM OUTPUT MAGNITUDE vs LOAD  
RESISTANCE  
FN7489.2  
August 15, 2005  
7
ISL59830  
Typical Performance Curves (Continued)  
1.6  
1.6  
1.2  
0.8  
0.4  
0
BACKDRIVE ACROSS 5RESISTOR  
A =+2  
V
TYPICAL CHANNEL  
1.2  
R =500Ω  
L
C =3.9pF  
L
0.8  
0.4  
0
0
1
2
3
4
5
2.2 2.4 2.6 2.8  
3
3.2 3.4 3.6 3.8  
4
BACKDRIVE VOLTAGE (V)  
SUPPLY VOLTAGE (V)  
FIGURE 23. BACKDRIVE VOLTAGE vs CURRENT  
FIGURE 24. PEAKING vs SUPPLY VOLTAGE  
JEDEC JESD51-3 LOW EFFECTIVE THERMAL  
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL  
CONDUCTIVITY TEST BOARD  
1.4  
CONDUCTIVITY TEST BOARD  
1.8  
1.6  
1.2  
1
1.4  
1.116W  
1.2  
791mW  
0.8  
1
0.8  
0.6  
0.4  
0.2  
0
0.6  
0.4  
0.2  
0
0
25  
50  
75 85 100  
125  
150  
0
25  
50  
75 85 100  
125  
150  
AMBIENT TEMPERATURE (°C)  
AMBIENT TEMPERATURE (°C)  
FIGURE 25. PACKAGE POWER DISSIPATION vs AMBIENT  
TEMPERATURE  
FIGURE 26. PACKAGE POWER DISSIPATION vs AMBIENT  
TEMPERATURE  
FN7489.2  
August 15, 2005  
8
ISL59830  
Block Diagram  
3.3V  
R
G
B
IN  
IN  
IN  
Y
+
R
OUT  
6dB  
-
REFERENCE  
Pb  
Pr  
+
G
OUT  
6dB  
-
+
B
OUT  
6dB  
-
-1.5V CHARGE  
PUMP  
0.1nF  
V
= 2V - V  
IN REFERENCE  
OUT  
Demo Board Schematic  
RED_IN  
R
75Ω  
1
RED_OUT  
R
R
R
75Ω  
75Ω  
75Ω  
4
5
6
GREEN_IN  
BLUE_IN  
1
2
3
4
5
6
7
8
RIN  
ROUT 16  
R
75Ω  
2
GIN  
GOUT 15  
BOUT 14  
VCC 13  
EN 12  
GREEN_OUT  
BLUE_OUT  
BIN  
V
CC  
C
3
0.1µF  
REF  
C
0.1µF  
4
R
75Ω  
3
VEE  
GND  
VEEOUT  
VCC 11  
NC 10  
ENABLE  
2
1
V
CC  
C
0.1µF  
2
C
0.1µF  
5
3
V
DGND DVCC 9  
CC  
REFERENCE  
CONTROL  
FN7489.2  
August 15, 2005  
9
ISL59830 + DC-Restore Solution  
1
2
3
4
5
6
7
8
IN1  
IN2 16  
COM1 COM2 15  
NC  
V-  
NC 14  
V+ 13  
NC 12  
NC 11  
R
2kΩ  
7
GND  
NC  
COM4 COM3 10  
YO  
Pb  
Pr  
R
75Ω  
1
IN4  
IN3 9  
Pb  
R
2kΩ  
R
8
2kΩ  
ISL43140  
9
YO  
Pr  
YO  
Pb  
Pr  
C
20pF  
5
L
L
L
1
2
3
C
C
C
0.1µF  
0.1µF  
0.1µF  
R
R
R
75Ω  
75Ω  
75Ω  
4
4
4
4
5
6
1
2
3
4
5
6
7
8
RIN  
ROUT 16  
R
2
75Ω  
GIN  
GOUT 15  
BOUT 14  
VCC 13  
EN 12  
C
20pF  
5
BIN  
V
CC  
REF  
REF  
C
C
C
5
20pF  
4
3
R
3
75Ω  
V
(-1.6V)  
EE  
0.1µF  
0.1µF  
VEE  
GND  
VEEOUT  
VCC 11  
NC 10  
R
1kΩ  
8
ENABLE  
V
V
V
CC  
CC  
CC  
2
1
V
+ C  
1
CC  
REFERENCE  
CONTROL  
C
0.1µF  
2
C
0.1µF  
1µF  
5
3
DGND DVCC  
ISL59830  
9
GND  
COMP  
VDD  
1
2
3
4
8
7
6
5
SYNC OUT  
C
2
C
4
COMP  
0.1µF  
OUT  
VIDEO IN  
0.1µF  
VSYNC  
OUT  
RESET  
R
C
2
0.1µF  
8
BACK  
PORCH  
OUT  
681Ω  
GND  
EL1881  
ISL59830  
distortion, low power, and high frequency amplifier capable  
of driving moderately capacitive loads with near rail-to-rail  
performance.  
Description of Operation and Application  
Information  
Theory Of Operation  
Input Output Range  
The ISL59830 is a highly practical and robust marriage of  
three high bandwidth, high speed, low power, rail-to-rail  
voltage feedback amplifiers with a charge pump, to provide a  
negative rail without an additional power supply. Designed to  
operate with a single supply voltage range of from 0V to  
3.3V, the ISL59830 eliminates the need for a split supply with  
the incorporation of a charge pump capable of generating a  
bottom rail as much as 1.6V below ground; for a 4.9V range  
on a single 3.3V supply. This performance is ideal for NTSC  
video with its negative-going sync pulses.  
The three amplifier channels have an input common mode  
voltage range from 0.15V below the bottom rail to within  
100mV of the positive supply, V + pin (Note: bottom rail is  
S
established by the charge pump at negative one half the  
positive supply). As the input signal moves outside the  
specified range, the output signal will exhibit increasingly  
higher levels of harmonic distortion. And of course, as load  
resistance becomes lower, the current drive capability of the  
device will be challenged and its ability to drive close to each  
rail is reduced. For instance, with a load resistance of 1kΩ  
the output swing is within a 100mV of the rails, while a load  
resistance of 150limits the output swing to within around  
300mV of the rails.  
The Amplifier  
The ISL59830 fabricated on a dielectrically isolated high  
speed 5V Bi-CMOS process with 4GHz PNPs and NPN  
transistor exceeding 20GHz - perfect for low distortion, low  
power demand and high frequency circuits. While the  
ISL59830 utilizes somewhat standard voltage mode  
feedback topologies, there are many non-standard analog  
features providing its outstanding bandwidth, rail-to-rail  
operation, and output drive capabilities. The input signal  
initially passes through a folded cascode, a topology  
providing enhanced frequency response essentially by fixing  
the base collector voltage at the junction of the input and  
gain stage. The collector of each input device looks directly  
into an emitter that is tied closely to ground through a  
resistor and biased with a very stable DC source. Since the  
voltage of this collector is "locked stable" the effective  
bandwidth limiting of the Miller capacitance is greatly  
reduced. The signal is then passed through a second fully-  
realized differential gain stage and finally through a  
proprietary common emitter output stage for improved rail-  
to-rail output performance. The result is a highly-stable, low  
Amplifier Output Impedance  
To achieve near rail-to-rail performance, the output stage of  
the ISL59830 uses transistors in the common emitter  
configuration, typically producing higher output impedance  
than the standard emitter follower output stage. The  
exceptionally high open loop gain of the ISL59830 and local  
feedback reduces output impedance to less than a 2at low  
frequency. However, since output impedance of the device is  
exponentially modulated by the magnitude of the open loop  
gain, output impedance increases with frequency as the  
open loop gain decreases with frequency. This inductive-like  
effect of the output impedance is countered in the ISL59830  
with proprietary output stage topology, keeping the output  
impedance low over a wide frequency range and making it  
possible to easily and effectively drive relatively heavy  
capacitive loads.(See Figure 10).  
I +  
N
I -  
N
OUT  
BIAS  
FIGURE 27.  
FN7489.2  
11  
August 15, 2005  
ISL59830  
capacitor placed as close to the pin and connected to the  
The Charge Pump  
ground plane of the board.  
The ISL59830 charge pump provides a bottom rail up to  
1.65V below ground while operating on a 0V to 3.3V power  
supply. The charge pump is internally regulated to one-half  
the potential of the positive supply. This internal multi-phase  
charge pump is driven by a 160MHz differential ring  
oscillator driving a series of inverters and charge storage  
circuitry. Each series inverter charges and places parallel  
adjoining charge circuitry slightly out of phase with the  
immediately preceding block. The overall effect is sequential  
discharge and generation of a very low ripple of about 10mV  
that is applied to the amplifiers providing a negative rail of up  
to -1.65V.  
Input, Output, and Supply Voltage Range  
The ISL59830 is designed to operate with a single supply  
voltage range of from 0V to 3.3V. The need for a split supply  
has been eliminated with the incorporation of a charge pump  
capable of generating a bottom rail as much as 1.6V below  
ground, for a 4.9V range on a single 3.3V supply. This  
performance is ideal for NTSC video with its negative-going  
sync pulses.  
Video Performance  
For good video performance, an amplifier is required to  
maintain the same output impedance and the same  
frequency and phase response as DC levels are changed at  
the output. This is especially difficult when driving a standard  
video load of 150because of the change in output current  
with changing DC levels. Special circuitry has been  
incorporated into the ISL59830 for the reduction of output  
impedance variation with the current output. This results in  
outstanding differential gain and differential phase  
specifications of 0.06% and 0.1°, while driving 150at a  
gain of +2. Driving higher impedance loads would result in  
similar or better differential gain and differential phase  
performance.  
TIME (20ns/DIV)  
NTSC  
FIGURE 28. CHARGE PUMP OSCILLATION  
The ISL59830, generating a negative rail internally, is ideally  
suited for NTSC video with its accompanying negative-going  
sync signals; easily handled by the ISL59830 without the  
need of an additional supply as the ISL59830 generates a  
negative rail with an internal charge pump referenced at  
negative 1/2 the positive supply.  
The system operates at sufficiently high frequencies that any  
related charge pump noise is far beyond standard video  
bandwidth requirements. Still, appropriate bypassing  
discipline must be observed, and all pins related to either the  
power supply or the charge pump must be properly  
bypassed. See "Power Supply Bypassing and Printed Circuit  
Board Layout" in this section.  
YPbPr  
YPbPr signals originating from a DVD player requiring three  
channels of very tightly-controlled amplifier gain accuracy  
present no difficulty for the ISL59830. Specifically, this  
standard encodes sync on the Y channel and it is a negative-  
going signal; easily handled by the ISL59830 without the  
need of an additional supply as the ISL59830 generates a  
negative rail placed at negative 1/2 the positive supply.  
Additionally, the Pb and Pr are bipolar analog signals and  
the video signals are negative-going; and again easily  
handled by the ISL59830.  
The V  
Pin  
REF  
Applying a voltage to the V  
pin simply places that  
REF  
voltage on what would usually be the ground side of the gain  
resistor of the amplifier, resulting in a DC-level shift of the  
output signal. Applying 100mV to the Vref pin would apply a  
100mV DC level shift to an incoming signal. The charge  
pump providing sufficient bottom room to accommodate the  
shifted signal.  
See Block Diagram on page 8.  
Driving Capacitive Loads and Cables  
The V Pin  
EE  
The V pin is the output pin for the charge pump. A  
EE  
The ISL59830, internally-compensated to drive 75cables,  
will drive 10pF loads in parallel with 1kwith less than 5dB  
of peaking. If less peaking is required, a small series resistor,  
usually between 5to 50, can be placed in series with the  
output. This will reduce peaking at the expense of a slight  
closed loop gain reduction. When used as a cable driver,  
double termination is always recommended for reflection-  
free performance. For those applications, a back-termination  
series resistor at the amplifier's output will isolate the  
voltmeter applied to this pin will display the output of the  
charge pump. This pin does not affect the functionality of the  
part. One may use this pin as an additional voltage source.  
Keep in mind that the output of this pin is generated by the  
internal charge pump and a fully regulated supply that must  
be properly bypassed. We recommend a 0.1µF ceramic  
FN7489.2  
12  
August 15, 2005  
ISL59830  
amplifier from the cable and allow extensive capacitive drive.  
Where:  
However, other applications may have high capacitive loads  
without a back-termination resistor. Again, a small series  
resistor at the output can help to reduce peaking. The  
ISL59830 is a triple amplifier designed to drive three  
channels; simply deal with each channel separately as  
described in this section.  
T
= Maximum junction temperature  
= Maximum ambient temperature  
JMAX  
T
AMAX  
Θ
= Thermal resistance of the package  
JA  
The maximum power dissipation actually produced by an IC  
is the total quiescent supply current times the total power  
supply voltage, plus the power in the IC due to the load, or:  
DC-Restore  
When the ISL59830 is AC-coupled it becomes necessary to  
restore the DC reference for the signal. This is accomplished  
with a DC-restore system applied between the capacitive  
"AC" coupling and the input of the device. Refer to  
for sourcing:  
V
i
OUT  
-----------------  
PD  
= V × I  
+ (V V  
i) ×  
MAX  
S
SMAX  
S
OUT  
R i  
L
Application Circuit for reference DC-restore solution.  
for sinking:  
Disable/Power-Down  
The ISL59830 can be disabled and placed its output in a  
high impedance state. The turn-off time is around 25ns and  
the turn-on time is around 200ns. When disabled, the  
amplifier's supply current is reduced to 30µA typically,  
thereby effectively eliminating the power consumption. The  
amplifier's power-down can be controlled by standard TTL or  
CMOS signal levels at the ENABLE pin. The applied logic  
PD  
= V × I  
+ (V  
i V ) × I  
i
LOAD  
MAX  
S
SMAX  
OUT  
S
Where:  
V = Supply voltage  
S
I
= Maximum quiescent supply current  
SMAX  
signal is relative to V - pin. Letting the ENABLE pin float or  
S
V
= Maximum output voltage of the application  
OUT  
applying a signal that is less than 0.8V above V - will enable  
S
the amplifier. The amplifier will be disabled when the signal  
R
= Load resistance tied to ground  
LOAD  
= Load current  
at ENABLE pin is 2V above V -.  
S
I
LOAD  
Output Drive Capability  
By setting the two P  
can solve the output current and R  
overheat.  
equations equal to each other, we  
DMAX  
The ISL59830 does not have internal short-circuit protection  
circuitry. A short-circuit current of 80mA sourcing and 150mA  
sinking for the output is connected to half way between the  
rails with a 10resistor. If the output is shorted indefinitely,  
the power dissipation could easily increase such that the part  
will be destroyed. Maximum reliability is maintained if the  
output current never exceeds ±40mA, after which the  
electro-migration limit of the process will be exceeded and  
the part will be damaged. This limit is set by the design of the  
internal metal interconnections.  
to avoid the device  
LOAD  
Power Supply Bypassing and Printed Circuit  
Board Layout  
Strip line design techniques are recommended for the input  
and output signal traces. As with any high frequency device,  
a good printed circuit board layout is necessary for optimum  
performance. Lead lengths should be as short as possible.  
The power supply pin must be well bypassed to reduce the  
risk of oscillation. For normal single supply operation, where  
Power Dissipation  
the V - pin is connected to the ground plane, a single 4.7µF  
S
With the high output drive capability of the ISL59830, it is  
possible to exceed the 150°C absolute maximum junction  
temperature under certain load current conditions.  
Therefore, it is important to calculate the maximum junction  
temperature for an application to determine if load conditions  
or package types need to be modified to assure operation of  
the amplifier in a safe operating area.  
tantalum capacitor in parallel with a 0.1µF ceramic capacitor  
from V + to GND will suffice. This same capacitor  
S
combination should be placed at each supply pin to ground if  
split-internal supplies are to be used. In this case, the V -  
S
pin becomes the negative supply rail.  
For good AC performance, parasitic capacitance should be  
kept to a minimum. Use of wire-wound resistors should be  
avoided because of their additional series inductance. Use  
of sockets should also be avoided if possible. Sockets add  
parasitic inductance and capacitance can result in  
compromised performance. Minimizing parasitic capacitance  
at the amplifier's inverting input pin is also very important.  
The maximum power dissipation allowed in a package is  
determined according to:  
T
T  
AMAX  
JMAX  
PD  
= --------------------------------------------  
MAX  
Θ
JA  
FN7489.2  
13  
August 15, 2005  
ISL59830  
Quarter Size Outline Plastic Packages (QSOP)  
M16.15A  
N
16 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE  
(0.150” WIDE BODY)  
INDEX  
M
M
B
0.25(0.010)  
H
AREA  
E
INCHES  
MILLIMETERS  
GAUGE  
PLANE  
-B-  
SYMBOL  
MIN  
MAX  
MIN  
1.55  
0.102  
1.40  
0.20  
0.191  
4.80  
3.81  
MAX  
1.73  
0.249  
1.55  
0.31  
0.249  
4.98  
3.99  
NOTES  
A
A1  
A2  
B
0.061  
0.004  
0.055  
0.008  
0.0075  
0.189  
0.150  
0.068  
0.0098  
0.061  
0.012  
0.0098  
0.196  
0.157  
-
1
2
3
-
L
-
0.25  
0.010  
SEATING PLANE  
A
9
-A-  
D
h x 45°  
C
D
E
-
3
-C-  
4
α
A2  
e
A1  
e
0.025 BSC  
0.635 BSC  
-
C
B
H
h
0.230  
0.010  
0.016  
0.244  
0.016  
0.035  
5.84  
0.25  
0.41  
6.20  
0.41  
0.89  
-
0.10(0.004)  
M
M
S
B
0.17(0.007)  
C
A
5
L
6
NOTES:  
N
α
16  
16  
7
1. Symbols are defined in the “MO Series Symbol List” in Section  
0°  
8°  
0°  
8°  
-
2.2 of Publication Number 95.  
Rev. 2 6/04  
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.  
3. Dimension “D” does not include mold flash, protrusions or gate  
burrs. Mold flash, protrusion and gate burrs shall not exceed  
0.15mm (0.006 inch) per side.  
4. Dimension “E” does not include interlead flash or protrusions.  
Interlead flash and protrusions shall not exceed 0.25mm (0.010  
inch) per side.  
5. The chamfer on the body is optional. If it is not present, a visual  
index feature must be located within the crosshatched area.  
6. “L” is the length of terminal for soldering to a substrate.  
7. “N” is the number of terminal positions.  
8. Terminal numbers are shown for reference only.  
9. Dimension “B” does not include dambar protrusion. Allowable  
dambar protrusion shall be 0.10mm (0.004 inch) total in excess  
of “B” dimension at maximum material condition.  
10. Controlling dimension: INCHES. Converted millimeter dimen-  
sions are not necessarily exact.  
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.  
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality  
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without  
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and  
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result  
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.  
For information regarding Intersil Corporation and its products, see www.intersil.com  
FN7489.2  
14  
August 15, 2005  

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