ISL59830IAZ-T7_技术文档

ISL59830

®

Data Sheet

May 4, 2006

FN7489.6

True Single Supply Video Driver

Features

The ISL59830 is a revolutionary device that allows true single-

supply operation of video amplifiers. The device runs off a

single 3.3V supply and generates the required negative

voltage internally. This allows for DC-accurate coupling of

video onto a 75Ω double-terminated line. Since the buffers

have an integrated 6dB gain, no external gain setting resistors

are required. An input reference voltage can be supplied to

shift the analog video level down by an amount equal to the

reference (typically 0.6V).

• Triple single-supply buffer

• Operates from single +3.3V supply

• No output DC blocking capacitor needed

• Fixed gain of 2 output buffer

• Output three-statable

• Enable/disable function

• 50MHz 0.1dB bandwidth

Ordering Information

• 200MHz -3dB bandwidth

PART

TAPE &

PKG.

• Pb-free plus anneal available (RoHS compliant)

PART NUMBER MARKING REEL

PACKAGE DWG. #

Applications

ISL59830IA

59830IA

-

7”

13”

-

16 Ld QSOP M16.15A

• Driving video

ISL59830IA-T7

ISL59830IA-T13 59830IA

Pinout

ISL59830IAZ

(See Note)

59830IAZ

16 Ld QSOP M16.15A

(Pb-Free)

ISL59830

(16 LD QSOP)

TOP VIEW

ISL59830IAZ-T7 59830IAZ

(See Note)

7”

16 Ld QSOP M16.15A

(Pb-Free)

RIN

GIN

1

2

3

4

5

6

7

8

16 ROUT

15 GOUT

14 BOUT

13 VCC

12 EN

ISL59830IAZ-T13 59830IAZ

(See Note)

13”

16 Ld QSOP M16.15A

(Pb-Free)

NOTE: Intersil Pb-free plus anneal products employ special Pb-free

material sets; molding compounds/die attach materials and 100%

matte tin plate termination finish, which are RoHS compliant and

compatible with both SnPb and Pb-free soldering operations. Intersil

Pb-free products are MSL classified at Pb-free peak reflow

temperatures that meet or exceed the Pb-free requirements of

IPC/JEDEC J STD-020.

BIN

REF

VEE

GND

11 VCC

10 NC

VEEOUT

DGND

9

DVCC

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1

1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

ISL59830

Absolute Maximum Ratings (T = 25°C)

A

V

, Supply Voltage between V and GND . . . . . . . . . . . . . . . . .5V

Operating Temperature . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C

Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Lead Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves

CC

, V

S

. . . . . . . . . . . . . . . . . . . . . . . . . . . .VCC+0.3V, VEE-0.3V

IN REF

Voltage between V and V

. . . . . . . . . . . . . . . . . . . . . . . . . .±2V

IN

REF

Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . . 30mA

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests

are at the specified temperature and are pulsed tests, therefore: T = T = T

A

J

C

AC Electrical Specifications

V

= DV

= +3.3V, REF = GND, T = 25°C, R = 150Ω, unless otherwise specified.

CC A L

CC

DESCRIPTION

3dB Bandwidth

PARAMETER

CONDITIONS

= 200mV

MIN

TYP

200

100

50

MAX

UNIT

MHz

V/µs

%

BW -3dB

V

OUT

PP

= 2V

PP

BW 0.1dB

0.1dB Bandwidth

Slew Rate

S

500

R

G

P

d

Differential Gain

Differential Phase

Hostile Crosstalk

Input to Output Isolation

Input Noise Voltage

0.07

0.06

-90

-70

20

°

X

I

6MHz

dB

T

dB

V

nV/√Hz

MHz

mV

N

Fcp

Charge Pump Switch Frequency

168

12

Load Reg

I

= 0mA to 10mA

60

EE

V

Output Amp Ripple Voltage

30

mV

RIPPLE

With Bead Core to DV

10

mV

CC

DC Electrical Specifications

V

= D = +3.3V, REF = GND, T = 25°C, R = 150Ω, unless otherwise specified.

VCC A L

CC

PARAMETER

V+

DESCRIPTION

CONDITIONS

MIN

TYP

MAX

3.6

UNIT

V

Supply Range

Gain Error

3.0

V %

G

R

= 150Ω, V = +2.5V to -1V

1.5

%

L

IN

ΔG

Gain Matching

= 150Ω

0.5

1.7

7

%

L

R

Input Resistance

Output Offset Voltage

Output Current

V

= 0V to 1.5V

1.0

-25

50

15

MΩ

mV

mA

Ω

IN

V

= 0

+25

OS

REF

I

R

= 10Ω, V = 1.2V

IN

OUT +

OUT -

L

Output Current

= 10Ω, V = -0.3V

IN

-18

Z

Output Impedance

Enabled

1

10

90

120

80

5

OUT

Three-stated

MΩ

dB

mA

kΩ

PSRR

Power Supply Rejection Ratio

Supply Current

60

4

I

Amp Enabled

Amp Disabled

150

6

S

R

Input Reference Resistor

REF

FN7489.6

May 4, 2006

2

ISL59830

Pin Descriptions

PIN NUMBER

PIN NAME

PIN FUNCTION

EQUIVALENT CIRCUIT

1

RIN

Analog input

V

CC

V

EE

CIRCUIT 1

2

3

4

GIN

BIN

Analog input

Reference input

Reference Circuit 1

REF

R

IN

V

CC

R

G

B

OUT

G

B

+

-

3

REF

V

EE

CIRCUIT 2

5

VEE

Chip substrate

V

CC

V

EE OUT

-

+

D

VCC

V

EE

CHARGE

PUMP

D

GND

CIRCUIT 3

6

7

GND

VEE OUT

DGND

DVCC

NC

Analog ground

Charge pump output

Charge pump ground

Charge pump supply voltage

Not connected

Reference Circuit 3

8

9

10

11, 13

12

VCC

Positive power supply

Chip enable

EN

V

CC

V

EE

CIRCUIT 4

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May 4, 2006

3

ISL59830

Pin Descriptions (Continued)

PIN NUMBER

PIN NAME

PIN FUNCTION

EQUIVALENT CIRCUIT

14

BOUT

Analog output

V

CC

V

EE

CIRCUIT 5

15

16

GOUT

ROUT

Analog output

Reference Circuit 5

Typical Performance Curves

3

5

A =+2

V

L

V

9pF

C =0pF

R =500Ω

L

2

1

4.7pF

2.2pF

3

1

1kΩ

0

500Ω

0pF

-1

-3

-5

-1

-2

-3

150Ω

75Ω

1M

10M

100M

1G

100K

1M

10M

100M

1G

FREQUENCY (Hz)

FIGURE 1. GAIN vs FREQUENCY FOR VARIOUS R

FIGURE 2. GAIN vs FREQUENCY FOR VARIOUS C

LOAD

5

300

A =+2

V

A =+2

V

L

C =0pF

R =500Ω

0

-5

L

-3dB ROLL-OFF

R =500Ω

L

240

180

120

60

-10

-15

-20

-25

-30

-35

-0.1dB ROLL-OFF

0

2.25

1

100

200

300

400

500

2.8

3.35

3.9

4.45

5

FREQUENCY (MHz)

TOTAL SUPPLY VOLTAGE, V

CC

- V (V)

EE

FIGURE 3. V

PIN OUTPUT FREQUENCY RESPONSE

FIGURE 4. GAIN ROLL-OFF

REF

FN7489.6

May 4, 2006

4

ISL59830

Typical Performance Curves (Continued)

-30

-40

1.6

A =+2

V

A =+2

V

R =500Ω

L

R =500Ω

L

C =3.9pF

L

-50

1.2

0.8

0.4

0

-60

ENABLED

-70

-80

DISABLED

-90

-100

-110

-120

100K

1M

10M

FREQUENCY (Hz)

100M

1G

2.2 2.4 2.6 2.8

3

3.2 3.4 3.6 3.8

4

SUPPLY VOLTAGE (V)

FIGURE 6. CROSS TALK CHANNEL TO CHANNEL (TYPICAL)

FIGURE 5. PEAKING vs SUPPLY VOLTAGE

-20

120

A =+2

V

L

A =+2

V

L

R =500Ω

-30

-40

-50

-60

-70

-80

-90

-100

100

80

60

40

20

0

100K

1M

10M

100M

1G

1

1.5

2

2.5

3

3.5

FREQUENCY (Hz)

SUPPLY VOLTAGE (V)

FIGURE 7. INPUT TO OUTPUT ISOLATION vs FREQUENCY

FIGURE 8. SUPPLY CURRENT vs SUPPLY VOLTAGE

200

95

A =+2

V

-3dB

R =500Ω

L

CL

V

=3.3V

160

A =+2

90

85

80

75

V

R =500Ω

L

120

80

40

0

-0.1dB

25

55

85

TEMPERATURE (°C)

115

145

25

55

85

115

145

TEMPERATURE (°C)

FIGURE 9. BANDWIDTH vs TEMPERATURE

FIGURE 10. SUPPLY CURRENT vs TEMPERATURE

FN7489.6

May 4, 2006

5

ISL59830

Typical Performance Curves (Continued)

100

-10

-30

10

1

-50

PSRR-

-70

PSRR+

0.1

0.01

-90

-110

10K

100K

1M

10M

100M

1K

10K

100K

1M

10M

100M

FREQUENCY (Hz)

FIGURE 11. OUTPUT IMPEDANCE vs FREQUENCY

FIGURE 12. POWER SUPPLY REJECTION RATIO vs

FREQUENCY

-30

-40

1K

100

THD

-50

-60

e

N

10

1

-70

2ND HD

3RD HD

-80

I +

N

I -

N

-90

-100

0.1

10

0

10

20

30

40

100

1K

10K

100K

1M

10M

FUNDAMENTAL FREQUENCY (MHz)

FREQUENCY (Hz)

FIGURE 14. HARMONIC DISTORTION vs FREQUENCY

FIGURE 13. VOLTAGE AND CURRENT NOISE vs FREQUENCY

-30

-40

-50

THD

F

=10MHz

-60

-70

-80

-90

IN

0

-0.02

-0.04

-0.06

-0.08

THD

F

=1MHz

IN

0.5

1

1.5

2

2.5

3

3.5

IRE

OUTPUT VOLTAGE (V

FIGURE 15.

)

P-P

FIGURE 16. DIFFERENTIAL GAIN

FN7489.6

May 4, 2006

6

ISL59830

Typical Performance Curves (Continued)

0

-0.02

-0.04

-0.06

-0.08

IRE

TIME (2µs/DIV)

FIGURE 17. DIFFERENTIAL PHASE

FIGURE 18. DISABLE TIME

TIME (200ns/DIV)

TIME (10ns/DIV)

FIGURE 20. SMALL SIGNAL RISE & FALL TIMES

FIGURE 19. ENABLE TIME

TIME (10ns/DIV)

TIME (20ns/DIV)

FIGURE 21. LARGE SIGNAL RISE & FALL TIMES

FIGURE 22. AMP OUTPUT NOISE (CHARGE PUMP

OSCILLATION)

FN7489.6

May 4, 2006

7

ISL59830

Typical Performance Curves (Continued)

1.6

1.2

0.8

0.4

0

3.25

BACKDRIVE ACROSS 5Ω RESISTOR

TYPICAL CHANNEL

VCC = 3.3V

3

2.75

A =+2

V

C =3.9pF

L

2.5

50

0

1

2

3

4

5

250

450

650

850

1050

BACKDRIVE VOLTAGE (V)

LOAD RESISTANCE (Ω)

FIGURE 24. BACKDRIVE VOLTAGE vs CURRENT

AMP DISABLED OUTPUT LOADING

FIGURE 23. MAXIMUM OUTPUT MAGNITUDE vs LOAD

RESISTANCE

JEDEC JESD51-3 LOW EFFECTIVE THERMAL

CONDUCTIVITY TEST BOARD

1.4

Block Diagram

V

CC

1.2

1

791mW

0.8

R

IN

Y

+

-

R

OUT

6dB

0.6

0.4

0.2

0

REFERENCE

G

B

IN

Pb

+

-

G

OUT

0

25

50

75 85 100

125

150

AMBIENT TEMPERATURE (°C)

FIGURE 25. PACKAGE POWER DISSIPATION vs AMBIENT

TEMPERATURE

Pr

+

-

B

OUT

DV

CC

JEDEC JESD51-7 HIGH EFFECTIVE THERMAL

CONDUCTIVITY TEST BOARD

1.8

V

EE-OUT

CHARGE

PUMP

1.6

V

EE

1.4

V

= 2V - V

IN REFERENCE

OUT

1.116W

1.2

1

0.8

0.6

0.4

0.2

0

25

50

75 85 100

125

150

AMBIENT TEMPERATURE (°C)

FIGURE 26. PACKAGE POWER DISSIPATION vs AMBIENT

TEMPERATURE

FN7489.6

May 4, 2006

8

ISL59830

Demo Board Schematic

RED_IN

R

1

75Ω

RED_OUT

R

75Ω

4

5

6

GREEN_IN

BLUE_IN

1

2

3

4

5

6

7

8

RIN

ROUT 16

R

2

75Ω

GIN

GOUT 15

BOUT 14

VCC 13

EN 12

GREEN_OUT

BLUE_OUT

BIN

V

CC

REF

R

1kΩ

C

3

0.1µF

7

4

R

3

1.0µF

75Ω

VEE

R

4

GND

VEEOUT

VCC 11

NC 10

ENABLE

2

V

CC

1

499Ω

V

CC

R

1kΩ

C

2

0.1µF

8

C

0.1µF

5

3

V

DGND DVCC 9

CC

REFERENCE

CONTROL

D

1

1N4148

(or similar)

Option: Panasonic 120Ω Bead

EXC3BP121H

Lower Amp output noise from charge pump

bandwidth limiting of the Miller capacitance is greatly

reduced. The signal is then passed through a second fully-

realized differential gain stage and finally through a

proprietary common emitter output stage for improved rail-

to-rail output performance. The result is a highly-stable, low

distortion, low power, and high frequency amplifier capable

of driving moderately capacitive loads with near rail-to-rail

performance.

Description of Operation and Application

Information

Theory Of Operation

The ISL59830 is a highly practical and robust marriage of

three high bandwidth, high speed, low power, rail-to-rail

voltage feedback amplifiers with a charge pump, to provide a

negative rail without an additional power supply. Designed to

operate with a single supply voltage range of from 0V to

3.3V, the ISL59830 eliminates the need for a split supply with

the incorporation of a charge pump capable of generating a

bottom rail as much as 1.6V below ground; for a 4.9V range

on a single 3.3V supply. This performance is ideal for NTSC

video with its negative-going sync pulses.

Input Output Range

The three amplifier channels have an input common mode

voltage range from 0.15V below the bottom rail to within

100mV of the positive supply, V + pin (Note: bottom rail is

S

established by the charge pump at negative one half the

positive supply). As the input signal moves outside the

specified range, the output signal will exhibit increasingly

higher levels of harmonic distortion. And of course, as load

resistance becomes lower, the current drive capability of the

device will be challenged and its ability to drive close to each

rail is reduced. For instance, with a load resistance of 1kΩ

the output swing is within a 100mV of the rails, while a load

resistance of 150Ω limits the output swing to within around

300mV of the rails.

The Amplifier

The ISL59830 fabricated on a dielectrically isolated high

speed 5V Bi-CMOS process with 4GHz PNPs and NPN

transistor exceeding 20GHz - perfect for low distortion, low

power demand and high frequency circuits. While the

ISL59830 utilizes somewhat standard voltage mode

feedback topologies, there are many non-standard analog

features providing its outstanding bandwidth, rail-to-rail

operation, and output drive capabilities. The input signal

initially passes through a folded cascode, a topology

providing enhanced frequency response essentially by fixing

the base collector voltage at the junction of the input and

gain stage. The collector of each input device looks directly

into an emitter that is tied closely to ground through a

resistor and biased with a very stable DC source. Since the

voltage of this collector is "locked stable" the effective

Amplifier Output Impedance

To achieve near rail-to-rail performance, the output stage of

the ISL59830 uses transistors in the common emitter

configuration, typically producing higher output impedance

than the standard emitter follower output stage. The

exceptionally high open loop gain of the ISL59830 and local

feedback reduces output impedance to less than a 2Ω at low

frequency. However, since output impedance of the device is

FN7489.6

May 4, 2006

10

ISL59830

I +

N

I -

N

OUT

BIAS

FIGURE 27.

exponentially modulated by the magnitude of the open loop

gain, output impedance increases with frequency as the

open loop gain decreases with frequency. This inductive-like

effect of the output impedance is countered in the ISL59830

with proprietary output stage topology, keeping the output

impedance low over a wide frequency range and making it

possible to easily and effectively drive relatively heavy

capacitive loads.(See Figure 11).

The Charge Pump

The ISL59830 charge pump provides a bottom rail up to

1.65V below ground while operating on a 0V to 3.3V power

supply. The charge pump is internally regulated to one-half

the potential of the positive supply. This internal multi-phase

charge pump is driven by a 160MHz differential ring

oscillator driving a series of inverters and charge storage

circuitry. Each series inverter charges and places parallel

adjoining charge circuitry slightly out of phase with the

immediately preceding block. The overall effect is sequential

discharge and generation of a very low ripple of about 10mV

that is applied to the amplifiers providing a negative rail of up

to -1.65V.

TIME (20ns/DIV)

FIGURE 28. CHARGE PUMP OSCILLATION (AMP OUTPUT)

The system operates at sufficiently high frequencies that any

related charge pump noise is far beyond standard video

bandwidth requirements. Still, appropriate bypassing

discipline must be observed, and all pins related to either the

power supply or the charge pump must be properly

bypassed. See "Power Supply Bypassing and Printed Circuit

Board Layout" in this section.

There are two options to reduce the output supply noise.

To maximize resistance to latch-up, a diode should be added

between the VEEOUT pin (anode) and GND (cathode), as

shown in the Demo Board Schematic. This prevents VEE

from rising more than 0.7V above ground during startup.

(VEE > 1V above GND can cause latchup under some

conditions.)

• Add a 120Ω bead in series between V

further reduce ripple.

and DV

to

CC

Add a 20pF capacitor between the back load 75Ω resistor

and ground (see the ISL59830A + DC-Restore Solution

schematic on page 10).

FN7489.6

May 4, 2006

11

ISL59830

specifications of 0.06% and 0.1°, while driving 150Ω at a

The V

REF

Applying a voltage to the V

gain of +2. Driving higher impedance loads would result in

similar or better differential gain and differential phase

performance.

pin simply places that

REF

voltage on what would usually be the ground side of the gain

resistor of the amplifier, resulting in a DC-level shift of the

output signal. Applying 100mV to the Vref pin would apply a

-100mV DC level shift to the outgoing signal. The charge

pump provides sufficient bottom room to accommodate the

NTSC

The ISL59830, generating a negative rail internally, is ideally

suited for NTSC video with its accompanying negative-going

sync signals; easily handled by the ISL59830 without the

need of an additional supply as the ISL59830 generates a

negative rail with an internal charge pump referenced at

negative 1/2 the positive supply.

shifted signal. V

may be connected to ground for back

REF

porch at ground.

Note: The V

REF

minus input resistors. Any common resistance on V

input is the common point of the 3 amps

REF

input will share the voltage induced on it with all the other

amps, so using a resistor source to get offset will cause

cross talk and gain change for the offset for all amps and

YPbPr

YPbPr signals originating from a DVD player requiring three

channels of very tightly-controlled amplifier gain accuracy

present no difficulty for the ISL59830. Specifically, this

standard encodes sync on the Y channel and it is a negative-

going signal; easily handled by the ISL59830 without the

need of an additional supply as the ISL59830 generates a

negative rail placed at negative 1/2 the positive supply.

Additionally, the Pb and Pr are bipolar analog signals and

the video signals are negative-going; and again easily

handled by the ISL59830.

amp +input gain change. Offset on the V

pin must be low

REF

impedance to prevent gain error and cross talk. A transistor

emitter follower should work like an NPN MMBT3904 with

the emitter connected to the V

pin and 1k pull down to V-

REF

with 1µF cap bypass to ground and the collector to V+ and

base to V offset source. If better tempco is needed then a

diode may be used in series with the pot to ground. A 499Ω

resistor may be added in series with the collector to prevent

damage when testing.

Driving Capacitive Loads and Cables

See the Block Diagram on page 8.

The ISL59830, internally-compensated to drive 75Ω cables,

will drive 10pF loads in parallel with 1kΩ with less than 5dB

of peaking. If less peaking is required, a small series resistor,

usually between 5Ω to 50Ω, can be placed in series with the

output. This will reduce peaking at the expense of a slight

closed loop gain reduction. When used as a cable driver,

double termination is always recommended for reflection-

free performance. For those applications, a back-termination

series resistor at the amplifier's output will isolate the

amplifier from the cable and allow extensive capacitive drive.

However, other applications may have high capacitive loads

without a back-termination resistor. Again, a small series

resistor at the output can help to reduce peaking. The

ISL59830 is a triple amplifier designed to drive three

channels; simply deal with each channel separately as

described in this section.

The V Pin

EE

The V pin is the output pin for the charge pump. A

EE

voltmeter applied to this pin will display the output of the

charge pump. This pin does not affect the functionality of the

part. One may use this pin as an additional voltage source.

Keep in mind that the output of this pin is generated by the

internal charge pump and a fully regulated supply that must

be properly bypassed. We recommend a 0.1µF ceramic

capacitor placed as close to the pin and connected to the

ground plane of the board.

Input, Output, and Supply Voltage Range

The ISL59830 is designed to operate with a single supply

voltage range of from 0V to 3.3V. The need for a split supply

has been eliminated with the incorporation of a charge pump

capable of generating a bottom rail as much as 1.6V below

ground, for a 4.9V range on a single 3.3V supply. This

performance is ideal for NTSC video with its negative-going

sync pulses.

DC-Restore

When the ISL59830 is AC-coupled it becomes necessary to

restore the DC reference for the signal. This is accomplished

with a DC-restore system applied between the capacitive

"AC" coupling and the input of the device. Refer to

Video Performance

For good video performance, an amplifier is required to

maintain the same output impedance and the same

frequency and phase response as DC levels are changed at

the output. This is especially difficult when driving a standard

video load of 150Ω because of the change in output current

with changing DC levels. Special circuitry has been

incorporated into the ISL59830 for the reduction of output

impedance variation with the current output. This results in

outstanding differential gain and differential phase

Application Circuit for reference DC-restore solution.

Amplifier Disable

The ISL59830 can be disabled and its output placed in a

high impedance state. The turn-off time is around 25ns and

the turn-on time is around 200ns. When disabled, the

amplifier's supply current is reduced to 80mA typically,

reducing power consumption. The amplifier's power-down

can be controlled by standard TTL or CMOS signal levels at

FN7489.6

May 4, 2006

12

ISL59830

the EN pin. The applied logic signal is relative to GND pin.

Where:

Letting the EN pin float or applying a signal that is less than

0.8V above GND will enable the amplifier. The amplifier will

be disabled when the signal at EN pin is 2V above GND. The

V = Supply voltage

S

I

= Maximum quiescent supply current

SMAX

V

charge pump remains active.

EE

V

= Maximum output voltage of the application

OUT

Output Drive Capability

R

= Load resistance tied to ground

LOAD

The ISL59830 does not have internal short-circuit protection

circuitry. A short-circuit current of 80mA sourcing and 150mA

sinking for the output is connected to half way between the

rails with a 10Ω resistor. If the output is shorted indefinitely,

the power dissipation could easily increase such that the part

will be destroyed. Maximum reliability is maintained if the

output current never exceeds ±40mA, after which the

electro-migration limit of the process will be exceeded and

the part will be damaged. This limit is set by the design of the

internal metal interconnections.

I

= Load current

LOAD

i = Number of output channels

By setting the two P equations equal to each other, we

DMAX

can solve the output current and R

overheat.

to avoid the device

LOAD

Power Supply Bypassing and Printed Circuit

Board Layout

Strip line design techniques are recommended for the input

and output signal traces. As with any high frequency device,

a good printed circuit board layout is necessary for optimum

performance. Lead lengths should be as short as possible.

The power supply pin must be well bypassed to reduce the

risk of oscillation. For normal single supply operation, where

the V - pin is connected to the ground plane, a single 4.7µF

tantalum capacitor in parallel with a 0.1µF ceramic capacitor

from V + to GND will suffice. This same capacitor

combination should be placed at each supply pin to ground if

Power Dissipation

With the high output drive capability of the ISL59830, it is

possible to exceed the 150°C absolute maximum junction

temperature under certain load current conditions.

Therefore, it is important to calculate the maximum junction

temperature for an application to determine if load conditions

or package types need to be modified to assure operation of

the amplifier in a safe operating area.

S

The maximum power dissipation allowed in a package is

determined according to:

split-internal supplies are to be used. In this case, the V -

pin becomes the negative supply rail.

S

T

– T

AMAX

JMAX

For good AC performance, parasitic capacitance should be

kept to a minimum. Use of wire-wound resistors should be

avoided because of their additional series inductance. Use

of sockets should also be avoided if possible. Sockets add

parasitic inductance and capacitance can result in

PD

= --------------------------------------------

MAX

Θ

JA

Where:

T

= Maximum junction temperature

= Maximum ambient temperature

JMAX

compromised performance. Minimizing parasitic capacitance

at the amplifier's inverting input pin is also very important.

T

AMAX

Θ

= Thermal resistance of the package

JA

The maximum power dissipation actually produced by an IC

is the total quiescent supply current times the total power

supply voltage, plus the power in the IC due to the load, or:

for sourcing:

V

i

OUT

R i

L

-----------------

i) ×

OUT

PD

= V × I

+ (V – V

MAX

S

SMAX

S

for sinking:

PD

= V × I

+ (V

i – V ) × I

i

LOAD

MAX

S

OUT

S

FN7489.6

May 4, 2006

13

ISL59830

Shrink Small Outline Plastic Packages (SSOP)

Quarter Size Outline Plastic Packages (QSOP)

M16.15A

N

16 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE

(0.150” WIDE BODY)

INDEX

M

B

0.25(0.010)

H

AREA

E

INCHES

MILLIMETERS

GAUGE

PLANE

-B-

SYMBOL

MIN

MAX

MIN

1.55

0.102

1.40

0.20

0.191

4.80

3.81

MAX

1.73

0.249

1.55

0.31

0.249

4.98

3.99

NOTES

A

A1

A2

B

0.061

0.004

0.055

0.008

0.0075

0.189

0.150

0.068

0.0098

0.061

0.012

0.0098

0.196

0.157

-

1

2

3

-

L

-

0.25

0.010

SEATING PLANE

A

9

-A-

D

h x 45°

C

D

E

-

3

-C-

4

α

A2

e

A1

e

0.025 BSC

0.635 BSC

-

C

B

H

h

0.230

0.010

0.016

0.244

0.016

0.035

5.84

0.25

0.41

6.20

0.41

0.89

-

0.10(0.004)

M

S

B

0.17(0.007)

C

A

5

L

6

NOTES:

N

α

16

7

1. Symbols are defined in the “MO Series Symbol List” in Section

2.2 of Publication Number 95.

0°

8°

0°

8°

-

Rev. 2 6/04

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate

burrs. Mold flash, protrusion and gate burrs shall not exceed

0.15mm (0.006 inch) per side.

4. Dimension “E” does not include interlead flash or protrusions.

Interlead flash and protrusions shall not exceed 0.25mm (0.010

inch) per side.

5. The chamfer on the body is optional. If it is not present, a visual

index feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. Dimension “B” does not include dambar protrusion. Allowable

dambar protrusion shall be 0.10mm (0.004 inch) total in excess

of “B” dimension at maximum material condition.

10. Controlling dimension: INCHES. Converted millimeter dimen-

sions are not necessarily exact.

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN7489.6

May 4, 2006

14


型号：	ISL59830IAZ-T7
厂家：	Intersil
描述：	True Single Supply Video Driver 真正的单电源视频驱动器驱动器
文件：	总14页 (文件大小：327K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ISL59830IAZ-T7 [INTERSIL]

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