ISL59832 [INTERSIL]
Dual Channel, Single Supply Video Reconstruction Filter with Charge Pump; 双通道，单电源视频重建滤波器与电荷泵
| 型号： | ISL59832 |
| 厂家： | 
Intersil |
| 描述： | Dual Channel, Single Supply Video Reconstruction Filter with Charge Pump |
| 文件： | 总14页 (文件大小：1197K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISL59832
®
Data Sheet
June 11, 2008
FN6267.1
Dual Channel, Single Supply Video
Features
Reconstruction Filter with Charge Pump
• 3.3V Nominal Supply, Operates Down to 3.0V
• DC-Coupled Outputs
The ISL59832 is a dual channel, single supply video driver
with reconstruction filter and charge pump. It is designed to
drive SDTV displays with S-Video (Y/C) signals. It operates
on a single supply (3.0V to 3.6V) and generates its own
negative supply (-1.5V) using a regulated charge pump.
Input signals can be AC- or DC-coupled. When AC-coupled,
the sync tip clamp sets the blank level to ground at the
output of Channel 1 thus ensuring that the sync-tip voltage
level is set to approximately -300mV at the back-termination
resistor of a standard video load. Channel 1 also has a sync
detector whose output is available at SYNC_OUT pin. In a
typical application where the luma is connected to
Channel 1, and chrominance is connected to Channel 2,
SYNC_IN is connected to SYNC_OUT thus providing timing
to Channel 2. Channel 2 has a keyed clamp which sets the
output to ground when SYNC_IN is driven to the logic high
state. The ISL59832 is capable of driving two DC- or
AC-coupled standard video loads. The ISL59832 features a
4th order Butterworth reconstruction filter that provides a
9MHz nominal -3dB frequency and 40dB of attenuation at
27MHz. Nominal operational current is 31mA. When
powered down, the device draws 1µA maximum supply
current. The ISL59832 is available in 16 Ld TQFN package.
• Inputs can be AC- or DC-Coupled
• Eliminates the Need for Large Output Coupling Capacitors
• Integrated Sync Tip Clamp sets Backporch to Ground at
the Output For Channel 1 for 1VP-P Standard Video Signal
• Integrated Keyed Clamp Puts Channel 2 Output to Ground
During Sync
• Each Output Drives 2 Standard Video Loads
• Response Flat to 5MHz, with 40dB Attenuation at 27MHz
• Pb-Free (RoHS compliant)
Pinout
ISL59832
(16 LD TQFN)
TOP VIEW
16 15 14 13
SYNC_IN
1
2
3
4
12
11
10
9
CAP+
CAP-
SYNC_OUT
Ordering Information
EP
V
S
V
CP
TEMP.
PART
NUMBER
PART
MARKING
RANGE
(°C)
PACKAGE
(Pb-Free)
PKG.
DWG. #
ENABLE
GND
CP
5
6
7
8
ISL59832IRZ
59 832IRZ -40 to +85 16 Ld TQFN
MDP0046
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination finish,
which is RoHS compliant and compatible with both SnPb and Pb-free
soldering operations). Intersil Pb-free products are MSL classified at
Pb-free peak reflow temperatures that meet or exceed the Pb-free
requirements of IPC/JEDEC J STD-020.
Block Diagram
ISL59832
CHANNEL 1
CLAMP +
LPF
Applications
• Set Top Box Receiver
• Television
VIDEO IN
SYNC
VIDEO OUT
(Y)
x2
(Y)
9MHz
DETECTOR
CHARGE PUMP
• DVD Player
CHANNEL 2
LPF
VIDEO IN
(C)
KEYED
CLAMP
VIDEO OUT
(C)
x2
9MHz
CHARGE PUMP
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2008. All Rights Reserved
1
All other trademarks mentioned are the property of their respective owners.
ISL59832
Absolute Maximum Ratings (TA = +25°C)
Thermal Information
VS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4V
IN to GND. . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to VS + 0.3V
or Thermal Resistance (Typical, Note 1)
θ
JA (°C/W)
46
V
16 Lead TQFN Package . . . . . . . . . . . . . . . . . . . . .
Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . ±50mA
Maximum Current into Any Pin . . . . . . . . . . . . . . . . . . . . . . . ±50mA
ESD Rating
Human Body Model (Per MIL-STD-883 Method 3015.7) . . .3500V
Machine Model (Per EIAJ ED-4701 Method C-111). . . . . . . .350V
Maximum Junction Temperature (Plastic Package) . . . . . . . +150°C
Maximum Storage Temperature Range. . . . . . . . . .-65°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: T = T = T
A
J
C
NOTES:
1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
2. Parameters with MIN and/or MAX limits are 100% tested at +27°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
Electrical Specifications VS = VCP = 3.3V, CF = 0.1µF, CS = 0.22µF, CFIL = 0.4µF, CIN1 = CIN2 = 0.1µF, RL1 = RL2 = 150Ω,
Typical TA = +27°C.
MIN
MAX
SYMBOL
PARAMETER
CONDITIONS
(Note 2)
TYP
(Note 2)
UNIT
DC CHARACTERISTICS
V
S, VCP
Supply Range
guaranteed by PSRR
3.0
3.3
-1.5
14
17
0.3
4
3.6
-1.25
16
V
VEEOUT
Charge Pump Output
Supply Current
-1.75
V
IS
ICP
IPD
IIN
IB
No load
mA
mA
µA
µA
µA
Charge Pump Supply Current
Power-Down Current
Input Pull-down Current
Input Bias Current
No load
20
ENABLE = 0.4V
Channel 1, VIN = 0.5V
2.5
10
0.4
-10
Channel 2, VIN = 0.5V,
SYNC_IN = 0V
-3
10
AV
DC Gain
1.94
1.4
2
2.05
V/V
V
VIN_MAX
Max DC Input Range
DC-Coupled Input, guaranteed by DC
gain test
VCLAMPOUT1
Output Sync Tip Clamp Level
(Channel 1)
VIN ≤ 0, AC-coupled input
Output level when SYNC_IN = 2.0V
Input floating
-650
-60
-590
-25
-525
0
mV
mV
VCLAMPOUT2
Keyed Clamp Level
(Channel 2)
VCLAMPIN
Input Clamp Level
0
30
70
mV
mV
VCLAMPIN2
Input Keyed Clamp Level
(Channel 2)
Input floating, input level when SYNC_IN
≥ 2.0V
275
300
375
VOS
Output Level Shift
(Channel 1)
VIN > 0, output shifted relative to input,
DC-coupled input
-685
-380
-620
-330
-550
-280
mV
mV
Output Level Shift
(Channel 2)
VIN > 0, output shifted relative to input,
DC-coupled input
FN6267.1
June 11, 2008
2
ISL59832
Electrical Specifications VS = VCP = 3.3V, CF = 0.1µF, CS = 0.22µF, CFIL = 0.4µF, CIN1 = CIN2 = 0.1µF, RL1 = RL2 = 150Ω,
Typical TA = +27°C. (Continued)
MIN
MAX
SYMBOL
PARAMETER
CONDITIONS
Force VIN = -0.3V, Channel 1
Force VIN = 1V, Channel 2
Force VIN = -0.3V, Channel 2
Channel 1
(Note 2)
TYP
-5
(Note 2)
UNIT
mA
µA
ICLAMP
Clamp Restore Current
-2.5
135
180
-200
-160
200
µA
VSLICE
Sync Detect Threshold
Power Supply Rejection
100
50
mV
dB
PSRRDC
VS = +3.0 to +3.6
77
AC CHARACTERISTICS
APB
ASB
dG
Passband Flatness
f = 5MHz, relative to 100kHz
f ≥ 27MHz relative to 100kHz
11-step modulated staircase
11-step modulated staircase
0
0.8
-50
1.25
-35
dB
dB
%
Stopband Attenuation
Differential Gain
0.45
-0.15
66
dP
Differential Phase
Signal To Noise Ratio
°
SNR
Peak signal (1.4VP-P) to RMS noise,
f = 10kHz to 10MHz
dB
GDMATCH
DC Group Delay Match
Channel-to-channel group delay
matching at 100kHz
0.1
ns
ΔGD
Group Delay Deviation
Power Supply Rejection
Deviation from 100kHz to 3.58MHz
8
ns
PSRR
V
IN = 100mVP-P sine wave, f = 100kHz to
35
dB
5MHz
XTALK
Channel-to-Channel Crosstalk
Input Voltage Noise
f = 100kHz to 5MHz
-60
dB
VNOISE
0.66
mVRMS
LOGIC (ENABLE, SYNC_IN)
VIL
Logic Low Input Voltage
0.8
1
V
V
VIH
Logic High Input Voltage
Logic Input Current
2.0
-1
II
CHARGE PUMP
fCP
µA
Charge Pump Clock Frequency
12.5
MHz
FN6267.1
June 11, 2008
3
ISL59832
Pin Descriptions
NUMBER
NAME
SYNC_IN
SYNC_OUT
VS
FUNCTION
1
2
Sync Input. Sync timing logic input for Channel 2.
Sync Output. Sync-detection logic output from Channel 1.
Positive Power Supply. Bypass to GND with a 0.1µF capacitor.
Enable. Connect to VS to enable device.
Video Input 1. Luma Channel.
3
4
ENABLE
IN1
5
6, 8
7
GND
Ground
IN2
Video Input 2. Chroma Channel.
9
GNDCP
VCP
Charge Pump Ground.
10
11
12
13
14
Charge Pump Power Supply. Bypass with a 0.1µF capacitor to GNDCP.
CAP-
Charge-Pump Flying Capacitor Negative Terminal. Connect a 0.1µF capacitor from CAP+ to CAP-
Charge-Pump Flying Capacitor Positive Terminal. Connect a 0.1µF capacitor from CAP+ to CAP-
Charge Pump Negative Output. Bypass with a 0.22µF capacitor to GND.
CAP+
VEEOUT
VEEIN
Negative Supply. Connect an RC filter between VEEIN and VEEOUT. See “S-Video Typical Application
Circuit” on page 6.
15
16
-
OUT2
OUT1
EP
Video Output 2
Video Output 1
Exposed Pad. Connect to VEEIN
FN6267.1
June 11, 2008
4
ISL59832
Block Diagram
SYNC_OUT
ENABLE
VS
SYNC DETECTOR
LPF
LEVEL
SHIFT
X2
OUT1
IN1
(-310mV)
9MHz
VEEIN
-
+
-593mV
LPF
LEVEL
SHIFT
X2
OUT2
IN2
(-165mV)
9MHz
VEEIN
-
KEYED
CLAMP
+
0V
SYNC_IN
VEEIN
CHARGE
PUMP
ISL59832
VCP
GND
VEEOUT
GNDCP CAP+
CAP-
FN6267.1
June 11, 2008
5
ISL59832
S-Video Typical Application Circuit
+3.3V
4.7μF
0.1μF
ENABLE
VS
SYNC_OUT
SYNC_IN
0.1μF
75Ω
75Ω
Luma
Source
IN1
OUT1
75Ω
75Ω
75Ω
ISL59832
0.1μF
Chrominance
Source
OUT2
IN2
75Ω
VEEIN
10Ω RFIL
VEEOUT
0.47μF
CFIL
0.22μF
CS
+3.3V
VCP
1.0μF
CCP2
0.1μF
CCP1
GNDCP
GND
CAP+
CAP-
CF
0.1μF
FN6267.1
June 11, 2008
6
ISL59832
Typical Performance Curves VCP = VS = 3.3V, CF = 0.1µF, CS = 0.22µF, CFIL = 0.4µF, CIN1= CIN2 = 0.1µF, RL1= RL2 = 150Ω.
10
2
CHANNEL 2
= 75Ω
CHANNEL 1
= 75Ω
R
0
R
L
L
1
-10
-20
-30
-40
-50
-60
-70
0
CHANNEL 2
= 75Ω
CHANNEL 2
= 150Ω
CHANNEL 1
= 150Ω
R
R
L
R
L
L
-1
-2
-3
-4
-5
CHANNEL 2
= 150Ω
R
L
CHANNEL 1
= 150Ω
R
L
CHANNEL 1
R
= 75Ω
L
0.1
1M
10M
100M
0.1
1M
FREQUENCY (Hz)
10M
FREQUENCY (Hz)
FIGURE 2. GAIN FLATNESS vs FREQUENCY
FIGURE 1. BANDWIDTH vs FREQUENCY
50
40
30
20
10
0
-1.40
-1.41
-1.42
-1.43
-1.44
-1.45
-1.46
-1.47
-1.48
ALL MEASUREMENTS
AT VEE
CHANNEL 1
LUMA
IN
V
V
= 3.3V
S
= 2.7 TO 3.6V
CP
CHANNEL 2
CHROMA
-10
-20
-30
-40
V
= V = 2.7V TO 3.6V
S
CP
V
V
= 3.3V
= 2.7V TO 3.6V
CP
S
0.1
1M
10M
100M
2.7
2.8
2.9
3.0
3.1
3.2
3.3
3.4
3.5
3.6
FREQUENCY (Hz)
SUPPLY VOLTAGE (V)
FIGURE 3. GROUP DELAY vs FREQUENCY
FIGURE 4. CHARGE PUMP VOLTAGE vs SUPPLY VOLTAGE
0
0
INPUT OF CHANNEL 1 TO OUTPUT OF
CHANNEL 2 AND VICE-VERSA
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
ENABLE = LOW
ANY INPUT TO ANY OUTPUT
-10
-20
-30
-40
-50
-60
-70
0.1
1M
FREQUENCY (Hz)
10M
100M
0.1
1M
FREQUENCY (Hz)
10M
100M
FIGURE 6. LUMA-TO-CHROMA CROSSTALK
FIGURE 5. INPUT-TO-OUTPUT ISOLATION vs FREQUENCY
FN6267.1
June 11, 2008
7
ISL59832
Typical Performance Curves VCP = VS = 3.3V, CF = 0.1µF, CS = 0.22µF, CFIL = 0.4µF, CIN1= CIN2 = 0.1µF, RL1= RL2 = 150Ω.
35
34
33
32
31
30
29
28
27
26
25
400
350
300
250
200
150
100
50
NO LOAD
INPUT FLOATING
NO LOAD
INPUT FLOATING
0
3.0
3.1
3.2
3.3
3.4
3.5
3.6
3.0
3.1
3.2
3.3
3.4
3.5
3.6
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
FIGURE 7. SUPPLY CURRENT vs SUPPLY VOLTAGE
FIGURE 8. DISABLED SUPPLY CURRENT vs SUPPLY
VOLTAGE
0
30
V
= 100mV
P-P
AC
-10
-20
-30
-40
-50
-60
V
= +3.3V + V
AC
S
25
20
15
10
5
0
0.001
0.01
0.1
1M
10M
0.1
1M
FREQUENCY (Hz)
10M
100M
FREQUENCY (Hz)
FIGURE 10. POWER SUPPLY REJECTION RATIO vs
FREQUENCY
FIGURE 9. OUTPUT IMPEDANCE vs FREQUENCY
0.6
0.05
0.03
WAVEFORM = MODULATED RAMP
WAVEFORM = MODULATED RAMP
0 IRE TO 100 IRE
0.5
0 IRE to 100 IRE
0.01
-0.01
-0.03
-0.05
-0.07
-0.09
-0.11
-0.13
-0.15
0.4
0.3
0.2
0.1
0
-0.1
-0.2
0
1
2
3
4
5
6
7
8
9
10 11
0
1
2
3
4
5
6
7
8
9
10
11
STEP
STEP
FIGURE 11. DIFFERENTIAL GAIN
FIGURE 12. DIFFERENTIAL PHASE
FN6267.1
June 11, 2008
8
ISL59832
Typical Performance Curves VCP = VS = 3.3V, CF = 0.1µF, CS = 0.22µF, CFIL = 0.4µF, CIN1= CIN2 = 0.1µF, RL1= RL2 = 150Ω.
TIME SCALE = 5µs/DIV
TIME SCALE = 10ns/DIV
CH1 = 1V/DIV
CH1 = 1V/DIV
CH2 = 1V/DIV
CH2 = 1V/DIV
ENABLE SIGNAL
DISABLE SIGNAL
ΔTIME = 35µs
OUTPUT SIGNAL
OUTPUT SIGNAL
FIGURE 14. ENABLE TIME
FIGURE 13. DISABLE TIME
TIMEBASE = 100ns/DIV
IN = CH1 = 200mV/DIV
OUT = CH2 = 500mV/DIV
TIME SCALE = 500ns/DIV
IN = CH1 = 200mV/DIV
OUT = CH2 = 500mV/DIV
INPUT
INPUT
OUTPUT
OUTPUT
FIGURE 15. 12.5T RESPONSE
FIGURE 16. 2T RESPONSE
TIME SCALE = 10µs/DIV
LUMA OUT = 500mV/DIV
CHROMA OUT = 500mV/DIV
TIME SCALE = 10µs/DIV
IN = CH1 = 500mV/DIV
OUT = CH2 = 1V/DIV
LUMA OUTPUT
CHANNEL 1
CHROMA OUTPUT
CHANNEL 2
INPUT
OUTPUT
FIGURE 18. S-VIDEO SCOPE SHOT
FIGURE 17. NTSC COLORBAR
FN6267.1
June 11, 2008
9
ISL59832
Typical Performance Curves VCP = VS = 3.3V, CF = 0.1µF, CS = 0.22µF, CFIL = 0.4µF, CIN1= CIN2 = 0.1µF, RL1= RL2 = 150Ω.
INPUT = NTSC VIDEO + 2Hz SQUARE WAVE
(BEFORE COUPLING CAPACITOR)
VIDEO SIGNAL
TIMEBASE = 1ms/DIV
TIME SCALE = 5µs/DIV
INPUT: 500mV/DIV
OUT = 500mV/DIV
OUTPUT: 500mV/DIV
CHANNEL 1 OUTPUT
SYNC_OUT = 500mV/DIV
SYNC_OUT
FIGURE 19. SYNC_OUT SIGNAL
FIGURE 20. LUMA CLAMP RESPONSE TO POSITIVE
TRANSIENT (CHANNEL 1)
INPUT = NTSC S-VIDEO (CHROMA) + 2Hz SQUARE WAVE
(BEFORE COUPLING CAPACITOR)
INPUT = NTSC VIDEO + 2Hz SQUARE WAVE
(BEFORE COUPLING CAPACITOR)
TIMEBASE = 2ms/DIV
INPUT: 500mV/DIV
OUTPUT: 500mV/DIV
TIMEBASE = 200µs/DIV
INPUT: 500mV/DIV
OUTPUT: 500mV/DIV
CHANNEL 1 OUTPUT
CHANNEL 2 OUTPUT
FIGURE 22. CHROMA CLAMP RESPONSE TO POSITIVE
TRANSIENT (CHANNEL 2)
FIGURE 21. LUMA CLAMP RESPONSE TO NEGATIVE
TRANSIENT (CHANNEL 1)
100
INPUT = NTSC S-VIDEO (CHROMA) + 2Hz SQUARE WAVE
(BEFORE COUPLING CAPACITOR)
RMS NOISE = 1.31mV
OUTPUT REFERRED
10
CHARGE PUMP NOISE,
TIMEBASE = 2ms/DIV
INPUT: 500mV/DIV
OUTPUT: 500mV/DIV
CONTRIBUTES ONLY A SMALL
PERCENTAGE OF THE
OVERALL NOISE
1
CHANNEL 2 OUTPUT
0.1
0.01
0M 2M 4M 6M 8M 10M 12M 14M 16M 18M 20M
FREQUENCY (Hz)
FIGURE 24. NOISE SPECTRUM
FIGURE 23. CHROMA CLAMP RESPONSE TO NEGATIVE
TRANSIENT (CHANNEL 2)
FN6267.1
June 11, 2008
10
ISL59832
Typical Performance Curves VCP = VS = 3.3V, CF = 0.1µF, CS = 0.22µF, CFIL = 0.4µF, CIN1= CIN2 = 0.1µF, RL1= RL2 = 150Ω.
0
V
= V = +3.3V
CP
TIME SCALE = 20ns/DIV
S
-10
-20
-30
-40
-50
-60
-70
R
= 150Ω
VERTICAL SCALE = 20mV/DIV
L
VOUT = 0 TO 2V , SINE WAVE
P
f
= 500kHz
1.1
IN
f
= 5MHz
IN
0.5
0.8
1.4
1.7
2.0
OUTPUT VOLTAGE (V)
FIGURE 26. THD (dBc) vs OUTPUT VOLTAGE (VP-P
)
FIGURE 25. CHARGE PUMP FEEDTHROUGH AT AMPLIFIER
OUTPUT
4.5
4.0
3.5
3.0
2.5
16 LD TQFN PACKAGE
4mmx4mm
= +46°C/W
2.0
1.5
1.0
0.5
0
θ
JA
0
5
10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90
AMBIENT TEMPERATURE (°C)
FIGURE 27. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
Description of Operation and Application Information
Theory of Operation
The ISL59832 is a single supply video driver with a
reconstruction filter and an on-board charge pump. It is
designed to drive SDTV displays with S-video (Y-C) or
composite video (CV) signals. The input signals can be AC
or DC-coupled. When AC-coupled, a sync tip clamp forces
the blank level to ground at the output of Channel 1 and a
keyed clamp forces the average level of Channel 2 to
ground. The ISL59832 is capable of driving two AC- or DC-
coupled standard video loads and has a 4th order
signal into a 150Ω load to ground, while the Channel 2
amplifier is able to drive a 2.8VP-P into a 150Ω or 75Ω load to
ground.
The outputs are highly-stable, low distortion, low power, high
frequency amplifiers capable of driving moderate (10pF)
capacitive loads.
Input/Output Range
The ISL59832 inputs have a dynamic range of 0 to 1.4VP-P
.
Butterworth reconstruction filter with nominal -3dB frequency
set to 10MHz, providing 40dB of attenuation at 27MHz. The
ISL59832 is designed to operate with a single supply voltage
range ranging from 3.0V to 3.6V. This eliminates the need for
a split supply with the incorporation of a charge pump
capable of generating a bottom rail as much as 1.5V below
ground; providing a 4.8V range on a single 3.3V supply. This
performance is ideal for NTSC video with negative-going
sync pulses.
This allows the device to handle the maximum possible
video signal inputs. As the input signal moves outside the
specified range, the output signal will exhibit increasingly
higher levels of harmonic distortion.
The Charge Pump
The ISL59832 charge pump provides a bottom rail up to
1.5V below ground while operating on a 3.0V to 3.6V power
supply. The charge pump is driven by an internal 13MHz
clock.
Output Amplifier
To reduce the noise on the power supply generated by the
charge pump connect a lowpass RC-network between
The ISL59832 output amplifiers provide a gain of +6dB. The
Channel 1 output amplifier is able to drive a 2.8VP-P video
FN6267.1
June 11, 2008
11
ISL59832
VEEOUT and VEEIN. See the Typical Application Circuit for
further information.
SYNC DETECTOR AND CLAMP TIMING
Channel 1 and Channel 3 also have sync detectors whose
outputs are available at SYNC_OUT.
VEE
Pin
OUT
The slice level for the sync detector is between 100 to
200mV. This means that if the signal level is below 100mV at
Channel 1, then SYNC_OUT is high. If the signal level is
above 200mV then SYNC_OUT is low. Figure 28 shows the
operation of the sync detector.
VEEOUT is the output pin for the charge pump. Keep in mind
that the output of this pin is a fully regulated supply that must
be properly bypassed. Bypass this pin with a 0.47µF ceramic
capacitor placed as close to the pin and connected to the
ground plane of the board.
NTSC LUMINANCE
CHANNEL 1 INPUT
VEE Pin
IN
+1.00V
VEEIN is the subtrate connection for the ISL59832. To
reduce the noise on the power supply generated by the
charge pump, connect a lowpass RC-network between
VEEOUT and VEEIN. See the “S-Video Typical Application
Circuit” on page 6 for further information.
+300mV
100mV < VSLICE < 200mV
+0mV
Video Performance
DIFFERENTIAL GAIN/PHASE
SYNC_OUT
For good video performance, an amplifier is required to
maintain the same output impedance and the same
frequency and phase response as DC levels are changed at
the output. Special circuitry has been incorporated into the
ISL59832 to reduce the output impedance variation with the
current output. This results in outstanding differential gain
and differential phase specifications of 0.45% and 0.15°,
while driving 150Ω at a gain of +2V/V.
+3.3V
+0mV
FIGURE 28. SYNC DETECTOR SLICE LEVEL
DC-Coupled Inputs (Channel 1)
When DC-coupling the inputs ensure that the lowest signal
level is greater than +50mV to prevent the clamp from
turning on and distorting the output. When DC-coupled the
ISL59832 shifts the signal by -620mV.
NTSC
The ISL59832, generating a negative rail internally, is ideally
suited for NTSC video with its accompanying negative-going
sync signals.
Amplifier Disable
The ISL59832 can be disabled and its outputs placed in high
impedance states. The turn-off time is around 10ns and the
turn-on time is around 35µs. The turn-on time is longer
because extra time is needed for the charge pump to settle
before the amplifiers are enabled. When disabled, the device
supply current is reduced to 2µA typically, reducing power
consumption. The device’s power-down can be controlled by
standard TTL or CMOS signal levels at the ENABLE pin.
The applied logic signal is relative to the GND pin. Applying
a signal that is less than 0.8V above GND will disable the
device. The device will be enabled when the ENABLE signal
is 2V above GND.
S-VIDEO
For a typical S-video application, connect the luma signal to
Channel 1, and connect the chrominance signal to
Channel 2. For clamp timing connect SYNC_OUT to
SYNC_IN. See the “S-Video Typical Application Circuit” on
page 6.
AC-Coupled Inputs
SYNC TIP CLAMP (CHANNEL 1)
The ISL59832 features a sync tip clamp that sets the black
level of the output video signal to ground. This ensures that
the sync-tip voltage level will be approximately -300mV at
the back-termination resistor of a standard video load. The
clamp is activated whenever the input voltage falls below 0V.
The correction voltage required to do this is stored across
the input AC-coupling capacitor. Refer to “S-Video Typical
Application Circuit” on page 6 for a detailed diagram.
Output Drive Capability
The maximum output current for the ISL59832 is ±50mA.
Maximum reliability is maintained if the output current never
exceeds ±50mA, after which the electro-migration limit of the
process will be exceeded and the part will be damaged. This
limit is set by the design of the internal metal interconnections.
Driving Capacitive Loads and Cables
KEYED CLAMP (CHANNEL 2)
The ISL59832, internally-compensated to drive 75Ω cables,
will drive 10pF loads in parallel with 150Ω or 75Ω with less
than 1.3dB of peaking.
Channel 2 has a keyed clamp which sets the output to
ground when SYNC_IN is driven to the logic high state.
SYNC_IN may be connected to SYNC_OUT which ensures
that Channel 2 clamps during the sync interval for Y-C
applications.
FN6267.1
June 11, 2008
12
ISL59832
By setting Equation 1 equal to Equation 2 and 3, we can
Power Dissipation
solve for the output current and RLOAD values needed to
avoid exceeding the maximum junction temperature.
With the high output drive capability of the ISL59832, it is
possible to exceed the +150°C absolute maximum junction
temperature under certain load current conditions.
Therefore, it is important to calculate the maximum junction
temperature for an application to determine if load conditions
or package types need to be modified to assure operation of
the amplifier in a safe operating area.
Power Supply Bypassing and Printed Circuit
Board Layout
As with any high frequency device, a good printed circuit
board layout is necessary for optimum performance. Strip
line design techniques are recommended for the input and
output signal traces to help control the characteristic
impedance. Furthermore, the characteristic impedance of
the traces should be 75Ω. Trace lengths should be as short
as possible between the output pin and the series 75Ω
resistor. The power supply pin must be well bypassed to
reduce the risk of oscillation. For normal single supply
operation, a single 4.7µF tantalum capacitor in parallel with a
0.1µF ceramic capacitor from VS and VCP to GND will
suffice.
The maximum power dissipation allowed in a package is
determined according to Equation 1:
T
– T
AMAX
JMAX
(EQ. 1)
--------------------------------------------
PD
=
MAX
Θ
JA
Where:
JMAX = Maximum junction temperature
TAMAX = Maximum ambient temperature
JA = Thermal resistance of the package
T
The AC performance of this circuit depends greatly on the
care taken in designing the PC board. The following are
recommendations to achieve optimum high frequency
performance from your PC board.
Θ
The maximum power dissipation actually produced by an IC
is the total quiescent supply current times the total power
supply voltage, plus the power in the IC due to the load, or:
• Use low inductance components, such as chip resistors
and chip capacitors whenever possible.
for sourcing:
• Minimize signal trace lengths. Trace inductance and
capacitance can easily limit circuit performance. Avoid
sharp corners; use rounded corners when possible. Vias
in the signal lines add inductance at high frequency and
should be avoided. PCB traces longer than 1" begin to
exhibit transmission line characteristics with signal rise/fall
times of 1ns or less. To maintain frequency performance
with longer traces, use striplines.
V
i
OUT
R i
L
(EQ. 2)
(EQ. 3)
-----------------
i) ×
OUT
PD
= V × I
+ (V – V
MAX
S
SMAX
S
for sinking:
PD
= V × I
+ (V
i – V ) × I
i
LOAD
MAX
S
SMAX
OUT
S
• Match channel-to-channel analog I/O trace lengths and
layout symmetry. This will minimize propagation delay
mismatches.
Where:
VS = Supply voltage
• Route all signal I/O lines over continuous ground planes
(i.e. no split planes or PCB gaps under these lines).
ISMAX = Maximum quiescent supply current
VOUT = Maximum output voltage of the application
RLOAD = Load resistance tied to ground
ILOAD = Load current
• Place termination resistors in their optimum location as
close to the device as possible.
• Use good quality connectors and cables, matching cable
types and keeping cable lengths to a minimum when
testing.
i = Number of output channels
• Place flying and output capacitor as close to the device as
possible for the charge pump.
• Decouple well, using a minimum of 2 power supply
decoupling capacitors, placed as close to the device as
possible. Avoid vias between the capacitor and the device
because vias adds unwanted inductance. Larger caps may
be farther away. When vias are required in a layout, they
should be routed as far away from the device as possible.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6267.1
June 11, 2008
13
ISL59832
QFN (Quad Flat No-Lead) Package Family
MDP0046
QFN (QUAD FLAT NO-LEAD) PACKAGE FAMILY
(COMPLIANT TO JEDEC MO-220)
A
MILLIMETERS
D
B
SYMBOL QFN44 QFN38
QFN32
TOLERANCE
±0.10
NOTES
A
A1
b
0.90
0.02
0.25
0.20
7.00
5.10
7.00
5.10
0.50
0.55
44
0.90 0.90
0.90
0.02
0.22
0.20
5.00
-
-
0.02 0.02
0.25 0.23
0.20 0.20
5.00 8.00
+0.03/-0.02
±0.02
1
2
3
PIN #1
I.D. MARK
-
c
Reference
Basic
-
E
D
-
D2
E
3.80 5.80 3.60/2.48
7.00 8.00 6.00
5.80 5.80 4.60/3.40
Reference
Basic
8
-
2X
0.075 C
E2
e
Reference
Basic
8
-
0.50 0.80
0.40 0.53
0.50
0.50
32
2X
0.075 C
L
±0.05
-
TOP VIEW
N
38
7
32
8
Reference
Reference
Reference
4
6
5
ND
NE
11
7
11
12
8
9
0.10 M C A B
b
L
MILLIMETERS
SYMBOL QFN28 QFN24 QFN20
PIN #1 I.D.
TOLER-
ANCE NOTES
3
QFN16
0.90
1
2
3
A
0.90
0.02
0.90 0.90
0.90
0.02
±0.10
-
-
A1
0.02 0.02
0.02
+0.03/
-0.02
(E2)
b
c
0.25
0.20
4.00
2.65
5.00
3.65
0.50
0.40
28
0.25 0.30
0.20 0.20
4.00 5.00
2.80 3.70
5.00 5.00
3.80 3.70
0.50 0.65
0.40 0.40
0.25
0.20
4.00
2.70
4.00
2.70
0.50
0.40
20
0.33
±0.02
-
-
0.20 Reference
4.00 Basic
2.40 Reference
4.00 Basic
2.40 Reference
5
NE
D
-
D2
E
-
-
7
(D2)
E2
e
-
BOTTOM VIEW
0.65
0.60
16
Basic
-
L
±0.05
-
0.10 C
e
N
24
5
20
5
Reference
Reference
Reference
4
6
5
C
ND
NE
6
5
4
SEATING
PLANE
8
7
5
5
4
Rev 11 2/07
0.08 C
NOTES:
SEE DETAIL "X"
N LEADS
& EXPOSED PAD
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
2. Tiebar view shown is a non-functional feature.
SIDE VIEW
3. Bottom-side pin #1 I.D. is a diepad chamfer as shown.
4. N is the total number of terminals on the device.
(c)
2
5. NE is the number of terminals on the “E” side of the package
(or Y-direction).
A
C
6. ND is the number of terminals on the “D” side of the package
(or X-direction). ND = (N/2)-NE.
(L)
A1
7. Inward end of terminal may be square or circular in shape with radius
(b/2) as shown.
N LEADS
DETAIL X
8. If two values are listed, multiple exposed pad options are available.
Refer to device-specific datasheet.
FN6267.1
June 11, 2008
14
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