ISL59885 [INTERSIL]
Auto-Adjusting Sync Separator for HD and SD Video; 自动调整同步分离器的HD和SD视频
| 型号： | ISL59885 |
| 厂家： | 
Intersil |
| 描述： | Auto-Adjusting Sync Separator for HD and SD Video |
| 文件： | 总13页 (文件大小：515K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISL59885
®
Data Sheet
September 8, 2005
FN7442.3
Auto-Adjusting Sync Separator for HD
and SD Video
Features
• NTSC, PAL, SECAM, HDTV, non-standard video sync
separation
The ISL59885 video sync separator is manufactured using
high performance analog CMOS process. This device
extracts ISL59885 sync timing information from both
standard and non-standard video input in the presence of
Macrovision pulses. It provides composite sync, vertical
sync, SD and HDTV detection, and horizontal sync outputs.
Fixed 70mV sync tip slicing provides sync edge detection
• Fixed 70mV slicing of video input levels from 0.5V
P-P
to
2V
P-P
• Single 3V to 5V supply
• Composite sync output
• Vertical output
when the video input level is between 0.5V
and 2V .
P-P
P-P
• Horizontal output
Timing is adjusted automatically for various video standards.
The composite sync output follows sync pulses and a
vertical sync pulse is output on the rising edge of the first
vertical serration following the vertical pre-equalizing string.
For non-standard vertical inputs, a default vertical pulse is
output when the vertical signal stays low for longer than the
vertical sync default delay time. The horizontal output gives
horizontal timing with pre/post equalizing pulses. ISL59885
has an auto input frequency detect feature that sets the right
timing for any input format.
• HDTV detection
• 81% to 90% Hsync blanking window (R5218)
• Macrovision compatible
• Available in 8 Ld SO package
• Pb-Free plus anneal available (RoHS compliant)
Applications
• High definition video equipment
The ISL59885 is available in an 8 Ld SO package and is
specified for operation over the full -40°C to +85°C
temperature range.
Demo Board
• A dedicated demo board is available
Ordering Information
Pinout
PART
TAPE &
REEL
-
7”
13”
-
PKG.
NUMBER
ISL59885IS
PACKAGE
8 Ld SO
8 Ld SO
8 Ld SO
DWG. #
ISL59885
(8 LD SO)
TOP VIEW
MDP0027
MDP0027
MDP0027
MDP0027
ISL59885IS-T7
ISL59885IS-T13
COMPOSITE SYNC OUT
COMPOSITE VIDEO IN
VERTICAL SYNC OUT
GND
1
2
3
4
8
7
6
5
VDD
ISL59885ISZ
(See Note)
8 Ld SO
(Pb-Free)
HORIZONTAL OUTPUT
ISL59885ISZ-T7
(See Note)
8 Ld SO
(Pb-Free)
7”
MDP0027
MDP0027
CSET
HD
ISL59885ISZ-T13
(See Note)
8 Ld SO
(Pb-Free)
13”
ISL59885ISR5218
ISL59885ISZR5218
8 Ld SO
-
-
MDP0027
MDP0027
8 Ld SO
(Pb-Free)
ISL59885IS-T7R5218
ISL59885ISZ-T7R5218
8 Ld SO
7”
7”
MDP0027
MDP0027
8 Ld SO
(Pb-Free)
ISL59885IS-T13R5218
ISL59885ISZ-T13R5218
8 Ld SO
13”
13”
MDP0027
MDP0027
8 Ld SO
(Pb-Free)
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100% matte
tin plate termination finish, which are RoHS compliant and compatible with
both SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2005. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.
ISL59885
Absolute Maximum Ratings (T = 25°C)
A
V
Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7V
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .400mW
CC
Pin Voltages. . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to V
+0.5V
CC
Operating Ambient Temperature Range . . . . . . . . . .-40°C to +85°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified
temperature and are pulsed tests, therefore: T = T = T
A
J
C
DC Electrical Specifications
V
= 3.3V, T = 25°C, C = 56nF, unless otherwise specified.
SET
DD
A
PARAMETER
DESCRIPTION
MIN
1.5
1.35
6
TYP
2.2
MAX
4
UNIT
mA
V
I
, Quiescent
V
= 3.3V
DD
DD
Pin 2, I
Clamp Voltage
= -100µA
1.5
1.65
30
LOAD
Clamp Discharge Current
Clamp Charge Current
Pin 2 = 2V
Pin 2 = 1V
15
µA
mA
V
-9
-7.2
0.24
3.2
-5.2
0.5
V
V
Output Low Voltage
Output High Voltage
I
I
I
= 1.6mA
= -40µA
= -1.6mA
OL
OL
OH
OH
3
V
OH
2.5
3.0
V
Dynamic Characteristics
PARAMETER
DESCRIPTION
MIN
TYP
35
MAX
75
UNIT
ns
Comp Sync Prop Delay, t
See Figure 9
See Figure 9
See Figure 9
CS
Horizontal Sync Delay, t
Horizontal Sync Width, t
40
80
ns
HS
3.8
5.2
280
6.2
350
µs
HS-PW
Vertical Sync Width, t
VS
Normal or default trigger, 50% - 50%, see
Figure 7
230
µs
Vertical Sync Default Delay, t
Hsync Blanking Window
Input Dynamic Range
See Figure 10
28
81
50
85
68
90
2
µs
%
VSD
ISL59885IS-R5218 only
Video input amplitude to maintain slice level
0.5
V
P-P
spec, V
= 3.3V
DD
Slice Level
V
above V
50
70
0
90
mV
V
SLICE
CLAMP
HD Pin Level
720p, 1080i, 1080p
Pin Descriptions
PIN NUMBER
PIN NAME
PIN FUNCTION
1
COMPOSITE
SYNC OUT
Composite sync pulse output; sync pulses start on a falling edge and end on a rising edge
2
3
COMPOSITE
VIDEO IN
AC coupled composite video input; sync tip must be at the lowest potential (positive picture phase)
Vertical sync pulse output; the falling edge of vert sync is the start of the vertical period
VERTICAL
SYNC OUT
4
5
6
7
GND
HD
Supply ground
Low when input horizontal frequency is greater than 20kHz
(An external capacitor to ground); bypass pin for internal bias generator.
Horizontal output; falling edge active
CSET
HORIZONTAL
OUTPUT
8
VDD
Positive supply
FN7442.3
September 8, 2005
2
ISL59885
Typical Performance Curves
V =3.3V & 5.0V
V =3.3V & 5.0V
S
S
H
(kHz)
H
FREQUENCY (kHZ)
SYNC
SYNC
FIGURE 1. H
SYNC
vs V
(R
CSET SET
= OPEN)
FIGURE 2. H
PULSEWIDTH vs H FREQUENCY
SYNC
SYNC
(R = OPEN)
SET
V =3.3V & 5.0V
S
VIN
0.5V/DIV
HSYNC
VSYNC
5V/DIV
5V/DIV
5V/DIV
CSYNC
100µs/DIV
V
(V)
CSET
FIGURE 4. MACROVISION COMPATIBILITY (NTSC)
FIGURE 3. H
SYNC
vs V
(R = OPEN)
CSET SET
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
1.2
1.8
1.6
1.4
1.2
1
1
781mW
0.8
1.136W
0.6
0.4
0.2
0
0.8
0.6
0.4
0.2
0
0
25
50
75 85 100
125
150
0
25
50
75 85 100
125
150
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 5. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
FIGURE 6. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
FN7442.3
September 8, 2005
3
ISL59885
SIGNAL 1a. COMPOSITE VIDEO INPUT, FIELD ONE
1.5µs ±0.1µs
TIME
+H
-H
+63.5µs
-0µs
VERTICAL BLANKING INTERVAL = 20H
1271µs
9
3H
8
3H
2
3H
5
1
3
4
6
7
10
19
H
20
21
START OF
FIELD ONE
H SYNC
H
H
0.5H
INTERVAL
PRE-EQUALIZING
PULSE INTERVAL
VERTICAL SYNC
PULSE INTERVAL
POST-EQUALIZING
PULSE INTERVAL
H
REF SUBCARRIER PHASE,
COLOR FIELD ONE
9 LINE VERTICAL INTERVAL
SIGNAL 1b. COMPOSITE SYNC OUTPUT, PIN 1
SIGNAL 1c. VERTICAL SYNC OUTPUT, PIN 3
t
VS
SIGNAL 1d. HORIZONTAL SYNC OUTPUT, PIN 7
NOTES:
b. The composite sync output reproduces all the video input sync pulses, with a propagation delay.
c. Vertical sync leading edge is coincident with the first vertical serration pulse leading edge, with a propagation delay.
d. Horizontal sync output produces the true “H” pulses of nominal width of 5µs. It has the same delay as the composite sync.
FIGURE 7. TIMING DIAGRAM
FN7442.3
4
September 8, 2005
ISL59885
CONDITIONS: V
= V
= V
= +5V, T = 25°C, NO FILTER (REGISTER 2 BIT 4=0)
CCD A
CCA1
CCA2
WHITE LEVEL
COLOR BURST
INPUT
DYNAMIC
RANGE
VIDEO
SYNC
SYNC LEVEL
50%
0.5V-2V
(@V
=5V)
SYNC IN
CCA1
0.5V-1V
=3.3V)
V
BLANK
(@V
CCA1
(BLANKING LEVEL
VOLTAGE)
V
SLICE
V
SYNC
(SYNC TIP
VOLTAGE)
SYNC
TIP
td
SYNCOUT
DEPENDS ON WIDTH OF INPUT SYNC AT 50% LEVEL
SYNC OUT
td
HOUT
H
OUT
T
HOUT
FIGURE 8. HORIZONTAL INTERVAL 525/625 LINE COMPOSITE
TYP
PARAMETER
DESCRIPTION
CONDITIONS
(Note 1)
65
UNIT
ns
td
td
SYNCOUT Timing Relative to Input
HOUT Timing Relative to Input
Horizontal Output Width
See Figure 8
See Figure 8
See Figure 8
SYNCOUT
HOUT
470
ns
T
5.2
us
HOUT
NOTE:
1. Delay variation is less than 2.5ns over temperature range.
FN7442.3
5
September 8, 2005
ISL59885
SIGNAL 2a.
COMPOSITE
VIDEO INPUT
SLICE LEVEL
70mV
COMP SYNC
t
CS
PROP DELAY
SIGNAL 2b.
COMPOSITE
SYNC OUTPUT
COMP SYNC -
t
CS-VS
SIGNAL 2c.
VERTICAL
VERT SYNC DELAY
SYNC OUTPUT
t
HS
SIGNAL 2d.
HORIZONTAL
SYNC OUTPUT
t
HS-PW
FIGURE 9. STANDARD VERTICAL TIMING
LINES
2
3
4
5
SIGNAL 3a.
COMPOSITE
VIDEO INPUT
(NO VERTICAL SYNC PULSES)
VERT SYNC
t
VSD
DEFAULT DELAY
SIGNAL 3b.
VERTICAL
SYNC OUTPUT
FIGURE 10. NON-STANDARD VERTICAL TIMING
FN7442.3
6
September 8, 2005
ISL59885
COMPOSITE VIDEO INPUT, BEGINNING OF FIELD ONE
START OF FIELD ONE
622
623
624
625
1
2
3
4
5
6
7
23
24
SYNCOUT OUTPUT
V
OUTPUT
OUTPUT
OUT
OUT
T
VS
H
NOTES:
b. The composite sync output reproduces all the video input sync pulses, with a propagation delay.
c. Vertical sync leading edge is coincident with the first vertical serration pulse leading edge, with a propagation delay.
FIGURE 11. EXAMPLE OF VERTICAL INTERVAL (625)
SYNCIN
1123
1124
1125
1
2
3
4
5
6
7
8 ...
21
SYNCOUT
H
V
OUT
OUT
SYNCIN
560
561
562
563
564
565
566
567
568
569
570 ... 583
SYNCOUT
H
OUT
V
OUT
FIGURE 12. EXAMPLE OF HDTV 1080I/30 LINE COMPOSITE VIDEO: INTERLACED
FN7442.3
September 8, 2005
7
ISL59885
SYNCIN
1245
1246
1247
1248
1249
1250
1
2
3
4
5 ...
48
SYNCOUT
H
V
OUT
OUT
SYNCIN
620
621
622
623
624
625
626
627
628
629
630 ... 673
SYNCOUT
H
OUT
V
OUT
FIGURE 13. HDTV 1080I/25 LINE COMPOSITE VIDEO: INTERLACED (1250 LINES)
FN7442.3
September 8, 2005
8
ISL59885
CONDITIONS: V
SYNCIN
= V
= V = +3.3V/+5V, T = 25°C, NO FILTER (REGISTER 2 BIT 4=0)
CCD A
CCA1
CCA2
td
SYNCOUT
SYNC OUT
td
HOUT
H
OUT
T
HOUT
FIGURE 14. HORIZONTAL INTERVAL (HDTV) (720p)
H Timing for HDTV, No Filter (using 720p input signal)
TYP
TYP
@ 3.3V
@ 5V
PARAMETER
DESCRIPTION
SYNCOUT Timing Relative to Input
HOUT Timing Relative to Input
Horizontal Output Width
CONDITIONS
(Note 1) (Note 1)
UNIT
ns
td
See Figure 14
See Figure 14
See Figure 14
56
48
50
36
SYNCOUT
HOUT
td
ns
T
1.90
1.90
us
HOUT
NOTE:
1. Delay variation is less than 2.5ns over temperature range.
FN7442.3
9
September 8, 2005
ISL59885
CONDITIONS: V
SYNCIN
= V
CCA2
= V = +3.3V/+5V, T = 25°C, FILTER (REGISTER 2 BIT 4=1)
CCD A
CCA1
td
SYNCOUT
SYNC OUT
td
HOUT
H
OUT
T
HOUT
FIGURE 15. HORIZONTAL INTERVAL (HDTV) (720p)
H Timing for HDTV, With Filter (using 720p input)
TYP
TYP
@ 3.3V
@ 5V
PARAMETER
DESCRIPTION
SYNCOUT Timing Relative to Input
HOUT Timing Relative to Input
Horizontal Output Width
CONDITIONS
(Note 1) (Note 1)
UNIT
ns
td
See Figure 15
See Figure 15
See Figure 15
120
112
200
110
100
200
SYNCOUT
HOUT
td
ns
T
ns
HOUT
NOTE:
1. Delay variation is less than 2.5ns over temperature range.
FN7442.3
10
September 8, 2005
ISL59885
present on the I/P signal after the true H sync will be ignored,
Applications Information
Video In
thus the horizontal output will not be affected by MacroVision
copy protection. When loss of sync, the Horizontal Sync
output is held high.
A simplified block diagram is shown following page.
An AC coupled video signal is input to Video In pin 2 via C ,
1
C
SET
nominally 0.1µF. Clamp charge current will prevent the
signal on pin 2 from going any more negative than Sync Tip
Ref, about 1.5V. This charge current is nominally about 1mA.
A clamp discharge current of about 10µA is always
An external C
capacitor connected from C
pin 6 to
SET
SET
capacitor should be a X7R grade or better as
ground. C
SET
the Y5U general use capacitors may be too leaky and cause
faulty operation. The C capacitor should be very close to
SET
pin to reduce possible board leakage. 56nF is
attempting to discharge C to Sync Tip Ref, thus charge is
1
the C
recommended. C
diagram 5. The C
and creates a voltage on C
converted to bias current for H
SET
lost between sync pulses that must be replaced during sync
pulses. The droop voltage that will occur can be calculated
from IT = CV, where V is the droop voltage, I is the discharge
current, T is the time between sync pulses (sync period -
simplified block diagram is shown in
capacitor rectifies 5us pulse current
SET
SET
. The C
voltage is
timing.
SET SET
and V
SYNC
SYNC
sync tip width), and C is C .
1
Chroma Filter
An NTSC video signal has a horizontal frequency of
A chroma filter is suggested to increase the S/N ratio of the
incoming video signal. Use of the optional chroma filter is
shown in the figure below. It can be implemented very simply
and inexpensively with a series resistor of 100Ω and a
capacitor of 570pF, which gives a single pole roll-off
frequency of about 2.79MHz during NTSC or PAL. This
sufficiently attenuates the 3.58MHz (NTSC) or 4.43MHz
(PAL) color burst signal, yet passes the approximately 15kHz
sync signals without appreciable attenuation. During HDTV,
the transistor turns off and a 100pF capacitor is left to filter
any noise present at the input. A chroma filter will increase
the propagation delay from the composite input to the
outputs.
15.73kHz, and a sync tip width of 4.7µs. This gives a period
of 63.6µs and a time T = 58.9µs. The droop voltage will then
be V = 5.9mV. This is less than 2% of a nominal sync tip
amplitude of 286mV. The charge represented by this droop
is replaced in a time given by T = CV/I, where I = clamp
charge current = 5.3mA. Here T = 590ns, about 12% of the
sync pulse width of 4.7µs. It is important to choose C large
1
enough so that the droop voltage does not approach the
switching threshold of the internal comparator.
Composite Sync
The Composite Sync output is simply a reproduction of the
input signal with the active video removed. The sync tip of
the Composite video signal is clamped to 1.5V at pin 2 and
then slices at 70mV above the sync tip reference. The output
signal is buffered out to pin 1. When loss of sync, the
Composite Sync output is held low.
ISL59885
CHROMA FILTER
1
2
3
4
C
V
8
7
6
5
SYNC
DD
0.1µF
VIDEO IN
R
F
C
H
C
VIN
OUT
100Ω
Vertical Sync
V
SYNC
SET
HD
A low-going Vertical Sync pulse is output during the start of
the vertical cycle of the incoming video signal. The vertical
cycle starts with a pre-equalizing phase of pulses with a duty
cycle of about 93%, followed by a vertical serration phase
that has a duty cycle of about 15%. Vertical Sync is clocked
out of the ISL59885 on the first rising edge during the
vertical serration phase. In the absence of vertical serration
pulses, a vertical sync pulse will be forced out after the
vertical sync default delay time, approximately 60µs after the
last falling edge of the vertical equalizing phase.
C
F
GND
100pF
C
F2
470pF
10kΩ
MMBT3904
HD-Detect
High definition video is flagged by HD going low when the
input horizontal frequency is greater than 20kHz.
Horizontal Sync
The horizontal circuit senses the composite sync edges and
produces the true horizontal pulses of nominal width 5.2µs.
The leading edge is triggered from the leading edge of the
input H sync, with the same propagation delay as composite
sync. The half line pulses present in the input signal during
vertical blanking are removed with an internal 2H line
eliminator circuit. This is a circuit that inhibits horizontal
output pulses until 75% of the line time is reached, then the
horizontal output operation is enabled again. Any signals
FN7442.3
September 8, 2005
11
ISL59885
Simplified Block Diagram
CLAMP
SYNC TIP REF
V
5V
1.5V
DD
V
8
DD
C
2
0.1µF
COMPOSITE
VIDEO IN
C
1
R
COMP.
F
2
-
COMPOSITE
SYNC
C
1
F
620Ω
SLICE
1.57V
+
0.1µF
510pF
GND
4
6
HD
5
3
7
HD
C
DETECTOR
SET
SYNC
C
3
REF
GEN
TIP
70mV
SLICE
56nF
VERTICAL
SYNC OUT
V SYNC
HORIZONTAL
SYNC OUT
H SYNC
2 H
ELIMINATOR
C
Bias Circuit
SET
V
V
DD
DD
C
+
-
SYNC
PULSE
5µs
C
SET
56nF
I
- TIMING
BIAS
FN7442.3
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September 8, 2005
ISL59885
Package Outline Drawing
NOTE: The package drawing shown here may not be the latest version. To check the latest revision, please refer to the Intersil website at
http://www.intersil.com/design/packages/index.asp
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN7442.3
13
September 8, 2005
相关型号：
ISL59885ISZ
Auto-Adjusting Sync Separator for HD and SD Video; SOIC8; Temp Range: -40° to 85°C
RENESAS
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