ISL59834 [INTERSIL]
Quad Channel, Single Supply, Video Reconstruction Filter with On-Board Charge Pump; 四通道，单电源，具有板载电荷泵视频重建滤波器
| 型号： | ISL59834 |
| 厂家： | 
Intersil |
| 描述： | Quad Channel, Single Supply, Video Reconstruction Filter with On-Board Charge Pump |
| 文件： | 总17页 (文件大小：1226K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISL59834
®
Data Sheet
June 11, 2008
FN6268.1
Quad Channel, Single Supply, Video
Reconstruction Filter with On-Board
Charge Pump
Features
• 3.3V Nominal Supply, Operates Down to 3.0V
• DC-Coupled Outputs
The ISL59834 is a quad channel, single supply, video
reconstruction filter with integrated charge pump. It is
designed to operate on a single supply (3.0V to 3.6V) and
generate its own negative supply (-1.5V) using a regulated
charge pump. Input signals to the ISL59834 can be AC- or
DC-coupled. When AC-coupled, the backporch clamp sets
the blank level to ground at the output. Channels 1 and 3
have a sync detector whose output is available at
SYNC_OUTA and SYNC_OUTB, respectively. SYNC_INA
and SYNC_INB are inputs that provide timing for Channel 2
and Channel 4, respectively. Channel 2 and Channel 4 have
keyed clamps, which set the outputs to ground when
SYNC_INA or SYNC_INB are driven to the logic high state.
Each of the four outputs are capable of driving two DC or
AC-coupled standard video loads. The ISL59834 features a
4th order Butterworth reconstruction filter that provides a
9MHz nominal -3dB frequency and 40dB of attenuation at
27MHz. Nominal operational current is 63mA. When
powered down, the device draws 5µA maximum supply
current. The ISL59834 is available in a 44 Ld 7x7 QFN
package.
• Inputs can be AC- or DC-Coupled
• Eliminates the Need for Large Output Coupling Capacitor
• Integrated Sync Tip Clamp sets the Backporch to Ground
at the Output for Channels 1 and 3
• Integrated Keyed Clamp puts Channel 2 and Channel 4
Outputs to Ground During Sync
• Each Output Drives 2 Standard Video Loads
• Response Flat to 5MHz with 40dB Attenuation at 27MHz
• Pb-Free (RoHS compliant)
Applications
• Set-Top Box Receiver
• Television
• DVD Player
• Digital Camera
• Cell Phone
Ordering Information
Block Diagram
PART
NUMBER
(NOTE)
TEMP.
RANGE
(°C)
PART
MARKING
PACKAGE
(Pb-Free)
PKG.
DWG. #
ISL59834
CHANNEL 1
ISL59834IRZ
59 834IRZ -40 to +85 44 Ld QFN
L44.7x7A
CLAMP +
SYNC
DETECTOR
LPF
VIDEO IN
(Y)
VIDEO OUT
(Y)
x2
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination
finish, which is RoHS compliant and compatible with both SnPb and
Pb-free soldering operations). Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020.
9MHz
CHARGE PUMP
CHANNEL 2
LPF
VIDEO IN
(C)
KEYED
CLAMP
VIDEO OUT
(C)
x2
9MHz
CHARGE PUMP
CHANNEL 3
CLAMP +
SYNC
DETECTOR
LPF
VIDEO IN
(Y)
VIDEO OUT
(Y)
x2
9MHz
CHARGE PUMP
CHANNEL 4
LPF
VIDEO IN
(C)
KEYED
CLAMP
VIDEO OUT
(C)
x2
9MHz
CHARGE PUMP
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2008. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL59834
Pinout
ISL59834
(44 LD QFN)
TOP VIEW
44 43 42 41 40 39 38 37 36 35 34
GND
IN2
OUT2
VEEA
VEEA
1
2
33
32
31
30
29
28
27
26
25
24
23
IN
GND
3
OUT
GND
CAPA+
CAPA-
4
CPA
CPA
V
5
V
S
CLK
B
6
ENABLE
SYNC_OUTB
SYNC_INB
OUT3
7
B
IN3
GND
IN4
8
9
OUT4
10
11
GND
VEEB
IN
12 13 14 15 16 17 18 19 20 21 22
FN6268.1
June 11, 2008
2
ISL59834
Absolute Maximum Ratings (TA = +25°C)
Thermal Information
VS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4V
IN to GND. . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to VS + 0.3V
Thermal Resistance (Typical, Note 1)
θ
JA (°C/W)
32
V
44 Lead QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . ±50mA
Maximum Current into Any Pin . . . . . . . . . . . . . . . . . . . . . . . ±50mA
ESD Rating
Human Body Model (Per MIL-STD-883 Method 3015.7) . . .3500V
Machine Model (Per EIAJ ED-4701 Method C-111). . . . . . . .350V
Maximum Junction Temperature (Plastic Package) . . . . . . . +150°C
Maximum Storage Temperature Range. . . . . . . . . .-65°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: T = T = T
A
J
C
NOTE:
1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
Electrical Specifications VCP = VS = 3.3V, CF1 = CF2 = 0.1µF, CS1 = CS2 = 0.22µF, CFIL1 = CFIL2 = 0.4µF, CIN1 = CIN2 = CIN3 = CIN4
0.1µF, RL1 = RL2 = 150Ω, Typical TA = +27°C.
=
MIN
MAX
SYMBOL
PARAMETER
CONDITIONS
(Note 2) TYP (Note 2) UNIT
DC CHARACTERISTICS
V
S, VCP
Supply Range
Guaranteed by PSRR
3.0
3.3
-1.5
28
35
0.6
4
3.6
-1.25
32
V
V
VEEOUT
Charge Pump Output
Supply Current
Measured at VEEIN
No load
-1.75
IS
mA
mA
µA
µA
µA
V/V
V
ICP
Charge Pump Supply Current
Power-down Current
Input Pull-down Current
Input Bias Current
DC Gain
No load
40
IPD
ENABLE = 0.4V
5
IIN
IB
Channels 1 and 3, VIN = 0.5V
Channels 2 and 4, VIN = 0.5V, SYNC_IN = 0V
0.4
-10
10
-3
10
AV
1.94
1.4
2
2.05
VIN_MAX
VCLAMPOUT1
Max DC Input Range
DC-coupled input, guaranteed by DC gain test
Output Sync Tip Clamp Level
(Channels 1 and 3)
VIN ≤ 0, AC-coupled input
-650
-590
-25
-525
0
mV
VCLAMPOUT2
VCLAMPIN1
VCLAMPIN2
VOS
Keyed Clamp Level
(Channels 2 and 4)
Output level when SYNC_IN ≥ 2.0V
Input floating
-60
0
mV
mV
mV
mV
mV
Input Clamp Level
(Channels 1 and 3)
30
70
Input Keyed Clamp Level
(Channels 2 and 4)
Input floating, input level when SYNC_IN ≥ 2.0V
275
-685
-380
300
-620
-330
375
-550
-280
-2.5
Output Level Shift
(Channels 1 and 3)
VIN > 0, output shifted relative to input, DC-coupled
input
Output Level Shift
(Channels 2 and 4)
VIN > 0, output shifted relative to input, DC-coupled
input
ICLAMP
Clamp Restore Current
Force VIN = -0.3V, Channels 1 and 3
Force VIN = 1V, Channel 2 and 4
Force VIN = -0.3V, Channels 2 and 4
Channels 1 and 3
-5
mA
µA
µA
mV
dB
135
180
-200
-160
200
VSLICE
Sync Detect Threshold
Power Supply Rejection
100
50
PSRRDC
VS = +3.0 to +3.6
77
FN6268.1
June 11, 2008
3
ISL59834
Electrical Specifications VCP = VS = 3.3V, CF1 = CF2 = 0.1µF, CS1 = CS2 = 0.22µF, CFIL1 = CFIL2 = 0.4µF, CIN1 = CIN2 = CIN3 = CIN4
0.1µF, RL1 = RL2 = 150Ω, Typical TA = +27°C. (Continued)
=
MIN
MAX
SYMBOL
PARAMETER
CONDITIONS
(Note 2) TYP (Note 2) UNIT
AC CHARACTERISTICS
APB
ASB
dG
Passband Flatness
f = 5MHz relative to 100kHz
0
0.8
-50
1.25
-35
dB
dB
%
Stopband Attenuation
Differential Gain
f ≥ 27MHz relative to 100kHz
11-step modulated staircase
11-step modulated staircase
0.45
-0.15
60
dP
Differential Phase
Signal-to-Noise Ratio
°
SNR
Peak signal (1.4VP-P) to RMS noise, f = 10kHz to
10MHz
dB
GDMATCH
DC Group Delay Match
Channel-to-channel group delay matching at
100kHz
0.1
ns
ΔGD
PSRR
XTALK
VNOISE
Group Delay Deviation
Power Supply Rejection
Channel-to-Channel Crosstalk
Input Voltage Noise
Deviation from 100kHz to 3.58MHz
8
ns
dB
VIN = 100mVP-P sine wave, f = 100kHz to 5MHz
f = 100kHz to 5MHz, inter-channel
25
-55
1.44
dB
mVRMS
LOGIC (ENABLEA, ENABLEB)
VIL
Logic Low Input Voltage
0.8
1
V
V
VIH
Logic High Input Voltage
Logic Input Current
2.0
-1
II
CHARGE PUMP
fCP
µA
Charge Pump Clock Frequency
9.5
MHz
NOTE:
2. Parameters with MIN and/or MAX limits are 100% tested at +27°C, unless otherwise specified. Temperature limits are established by
characterization and are not production tested.
FN6268.1
June 11, 2008
4
ISL59834
Pin Descriptions
NUMBER
NAME
GND
FUNCTION
1, 3, 9, 11
Ground
2
4
IN2
Video Input 2. Chroma Channel.
Charge Pump A Ground
GNDCPA
VCPA
5
Charge Pump A Power Supply. Bypass with a 0.1µF capacitor to GNDCPA.
Positive Power Supply. Bypass to GND with a 0.1µF capacitor.
6, 41
7
VS
ENABLEB
Channel 3 and Channel 4 Enable. Connect to VS to enable channels. ENABLEA must be tied to
ENABLEB.
8
IN3
IN4
NC
Video Input 3. Luma Channel.
Video Input 4. Chroma Channel.
No Connect.
10
12, 13, 16, 17, 18,
21, 35, 38, 40, 43
14
15
19
GNDCPB
VCPB
Charge Pump B Ground.
Charge Pump B Power Supply. Bypass with a 0.1µF capacitor to GNDCPB
.
CAPB-
Charge-Pump B Flying Capacitor Negative Terminal. Connect a 0.1µF capacitor from CAPB+ to
CAPB-.
20
CAPB+
Charge-Pump B Flying Capacitor Positive Terminal. Connect a 0.1µF capacitor from CAPB+ to CAPB-
.
22
23
VEEBOUT
VEEBIN
Charge Pump Negative Output. Bypass with a 0.22µF capacitor to GCP2.
Negative Supply for Channels 3 and 4. Connect an RC filter between VEEBIN and VEEBOUT. See
Typical Application Diagram. VEEAIN must be tied to VEEBIN.
24
25
26
OUT4
OUT3
Video Output 4
Video Output 3
SYNC_INB
Sync Input. Sync logic input for Channel 4.
Sync Output. Sync logic output from Channel 3.
27
28
SYNC_OUTB
CLKB
Channel 3 and Channel 4 Charge Pump Clock Output. Can also be driven by external clock. CLKA
must be tied to CLKB.
29
30
CAPA-
CAPA+
Charge-Pump A Flying Capacitor Negative Terminal. Connect a 0.1µF capacitor from CAPA+ to
CAPA-.
Charge-Pump A Flying Capacitor Positive Terminal. Connect a 0.1µF capacitor from CAPB+ to
CAPB-.
31
32
VEEAOUT
VEEAIN
Charge Pump Negative Output. Bypass with a 0.22µF capacitor to GNDCPA.
Negative Supply for Channels 1 and 2. Connect an RC filter between VEEAIN and VEEAOUT. See
Typical Application Diagram. VEEAIN must be tied to VEEBIN.
33
34
36
37
39
OUT2
OUT1
Video Output 2
Video Output 1
SYNC_INA
SYNC_OUTA
CLKA
Sync Input. Sync logic input for Channel 2.
Sync Output. Sync logic output from Channel 1.
Channel 1 and Channel 2 Charge Pump Clock Output. Can also be driven by external clock. CLKA
must be tied to CLKB.
42
ENABLEA
Channel 1 and Channel 2 enable. Connect to VS to enable channels. ENABLEA must be tied to
ENABLEB.
44
-
IN1
EP
Video Input 1. Luma Channel.
Exposed Pad. Connect to VEEAIN or VEEBIN
.
FN6268.1
June 11, 2008
5
ISL59834
Functional Diagram
VS
ENABLEA
ENABLEB
SYNC_OUTA
SYNC DETECTOR
LPF
LEVEL
SHIFT
X2
OUT1
IN1
(-310mV)
9MHz
VEEAIN
-
+
-593mV
LPF
LEVEL
SHIFT
X2
OUT2
IN2
(-165mV)
9MHz
VEEAIN
-
KEYED
+
0V
SYNC_INA
SYNC_OUTB
SYNC DETECTOR
LPF
LEVEL
SHIFT
X2
OUT3
IN3
(-310mV)
9MHz
VEEBIN
-
+
-593mV
LPF
LEVEL
SHIFT
OUT4
X2
IN4
(-165mV)
9MHz
VEEBIN
-
KEYED
+
0V
VEEAIN
VEEBIN
SYNC_INB
ISL59834
CHARGE
PUMP B
CHARGE
PUMP A
VCPB
CLKB
CAPB-
VEEBOUT
CAPB+
GNDCPB
CLKA
CAPA-
VCPA
VEEAOUT
GND
CAPA+
GNDCPA
FN6268.1
June 11, 2008
6
ISL59834
Component (YPbPr) Application Diagram
+3.3V
4.7µF
0.1µF
ENABLEA
IN1
ENABLEB VS
SYNC_OUTA
SYNC_INA
0.1µF
Y
CURRENT
DAC
SYNC_OUTB
SYNC_INB
150Ω
75Ω
75Ω
OUT1
0.1µF
PB
75Ω
75Ω
CURRENT
DAC
IN2
150Ω
OUT2
0.1µF
PR
CURRENT
DAC
IN4
IN3
75Ω
75Ω
OUT3
OUT4
150Ω
ISL59834
MPEG
DECODER
75Ω
75Ω
0.1µF
COMPOSITE
SOURCE
75Ω
CLKA
CLKB
VEEAIN
VEEBIN
RFIL1 10Ω
RFIL2
10Ω
VEEBOUT
VEEAOUT
0.22µF
CFIL2
0.47µF
0.47µF
+3.3V
0.22µF
CFIL1
CS1
CS2
+3.3V
VCPA
VCPB
0.1µF
1.0µF
CCP2B
1.0µF
CCP1A
0.1µF
CCP1B
GNDCPA
GND
GNDCPB
CCP2A
CAPA+ CAPA- CAPB+ CAPB-
CF1
CF2
0.1µF
0.1µF
s
FN6268.1
June 11, 2008
7
ISL59834
S-Video Application Diagram
+3.3V
4.7μF
0.1μF
ENABLEA
ENABLEB VS
SYNC_OUTA
SYNC_INA
0.1μF
IN1
SYNC_OUTB
SYNC_INB
Y1
75Ω
75Ω
75Ω
OUT1
0.1μF
75Ω
75Ω
C1
IN2
75Ω
75Ω
OUT2
0.1μF
0.1μF
IN3
IN4
Y2
C2
75Ω
75Ω
OUT3
OUT4
ISL59834
75Ω
75Ω
75Ω
CLKA
CLKB
VEEAIN
VEEBIN
RFIL1 10Ω
10Ω RFIL2
VEEBOUT
VEEAOUT
0.22μF
CFIL2
0.22μF
CFIL1
0.47μF
0.47μF
CS1
CS2
+3.3V
+3.3V
VCPA
VCPB
1.0μF
CCP1A
1.0μF
CCP2B
0.1μF
0.1μF
CCP1B
CCP2A
GNDCPA
GND
GNDCPB
CAPA+
CAPA- CAPB+ CAPB-
CF2
CF1
0.1μF
0.1μF
FN6268.1
June 11, 2008
8
ISL59834
Typical Performance Curves VCP = VS = 3.3V, CF1 = CF2 = 0.1µF, CS1 = CS2 = 0.22µF, CFIL1 = CFIL2 = 0.4µF, CIN1 = CIN2
=
C
IN3 = CIN4 = 0.1µF, RL1 = RL2 = 150Ω.
10
0
2
1
0
CHANNEL 2, 4
L = 75Ω
CHANNEL 1, 3
R
RL = 75Ω
-10
-20
-30
-40
-50
-60
-70
CHANNEL 2, 4
L = 75Ω
CHANNEL 2, 4
CHANNEL 1, 3
RL = 150Ω
R
RL = 150Ω
-1
-2
-3
-4
-5
CHANNEL 2, 4
RL = 150Ω
CHANNEL 1, 3
RL = 150Ω
CHANNEL 1, 3
RL = 75Ω
0.1
1M
10M
100M
0.1
1M
FREQUENCY (Hz)
FIGURE 2. GAIN FLATNESS vs FREQUENCY
10M
FREQUENCY (Hz)
FIGURE 1. BANDWIDTH vs FREQUENCY
50
40
30
20
10
0
-1.40
-1.41
-1.42
-1.43
-1.44
-1.45
-1.46
-1.47
-1.48
ALL MEASUREMENTS
CHANNEL 1, 3
LUMA
AT VEEIN
VS = 3.3V
CP = 2.7 TO 3.6V
V
CHANNEL 2, 4
CHROMA
-10
-20
-30
-40
VCP = VS 2.7V TO 3.6V
VCP = 3.3V
S = 2.7V TO 3.6V
V
0.1
1M
10M
100M
2.7
2.8
2.9
3.0 3.1
3.2
3.3
3.4
3.5
3.6
FREQUENCY (Hz)
SUPPLY VOLTAGE (V)
FIGURE 3. GROUP DELAY vs FREQUENCY
FIGURE 4. CHARGE PUMP VOLTAGE vs SUPPLY VOLTAGE
0
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
INPUT OF CHANNEL 1/2 TO OUTPUT OF CHANNEL 3/4
-10
ENABLE = LOW
ANY INPUT TO ANY OUTPUT
-20
-30
-40
-50
-60
-70
-80
-90
0.1
1M
FREQUENCY (Hz)
10M
100M
0.1
1M
FREQUENCY (Hz)
10M
100M
FIGURE 5. INPUT-TO-OUTPUT ISOLATION vs FREQUENCY
FIGURE 6. INTER-CHANNEL CROSSTALK
FN6268.1
June 11, 2008
9
ISL59834
Typical Performance Curves VCP = VS = 3.3V, CF1 = CF2 = 0.1µF, CS1 = CS2 = 0.22µF, CFIL1 = CFIL2 = 0.4µF, CIN1 = CIN2
=
C
IN3 = CIN4 = 0.1µF, RL1 = RL2 = 150Ω. (Continued)
70
0
-10
-20
-30
-40
-50
-60
-70
NO LOAD
INPUT OF CHANNEL 1, 3 TO OUTPUT OF
CHANNEL 2, 4 AND VICE-VERSA
68
INPUT FLOATING
66
64
62
60
58
56
54
52
50
0.1
1M
FREQUENCY (Hz)
10M
100M
3.0
3.1
3.2
3.3
3.4
3.5
3.6
SUPPLY VOLTAGE (V)
FIGURE 7. LUMA-TO-CHROMA CROSSTALK
FIGURE 8. SUPPLY CURRENT vs SUPPLY VOLTAGE
1500
1400
1300
1200
1100
1000
900
30
NO LOAD
INPUT FLOATING
25
20
15
10
5
800
700
600
0
500
0.1
1M
10M
FREQUENCY (Hz)
100M
3.0
3.1
3.2
3.3
3.4
3.5
3.6
SUPPLY VOTLAGE (V)
FIGURE 10. OUTPUT IMPEDANCE vs FREQUENCY
FIGURE 9. DISABLED SUPPLY CURRENT vs SUPPLY
VOLTAGE
0
0.05
WAVEFORM = MODULATED RAMP
0 IRE TO 100 IRE
0.03
0.01
-10
VAC = 100mVP-P
-20
-0.01
-0.03
-0.05
-0.07
-0.09
-0.11
-0.13
-0.15
VS = +3.3V + VAC
-30
-40
-50
-60
0.001
0.01
0.1
1M
10M
0
1
2
3
4
5
6
7
8
9
10 11
STEP
FIGURE 12. DIFFERENTIAL GAIN
FREQUENCY (Hz)
FIGURE 11. POWER SUPPLY REJECTION RATIO vs
FREQUENCY
FN6268.1
June 11, 2008
10
ISL59834
Typical Performance Curves VCP = VS = 3.3V, CF1 = CF2 = 0.1µF, CS1 = CS2 = 0.22µF, CFIL1 = CFIL2 = 0.4µF, CIN1 = CIN2
=
C
IN3 = CIN4 = 0.1µF, RL1 = RL2 = 150Ω. (Continued)
0.6
0.5
0.4
0.3
0.2
0.1
0
TIME SCALE = 10ns/DIV
DISABLE = 1V/DIV
OUTPUT = 1V/DIV
WAVEFORM = MODULATED RAMP
0 IRE to 100 IRE
DISABLE SIGNAL
OUTPUT SIGNAL
-0.1
-0.2
0
1
2
3
4
5
6
7
8
9
10 11
STEP
FIGURE 14. DISABLE TIME
FIGURE 13. DIFFERENTIAL PHASE
TIME SCALE = 5µs/DIV
ENABLE = 1V/DIV
OUTPUT = 1V/DIV
TIME SCALE = 500ns/DIV
IN = 200mV/DIV
OUT = 500mV/DIV
ENABLE SIGNAL
INPUT
ΔTIME = 35µs
OUTPUT
OUTPUT SIGNAL
FIGURE 15. ENABLE TIME
FIGURE 16. 12.5T RESPONSE (CHANNELS 1 and 3)
TIMEBASE = 100ns/DIV
IN = 200mV/DIV
OUT = 500mV/DIV
TIME SCALE = 10µs/DIV
IN = 500mV/DIV
OUT = 1V/DIV
INPUT
INPUT
OUTPUT
OUTPUT
FIGURE 18. NTSC COLORBAR (CHANNELS 1 and 3)
FIGURE 17. 2T RESPONSE (CHANNELS 1 and 3)
FN6268.1
June 11, 2008
11
ISL59834
Typical Performance Curves VCP = VS = 3.3V, CF1 = CF2 = 0.1µF, CS1 = CS2 = 0.22µF, CFIL1 = CFIL2 = 0.4µF, CIN1 = CIN2
=
C
IN3 = CIN4 = 0.1µF, RL1 = RL2 = 150Ω. (Continued)
TIME SCALE = 10µs/DIV
LUMA OUT = 500mV/DIV
CHROMA OUT = 500mV/DIV
LUMA OUTPUT
CHANNELS 1, 3
VIDEO SIGNAL (CHANNEL 1 or 3)
TIME SCALE = 5µs/DIV
OUT = 500mV/DIV
SYNC_OUT = 500mV/DIV
CHROMA OUTPUT
CHANNELS 2, 4
SYNC_OUT
FIGURE 19. S-VIDEO SCOPE SHOT
FIGURE 20. SYNC_OUT SIGNAL
INPUT = NTSC VIDEO + 2Hz SQUARE WAVE
(BEFORE COUPLING CAPACITOR)
INPUT = NTSC VIDEO + 2Hz SQUARE WAVE
(BEFORE COUPLING CAPACITOR)
TIMEBASE = 1ms/DIV
INPUT: 500mV/DIV
OUTPUT: 500mV/DIV
TIMEBASE = 200µs/DIV
INPUT: 500mV/DIV
OUTPUT: 500mV/DIV
CHANNEL 1 OR
CHANNEL 3 OUTPUT
CHANNEL 1 OR
CHANNEL 3 OUTPUT
FIGURE 21. LUMA CLAMP RESPONSE TO POSITIVE
TRANSIENT (CHANNEL 1 AND 3)
FIGURE 22. LUMA CLAMP RESPONSE TO NEGATIVE
TRANSIENT (CHANNEL 1 AND 3)
INPUT = NTSC S-VIDEO (CHROMA) + 2Hz SQUARE WAVE
(BEFORE COUPLING CAPACITOR)
INPUT = NTSC S-VIDEO (CHROMA) + 2Hz SQUARE WAVE
(BEFORE COUPLING CAPACITOR)
TIMEBASE = 2ms/DIV
INPUT: 500mV/DIV
OUTPUT: 500mV/DIV
TIMEBASE = 2ms/DIV
INPUT: 500mV/DIV
OUTPUT: 500mV/DIV
CHANNEL 2 OR CHANNEL 4 OUTPUT
CHANNEL 2 OR CHANNEL 4 OUTPUT
FIGURE 24. CHROMA CLAMP RESPONSE TO NEGATIVE
TRANSIENT (CHANNEL 2 AND 4)
FIGURE 23. CHROMA CLAMP RESPONSE TO POSITIVE
TRANSIENT (CHANNEL 2 AND 4)
FN6268.1
June 11, 2008
12
ISL59834
Typical Performance Curves VCP = VS = 3.3V, CF1 = CF2 = 0.1µF, CS1 = CS2 = 0.22µF, CFIL1 = CFIL2 = 0.4µF, CIN1 = CIN2
=
C
IN3 = CIN4 = 0.1µF, RL1 = RL2 = 150Ω. (Continued)
100
10
1
TIME SCALE = 50ns/DIV
VERTICAL SCALE = 20mV/DIV
RMS NOISE = 2.87mV
OUTPUT REFERRED
CHARGE PUMP NOISE,
CONTRIBUTES ONLY A SMALL
PERCENTAGE OF THE
OVERALL NOISE
0.1
0M 1M 2M 3M 4M 5M 6M 7M 8M 9M 10M
FREQUENCY (Hz)
FIGURE 26. CHARGE PUMP FEEDTHROUGH AT AMPLIFIER
OUTPUT
FIGURE 25. NOISE SPECTRUM
4.5
4.0
3.5
3.0
0
VS = VCP = +3.3V
-10
RL = 150Ω
VOUT = 0 TO 2VP, SINE WAVE
-20
-30
-40
-50
-60
-70
2.5
44 LD QFN PACKAGE
7mmx7mm
2.0
1.5
1.0
0.5
0
θJA = +32°C/W
fIN = 500kHz
fIN = 5MHz
0
5
10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90
AMBIENT TEMPERATURE (°C)
0.5
0.8
1.1
OUTPUT VOLTAGE (V)
FIGURE 27. THD (dBc) vs OUTPUT VOLTAGE (VP-P
1.4
1.7
2.0
FIGURE 28. PACKAGE POWER DISSIPATION
)
Description of Operation and Application Information
Output Amplifier
Theory of Operation
The ISL59834 output amplifiers provide a gain of +6dB. The
output amplifiers are able to drive a 2.8VP-P video signal into
a 150Ω or 75Ω load to ground.
The ISL59834 is a single supply video driver with a
reconstruction filter and an on-board charge pump. It is
designed to drive SDTV displays with component (YPbPr),
S-video (Y-C), or composite video (CV) signals. The input
signals can be AC or DC-coupled. When AC-coupled, a sync
tip clamp sets the blank level to ground at the output of
Channel 1 and Channel 3. Keyed clamps force the average
levels of Channel 2 and Channel 4 to ground. The keyed
clamps force the outputs to ground when SYNC_INA or
SYNC_INB are driven to the logic high state. The ISL59834
outputs are capable of driving two AC or DC-coupled
standard video loads and have a 4th order Butterworth
reconstruction filter with nominal -3dB frequency set to
9MHz, providing 40dB of attenuation at 27MHz. The
ISL59834 is designed to operate with a single supply voltage
range ranging from 3.0V to 3.6V. This eliminates the need for
a split supply with the incorporation of two charge pumps
capable of generating a bottom rail as much as 1.5V below
ground; providing a 4.8V range on a single 3.3V supply. This
performance is ideal for NTSC video with negative-going
sync pulses.
The outputs are highly-stable, low distortion, low power, high
frequency amplifiers capable of driving moderate (~10pF)
capacitive loads.
Input/Output Range
The ISL59834 has a dynamic input range of 0 to 1.4VP-P
This allows the device to handle high amplitude video signal
inputs. As the input signal moves outside the specified
range, the output signal will exhibit increasingly higher levels
of harmonic distortion.
Charge Pump
The ISL59834 contains two charge pumps; charge pump A
supplies Channel 1 and 2, while charge pump B supplies
Channel 3 and 4. The ISL59834 charge pumps provide a
bottom rail up to 1.5V below ground while operating on a
3.0V to 3.6V power supply. The charge pumps are internally
regulated and are driven by internal 9.5MHz clocks. The
FN6268.1
June 11, 2008
13
ISL59834
clock pins for both charge pumps (CLKA and CLKB) must be
AC-Coupled Inputs
shorted together.
SYNC TIP CLAMP (CHANNEL 1 AND 3)
To reduce the noise on the power supply generated by the
charge pump, connect a lowpass RC-network between
VEEOUT and VEEIN. See the “Typical Application Circuits”
for further information.
The ISL59834 features a sync tip clamp that forces the black
level of the output video signal to ground. This ensures that
the sync-tip voltage level will be approximately -300mV at
the back-termination resistor of a standard video load. The
clamp is activated whenever the input voltage falls below 0V.
The correction voltage required to do this is stored across
the input AC-coupling capacitor. Refer to Typical Application
Circuit for a detailed diagram.
VEE
Pins
OUT
VEEAOUT and VEEBOUT are the output pins for the charge
pumps. Keep in mind that these outputs are fully regulated
supplies that must be properly bypassed. Bypass these pins
with a 0.47µF ceramic capacitor placed as close to the pin
and connected to the ground plane of the board.
KEYED CLAMP (CHANNEL 2 AND 4)
Channel 2 and Channel 4 have a keyed clamp, which forces
the output to ground when SYNC_INA (Channel 2) or
SYNC_INB (Channel 4) are driven to the logic high state.
The SYNC_IN pins may be connected to either SYNC_OUT
pins or they may be driven by external sources.
VEE Pins
IN
VEEAIN and VEEBIN are the subtrate connections for the
ISL59834, these two pins must be shorted together. To
reduce the noise on the power supply generated by the
charge pump, connect a lowpass RC-network between
VEEOUT and VEEIN. See the “Typical Application Circuits”
for further information.
SYNC DETECTOR AND CLAMP TIMING
Channel 1 and Channel 3 also have sync detectors whose
outputs are available at SYNC_OUTA and SYNC_OUTB
pins respectively.
Video Performance
The slice level for the sync detectors is between 100mV to
200mV. This means that if the signal level is below 100mV at
Channel 1 or 3, then SYNC_OUTA or SYNC_OUTB are
high. If the signal level is above 200mV, then SYNC_OUTA
or SYNC_OUTB are low. Figure 29 shows the operation of
the sync detector.
DIFFERENTIAL GAIN/PHASE
For good video performance, an amplifier is required to
maintain the same output impedance and the same
frequency and phase response as DC levels are changed at
the output. Special circuitry has been incorporated into the
ISL59834 to reduce the output impedance variation with the
current output. This results in outstanding differential gain
and differential phase specifications of 0.45% and 0.15°,
while driving 150Ω at a gain of +2V/V.
NTSC LUMINANCE
CHANNEL 1 OR 3
INPUT
+1.00V
NTSC
The ISL59834, generating a negative rail internally, is ideally
suited for NTSC video with its accompanying negative-going
sync signals.
+300mV
100mV < VSLICE < 200mV
+0mV
S-VIDEO
SYNC_OUTA OR
SYNC_OUTB
+3.3V
For a typical S-video application with two S-video signals,
connect the luma signals to Channel 1 and 3, and connect
the chrominance signals to Channel 2 and 4. For clamp
timing, connect SYNC_OUTA to SYNC_INA and
SYNC_OUTB to SYNC_INB. See the “S-Video Typical
Application Circuit” on page 8.
+0mV
FIGURE 29. SYNC DETECTOR SLICE LEVEL
DC-Coupled Inputs (Channel 1 and 3)
YPbPr
When DC-coupling the inputs, ensure that the lowest signal
level is greater than +50mV to prevent the clamp from
turning on and distorting the output. When DC-coupled, the
ISL59834 shifts the signal by -620mV.
For a typical component video application, connect Y to
Channel 1, Pb to Channel 2 and Pr to Channel 4. Channel 3
can be optionally used a composite signal. For the clamp
timing, connect SYNC_OUTA to both SYNC_INA and
SYNC_INB and leave SYNC_OUTB floating. See the
“YPbPr Typical Application Circuit” on page 7.
Amplifier Disable
The ISL59834 can be disabled and its output placed in a
high impedance state. ENABLEA shuts off Channel 1 and 2
while ENABLEB shuts off Channel 3 and 4. Both ENABLE
pins must be shorted together. The turn-off time is around
10ns and the turn-on time is around 35µs. The turn-on time
FN6268.1
June 11, 2008
14
ISL59834
is longer because extra time is needed for the charge pump
Where:
VS = Supply voltage
to settle before the amplifiers are enabled. When disabled,
the device supply current is reduced to 5µA. Power-down is
controlled by standard TTL or CMOS signal levels at the
ENABLE pins. The applied logic signal is relative to the GND
pin. Applying a signal that is less than 0.8V above GND will
disable the device. The device will be enabled when the
ENABLE signals are 2V above GND.
ISMAX = Maximum quiescent supply current
VOUT = Maximum output voltage of the application
RLOAD = Load resistance tied to ground
ILOAD = Load current
Output Drive Capability
i = Number of output channels
The maximum output current for the ISL59834 is ±50mA.
Maximum reliability is maintained if the output current never
exceeds ±50mA, after which the electro-migration limit of the
process will be exceeded and the part will be damaged. This
limit is set by the design of the internal metal
By setting Equation 1 equal to Equation 2 and 3, we can
solve for the output current and RLOAD values needed to
avoid exceeding the maximum junction temperature.
Power Supply Bypassing and Printed Circuit
Board Layout
interconnections.
As with any high frequency device, a good printed circuit
board layout is necessary for optimum performance. Strip
line design techniques are recommended for the input and
output signal traces to help control the characteristic
impedance. Furthermore, the characteristic impedance of
the traces should be 75Ω. Trace lengths should be as short
as possible between the output pin and the series 75Ω
resistor. The power supply pin must be well bypassed to
reduce the risk of oscillation. For normal single supply
operation, a single 4.7µF tantalum capacitor in parallel with a
0.1µF ceramic capacitor from VS and VCP to GND will
suffice.
Driving Capacitive Loads and Cables
The ISL59834 (internally-compensated to drive 75Ω cables)
will drive 10pF loads in parallel with 150Ω or 75Ω with less
than 1.3dB of peaking.
Power Dissipation
With the high output drive capability of the ISL59834, it is
possible to exceed the +150°C absolute maximum junction
temperature under certain load current conditions.
Therefore, it is important to calculate the maximum junction
temperature for an application to determine if load conditions
or package types need to be modified to assure operation of
the amplifier in a safe operating area.
The AC performance of this circuit depends greatly on the
care taken in designing the PC board. The following are
recommendations to achieve optimum high frequency
performance from your PC board.
The maximum power dissipation allowed in a package is
determined according to Equation 1:
T
– T
AMAX
JMAX
(EQ. 1)
--------------------------------------------
PD
=
MAX
Θ
• Use low inductance components, such as chip resistors
and chip capacitors whenever possible.
JA
Where:
JMAX = Maximum junction temperature
AMAX = Maximum ambient temperature
JA = Thermal resistance of the package
• Minimize signal trace lengths. Trace inductance and
capacitance can easily limit circuit performance. Avoid
sharp corners; use rounded corners when possible. Vias
in the signal lines add inductance at high frequency and
should be avoided. PCB traces longer than 1" begin to
exhibit transmission line characteristics with signal rise/fall
times of 1ns or less. To maintain frequency performance
with longer traces, use striplines.
T
T
Θ
The maximum power dissipation actually produced by an IC
is the total quiescent supply current times the total power
supply voltage, plus the power in the IC due to the load, or:
• Match channel-to-channel analog I/O trace lengths and
layout symmetry. This will minimize propagation delay
mismatches.
for sourcing:
V
i
OUT
(EQ. 2)
(EQ. 3)
---------------------
i) ×
OUT
PD
= V × I
+ (V – V
• Route all signal I/O lines over continuous ground planes
(i.e. no split planes or PCB gaps under these lines).
MAX
S
SMAX
S
R
i
LOAD
• Place termination resistors in their optimum location as
close to the device as possible.
for sinking:
PD
= V × I
+ (V
i – V ) × I
i
MAX
S
SMAX
OUT
S
LOAD
FN6268.1
June 11, 2008
15
ISL59834
• Use good quality connectors and cables, matching cable
types and keeping cable lengths to a minimum when
testing.
• Place flying and output capacitors as close to the device
as possible for the charge pump.
Decouple well, using a minimum of 2 power supply
decoupling capacitors, placed as close to the device as
possible. Avoid vias between the capacitor and the device
because vias add unwanted inductance. Larger capacitors
may be farther away. When vias are required in a layout,
they should be routed as far away from the device as
possible.
FN6268.1
June 11, 2008
16
ISL59834
Quad Flat No-Lead Plastic Package (QFN)
L44.7x7A
B
A
44 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-220)
D
MILLIMETERS
SYMBOL
MIN
0.80
0.00
0.20
NOMINAL
0.85
MAX
0.90
0.05
0.30
NOTES
1
2
3
PIN #1
I.D. MARK
A
A1
b
-
E
0.02
-
0.25
-
c
0.203 REF
7.00 BASIC
5.10 REF
7.00 BASIC
5.10 REF
0.50 BASIC
0.55
-
(2X)
0.075 C
D
-
D2
E
8
-
TOP VIEW
E2
e
8
-
L
0.50
0.60
-
0.10 C
e
N
44 REF
11 REF
11 REF
4
C
ND
NE
6
SEATING
PLANE
5
Rev. 1 1/07
0.08 C
N LEADS AND
EXPOSED PAD
SEE DETAIL “X”
NOTES:
SIDE VIEW
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
2. Tiebar view shown is a non-functional feature.
3. Bottom-side pin #1 I.D. is a diepad chamfer as shown.
4. N is the total number of terminals on the device.
0.01 M C A B
b
PIN #1 I.D.
L
5. NE is the number of terminals on the “E” side of the package
(or Y-direction).
N LEADS
3
1
2
3
6. ND is the number of terminals on the “D” side of the package
(or X-direction). ND = (N/2)-NE.
(E2)
7. Inward end of terminal may be square or circular in shape with
radius (b/2) as shown.
8. If two values are listed, multiple exposed pad options are
available. Refer to device-specific datasheet.
5
NE
9. One of 10 packages in MDP0046
7
(D2)
BOTTOM VIEW
C
A
2
(c)
(L)
N LEADS
A1
DETAIL “X”
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6268.1
June 11, 2008
17
相关型号：
ISL59834IRZ
Quad Channel, Single Supply, Video Reconstruction Filter with On-Board Charge Pump
INTERSIL
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