TUA6020 [INFINEON]
2 Band TV Tuner Mixer-Oscillator-PLL with balanced IF-Amplifier; 2波段电视调谐器混频器，振荡器， PLL与平衡IF放大器
| 型号： | TUA6020 |
| 厂家： | 
Infineon |
| 描述： | 2 Band TV Tuner Mixer-Oscillator-PLL with balanced IF-Amplifier |
| 文件： | 总39页 (文件大小：712K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Wireless Components
2 Band TV Tuner Mixer-Oscillator-PLL with balanced IF-Amplifier
TUA6020 Version 1.2
Specification April 2000
preliminary
Revision History: Current Version: 04.00
Previous Version:Target Data Sheet
Page
Page
Subjects (major changes since last revision)
(in previous
Version)
(in current
Version)
5-8, 5-9
all
5-8, 5-9
all
oscillator phase noise data
status: target to preliminary
Input impedance of VHF mixer
Output impedance of IF output
5-27
5-29
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Edition 03.04.00
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TUA6020
preliminary
Product Info
Product Info
Package
General Description The TUA6020 is a 5 V mixer/oscillator
and synthesizer for analog and digital
TV and VCR tuners.
Features General
Suitable for analog and digital ter-
restrial TV tuner
Full ESD protection
Mixer/Oscillator
High impedance mixer input for
LOW/MID band
Low impedance mixer input for
HIGH band
2
4 pin oscillator for LOW/MID band
4 pin oscillator for HIGH band
IF-Amplifier
Fast I C bus
3 NPN bandswitch buffers
Internal LOW-MID/HIGH switch
Lock-in flag
balanced SAW preamplifier
Low output impedance
PLL
Power-down reset
Programmable reference divider
ratios: 24, 64, 80, 128
PLL with short lock-in time
High voltage VCO tuning output
Programmable charge pump cur-
rent
Application
The IC is suitable for PAL tuner in TV- and VCR-sets or set-top receivers for
analog TV and Digital Video Broadcasting.
Ordering Information
Type
Ordering Code
Package
TUA6020
Q67037-A1127-A701
(tape and reel)
P-TSSOP-28-1
Wireless Components
Product Info
Specification, April 2000
1
Table of Contents
1
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
2
Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.3 Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
2.4 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
3
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3.1 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
3.2 Internal Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
3.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
3.4 Circuit Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
4
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
4.1 Evaluation board, PAL application . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
4.2 Evaluation board, low phase noise application. . . . . . . . . . . . . . . . . . 4-3
5
Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
5.1 Electrical Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
5.1.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
5.1.2 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
5.1.3 AC/DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
5.2 Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
Table 5-4 Bit Allocation Read / Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
Table 5-5 Description of symbols. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
Table 5-6 Address selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
Table 5-7 Test modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
Table 5-8 Reference divider ratio. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
Table 5-9 IC frequency range selection. . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
5.3 I2C Bus Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12
5.4 Test Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13
5.4.1 Gain (GV) test Set-up in LOW/MID band . . . . . . . . . . . . . . . . . . . . . 5-13
5.4.2 Gain (GV) test Set-up in HIGH band . . . . . . . . . . . . . . . . . . . . . . . . 5-13
5.4.3 Matching circuit for optimum noise figure in LOW/MID band . . . . . . 5-14
5.4.4 Noise Figure Test Set-up in LOW/MID band . . . . . . . . . . . . . . . . . . 5-14
5.4.5 Noise Figure Test Set-up in HIGH band. . . . . . . . . . . . . . . . . . . . . . 5-15
TUA6020
preliminarytarget
Table of Contents
5.4.6 Cross modulation Test Set-up in LOW/MID band. . . . . . . . . . . . . . . 5-15
5.4.7 Cross modulation Test Set-up in HIGH band . . . . . . . . . . . . . . . . . . 5-16
5.4.8 Measurement of fref and fdiv . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16
5.5 Electrical Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17
5.5.1 Input admittance (S11) of the LOW/MID band mixer input. . . . . . . . 5-17
5.5.2 Input impedance (S11) of the HIGH band mixer input . . . . . . . . . . . 5-17
5.5.3 Output admittance (S22) of the Mixer output . . . . . . . . . . . . . . . . . . 5-18
5.5.4 Output impedance (S22) of the IF output . . . . . . . . . . . . . . . . . . . . . 5-18
Wireless Components
1 - 2
Specification, April 2000
2
Product Description
Contents of this Chapter
2.1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.3 Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
2.4 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
TUA6020
targetpreliminary
Product Description
2.1 General Description
The TUA6020 device combines a digitally programmable phase locked loop
(PLL), with a mixer-oscillator block including two balanced mixers and oscilla-
tors for use in TV and VCR tuners.
The PLL block with four selectable chip addresses forms a digitally programma-
ble phase locked loop. With a 4 MHz quartz crystal, the PLL permits precise set-
ting of the frequency of the tuner oscillator up to 1024 MHz in increments of
31.25, 50, 62.5 or 166.7 kHz. The tuning process is controlled by a micropro-
2
cessor via an I C bus. The device has three output ports. A flag is set when the
2
loop is locked. It can be read by the processor via the I C bus.
The mixer-oscillator block includes two balanced mixers (one mixer with high-
impedance input and one mixer with a balanced low-impedance input), two fre-
quency and amplitude-stable balanced oscillators for LOW/MID and HIGH, an
IF amplifier, a low-noise reference voltage source, and a band switch.
2.2 Features
General
Suitable for analog and digital terrestrial TV tuner
Full ESD protection
Mixer/Oscillator
High impedance mixer input for LOW/MID band
Low impedance mixer input for HIGH band
4 pin oscillator for LOW/MID band
4 pin oscillator for HIGH band
IF-Amplifier
balanced SAW preamplifier
Low output impedance
PLL
PLL with short lock-in time
High voltage VCO tuning output
2
Fast I C bus
3 NPN bandswitch buffers
Internal LOW-MID/HIGH switch
Lock-in flag
Power-down reset
Wireless Components
2 - 2
Specification, April 2000
TUA6020
targetpreliminary
Product Description
Programmable reference divider ratios: 24, 64, 80, 128
Programmable charge pump current
2.3 Application
The IC is suitable for PAL tuners in TV- and VCR-sets or set-top receivers
for analog TV and Digital Video Broadcasting.
2.4 Package Outlines
P-TSSOP-28-1
Wireless Components
2 - 3
Specification, April 2000
3
Functional Description
Contents of this Chapter
3.1 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
3.2 Internal Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
3.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
3.4 Circuit Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
3.4.1 Mixer-Oscillator block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
3.4.2 PLL block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
3.4.3 I2C-Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
TUA6020
preliminarytarget
Functional Description
3.1 Pin Configuration
HIGHIN
HIGHIN
LOW/MIDIN
VCC
1
2
3
4
5
6
7
8
9
28 OSCHIGHIN
27 OSCHIGHOUT
26 OSCHIGHOUT
25 OSCHIGHIN
24 OSCLOW/MIDIN
23 OSCLOW/MIDOUT
22 OSCLOW/MIDOUT
21 OSCLOW/MIDIN
20 RFGND
MIXOUT
MIXOUT
PLLGND
SDA
TUA6020
SCL
AS 10
XTAL 11
PHIGH 12
PLOW 13
PMID 14
19 VCC*)
18 IFOUT
17 IFOUT
16 VT
15 CP
*) for future purposes
Pin_config
Figure 3-1
Pin Configuration
Wireless Components
3 - 2
Specification, April 2000
TUA6020
preliminarytarget
Functional Description
3.2 Internal Pin Configuration
Table 3-1 Pin Definition and Function
Pin No. Symbol
Equivalent I/O-Schematic
Average DC voltage
LOW/MID
HIGH
1
HIGHIN
0.0 V
0.9 V
1
2
2
HIGHIN
0.0 V
1.8 V
0.9 V
0.0 V
3
LOW/MIDIN
3
4
5
VCC
supply voltage
5.0 V
3.8 V
5.0 V
3.8 V
MIXOUT
IF Amp.
5
6
6
7
MIXOUT
PLLGND
3.8 V
0.0 V
3.8 V
0.0 V
Oscillator
digital ground
Wireless Components
3 - 3
Specification, April 2000
TUA6020
preliminarytarget
Functional Description
Table 3-1 Pin Definition and Function (continued)
Pin No. Symbol Equivalent I/O-Schematic
Average DC voltage
LOW/MID
HIGH
8
SDA
n.a.
n.a.
8
9
SCL
n.a.
n.a.
9
10
AS
V
V
AS
AS
10
11
XTAL
3.0 V
3.0 V
11
Wireless Components
3 - 4
Specification, April 2000
TUA6020
preliminarytarget
Functional Description
Table 3-1 Pin Definition and Function (continued)
Pin No. Symbol Equivalent I/O-Schematic
Average DC voltage
LOW/MID
HIGH
12
13
PHIGH
PLOW
5 V
V
CE
12
13
14
5 V or V
5 V
CE
CE
14
15
PMID
CP
5 V or V
1.9 V
5 V
1.9 V
15
16
16
VT
V
V
T
T
17
18
IFOUT
IFOUT
2.3 V
2.3 V
2.3 V
2.3 V
17
18
19
20
VCC
supply voltage
analog ground
5.0 V
0.0 V
5.0 V
0.0 V
RFGND
Wireless Components
3 - 5
Specification, April 2000
TUA6020
preliminarytarget
Functional Description
Table 3-1 Pin Definition and Function (continued)
Pin No. Symbol Equivalent I/O-Schematic
Average DC voltage
LOW/MID
HIGH
21
22
23
24
OSCLOW/
MIDIN
1.6 V
0.0 V
OSCLOW/
MIDOUT
2.3 V
2.3 V
1.6 V
0.0 V
0.0 V
0.0 V
22
21
23
24
OSCLOW/
MIDOUT
OSCLOW/
MIDIN
25
26
27
28
OSCHIGHIN
0.0 V
0.0 V
0.0 V
0.0 V
1.6 V
2.8 V
2.8 V
1.6 V
OSCHIG-
HOUT
OSCHIG-
HOUT
26
25
27
28
OSCHIGHIN
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Specification, April 2000
TUA6020
preliminarytarget
Functional Description
3.3 Block Diagram
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Charge
Pump
Oscillator
HIGH
Oscillator
LOW/MID
SAW
Driver
HIGH
Phase/
Frequency
Comparator
LOW
or MID
CP, OS
fdiv
fref
Prog.
Divider
Reference
Divider
Mixer
HIGH
Mixer
LOW/MID
HIGH
Lock
Detector
LOW
or MID
Crystal
Oscillator
RF Input
HIGH
RF Input
LOW/MID
FL
HIGH
LOW
or MID
I2C Bus
PORTS
VCC
1
2
3
4
5
6
8
9
10
11
12
13
14
7
Block_diag
Figure 3-2
Block Diagram
Wireless Components
3 - 7
Specification, April 2000
TUA6020
preliminarytarget
Functional Description
3.4 Circuit Description
3.4.1 Mixer-Oscillator block
The mixer oscillator section includes two balanced mixers (double balanced
mixer), two balanced oscillators for LOW/MID and HIGH, an IF amplifier, a ref-
erence voltage source and a band switch.
Filters between tuner input and IC separate the TV frequency signals into two
bands. The band switching in the tuner front-end is done by using two or three
port outputs. In the selected band the signal passes a tuner input stage with
MOSFET amplifier, a double-tuned bandpass filter and is then fed to the bal-
anced mixer input of the IC which has in case of LOW / MID a high-impedance
input and in case of HIGH a low-impedance input. The input signal is mixed
there with the signal from the activated on chip oscillator to the IF frequency
which is filtered out at the balanced high-impedance output pair by means of a
parallel tuned circuit. The following SAW preamplifier has a low output imped-
ance to drive the SAW filter directly.
3.4.2 PLL block
The oscillator signal is internally DC-coupled as a differential signal to the pro-
grammable divider inputs. The signal subsequently passes through a program-
mable divider with ratio N = 256 through 32767 and is then compared in a digital
frequency / phase detector to a reference frequency f = 31.25, 50, 62.5 or
ref
166.7 kHz.This frequency is derived from an unbalanced, low-impedance 4
MHz crystal oscillator (pin XTAL) divided by R = 128, 80, 64 or 24.
The phase detector has two outputs that drive two current sources of opposite
polarity as charge pump. If the negative edge of the divided VCO signal appears
prior to the negative edge of the reference signal, the positive current source
pulses for the duration of the phase difference. In the reverse case the I- current
source pulses. If the two signals are in phase, the charge pump output (CP)
goes into the high-impedance state (PLL is locked). An active low-pass filter
integrates the current pulses to generate the tuning voltage for the VCO (inter-
nal amplifier, external pull-up resistor at TUNE and external RC circuitry). The
charge pump output is also switched into the high-impedance state if the control
bits T0 = 1 and T1 = 0. Here it should be noted, however, that the tuning voltage
can alter over a long period in the high-impedance state as a result of self-dis-
charge in the peripheral circuitry. TUNE may be switched off by the control bit
OS to allow external adjustments.
If the VCO is not oscillating the PLL locks to a tuning voltage of 33V (V ).
TH
By means of control bit CP the pump current can be switched between two val-
ues by software. This programmability permits alteration of the control response
time of the PLL in the locked-in state. In this way different VCO gains can be
compensated, for example.
Wireless Components
3 - 8
Specification, April 2000
TUA6020
preliminarytarget
Functional Description
The software-switched ports PLOW, PMID and PHIGH are general-purpose
open-collector outputs. The test bits T0 = 0 and T1 = 1, switch the test signals
fref (i.e.fXTAL / 64) and fdiv (divided input signal) to PMID and PLOW respec-
tively.
The lock detector resets the lock flag FL if the width of the charge pump current
pulses is wider than the period of the crystal oscillator (i.e. 250 ns). Hence, if FL
= 1, the maximum deviation of the input frequency from the programmed fre-
quency is given by
αf ==ꢀ I Γ (K
/ f
) Γ=(C1+C2) / (C1ΓC2)
P
VCO XTAL
where I is the charge pump current, K
the VCO gain, f
the crystal oscil-
P
VCO
XTAL
lator frequency and C1, C2 the capacitances in the loop filter (see Figure 4-1 Eval-
uation board, PAL application on page 2). As the charge pump pulses at i.e. 62.5
kHz (= f ), it takes a maximum of 16=←s for FL to be reset after the loop has lost
ref
lock state.
Once FL has been reset, it is set only if the charge pump pulse width is less than
250 ns for eight consecutive f periods. Therefore it takes between 128 and
ref
144=←s for FL to be set after the loop regains lock.
3.4.3 I2C-Bus Interface
2
Data is exchanged between the processor and the PLL via the I C bus. The
clock is generated by the processor (input SCL), while pin SDA functions as an
input or output depending on the direction of the data (open collector, external
pull-up resistor). Both inputs have hysteresis and a low-pass characteristic,
2
which enhance the noise immunity of the I C bus.
2
The data from the processor pass through an I C bus controller. Depending on
their function the data are subsequently stored in registers. If the bus is free,
both lines will be in the marking state (SDA, SCL are HIGH). Each telegram
begins with the start condition and ends with the stop condition. Start condition:
SDA goes LOW, while SCL remains HIGH. Stop condition: SDA goes HIGH
while SCL remains HIGH. All further information transfer takes place during
SCL = LOW, and the data is forwarded to the control logic on the positive clock
edge.
The table ”Bit Allocation” (see Table 5-4 Bit Allocation Read / Write on page 10)
should be referred to the following description. All telegrams are transmitted
byte-by-byte, followed by a ninth clock pulse, during which the control logic
returns the SDA line to LOW (acknowledge condition). The first byte is com-
prised of seven address bits. These are used by the processor to select the PLL
from several peripheral components (chip select). The LSB bit (R/W) deter-
mines whether data are written into (R/W = 0) or read from (R/W = 1) the PLL.
In the data portion of the telegram during a WRITE operation, the MSB bit of the
first or third data byte determines whether a divider ratio or control information
is to follow. In each case the second byte of the same data type has to follow
the first byte.
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Specification, April 2000
TUA6020
preliminarytarget
Functional Description
If the address byte indicates a READ operation, the PLL generates an acknowl-
edge and then shifts out the status byte onto the SDA line. If the processor gen-
erates an acknowledge, a further status byte is output; otherwise the data line
is released to allow the processor to generate a stop condition. The status word
consists the lock flag and the power-on flag.
Four different chip addresses can be set by appropriate DC level at pin AS (see
Table 5-6 Address selection on page 11).
While applying the supply voltage, a power-on reset circuit prevents the PLL
from setting the SDA line to LOW, which would block the bus. The power-on
reset flag POR is set at power-on and when V falls below 3.2 V. It will be reset
CC
at the end of a READ operation.
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Specification, April 2000
4
Applications
Contents of this Chapter
4.1 Evaluation board, PAL application . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
4.2 Evaluation board, low phase noise application. . . . . . . . . . . . . . . . . . 4-3
TUA6020
preliminarytarget
Applications
4.1 Evaluation board, PAL application
560
10n
+ 33 V
100n
2k7
2k7
BB659
IFOUT
RLoad = 75
Ω
1k8
15p
1k8
4n7
1k
100k
33k
BA892
1p
BB565
220
82p
100n
1k
3k3
C2
2n2
VCC
2:10**)
12p
L1
L2
L3
120p
2p2
22k
C1
47n
4n7
1p2
1p2
1p2
1p2
2p7
2p2
2p7
28
27
26
25
24
23
22
21
20
19
10
18
17
12
16
13
15
14
TUA6020
1
2
3
4
5
6
7
8
9
11
2p2
18p
1n
22p
22p
L4
220
220
47n
68p
68p
4 MHz
1:1*)
4n7
VCC
100p 100p
4n7
4n7
4n7
4n7
LOW/
MID
HIGH
RGen = 75
Ω
RGen = 75 Ω
SDA SCL
AS
PHIGH PLOW PMID
Application Circuit
Figure 4-1
Evaluation board, PAL application
Table 4-1 Recommended band limits in MHz
RF input Oscillator
Table 4-1 Coils
turns
1.5
⍪
wire ⍪
0.5 mm
0.5 mm
0.5 mm
0.3 mm
min
48.25
max
min
87.15
max
L1
L2
L3
L4
*)
2.4 mm
3 mm
LOW
MID
140.25
179.15
2.5
8.5
147.25 423.25 186.15 462.15
431.25 855.25 470.15 894.15
3.2 mm
4 mm
HIGH
14.5
TOKO B4F Type 617DB-1023
TOKO 7KL600 GCS-A1010DX
**)
Wireless Components
4 - 2
Specification, April 2000
TUA6020
preliminarytarget
Applications
4.2 Evaluation board, low phase noise application
560
47n
22n
+ 33 V
100n
2k7
82p
2k7
BB659
IFOUT
RLoad = 75
Ω
1k8
15p
1k8
4n7
1k
100k
33k
560
BA892
1p
BB565
220
100n
1k
3k3
C2
2n2
VCC
2:10**)
12p
L1
L2
L3
120p
2p2
12k
C1
100n
4n7
1p2
1p2
1p2
1p2
2p7
2p2
2p7
28
27
26
25
24
23
22
21
20
19
10
18
17
12
16
13
15
14
TUA6020
1
2
3
4
5
6
7
8
9
11
2p2
18p
1n
22p
22p
L4
220
220
47n
68p
68p
4 MHz
1:1*)
4n7
VCC
100p 100p
4n7
4n7
4n7
4n7
LOW/
MID
HIGH
RGen = 75
Ω
RGen = 75 Ω
SDA SCL
AS
PHIGH PLOW PMID
Application Circuit digital
Figure 4-2
Evaluation board, low phase noise application
Table 4-1 Recommended band limits in MHz
RF input Oscillator
Table 4-1 Coils
turns
1.5
⍪
wire ⍪
0.5 mm
0.5 mm
0.5 mm
0.3 mm
min
48.25
max
min
87.15
max
L1
L2
L3
L4
*)
2.4 mm
3 mm
LOW
MID
140.25
179.15
2.5
8.5
147.25 423.25 186.15 462.15
431.25 855.25 470.15 894.15
3.2 mm
4 mm
HIGH
14.5
TOKO B4F Type 617DB-1023
TOKO 7KL600 GCS-A1010DX
**)
Wireless Components
4 - 3
Specification, April 2000
5
Reference
Contents of this Chapter
5.1 Electrical Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
5.1.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
5.1.2 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
5.1.3 AC/DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
5.2 Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
Table 5-4 Bit Allocation Read / Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
Table 5-5 Description of symbols. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
Table 5-6 Address selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
Table 5-7 Test modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
Table 5-8 Reference divider ratio. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
Table 5-9 IC frequency range selection. . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
5.3 I2C Bus Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12
5.4 Test Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13
5.4.1 Gain (GV) test Set-up in LOW/MID band . . . . . . . . . . . . . . . . . . . . . 5-13
5.4.2 Gain (GV) test Set-up in HIGH band . . . . . . . . . . . . . . . . . . . . . . . . 5-13
5.4.3 Matching circuit for optimum noise figure in LOW/MID band . . . . . . 5-14
5.4.4 Noise Figure Test Set-up in LOW/MID band . . . . . . . . . . . . . . . . . . 5-14
5.4.5 Noise Figure Test Set-up in HIGH band. . . . . . . . . . . . . . . . . . . . . . 5-15
5.4.6 Cross modulation Test Set-up in LOW/MID band. . . . . . . . . . . . . . . 5-15
5.4.7 Cross modulation Test Set-up in HIGH band . . . . . . . . . . . . . . . . . . 5-16
5.4.8 Measurement of fref and fdiv . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16
5.5 Electrical Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17
5.5.1 Input admittance (S11) of the LOW/MID band mixer input. . . . . . . . 5-17
5.5.2 Input impedance (S11) of the HIGH band mixer input . . . . . . . . . . . 5-17
5.5.3 Output admittance (S22) of the Mixer output . . . . . . . . . . . . . . . . . . 5-18
5.5.4 Output impedance (S22) of the IF output . . . . . . . . . . . . . . . . . . . . . 5-18
TUA6020
preliminarytarget
Reference
5.1 Electrical Data
5.1.1 Absolute Maximum Ratings
WARNING
The maximum ratings may not be exceeded under any circumstances, not even
momentarily and individually, as permanent damage to the IC may result.
Table 5-1 Absolute Maximum Ratings, Ambient temperature T
= - 20°C ... + 85°C
AMB
Limit Values
1).
Symbol
Unit
Remarks
Parameter
min
-0.3
max
Supply voltage
V
6
V
CC
Junction temperature
Storage temperature
T
T
+150
+125
120
C
C
K/W
J
-40
Stg
Thermal resistance
(junction to ambient)
R
thJA
PLL
CP
V
-0.3
3
1
V
CP
I
mA
V
CP
Crystal oscillator pin XTAL
V
V
XTAL
XTAL
CC
I
-5
mA
V
Bus input/output SDA
V
-0.3
V
SDA
CC
Bus output current SDA
Bus input SCL
I
5
mA
V
open collector
SDA(L)
V
V
V
V
-0.3
-0.3
-0.3
-0.3
-1
V
SCL
AS
T
CC
CC
Chip address switch AS
Tuning voltage output (loop filter)
Port outputs PLOW, PMID, PHIGH
V
V
35
V
V
V
P
CC
I
25
mA
t
= 0.1 sec.
P(L)
max
at 5.5 V
t = 0.1 sec.
max
Total port output current
πI
40
mA
P(L)
at 5.5 V
Mixer-Oscillator
Mixer inputs LOW/MID
V
V
-0.3
-5
3
2
6
V
i
i
Mixer inputs HIGH
V
I
mA
i
Wireless Components
5 - 2
Specification, April 2000
TUA6020
preliminarytarget
Reference
Table 5-1 Absolute Maximum Ratings, Ambient temperature T
= - 20°C ... + 85°C (continued)
AMB
1)
Symbol
Limit Values
Unit
Remarks
Parameter
min
-0.3
max
Oscillator base voltage
V
V
3
V
V
B
C
Oscillator collector voltage
V
CC
2).
ESD-Protection
all pins
V
2
kV
ESD
1). All values are referred to ground (pin), unless stated otherwise.
Currents with a positive sign flow into the pin and currents with a negative sign flow out of pin.
2). According to MIL STD 883D, method 3015.7 and EOS/ESD assn. standardS5.1 - 1993
Wireless Components
5 - 3
Specification, April 2000
TUA6020
preliminarytarget
Reference
5.1.2 Operating Range
Within the operational range the IC operates as described in the circuit
description. The AC / DC characteristic limits are not guaranteed.
Table 5-2 Operating Range
Parameter
Symbol
Limit Values
Unit
Test Conditions
L
Item
min
max
+5.5
Supply voltage
V
+4.5
V
CC
Programmable divider factor
N
256
30
32767
500
LOW/MID Mixer input frequency
range
f
f
f
f
MHz
MHz
MHz
i
HIGH Mixer input frequency
range
400
65
900
560
i
LOW/MID Oscillator frequency
range
O
HIGH Oscillator frequency range
Ambient temperature
430
-20
950
+85
MHz
O
T
C
AMB
Wireless Components
5 - 4
Specification, April 2000
TUA6020
preliminarytarget
Reference
5.1.3 AC/DC Characteristics
AC / DC characteristics involve the spread of values guaranteed in the specified
supply voltage and ambient temperature range. Typical characteristics are the
median of the production.
Table 5-3 AC/DC Characteristics with T
= 25 °C, V
CC
AMB
Symbol
Limit Values
Unit
Test Conditions
L
Item
min
typ
max
Supply
Supply voltage
V
4.5
56
5
5.5
84
V
CC
Current consumption
I
70
mA
CC
Digital Unit
PLL
Crystal oscillator connections XTAL
Crystal frequency
Crystal resistance
Oscillation frequency
Input impedance
f
3.2
10
4.0
4.8
100
MHz
τ
series resonance
series resonance
XTAL
R
XTAL
XTAL
f
3,99975
-500
4,000
-700
4,00025
-900
MHz
τ
f
f
= 4 MHz
= 4 MHz
XTAL
XTAL
Z
XTAL
Charge pump output CP
HIGH output current
LOW output current
Tristate current
I
I
I
ꢀ90
ꢀ22
ꢀ220
ꢀ50
+1
ꢀ300
ꢀ75
µA
µA
nA
CP = 1, V = 2 V
CP
CPH
CPL
CPZ
CP = 0, V = 2 V
CP
T0 = 1, T1 = 0,
V
= 2 V
CP
Output voltage
V
1.0
2.5
V
PLL locked
CP
Drive output VT (open collector)
HIGH output current
I
10
µA
V
V
= 33 V, T0 = 1,
TH
TH
T1 = 0
LOW output voltage
V
0.4
I
TL
= 1.0 mA
TL
2
I C-Bus
Bus inputs SCL, SDA
HIGH input voltage
V
V
3
0
5.5
1.5
10
V
V
IH
IL
LOW input voltage
HIGH input current
LOW input current
I
I
µA
µA
V
V
= V
CC
IH
IL
IH
IL
-10
= 0 V
Bus output SDA (open collector)
HIGH output current
I
10
µA
V
= 5.5 V
OH
OH
Wireless Components
5 - 5
Specification, April 2000
TUA6020
preliminarytarget
Reference
Table 5-3 AC/DC Characteristics with T
= 25 °C, V
(continued)
CC
AMB
Symbol
Limit Values
Unit
Test Conditions
L
Item
min
typ
max
0.4
LOW output voltage
V
V
I
= 3 mA
OL
OL
Edge speed SCL,SDA
Rise time
t
t
300
300
ns
ns
r
f
Fall time
Clock timing SCL
Frequency
f
t
t
0
400
kHz
µs
SCL
H
HIGH pulse width
LOW pulse width
0.6
1.3
µs
L
Start condition
Set-up time
t
t
0.6
0.6
µs
µs
susta
hsta
Hold time
Stop condition
Set up time
t
t
0.6
1.3
µs
µs
susto
buf
Bus free
Data transfer
Set-up time
t
t
0.1
0
µs
µs
sudat
hdat
Hold time
Input hysteresis
SCL, SDA
V
200
mV
hys
Pulse width of spikes
which are suppressed
t
0
50
ns
sp
Capacitive load for
each bus line
C
400
pF
L
Port outputs PLOW, PMID, PHIGH (open collector)
HIGH output current
LOW output voltage
I
1
µA
V
V
= 5 V
POH
POH
V
0.5
I
= 25 mA
POL
POL
Address selection input AS
HIGH input current
LOW input current
I
I
50
µA
µA
V
V
= 5 V
= 0 V
ASH
ASL
ASH
ASL
-50
Wireless Components
5 - 6
Specification, April 2000
TUA6020
preliminarytarget
Reference
Table 5-3 AC/DC Characteristics with T
= 25 °C, V
(continued)
CC
AMB
Symbol
Limit Values
Unit
Test Conditions
L
Item
min
typ
max
Analog Unit
LOW/MID Band Section (including IF amplifier)
Voltage gain
G
20
23
9
26
11
dB
dB
f
= 43.25 to 463.25
RF
V
MHz, f = 33.4 to
IF
58.75 MHz
Mixer noise figure
NF
f
= 43.25 to 463.25
RF
MHz
Output voltage
causing 0.8% of
crossmodulation in
channel, see 5.4.6 on
page 15
V
V
118
117
dBµV
dBµV
f
= 48.25 MHz
= 399.25 MHz
i
i
RFw
f
RFw
Input IP2
IIP2
IIP2
IIP3
IIP3
137
137
119
119
dBµV
dBµV
dBµV
dBµV
f
f
= 48.25 MHz
= 98.50 MHz,
RF1
RF2
P
= P
RF2
RF1
f
f
= 415.25 MHz
= 832.50 MHz,
= P
RF1
RF2
P
RF1
RF2
Input IP3
f
= 48.25 MHz
= 49.25 MHz
RF1
f
RF2
P
= P
RF2
RF1
f
f
= 252.25 MHz
= 253.25 MHz,
= P
RF1
RF2
P
RF1
RF2
Output voltage caus-
ing 1 dB compression
V
V
121
121
1
dBµV
dBµV
kτ
f
= 48.25 MHz
o
o
RF
f
= 252.25 MHz
RF
Mixer input
impedance
R
0.5
1.5
3
parallel equivalent
circuit, f = 100 MHz
i
RF
C
2
pF
parallel equivalent
i
circuit, f = 100 MHz
RF
Oscillator frequency
shift, PLL unlocked
αf
αf
αf
400
500
100
kHz
kHz
V = 5 Vꢀ10%
Osc(V)
Osc(T)
Osc(t)
S
Oscillator frequency
drift, PLL unlocked
αT = 25=C
Oscillator frequency
drift, PLL unlocked
kHz
t = 5 s up to 15 min
after switching on
Oscillator pulling,
PLL unlocked
V
100
100
108
108
dBµV
αf = 10 kHz
i
f
= 48.25 MHz
RF
dBµV
αf = 10 kHz
= 399.25 MHz
V
i
f
RF
Wireless Components
5 - 7
Specification, April 2000
TUA6020
preliminarytarget
Reference
Table 5-3 AC/DC Characteristics with T
= 25 °C, V
(continued)
CC
AMB
Symbol
Limit Values
Unit
Test Conditions
L
Item
min
typ
max
N + 5 pulling,
PLL unlocked
N+5
N+5
-50
dBc
dBc
f
f
= 48.25 MHz,
RF
= 83.25 MHz,
RF1
P
=P
= 80dBµV
RF1
RF
-50
f
f
= 399.25 MHz,
RF
= 439.25 MHz,
RF1
P
=P
= 80dBµV
RF1
RF
Oscillator
χ
χ
a
-58
-88
15
-60
-90
20
dBc/Hz fm = 1kHz
dBc/Hz fm = 10kHz
OSC
OSC
1).
phase noise
IF suppression
dB
V = 80 dBµV
i
HIGH Band Section (including IF amplifier)
Voltage gain
G
31
34
37
dB
f
= 367.25 MHz to
RF
V
863.25 MHz,
= 33.4MHz to
f
IF
58.75 MHz
f = 367.25 to
RF
Mixer noise figure
NF
6
9
dB
dB
615.25 MHz
f = 623.25 to
RF
7
10
863.25 MHz
Output voltage
causing 0.8% of
crossmodulation in
channel, see 5.4.7 on
page 16
V
V
116
117
dBµV
dBµV
f
= 503.25 MHz
i
i
RFw
RFw
f
= 799.25 MHz
Input IP2
IIP2
IIP3
IIP3
139
108
108
dBµV
dBµV
dBµV
f
f
= 423.25 MHz
= 848.50 MHz,
RF1
RF2
P
= P
RF2
RF1
Input IP3
f
f
= 503.25 MHz
= 504.25 MHz
RF1
RF2
P
= P
RF2
RF1
f
f
= 799.25 MHz
= 800.25 MHz
RF1
RF2
P
= P
RF2
RF1
Output voltage caus-
ing 1 dB compression
V
V
121
121
20
dBµV
dBµV
τ
f
f
= 503.25 MHz
= 799.25 MHz
o
o
RF
RF
Mixer input
impedance
R
14
6
26
14
serial equivalent cir-
cuit, f = 600 MHz
i
RF
L
10
nH
serial equivalent cir-
i
cuit, f = 600 MHz
RF
Oscillator frequency
shift, PLL unlocked
αf
400
kHz
V = 5 Vꢀ10%
S
Osc(V)
Wireless Components
5 - 8
Specification, April 2000
TUA6020
preliminarytarget
Reference
Table 5-3 AC/DC Characteristics with T
= 25 °C, V
(continued)
CC
AMB
Symbol
Limit Values
Unit
Test Conditions
L
Item
min
typ
max
800
Oscillator frequency
drift, PLL unlocked
αf
αf
kHz
kHz
αT = 25=C
Osc(T)
Osc(t)
Oscillator frequency
drift, PLL unlocked
100
t = 5 s up to 15 min
after switching on
Oscillator pulling,
PLL unlocked
V
100
100
-50
108
108
dBµV
αf = 10 kHz
i
f
= 375.25 MHz
RF
dBµV
dBc
αf = 10 kHz
V
i
f
= 847.25 MHz
RF
N + 5 pulling,
PLL unlocked
V
f
f
= 471.25 MHz,
i
RF
= 511.25 MHz,
RF1
P
=P
= 80dBµV
RF1
RF
V
-50
dBc
f
f
= 847.25 MHz,
RF
i
= 887.25 MHz,
RF1
P
=P
= 80 dBµV
RF1
RF
Oscillator
χ
χ
a
-58
-88
15
-60
-90
20
dBc/Hz fm = 1kHz
dBc/Hz fm = 10kHz
OSC
OSC
1)
phase noise
IF suppression
dB
V = 80 dBµV
i
SAW preamplifier
IF output impedance,
double ended
R
125
10
τ
serial equivalent
circuit,
IF
L
nH
IF
f
= 38.9 MHz
IF
IF output impedance,
single ended
R
75
5
τ
serial equivalent
circuit,
IF
L
nH
IF
f
= 38.9 MHz
IF
Rejection at the IF outputs
Divider interference
Vo
30
dBµV
dBc
2).
level
Channel S02 beat
INT
66
f
= 76.25 MHz
= 80 dBµV
RF
S02
3).
P
rejection
RF
This value is only guaranteed in lab.
1). Measured in the evaluation board (see Chapter 4), worst case in band
2). This is the level of divider interferences close to the IF frequency. For example channel S3:
fOSC = 158.15 MHz, 1/4 fOSC = 39.5375 MHz. Measured in the evaluation
board (see Chapter 4).
3). Channel S02 beat is the interfering product of f , f and f
of channel S02, f
= 37.35 MHz.
RF IF
OSC
beat
The possible mechanisms are f
- 2 x f or 2 x f
- f
. Measured in evaluation board
OSC
IF
RFpix OSC
(see Chapter 4).
Wireless Components
5 - 9
Specification, April 2000
TUA6020
preliminarytarget
Reference
5.2 Programming
Table 5-4 Bit Allocation Read / Write
Byte
MSB
bit6
bit5
bit4
bit3
bit2
bit1
LSB
Ack
Write Data
Address Byte
Progr. Divider Byte 1
Progr. Divider Byte 2
Control Byte
1
0
1
N14
N6
CP
x
0
N13
N5
T1
x
0
N12
N4
T0
x
0
N11
N3
FP
x
MA1
N10
N2
MA0
N9
0
A
A
A
A
A
N8
N0
OS
N7
1
N1
RSA
RSB
Bandswitch Byte
x
PHIGH PLOW
PMID
1).
1).2).
1). 2).
Read Data
Address Byte
Status Byte
1
1
0
x
0
x
0
x
MA1
x
MA0
x
1
x
A
A
POR
FL
1). see Table 5-9 IC frequency range selection on page 11
2). In a tuner PLOW and PMID are interchangeable. Both bits switch the IC into LOW/MID (VHF) mode.
Table 5-5 Description of symbols
Symbol
Description
Address selection bits (see Table 5-6 Address selection on page 11)
programmable divider bits:
MA0, MA1
N14 to N0
14
13
3
2
1
N = 2 x N14 + 2 x N13 + ..... + 2 x N3 + 2 x N2 + 2 x N1 + N0
CP
Charge pump current:
bit = 0: charge pump current = 50 µA
bit = 1: charge pump current = 220µA
T1, T0
FP
test bits (see Table 5-7 Test modes on page 11)
reserved for future purposes, actually ignored, default: 1
reference divider bits (see Table 5-8 Reference divider ratio on page 11)
RSA, RSB
OS
Tuning amplifier control bit: bit = 0: enable V
T
bit = 1: disable V
T
PLOW, PMID, PHIGH
NPN ports control bits:
bit = 0: NPN open-collector output is inactive
bit = 1: NPN open-collector output is active
(see Table 5-9 IC frequency range selection on page 11)
FL
PLL lock flag, bit = 1: loop is locked
POR
Power-on reset flag
flag is set at power-on and reset at the end of READ operation
x
don‘t care
Wireless Components
5 - 10
Specification, April 2000
TUA6020
preliminarytarget
Reference
Table 5-6 Address selection
Voltage at AS
MA1
MA0
(0...0.1) * V
open circuit
0
0
CC
0
1
1
0
(0.4...0.6) * V
CC
(0.9...1) * V
1
1
CC
Table 5-7 Test modes
Test mode
T1
0
T0
0
Normal operation
Charge pump output, CP is in high-impedance state
0
1
PLOW = f output, PMID = f output
1
0
div
ref
not used
1
1
Table 5-8 Reference divider ratio
Reference divider ratio
1).
ref
RSA
RSB
f
80
50 kHz
31.25 kHz
166.7 kHz
62.5 kHz
0
0
1
1
0
1
0
1
128
24
64
1). With a 4 MHz quartz.
Table 5-9 IC frequency range selection
Frequency range
1).
1.)
Bit 2 (PHIGH)
Bit 1 (PLOW)
Bit 0 (PMID)
LOW/MID (VHF)
LOW/MID (VHF)
HIGH (UHF)
0
0
1
1
0
0
0
1
0
1). In a tuner PLOW and PMID are interchangeable. Both bits switch the IC into LOW/MID (VHF) mode.
Wireless Components
5 - 11
Specification, April 2000
Addressing
Ack. 1st Byte Ack. 2nd Byte Ack. 3rd Byte Ack. 4th Byte
Ack.
MA MA R/W
SCL:
Note: SDA:
Telegram examples:
Abbreviations:
Start-ADB-DB1-DB2-CB-BB-Stop
Start-ADB-CB-BB-DB1-DB2-Stop
Start-ADB-DB1-DB2-Stop
Start= start condition
ADB= address byte
DB1= prog. divider byte 1
DB2= prog. divider byte 2
CB= Control byte
Start-ADB-CB-BB-Stop
BB= Bandswitch byte
Stop= stop condition
TUA6020
preliminarytarget
Reference
5.4 Test Circuits
5.4.1 Gain (GV) test Set-up in LOW/MID band
LOW/
MIDIN
IFOUT
Transformer
50
Ω
Device
under
Test
N1
N2
Vmeas
RMS
50
Ω
V0
50
Ω
V
Vi
C
spectrum
analyser
V'meas
Votmeter
IFOUT
N1 : N2 = 10 : 2 turns
GVHF2
Z >> 50 τ => V = 2 x V = 80 dBµV
meas
i
i
V = V
+ 6dB = 80 dBµV
i
meas
V = V’
+ 16 dB (transformer ratio N1:N2 and transformer loss)
0
meas
G = 20 log(V / V )
v
0
i
5.4.2 Gain (GV) test Set-up in HIGH band
HIGHIN IFOUT
Transformer
N1 N2
50
Ω
Device
under
Test
Vmeas
Balun
1:1
Vi
V0
50
spectrum
analyser
Ω
V
50
Ω
C
RMS
Votmeter
V'meas
HIGHIN
IFOUT
N1 : N2 = 10 : 2 turns
GUHF2
V = V
= 70 dBµV
i
meas
V = V’
+ 16 dB (transformer ratio N1:N2 and transformer loss)
0
meas
G = 20 log(V / V ) + 1 dB (1 dB = insertion loss of balun)
v
0
i
Wireless Components
5 - 13
Specification, April 2000
TUA6020
preliminarytarget
Reference
5.4.3 Matching circuit for optimum noise figure in LOW/MID band
15p
1n
22p
1n
In
Out
In
Out
7 turns
22p
wire
coil
⍪
0.5 mm
⍪
5.5 mm
50
τ
semi rigid cable
300 mm long
96 pF/m
33dB/100m
22p
Nfm
For f = 150 MHz
For f = 50 MHz
RF
RF
loss = 1.3 dB
loss = 0 dB
image suppression = 13 dB
image suppression = 16 dB
5.4.4 Noise Figure Test Set-up in LOW/MID band
LOW/
MIDIN
Noise
Source
IFOUT
IN OUT
Noise
Figure
Meter
Transformer
N1 N2
Matching
Circuit
Device
under
Test
C
IFOUT
N1 : N2 = 10 : 2 turns
NF = NFmeas - loss of matching circuit (dB)
NFVHF2
Wireless Components
5 - 14
Specification, April 2000
TUA6020
preliminarytarget
Reference
5.4.5 Noise Figure Test Set-up in HIGH band
Noise
Source
HIGHIN IFOUT
Transformer
Noise
Figure
Meter
Device
under
Test
N1
N2
Balun
1:1
C
HIGHIN
IFOUT
N1 : N2 = 10 : 2 turns
loss of balun = 1 dB
NF = NFmeas - loss of balun (dB)
NFUHF2
5.4.6 Cross modulation Test Set-up in LOW/MID band
Vmeas
50
Ω
V
RMS
Votmeter
unwanted
signal
source
AM = 80 %
18 dB
attenuator
LOW/
MIDIN
A
IFOUT
C
Transformer
N1 N2
50
Ω
Device
under
Test
38.9 MHz
50
Hybrid
V0
Vi
Ω
C
V
modulation
analyser
50
Ω
V'meas
B
D
IFOUT
N1 : N2 = 10 : 2 turns
RMS
Votmeter
wanted
signal
source
50
Ω
XVHF2
Zi >> 50 τ => Vi = 2 x Vmeas
V’meas = V0 - 16 dB (transformer ratio N1:N2 and transformer loss)
wanted output signal at fpix, Vo = 100 dBµV
unwanted output signal at fsnd, 80 % AM modulated with 1 kHz
Wireless Components
5 - 15
Specification, April 2000
TUA6020
preliminarytarget
Reference
5.4.7 Cross modulation Test Set-up in HIGH band
Vmeas
50
Ω
V
RMS
Votmeter
unwanted
signal
source
AM = 80 %
18 dB
attenuator
A
C
HIGHIN IFOUT
Transformer
N1 N2
50
Ω
Device
under
Test
Balun
1:1
38.9 MHz
50
Hybrid
Vi
V0
Ω
C
V
modulation
analyser
50
Ω
V'meas
B
D
HIGHIN IFOUT
N1 : N2 = 10 : 2 turns
RMS
Votmeter
wanted
signal
source
50
Ω
XUHF2
V’meas = V0 - 16 dB (transformer ratio N1:N2 and transformer loss)
wanted output signal at fpix, Vo = 100 dBµV
unwanted output signal at fsnd, 80 % AM modulated with 1 kHz
5.4.8 Measurement of fref and fdiv
VVCC
+ 5 V
Test Mode: T1 = 1, T0 = 0
5k
5k
fQ = fref * R
R: reference divider ratio
Counter
Counter
PMID
fref
18p
4 MHz
PLOW
fVCO = fdiv * N
N: divider ratio
fdiv
MEAS_COF
Wireless Components
5 - 16
Specification, April 2000
TUA6020
preliminarytarget
Reference
5.5 Electrical Diagrams
5.5.1 Input admittance (S11) of the LOW/MID band mixer input
Y = 20mS (single ended)
0
0
48.25 MHz
407.25 MHz
5.5.2 Input impedance (S11) of the HIGH band mixer input
Z = 50 τ (balanced)
0
855.25 MHz
415.25 MHz
Rdiff
0
Wireless Components
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Specification, April 2000
TUA6020
preliminarytarget
Reference
5.5.3 Output admittance (S22) of the Mixer output
Y = 20mS (balanced)
0
0
Rdiff
38.9 MHz
5.5.4 Output impedance (S22) of the IF output
Z = 50 τ (single/ double ended)
0
0
Rse
Rdiff
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Specification, April 2000
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