TUA6024-K [INFINEON]

Video Tuner, 2-Band, PDSO28, 1 MM HEIGHT, PLASTIC, TSSOP-28;
TUA6024-K
型号: TUA6024-K
厂家: Infineon    Infineon
描述:

Video Tuner, 2-Band, PDSO28, 1 MM HEIGHT, PLASTIC, TSSOP-28

放大器 射频 光电二极管 商用集成电路
文件: 总34页 (文件大小:420K)
中文:  中文翻译
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Wireless Components  
2 Band TV Tuner Mixer-Oscillator-PLL with balanced IF-Amplifier  
TUA6024 Version 2.0  
Specification December 1999  
Revision History: Current Version: 12.99  
Previous Version:Target Data Sheet  
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Version)  
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Edition 03.99  
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TUA6024  
Product Info  
Product Info  
Package  
General Description The TUA6024 is a 5 V mixer/oscillator  
and sythesizer for analog and digital  
TV and VCR tuners.  
Features General  
Suitable for analog and digital ter-  
restrial TV tuner  
Full ESD protection  
Mixer/Oscillator  
High impedance mixer input for  
LOW/MID band  
Low impedance mixer input for  
HIGH band  
4 pin oscillator for LOW/MID band Fast I2C bus  
4 pin oscillator for HIGH band  
IF-Amplifier  
3 NPN bandswitch buffers  
Internal LOW-MID/HIGH switch  
balanced SAW preamplifier  
Low output impedance  
PLL  
Lock-in flag  
Power-down reset  
Programmable reference divider  
ratios: 64, 80, 128  
PLL with short lock-in time  
High voltage VCO tuning output  
Programmable charge pump cur-  
rent  
Application  
The IC is suitable for PAL tuner in  
TV- and VCR-sets or set-top  
receivers for analog TV and Digital  
Video Broadcasting.  
Ordering Information  
Type  
Ordering Code  
Q67037-A1057  
Q67037-A1056  
Package  
TUA6024-K  
TUA6024-S  
P-TSSOP-28-1  
P-TSSOP-28-1  
Wireless Components  
Product Info  
Specification, December 1999  
1
Table of Contents  
1
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1  
2
Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1  
2.1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2  
2.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2  
2.3 Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3  
2.4 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3  
3
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1  
3.1 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2  
3.2 Internal Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3  
3.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7  
3.4 Circuit Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8  
4
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1  
4.1 Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2  
5
Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1  
5.1 Electrical Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2  
5.1.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2  
5.1.2 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4  
5.1.3 AC/DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5  
5.2 Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10  
Table 5-4 Bit Allocation Read / Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10  
Table 5-5 Description of symbols. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10  
Table 5-6 Address selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11  
Table 5-7 Test modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11  
Table 5-8 Reference divider ratio. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11  
5.3 I2C Bus Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12  
5.4 Test Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13  
5.4.1 Gain (GV) test Set-up in LOW/MID. . . . . . . . . . . . . . . . . . . . . . . . . . 5-13  
5.4.2 Gain (GV) test Set-up in HIGH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13  
5.4.3 Matching circuit for optimum noise figure in LOW/MID. . . . . . . . . . . 5-14  
5.4.4 Noise Figure Test Set-up in LOW/MID . . . . . . . . . . . . . . . . . . . . . . . 5-14  
5.4.5 Noise Figure Test Set-up in HIGH . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15  
5.4.6 Measurement of fref and fdiv . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15  
Wireless Components  
1 - 1  
Specification, December 1999  
 
2
Product Description  
Contents of this Chapter  
2.1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2  
2.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2  
2.3 Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3  
2.4 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3  
Wireless Components  
2 - 1  
Specification, December 1999  
TUA6024  
Product Description  
2.1 General Description  
The TUA6024 device combines a digitally programmable phase locked loop  
(PLL), with a mixer-oscillator block including two balanced mixers and oscilla-  
tors for use in TV and VCR tuners.  
The PLL block with four selectable chip addresses forms a digitally programma-  
ble phase locked loop. With a 4 MHz quartz crystal, the PLL permits precise set-  
ting of the frequency of the tuner oscillator up to 900 MHz in increments of  
31.25, 50 or 62.5 kHz. The tuning process is controlled by a microprocessor via  
an I2C bus. The device has three output ports. A flag is set when the loop is  
locked it can be read by the processor via the I2C bus.  
The mixer-oscillator block includes two balanced mixers (one mixer with high-  
impedance input and one mixer with a balanced low-impedance input), two fre-  
quency and amplitude-stable balanced oscillators for LOW/MID and HIGH, an  
IF amplifier, a low-noise reference voltage source, and a band switch.  
2.2 Features  
General  
Suitable for analog and digital terrestrial TV tuner  
Full ESD protection  
Mixer/Oscillator  
High impedance mixer input for LOW/MID band  
Low impedance mixer input for HIGH band  
4 pin oscillator for LOW/MID band  
4 pin oscillator for HIGH band  
IF-Amplifier  
balanced SAW preamplifier  
Low output impedance  
PLL  
PLL with short lock-in time  
High voltage VCO tuning output  
Fast I2C bus  
3 NPN bandswitch buffers  
Internal LOW-MID/HIGH switch  
Lock-in flag  
Power-down reset  
Wireless Components  
2 - 2  
Specification, December 1999  
TUA6024  
Product Description  
Programmable reference divider ratios: 64, 80, 128  
Programmable charge pump current  
2.3 Application  
The IC is suitable for PAL tuners in TV- and VCR-sets or set-top receivers  
for analog TV and Digital Video Broadcasting.  
2.4 Package Outlines  
P-TSSOP-28-1  
Wireless Components  
2 - 3  
Specification, December 1999  
3
Functional Description  
Contents of this Chapter  
3.1 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2  
3.2 Internal Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3  
3.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7  
3.4 Circuit Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8  
3.4.1 Mixer-Oscillator block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8  
3.4.2 PLL block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8  
3.4.3 I2C-Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9  
Wireless Components  
3 - 1  
Specification, December 1999  
TUA6024  
Functional Description  
3.1 Pin Configuration  
OSCHIGHIN  
OSCHIGHOUT  
OSCHIGHOUT  
OSCHIGHIN  
1
2
3
4
5
6
7
8
9
28 HIGHIN  
27 HIGHIN  
26 LOW/MIDIN  
25  
VCC  
OSCLOW/MIDIN  
OSCLOW/MIDOUT  
24 MIXOUT  
23 MIXOUT  
22  
OSCLOW/MIDOUT  
OSCLOW/MIDIN  
RFGND  
PLLGND  
TUA6024  
21  
SDA  
20 SCL  
ADC 10  
IFOUT 11  
IFOUT 12  
VT 13  
19 AS  
18 XTAL  
17 PHIGH  
16 PMID  
15 PLOW  
CP 14  
Pin_config  
Figure 3-1  
Pin Configuration  
Wireless Components  
3 - 2  
Specification, December 1999  
TUA6024  
Functional Description  
3.2 Internal Pin Configuration  
Table 3-1 Pin Definition and Function  
Pin No. Symbol  
Equivalent I/O-Schematic  
Average DC voltage  
LOW/MID  
HIGH  
1
2
3
4
OSCHIGHIN  
0.0 V  
1.6 V  
OSC-  
HIGHOUT  
0.0 V  
0.0 V  
0.0 V  
2.3 V  
2.3 V  
1.6 V  
OSC-  
HIGHOUT  
2
1
3
4
OSCHIGHIN  
5
6
7
8
OSCLOW/  
MIDIN  
1.6 V  
2.8 V  
2.8 V  
1.6 V  
0.0 V  
0.0 V  
0.0 V  
0.0 V  
OSCLOW/  
MIDOUT  
6
5
7
8
OSCLOW/  
MIDOUT  
OSCLOW/  
MIDIN  
Wireless Components  
3 - 3  
Specification, December 1999  
TUA6024  
Functional Description  
Table 3-1 Pin Definition and Function (continued)  
Pin No. Symbol Equivalent I/O-Schematic  
Average DC voltage  
LOW/MID  
HIGH  
9
RFGND  
ADC  
analog ground  
0.0 V  
0.0 V  
10  
V
V
ADC  
ADC  
10  
11  
IFOUT  
2.3 V  
2.3 V  
11  
12  
12  
13  
IFOUT  
2.3 V  
2.3 V  
VT  
VT  
VT  
14  
13  
14  
CP  
1.9 V  
1.9 V  
Wireless Components  
3 - 4  
Specification, December 1999  
TUA6024  
Functional Description  
Table 3-1 Pin Definition and Function (continued)  
Pin No. Symbol Equivalent I/O-Schematic  
Average DC voltage  
LOW/MID  
HIGH  
15  
16  
PMID  
5 V or VCE  
5 V  
15  
16  
17  
PLOW  
5 V or VCE  
5 V  
17  
18  
PHIGH  
XTAL  
5 V  
VCE  
3.0 V  
3.0 V  
18  
19  
AS  
VAS  
VAS  
19  
20  
SCL  
n.a.  
n.a.  
20  
Wireless Components  
3 - 5  
Specification, December 1999  
TUA6024  
Functional Description  
Table 3-1 Pin Definition and Function (continued)  
Pin No. Symbol Equivalent I/O-Schematic  
Average DC voltage  
LOW/MID  
HIGH  
21  
SDA  
n.a.  
n.a.  
21  
22  
23  
PLLGND  
MIXOUT  
digital ground  
0.0 V  
3.8 V  
0.0 V  
3.8 V  
IF Amp.  
23  
24  
24  
MIXOUT  
3.8 V  
3.8 V  
Oscillator  
25  
26  
VCC  
supply voltage  
5.0 V  
1.8 V  
5.0 V  
0.0 V  
LOW/MIDIN  
26  
27  
28  
HIGHIN  
HIGHIN  
0.0 V  
0.0 V  
0.9 V  
0.9 V  
27  
28  
Wireless Components  
3 - 6  
Specification, December 1999  
TUA6024  
Functional Description  
3.3 Block Diagram  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
VCC  
I2C Bus  
PORTS  
LOW  
or MID  
RF Input  
HIGH  
RF Input  
LOW/MID  
HIGH  
FL  
Crystal  
Oscillator  
LOW  
or MID  
Lock  
Detector  
Mixer  
HIGH  
Mixer  
LOW/MID  
HIGH  
Reference  
Divider  
Prog.  
Divider  
fref  
fdiv  
LOW  
or MID  
Phase/  
Frequency  
Comparator  
Oscillator  
HIGH  
Oscillator  
LOW/MID  
SAW  
Driver  
HIGH  
Charge  
Pump  
ADC  
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
Block_diag  
Figure 3-2  
Block Diagram  
Wireless Components  
3 - 7  
Specification, December 1999  
TUA6024  
Functional Description  
3.4 Circuit Description  
3.4.1 Mixer-Oscillator block  
The mixer oscillator section includes two balanced mixers (double balanced  
mixer), two balanced oscillators for LOW and / or MID band and HIGH, a refer-  
ence voltage source and a band switch.  
Filters between tuner input and IC separate the TV frequency signals into two  
bands. The band switching in the tuner front-end is done by using two or three  
port outputs. In the selected band the signal passes a tuner input stage with  
MOSFET amplifier, a double-tuned bandpass filter and is then fed to the bal-  
anced mixer input of the IC which has in case of LOW / MID a high-impedance  
input and in case of HIGH a low-impedance input. The input signal is mixed  
there with the signal from the activated on chip oscillator to the IF frequency  
which is filtered out at the balanced high-impedance output pair by means of a  
parallel tuned circuit. The following SAW preamplifier has a low output imped-  
ance to drive the SAW filter directly.  
3.4.2 PLL block  
The oscillator signal is internally DC-coupled as a differential signal to the pro-  
grammable divider inputs. The signal subsequently passes through a program-  
mable divider with ratio N = 256 through 32767 and is then compared in a digital  
frequency / phase detector to a reference frequency fref = 31.25, 50 or 62.5 kHz.  
This frequency is derived from a unbalanced, low-impedance 4 MHz crystal  
oscillator (pin XTAL) divided by R = 128, 80 or 64.  
The phase detector has two outputs that drive two current sources of opposite  
palarity as charge pump. If the negative edge of the divided VCO signal appears  
prior to the negative edge of the reference signal, the positive current source  
pulses for the duration of the phase difference. In the reverse case the I- current  
source pulses. If the two signals are in phase, the charge pump output (CP)  
goes into the high-impedance state (PLL is locked). An active low-pass filter  
integrates the current pulses to generate the tuning voltage for the VCO (inter-  
nal amplifier, external pullup resistor at TUNE and external RC circuitry). The  
charge pump output is also switched into the high-impedance state if the control  
bit T0 = 1. Here it should be noted, however, that the tuning voltage can alter  
over a long period in the high-impedance state as a result of self-discharge in  
the peripheral circuity. TUNE may be switched off by the control bit OS to allow  
external adjustments.  
If the VCO is not oscillating the PLL locks to a tuning voltage of 33V .  
Wireless Components  
3 - 8  
Specification, December 1999  
TUA6024  
Functional Description  
By means of control bit CP the pump current can be switched between two val-  
ues by software. This programmability permits alteration of the control response  
of the PLL in the locked-in state. In this way different VCO gains can be com-  
pensated, for example.  
The software-switched ports PLOW, PMID and PHIGH are general-purpose  
open-collector outputs. The test bit T1 = 1, switches the test signals fref  
(i.e.fXTAL / 64) and fdiv (divided input signal) to PLOW and PMID respectively.  
The lock detector resets the lock flag FL if the width of the charge pump current  
pulses is wider than the period of the crystal oscillator (i.e. 250 ns). Hence, if FL  
= 1, the maximum deviation of the input frequency from the programmed fre-  
quency is given by  
f = ± IP (KVCO / fXTAL) (C1+C2) / (C1C2)  
where IP is the charge pump current, KVCO the VCO gain, fXTAL the crystal oscil-  
lator frequency and C1, C2 the capacitances in the loop filter (see Figure 4-1 Evalu-  
ation Board on page 2). As the charge pump pulses at i.e. 62.5 kHz (= fref), it takes a  
maximum of 16 µs for FL to be reset after the loop has lost lock state.  
Once FL has been reset, it is set only if the charge pump pulse width is less than  
250 ns for eight consecutive fref periods. Therefore it takes between 128 and  
144 µs for FL to be set after the loop regains lock.  
3.4.3 I2C-Bus Interface  
Data is exchanged between the processor and the PLL via the I2C bus. The  
clock is generated by the processor (input SCL), while pin SDA functions as an  
input or output depending on the direction of the data (open collector, external  
pull-up resistor). Both inputs have hysteresis and a low-pass characteristic,  
which enhance the noise immunity of the I2C bus.  
The data from the processor pass through an I2C bus controller. Depending on  
their function the data are subsequently stored in registers. If the bus is free,  
both lines will be in the marking state (SDA, SCL are HIGH). Each telegram  
begins with the start condition and ends with the stop condition. Start condition:  
SDA goes LOW, while SCL remains HIGH. Stop condition: SDA goes HIGH  
while SCL remains HIGH. All further information transfer takes place during  
SCL = LOW, and the data is forwarded to the control logic on the positive clock  
edge.  
The table Bit Allocation(see Table 5-4 Bit Allocation Read / Write on page 10) should be  
referred to the following description. All telegrams are transmitted byte-by-byte,  
followed by a ninth clock pulse, during which the control logic returns the SDA  
line to LOW (acknowledge condition). The first byte is comprised of seven  
address bits. These are used by the processor to select the PLL from several  
peripheral components (chip select). The LSB bit (R/W) determines whether  
data are written into (R/W = 0) or read from (R/W = 1) the PLL.  
Wireless Components  
3 - 9  
Specification, December 1999  
TUA6024  
Functional Description  
In the data portion of the telegram during a WRITE operation, the MSB bit of the  
first or third data byte determines whether a divider ratio or control information  
is to follow. In each case the second byte of the same data type has to follow  
the first byte.  
If the address byte indicates a READ operation, the PLL generates an acknowl-  
edge and then shifts out the status byte onto the SDA line. If the processor gen-  
erates an acknowledge, a further status byte is output; otherwise the data line  
is released to allow the processor to generate a stop condition. The status word  
consists the lock flag and the power-on flag.  
Four different chip addresses can be set by appropriate DC level at pin AS (see  
Table 5-6 Address selection on page 11).  
While applying the supply voltage, a power-on reset circuit prevents the PLL  
from setting the SDA line to LOW, which would block the bus. The power-on  
reset flag POR is set at power-on and when VCC falls below 3.2 V. It will be reset  
at the end of a READ operation.  
Wireless Components  
3 - 10  
Specification, December 1999  
4
Applications  
Contents of this Chapter  
4.1 Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2  
Wireless Components  
4 - 1  
Specification, November 1999  
TUA6024  
Applications  
4.1 Circuit  
SDA SCL  
100p 100p  
AS  
PHIGH  
PLOW  
4n7  
PMID  
RGen = 75  
HIGH  
RGen = 75 Ω  
VCC  
LOW/  
MID  
4n7  
4n7  
4n7  
4n7  
1:1*)  
4 MHz  
18p  
68p  
L4  
68p  
47n  
220  
220  
1n  
22p  
2p2  
22p  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
10  
18  
11  
17  
12  
16  
13  
15  
14  
TUA6024  
1
2
3
4
5
6
7
8
9
C1  
100p  
1p2  
1p2  
L1  
1p2  
1p2  
2p7  
L2  
2p2  
L3  
2p2  
2p7  
22n  
27p  
C2  
100p  
2:10**)  
ADC  
4n7  
1k  
100n  
1p2  
18p  
4k7  
220  
BA892  
3k3  
1k  
100k  
33k  
1k  
82p  
2k7  
4n7  
4k7  
BB565  
RLoad = 75  
4n7  
+ 33 V  
IFoutput  
BB659C  
2k7  
1n  
Application Circuit.wmf  
Figure 4-1  
Evaluation Board  
Table 4-1 Recommended band limits in MHz  
RF input Oscillator  
Table 4-1 Coils  
turns  
1.5  
E
wire E  
0.4 mm  
0.5 mm  
0.5 mm  
0.3 mm  
min  
48.25  
max  
min  
87.15  
max  
L1  
L2  
L3  
L4  
*)  
2 mm  
2.5 mm  
3 mm  
LOW  
MID  
147.25  
186.15  
3.5  
8.5  
154.25 423.25 193.15 462.25  
432.25 855.25 471.25 894.25  
HIGH  
14.5  
4 mm  
TOKO B4F Type 617DB-1023  
TOKO 7KL600 GCS-A1010DX  
**)  
Wireless Components  
4 - 2  
Specification, November 1999  
5
Reference  
Contents of this Chapter  
5.1 Electrical Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2  
5.1.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2  
5.1.2 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4  
5.1.3 AC/DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5  
5.2 Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10  
Table 5-4 Bit Allocation Read / Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10  
Table 5-5 Description of symbols. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10  
Table 5-6 Address selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11  
Table 5-7 Test modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11  
Table 5-8 Reference divider ratio. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11  
Table 5-9 A/D converter levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11  
5.3 I2C Bus Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12  
5.4 Test Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13  
5.4.1 Gain (GV) test Set-up in LOW/MID. . . . . . . . . . . . . . . . . . . . . . . . . . 5-13  
5.4.2 Gain (GV) test Set-up in HIGH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13  
5.4.3 Matching circuit for optimum noise figure in LOW/MID. . . . . . . . . . . 5-14  
5.4.4 Noise Figure Test Set-up in LOW/MID . . . . . . . . . . . . . . . . . . . . . . . 5-14  
5.4.5 Noise Figure Test Set-up in HIGH . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15  
5.4.6 Measurement of fref and fdiv . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15  
Wireless Components  
5 - 1  
Specification, December 1999  
TUA6024  
Reference  
5.1 Electrical Data  
5.1.1 Absolute Maximum Ratings  
WARNING  
The maximum ratings may not be exceeded under any circumstances, not even  
momentarily and individually, as permanent damage to the IC may result.  
Table 5-1 Absolute Maximum Ratings, Ambient temperature T  
=--20°C ... + 85°C  
AMB  
1).  
Symbol  
Limit Values  
Unit  
Remarks  
Parameter  
min  
-0.3  
max  
Supply voltage  
VCC  
TJ  
6
V
Junction temperature  
Storage temperature  
+150  
+125  
120  
°C  
°C  
K/W  
TStg  
RthJA  
-40  
Thermal resistance  
(junction to ambient)  
PLL  
CP  
VCHGPMP  
ICHGPMP  
VXTAL  
IXTAL  
VSDA  
ISDA(L)  
VSCL  
VAS  
-0.3  
3
1
V
mA  
V
Crystal oscillator pin XTAL  
VCC  
-5  
mA  
V
Bus input/output SDA  
-0.3  
VCC  
5
Bus output current SDA  
Bus input SCL  
mA  
V
open collector  
-0.3  
-0.3  
-0.3  
-0.3  
-1  
VCC  
VCC  
35  
Chip address switch AS  
VCO tuning output (loop filter)  
Port outputs PLOW, PMID, PHIGH  
V
VT  
V
VP  
VCC  
25  
V
IP(L)  
mA  
tmax = 0.1 sec.  
at 5.5 V  
Total port output current  
ΣIP(L)  
40  
mA  
tmax = 0.1 sec.  
at 5.5 V  
Mixer-Oscillator  
Mix inputs LOW/MID  
VMIX V  
VMIX U  
IMIX U  
-0.3  
-5  
3
2
6
V
Mix inputs HIGH  
V
mA  
Wireless Components  
5 - 2  
Specification, December 1999  
TUA6024  
Reference  
Table 5-1 Absolute Maximum Ratings, Ambient temperature T  
=--20°C ... + 85°C (continued)  
AMB  
Parameter 1)  
Symbol  
Limit Values  
Unit  
Remarks  
min  
-0.3  
max  
VCO base voltage  
VB  
VC  
3
V
V
VCO collector voltage  
VCC  
2).  
ESD-Protection  
all pins  
VESD  
1
kV  
1). All values are referred to ground (pin), unless stated otherwise.  
Currents with a positive sign flows into the pin and currents with a negative sign flows out of pin.  
2). According to MIL STD 883D, method 3015.7 and EOS/ESD assn. standardS5.1 - 1993  
Wireless Components  
5 - 3  
Specification, December 1999  
TUA6024  
Reference  
5.1.2 Operating Range  
Within the operational range the IC operates as described in the circuit  
description. The AC / DC characteristic limits are not guaranteed.  
Table 5-2 Operating Range  
Parameter  
Symbol  
Limit Values  
Unit  
Test Conditions  
L
Item  
min  
max  
+5.5  
Supply voltage  
VCC  
+4.5  
V
Programmable divider factor  
N
256  
30  
32767  
500  
LOW/MID Mixer input frequency  
range  
fMIXV  
MHz  
MHz  
MHz  
HIGH Mixer input frequency  
range  
fMIXU  
fOH  
400  
65  
900  
560  
LOW/MID Oscillator frequency  
range  
HIGH Oscillator frequency range fOU  
Ambient temperature Tamb  
430  
-20  
950  
+85  
MHz  
°C  
Wireless Components  
5 - 4  
Specification, December 1999  
TUA6024  
Reference  
5.1.3 AC/DC Characteristics  
AC / DC characteristics involve the spread of values guaranteed in the specified  
supply voltage and ambient temperature range. Typical characteristics are the  
median of the production.  
Table 5-3 AC/DC Characteristics with TA 25 °C, VCC  
Symbol  
Limit Values  
Unit  
Test Conditions  
L
Item  
min  
typ  
max  
Supply  
Supply voltage  
VCC  
ICC  
4.5  
56  
5
5.5  
84  
V
Current consumption  
70  
mA  
Digital Unit  
PLL  
Crystal oscillator connections XTAL  
Crystal frequency  
Crystal resistance  
Oscillation frequency  
Input impedance  
fXTAL  
RXTAL  
fXTAL  
ZXTAL  
3.2  
10  
4.0  
4.8  
100  
MHz  
series resonance  
series resonance  
fXTAL = 4 MHz  
3,99975  
-500  
4,000  
-700  
4,00025  
-900  
MHz  
fXTAL = 4 MHz  
Charge pump output CP  
HIGH output current  
LOW output current  
Tristate current  
ICPH  
±90  
±22  
±220  
±50  
+1  
±300  
±75  
µA  
µA  
nA  
V
CP = 1, VCP = 2 V  
CP = 0, VCP = 2 V  
T0 = 1, VCP = 2 V  
PLL locked  
ICPL  
ICPZ  
VCP  
Output voltage  
1.0  
2.5  
Drive output VT (open collector)  
HIGH output current  
LOW output voltage  
ITH  
10  
µA  
V
VTH = 33 V, T0 = 1  
ITL = 1.0 mA  
VTL  
0.4  
I2C-Bus  
Bus inputs SCL, SDA  
HIGH input voltage  
VIH  
VIL  
IIH  
3
0
5.5  
1.5  
10  
V
V
LOW input voltage  
HIGH input current  
LOW input current  
µA  
µA  
VIH = VS  
VIL = 0 V  
IIL  
-10  
Bus output SDA (open collector)  
HIGH output current  
LOW output voltage  
IOH  
10  
µA  
V
VOH = 5.5 V  
IOL = 3 mA  
VOL  
0.4  
Wireless Components  
5 - 5  
Specification, December 1999  
TUA6024  
Reference  
Table 5-3 AC/DC Characteristics with TA 25 °C, VCC (continued)  
Symbol  
Limit Values  
Unit  
Test Conditions  
L
Item  
min  
typ  
max  
Edge speed SCL,SDA  
Rise time  
tr  
tf  
300  
300  
ns  
ns  
Fall time  
Clock timing SCL  
Frequency  
fSCL  
tH  
0
400  
kHz  
µs  
HIGH pulse width  
LOW pulse width  
0.6  
1.3  
tL  
µs  
Start condition  
Set-up time  
tsusta  
thsta  
0.6  
0.6  
µs  
µs  
Hold time  
Stop condition  
Set up time  
tsusto  
tbuf  
0.6  
1.3  
µs  
µs  
Bus free  
Data transfer  
Set-up time  
tsudat  
thdat  
Vhys  
0.1  
0
µs  
µs  
Hold time  
Input hysteresis  
SCL, SDA  
200  
mV  
Pulse width of spikes  
which are suppressed  
tsp  
CL  
0
50  
ns  
Capacitive load for  
each bus line  
400  
pF  
Port outputs PLOW, PMID, PHIGH (open collector)  
HIGH output current  
LOW output voltage  
IPOH  
1
µA  
V
VPOH = 5 V  
VPOL  
0.5  
IPOL = 25 mA  
ADC port input  
HIGH input current  
IADCH  
IADCL  
10  
50  
µA  
µA  
LOW input current  
-10  
-50  
Address selection input AS  
HIGH input current  
LOW input current  
IASH  
IASL  
µA  
µA  
VASH = 5 V  
VASL = 0 V  
Wireless Components  
5 - 6  
Specification, December 1999  
TUA6024  
Reference  
Table 5-3 AC/DC Characteristics with TA 25 °C, VCC (continued)  
Symbol  
Limit Values  
Unit  
Test Conditions  
L
Item  
min  
typ  
max  
Analog Unit  
LOW/MID Band Section (including IF amplifier)  
Voltage gain  
GV  
20  
23  
26  
dB  
fRF = 43.25 to 463.25  
MHz, fIF = 33.4 to  
58.75 MHz  
Mixer noise figure  
NF  
Ri  
9
2
2
11  
3
dB  
kΩ  
pF  
fRF = 43.25 to 463.25  
MHz  
Mixer input  
impedance  
1
serial equivalent cir-  
cuit, fMixV = 100 MHz  
Ci  
3
serial equivalent cir-  
cuit, fMixV = 100 MHz  
Oscillator frequency  
shift, PLL unlocked  
fOsc(V)  
fOsc(T)  
fOsc(t)  
400  
500  
100  
kHz  
kHz  
kHz  
VCC = 5 V±10%  
Oscillator frequency  
drift, PLL unlocked  
T = 25 °C  
Oscillator frequency  
drift, PLL unlocked  
t = 5 s up to 15 min  
after switching on  
Wireless Components  
5 - 7  
Specification, December 1999  
TUA6024  
Reference  
Table 5-3 AC/DC Characteristics with TA 25 °C, VCC (continued)  
Symbol  
Limit Values  
Unit  
Test Conditions  
L
Item  
min  
100  
typ  
max  
Oscillator pulling,  
PLL unlocked  
Vi  
108  
dBµV  
dBµV  
f = 10 kHz  
f
RF = 48.25 MHz  
100  
-50  
108  
f = 10 kHz  
fRF = 399.25 MHz  
Vi  
N + 5 pulling,  
PLL unlocked  
N+5  
dBc  
dBc  
fRF = 48.25 MHz,  
fRF1 = 83.25 MHz,  
P
RF=PRF1 = 80dBµV  
fRF = 399.25 MHz,  
RF1 = 439.25 MHz,  
RF=PRF1 = 80dBµV  
dBc/Hz fm = 10kHz  
N+5  
-50  
f
P
Oscillator  
phase noise 1).  
ΦOSC  
-80  
15  
-86  
20  
IF suppression  
aIF  
dB  
dB  
VMixB = 80 dBµV  
HIGH Band Section (including IF amplifier)  
Voltage gain  
GMixU  
31  
34  
37  
fRF = 367.25 MHz to  
863.25 MHz,  
f
IF = 33.4MHz to  
58.75 MHz  
Mixer noise figure  
NFMixU  
6
7
9
dB  
dB  
fRF = 367.25 to  
615.25 MHz  
10  
26  
14  
fRF = 623.25 to  
863.25 MHz  
Mixer input  
impedance  
Ri  
Li  
14  
6
20  
10  
serial equivalent cir-  
cuit, fMixU = 600 MHz  
nH  
serial equivalent cir-  
cuit, fMixU = 600 MHz  
Wireless Components  
5 - 8  
Specification, December 1999  
TUA6024  
Reference  
Table 5-3 AC/DC Characteristics with TA 25 °C, VCC (continued)  
Symbol  
Limit Values  
Unit  
Test Conditions  
L
Item  
min  
typ  
max  
400  
Oscillator frequency  
shift, PLL unlocked  
fOsc(V)  
fOsc(T)  
fOsc(t)  
VMIXU  
kHz  
kHz  
VCC = 5 V±10%  
T = 25 °C  
Oscillator frequency  
drift, PLL unlocked  
800  
100  
Oscillator frequency  
drift, PLL unlocked  
kHz  
t = 5 s up to 15 min  
after switching on  
Oscillator pulling,  
PLL unlocked  
100  
100  
-50  
108  
108  
dBµV  
f = 10 kHz  
f
RF = 375.25 MHz  
dBµV  
dBc  
f = 10 kHz  
fRF = 847.25 MHz  
N + 5 pulling,  
PLL unlocked  
VMIXU  
fRF = 471.25 MHz,  
f
RF1 = 511.25 MHz,  
PRF =PRF1 = 80dBµV  
VMIXU  
-50  
dBc  
fRF = 847.25 MHz,  
f
RF1 = 887.25 MHz,  
RF=PRF1 = 80 dBµV  
P
Oscillator  
phase noise 1)  
-80  
15  
-86  
20  
dBc/Hz fm = 10kHz  
IF suppression  
aIF  
dB  
VMixB = 80 dBµV  
SAW preamplifier  
IF output impedance  
RIF  
LIF  
80  
serial equivalent  
circuit,  
fIF = 38.9 MHz  
7
nH  
Rejection at the IF outputs  
Divider interference  
rejection 2)  
a
70  
66  
dBc  
dBc  
PRF = 80 dBµV  
fRF = 76.25 MHz  
Channel S02 beat  
a
2).  
PRF = 80 dBµV  
rejection  
This value is only guaranteed in lab.  
1). Measured in evaluation board.  
2). Channel S02 beat is the interfering product of fRF, fIF and fOSC of channel S02, fbeat = 37.35 MHz.  
The possible mechanisms are fOSC - 2 x fIF or 2 x fRFpix - fOSC. Measured in evaluation board.  
Wireless Components  
5 - 9  
Specification, December 1999  
TUA6024  
Reference  
5.2 Programming  
Table 5-4 Bit Allocation Read / Write  
Byte  
MSB  
bit6  
bit5  
bit4  
bit3  
bit2  
bit1  
LSB  
Ack  
Remark  
s
Write Data  
Address Byte  
1
0
1
0
0
0
MA1  
N10  
MA0  
N9  
0
A
A
Progr. Divider  
Byte 1  
N14  
N13  
N12  
N11  
N8  
Progr. Divider  
Byte 2  
N7  
N6  
N5  
N4  
N3  
N2  
N1  
N0  
A
Control Byte  
1
x
CP  
x
T1  
x
T0  
x
FP  
x
RSA  
RSB  
OS  
A
A
Bandswitch  
Byte  
P-  
HIGH  
PMID  
1).  
PLOW  
1.)  
TUA  
6024-K  
Bandswitch  
Byte  
x
x
x
x
P-  
HIGH  
x
PMID  
1.)  
PLOW  
1.)  
A
TUA  
6024-S  
Read Data  
Address Byte  
Status Byte  
1
1
0
x
0
x
0
x
MA1  
x
MA0  
x
1
x
A
A
POR  
FL  
1). In a tuner PLOW and PMID are interchangeable. Both bits switch the IC into LOW/MID (VHF) mode.  
Table 5-5 Description of symbols  
Symbol  
Description  
MA0, MA1  
N14 to N0  
Address selection bits (see Table 5-6 Address selection on page 11)  
programmable divider bits:  
N = 214 x N14 + 213 x N13 + ..... + 23 x N3 + 22 x N2 + 21 x N1 + N0  
CP  
charge pump current:  
bit = 0: charge pump current = 50 µA  
bit = 1: charge pump current = 220µA  
T1, T0  
FP  
test bits (see Table 5-7 Test modes on page 11)  
reserved for future purposes, actually ignored, default: 1  
reference divider bits (see Table 5-8 Reference divider ratio on page 11)  
RSA, RSB  
OS  
tuning amplifier control bit: bit = 0: enable VT  
bit = 1: disable VT  
PLOW, PMID, PHIGH  
NPN ports control bits:  
bit = 0: NPN open-collector output is inactive  
bit = 1: NPN open-collector output is active  
FL  
PLL lock flag  
bit = 1: loop is locked  
POR  
Power-on reset flag  
flag is set at power-on and reset at the end of READ operation  
x
dont care  
Wireless Components  
5 - 10  
Specification, December 1999  
TUA6024  
Reference  
Table 5-6 Address selection  
Voltage at AS  
MA1  
MA0  
(0...0.1) * VCC  
0
0
open circuit  
0
1
1
0
(0.4...0.6) * VCC  
(0.9...1) * VCC  
1
1
Table 5-7 Test modes  
Test mode  
T1  
0
T0  
0
Normal operation  
Charge pump output, CP is in high-impedance state  
0
1
PLOW = f output, PMID = fref output  
div  
1
0
not used  
1
1
Table 5-8 Reference divider ratio  
Reference divider ratio  
1).  
RSA  
RSB  
f
ref  
80  
50 kHz  
31.25 kHz  
62.5 kHz  
x
0
1
0
1
1
128  
64  
1). With a 4 MHz quartz.  
Table 5-9 A/D converter levels  
Voltage at ADC  
A2  
A1  
A0  
(0...0.15)*V  
CC  
0
0
0
(0.15...0.3)*V  
CC  
0
0
0
1
0
1
1
0
1
0
1
0
(0.3...0.45)*V  
CC  
(0.45...0.6)*V  
CC  
(0.6...1)*V  
CC  
Wireless Components  
5 - 11  
Specification, December 1999  
Addressing  
Ack. 1st Byte Ack. 2nd Byte Ack. 3rd Byte Ack. 4th Byte  
Ack.  
MA MA R/W  
SCL:  
Note: SDA:  
Telegram examples:  
Abbreviations:  
Start-ADB-DB1-DB2-CB-BB-Stop  
Start-ADB-CB-BB-DB1-DB2-Stop  
Start-ADB-CB-AB-DB1-DB2-Stop  
Start-ADB-DB1-DB2-Stop  
Start= start condition  
ADB= address byte  
DB1= prog. divider byte 1  
DB2= prog. divider byte 2  
CB= Control byte  
Start-ADB-CB-BB-Stop  
BB= Bandswitch byte  
Stop= stop condition  
TUA6024  
Reference  
5.4 Test Circuits  
5.4.1 Gain (GV) test Set-up in LOW/MID  
LOW/  
IFOUT  
MIDIN  
Transformer  
N1 N2  
50  
Device  
under  
Test  
Vmeas  
RMS  
50  
V0  
50  
V
Vi  
C
spectrum  
analyser  
V'meas  
Votmeter  
IFOUT  
N1 : N2 = 10 : 2 turns  
GVHF2  
Zi >> 50 => Vi = 2 x Vmeas = 80 dBµV  
Vi = Vmeas + 6dB = 80 dBµV  
V0 = Vmeas + 16 dB (transformer ratio N1:N2 and transformer loss)  
Gv = 20 log(V0 / Vi)  
5.4.2 Gain (GV) test Set-up in HIGH  
HIGHIN IFOUT  
Transformer  
N1 N2  
50  
Device  
under  
Test  
Vmeas  
Balun  
1:1  
Vi  
V0  
50  
spectrum  
analyser  
V
50  
C
RMS  
Votmeter  
V'meas  
HIGHIN  
IFOUT  
N1 : N2 = 10 : 2 turns  
GUHF2  
Vi = Vmeas = 70 dBµV  
V0 = Vmeas + 16 dB (transformer ratio N1:N2 and transformer loss)  
Gv = 20 log(V0 / Vi) + 1 dB (1 dB = insertion loss of balun)  
Wireless Components  
5 - 13  
Specification, December 1999  
TUA6024  
Reference  
5.4.3 Matching circuit for optimum noise figure in LOW/MID  
15p  
1n  
22p  
1n  
In  
Out  
In  
Out  
7 turns  
22p  
wire  
coil  
0.5 mm  
5.5 mm  
50  
τ
semi rigid cable  
300 mm long  
96 pF/m  
33dB/100m  
22p  
NFM  
For fRF = 150 MHz  
For fRF = 50 MHz  
loss = 1.3 dB  
loss = 0 dB  
image suppression = 13 dB  
image suppression = 16 dB  
5.4.4 Noise Figure Test Set-up in LOW/MID  
LOW/  
MIDIN  
Noise  
Source  
IFOUT  
IN OUT  
Noise  
Figure  
Meter  
Transformer  
N1 N2  
Matching  
Circuit  
Device  
under  
Test  
C
IFOUT  
N1 : N2 = 10 : 2 turns  
NF = NFmeas - loss of matching circuit (dB)  
NFVHF2  
Wireless Components  
5 - 14  
Specification, December 1999  
TUA6024  
Reference  
5.4.5 Noise Figure Test Set-up in HIGH  
Noise  
Source  
HIGHIN IFOUT  
Noise  
Figure  
Meter  
Transformer  
N1 N2  
Device  
under  
Test  
Balun  
1:1  
C
HIGHIN  
IFOUT  
N1 : N2 = 10 : 2 turns  
loss of balun = 1 dB  
NF = NFmeas - loss of balun (dB)  
NFUHF2  
5.4.6 Measurement of fref and fdiv  
VVCC  
+ 5 V  
Test Mode: T1 = 1, T0 = 0  
5k  
5k  
fQ = fref * R  
Counter  
Counter  
R: reference divider ratio  
PMID  
fref  
18p  
4 MHz  
PLOW  
fVCO = fdiv * N  
N: divider ratio  
fdiv  
freq_meas_cof  
Wireless Components  
5 - 15  
Specification, December 1999  

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