TUA6026-S [INFINEON]
Video Tuner, 2-Band, PDSO28, 1 MM HEIGHT, PLASTIC, TSSOP-28;
| 型号： | TUA6026-S |
| 厂家： | 
Infineon |
| 描述： | Video Tuner, 2-Band, PDSO28, 1 MM HEIGHT, PLASTIC, TSSOP-28 放大器 射频 光电二极管 商用集成电路 |
| 文件： | 总30页 (文件大小：222K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Components
for Entertainment Electronics
2 Band TV Tuner
TUA 6026
Mixer-Oscillator-PLL
with Unbalanced IF-Amplifier
Preliminary Data Sheet 1998-09-01
Edition 1998-09-01
This edition was realized using
the software system FrameMaker
Published by Siemens AG, Bereich
Halbleiter, Marketing-Kommunikation,
Balanstraße 73,
81541 München
© Siemens AG 1998.
All Rights Reserved.
Attention please!
As far as patents or other rights of third
parties are concerned, liability is only
assumed for components, not for
applications, processes and circuits
implemented within components or
assemblies.
The information describes the type of
component and shall not be considered
as assured characteristics.
Terms of delivery and rights to change
design reserved.
For questions on technology, delivery
and prices please contact
the Semiconductor Group Offices in
Germany or the Siemens Companies and
Representatives worldwide
(see address list).
Due to technical requirements compo-
nents may contain dangerous substanc-
es. For information on the types in ques-
tion please contact your nearest
Siemens Office, Semiconductor Group.
Siemens AG is an approved CECC man-
ufacturer.
Packing
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For packing material that is returned to us
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Components used in life-support de-
vices or systems must be expressly
authorized for such purpose!
Critical components1 of the Semiconduc-
tor Group of Siemens AG, may only be
used in life-support devices or systems2
with the express written approval of the
Semiconductor Group of Siemens AG.
1 A critical component is a component
used in a life-support device or system
whose failure can reasonably be
expected to cause the failure of that
life-support device or system, or to
affect its safety or effectiveness of that
device or system.
2 Life support devices or systems are
intended (a) to be implanted in the
human body, or (b) to support and/or
maintain and sustain human life. If
they fail, it is reasonable to assume
that the health of the user may be
endangered.
TUA 6026
Revision History:
Current Version: 1998-09-01
Editorial Update
Previous Version:
Page
(in previous (in current
Version) Version)
Page
Subjects (major changes since last revision)
Data Classification
Maximum Ratings
Maximum ratings are absolute ratings; exceeding only one of these values may cause
irreversible damage to the integrated circuit.
Recommended Operating Conditions
Under this conditions the functions given in the circuit description are fulfilled. Nominal
conditions specify mean values expected over the production spread and are the
proposed values for interface and application. If not stated otherwise, nominal values will
apply at TA=25°C and the nominal supply voltage.
Characteristics
The listed characteristics are ensured over the operating range of the integrated circuit.
Edition 1998-09-01
Published by Siemens AG, Semiconductor Group
Copyright Siemens AG 1998. All rights reserved.
Terms of delivery and right to change design reserved.
TUA 6026
Page
Table of Contents
1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.1
1.2
1.3
1.4
1.5
1.6
2
2.1
2.2
2.3
2.3.1
2.3.2
2.3.3
2.3.4
2.3.5
2.3.6
2.3.7
2.3.8
Circuit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Mixer-Oscillator Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
PLL Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
I2C-Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Bit Allocation Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Description of Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
UHF/VHF Bandswitch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Address Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Test Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Reference Divider Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
A/D Converter Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
I2C-Bus Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
AC/DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.1
3.2
3.3
4
4.1
4.2
Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
DC and RF Parameter Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Measurement of Crystal Oscillator Frequency . . . . . . . . . . . . . . . . . . . . . . . 25
5
5.1
5.2
Application Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Application Circuit 1, PAL (evaluation board) . . . . . . . . . . . . . . . . . . . . . . . . 26
Application Circuit 2, NTSC (evaluation board) . . . . . . . . . . . . . . . . . . . . . . 27
6
Electrical Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Input Admittance VHF Mixer Input Y0 = 20 ms (single ended) . . . . . . . . . . . 28
Input Impedance UHF Mixer Input Z0 = 50 Ω (symmetrical) . . . . . . . . . . . . 29
Output Impedance IF Output Y0 = 20 ms (single ended) . . . . . . . . . . . . . . . 29
6.1
6.2
6.3
7
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Semiconductor Group
4
1998-09-01
2 Band TV Tuner
Mixer-Oscillator-PLL
with Unbalanced IF-Amplifier
TUA 6026
BIPOLAR
Preliminary Data
1
Overview
1.1
Features
General
• Suitable for NTSC and PAL tuners
• Full ESD protection
Mixer/Oscillator
P-TSSOP-28-1
• High impedance mixer input for VHF
• Low impedance mixer input for UHF
• 4 pin oscillator for VHF
• 4 pin oscillator for UHF
IF-Amplifier
• Unbalanced SAW preamplifier
• Low output impedance
PLL
• PLL with short lock-in time;
no asynchronous divider stage
• High voltage VCO tuning output
• Fast I2C Bus
• 4 NPN bandswitch buffers
• Internal VHF/UHF switch
• Lock-in flag
• Power-down reset
• Programmable reference divider ratio (64, 80, 128)
• Programmable charge pump current
Type
Ordering Code
Q67037-A1053
Q67037-A1058
Package
TUA 6026-K
TUA 6026-S
P-TSSOP-28-1
P-TSSOP-28-1
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TUA 6026
1.2
Functional Description
The TUA 6026 device combines a digitally programmable phase locked loop (PLL), with
a mixer-oscillator block including two balanced mixers and oscillators for use in TV
tuners.
The PLL block with four hard-switched chip addresses forms a digitally programmable
phase locked loop. With a 4 MHz quartz crystal, the PLL permits precise setting of the
frequency of the tuner oscillator up to 900 MHz in increments of 62.5 kHz. The tuning
process is controlled by a microprocessor via an I2C Bus. The device has four output
ports, two of them (P0 and P1) can also be used as TTL input ports. A flag is set when
the loop is locked. The input ports and lock flag can be read by the processor via the
I2C Bus.
The mixer-oscillator block includes two balanced mixers (one mixer with high-impedance
input and one mixer with a balanced low-impedance input), two frequency and
amplitude-stable balanced oscillators for VHF, HYPER and UHF, a low-noise reference
voltage source and a band switch.
1.3
Application
The IC is suitable for NTSC and PAL tuners in TV- and VCR-sets or cable set-top
receivers for analog TV and Digital Video Broadcasting.
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TUA 6026
1.4
Pin Configuration
OU-B2
OU-C1
OU-C2
OU-B1
OV-B2
OV-C1
OV-C2
OV-B1
GNDA
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
MIXU
2
MIXU
MIXV
VVCC
3
4
5
MIXout
6
MIXout
GNDD
7
TUA 6026
8
SDA
SCL
CAS
Q
9
ADC
IFout
10
11
12
13
14
P3
P2
TUNE
P1/I1
P0/I0
CHGPMP
UEP10802
Figure 1
1.5
Pin Definitions and Functions
Function
Pin No. Symbol
1
2
3
4
5
6
7
OU-B2
OU-C1
OU-C2
OU-B1
OV-B2
OV-C1
OV-C2
UHF oscillator amplifier, high-impedance base input,
symmetrical to OU-B1
UHF oscillator amplifier, high-impedance collector output,
symmetrical to OU-C2
UHF oscillator amplifier, high-impedance collector output,
symmetrical to OU-C1
UHF oscillator amplifier, high-impedance base input,
symmetrical to OU-B2
HYPER oscillator amplifier, high-impedance base input,
symmetrical to OV-B1
HYPER oscillator amplifier, high-impedance collector output,
symmetrical to OV-C2
HYPER oscillator amplifier, high-impedance collector output,
symmetrical to OV-C1
Semiconductor Group
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1998-09-01
TUA 6026
1.5
Pin Definitions and Functions (cont’d)
Function
Pin No. Symbol
8
OV-B1
HYPER oscillator amplifier, high-impedance base input,
symmetrical to OV-B2
9
GNDA
ADC
IFout
P3
Analog Ground
ADC input
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
IF output
Port output
TUNE
VCO tuning voltage output
CHGPMP Charge pump output/loop filter
P0/I0
P1/I1
P2
Port output/TTL input
Port output/TTL input
Port output
Q
4 MHz low-impedance crystal oscillator input
Chip address select
Clock input for the I2C Bus
CAS
SCL
SDA
GNDD
MIXout
MIXout
VVCC
MIXV
MIXU
MIXU
Data input/output for the I2C Bus
Digital Ground
Inverse Mixer output, symmetrical to MIXout
Mixer output, symmetrical to MIXout
Analog supply voltage
VHF mixer input, high-impedance
UHF mixer input, low-impedance, symmetrical to MIXU
UHF mixer input, low-impedance, symmetrical to MIXU
Semiconductor Group
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1998-09-01
TUA 6026
1.6
Block Diagram
MIXU MIXU MIXV VVCC MIXout MIXout GNDD SDA
SCL
20
CAS
19
Q
P2
17
P1/I1 P0/I0
16 15
28
27
26
25
24
23
22
21
18
Mixer
UHF
Mixer
VHF/HYPER
Ι2C-Bus
Interface
I/O-PORTS
Crystal
Oscillator
Reference
Divider
Isolation
Amplifier
Isolation
Amplifier
Progr.
Divider
Phase Det.
ChgPump
Oscillator
UHF
Oscillator
VHF/HYPER
A
D
1
2
3
4
5
6
7
8
9
10
11
12
13
14
OU-B2 OU-C1 OU-C2 OU-B1 OV-B2 OV-C1 OV-C2 OV-B1 GNDA ADC IFout
P3 TUNE CHGPMP
UEB10803
Figure 2
Semiconductor Group
9
1998-09-01
TUA 6026
2
Circuit Description
2.1
Mixer-Oscillator Block
The mixer oscillator section includes two balanced mixers (double balanced mixer), two
balanced oscillators for VHF low and/or HYPER band and UHF, a reference voltage
source and a band switch.
Filters between tuner input and IC separate the TV frequency signals into two bands.
The band switching in the tuner front-end is done by using two or three port outputs. In
the selected band the signal passes a tuner input stage with MOSFET amplifier, a
double-tuned bandpass filter and is then fed to the balanced mixer input of the IC which
has in case of VHF/Hyperband a high-impedance input and in case of UHF a low-
impedance input.
The input signal is mixed there with the signal from the activated on chip oscillator to the
IF frequency which is filtered out at the balanced high-impedance output pair by means
of a parallel tuned circuit. The following SAW preamplifier has a low output impedance
to drive a 75 Ω load directly.
2.2
PLL Block
The mixer-oscillator signal VCO/VCO is internally DC-coupled as a differential signal at
the programmable divider inputs. The signal subsequently passes through a
programmable divider with ratio N = 256 through 32767 and is then compared in a digital
frequency/phase detector to a reference frequency fref = 62.5 kHz. This frequency is
derived from a unbalanced, low-impedance 4 MHz crystal oscillator (pin Q) divided by
Q = 64.
The phase detector has two outputs UP and DOWN that drive two current sources I+
and I- of a charge pump. If the negative edge of the divided VCO signal appears prior to
the negative edge of the reference signal, the I+ current source pulses for the duration
of the phase difference. In the reverse case the I- current source pulses. If the two
signals are in phase, the charge pump output (CHGPMP) goes into the high-impedance
state (PLL is locked). An active low-pass filter integrates the current pulses to generate
the tuning voltage for the VCO (internal amplifier, external pullup resistor at TUNE and
external RC circuitry). The charge pump output is also switched into the high-impedance
state when the control bit T0 = 1. Here it should be noted, however, that the tuning
voltage can alter over a long period in the high-impedance state as a result of self-
discharge in the peripheral circuity. TUNE may be switched off by the control bit OS to
allow external adjustments.
If the VCO is not working the PLL locks to a tuning voltage of 33 V.
By means of control bit 5I the pump current can be switched between two values by
software. This programmability permits alteration of the control response of the PLL in
the locked-in state. In this way different VCO gains can be compensated, for example.
Semiconductor Group
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1998-09-01
TUA 6026
The software-switched ports P0, P1, and P2 are general-purpose open-collector
outputs. The test bit T1 = 1, switches the test signals fref (4 MHz / 64) and Cy (divided
input signal) to P0 and P1 respectively. P0, P1 are bidirectional.
The lock detector resets the lock flag FL when the width of the charge pump current
pulses is greater than the period of the crystal oscillator (i.e. 250 ns). Hence, when
FL = 1, the maximum deviation of the input frequency from the programmed frequency
is given by
∆f = ±IP (KVCO / fQ) (C1 + C2) / (C1C2)
where IP is the charge pump current, KVCO the VCO gain, fQ the crystal oscillator
frequency and C1, C2 the capacitances in the loop filter (see ”Application Circuits” on
page 26). As the charge pump pulses at 62.5 kHz (= fref), it takes a maximum of 16 µs
for FL to be reset after the loop has lost lock state.
Once FL has been reset, it is set only if the charge pump pulse width is less than 250 ns
for eight consecutive fref periods. Therefore it takes between 128 and 144 µs for FL to be
set after the loop regains lock.
2.3
I2C-Bus Interface
Data is exchanged between the processor and the PLL via the I2C Bus. The clock is
generated by the processor (input SCL), while pin SDA functions as an input or output
depending on the direction of the data (open collector, external pull-up resistor). Both
inputs have hysteresis and a low-pass characteristic, which enhance the noise immunity
of the I2C Bus.
The data from the processor pass through an I2C-Bus controller. Depending on their
function the data are subsequently stored in registers. If the bus is free, both lines will be
in the marking state (SDA, SCL are HIGH). Each telegram begins with the start condition
and ends with the stop condition. Start condition: SDA goes LOW, while SCL remains
HIGH. Stop condition: SDA goes HIGH while SCL remains HIGH. All further information
transfer takes place during SCL = LOW, and the data is forwarded to the control logic on
the positive clock edge.
The table ”Bit Allocation” (see ”Bit Allocation Read/Write” on page 12) should be referred
to the following description. All telegrams are transmitted byte-by-byte, followed by a
ninth clock pulse, during which the control logic returns the SDA line to LOW
(acknowledge condition). The first byte is comprised of seven address bits. These are
used by the processor to select the PLL from several peripheral components (chip
select). The LSB bit (R/W) determines whether data are written into (R/W = 0) or read
from (R/W = 1) the PLL.
In the data portion of the telegram during a WRITE operation, the MSB bit of the first or
third data byte determines whether a divider ratio or control information is to follow. In
Semiconductor Group
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TUA 6026
each case the second byte of the same data type has to follow the first byte. If the
address byte indicates a READ operation, the PLL generates an acknowledge and then
shifts out the status byte onto the SDA line. If the processor generates an acknowledge,
a further status byte is output; otherwise the data line is released to allow the processor
to generate a stop condition. The status word consists of two bits from the TTL input
ports, three bits from the A/D converter, the lock flag and the power-on flag.
Four different chip addresses can be set by appropriate DC level at pin CAS
(see ”Address Selection” on page 14).
When the supply voltage is applied, a power-on reset circuit prevents the PLL from
setting the SDA line to LOW, which would block the bus. The power-on reset flag POR
is set at power-on and if VVCC falls below 3.2 V. It will be reset at the end of a READ
operation.
2.3.1 Bit Allocation Read/Write
Byte
MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 LSB Ack Remarks
Write Data
Address byte
1
0
1
0
0
0
MA1 MA0 0
A
A
Progr. divider
byte 1
n14 n13 n12 n11 n10 n9
n8
Progr. divider
byte 2
n7
n6
n5
n4
n3
n2
n1
n0
A
Control byte 1
Control byte 2
Read Data
1
x
5I
x
T1
x
T0
x
1
RSA RSB OS
P2 P1 P0
A
A
P3
Address byte
Status byte
1
1
0
x
0
0
MA1 MA0 1
A2 A1 A0
A
A
POR FL
I1
I0
Semiconductor Group
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1998-09-01
TUA 6026
2.3.2 Description of Symbols
Symbol
Description
MA0, MA1
n14 to n0
Address selection bits (see ”Address Selection” on page 14)
Programmable divider bits:
N = 214 n14 + 213 n13 + ... + 23 n3 + 22 n2 + 21 n1 + n0
*
*
*
*
*
5I
Charge pump current:
Bit = 0 : Charge pump current = 50 µA
Bit = 1 : Charge pump current = 220 µA
T1, T0
RSA, RSB
OS
Test bits (see ”Test Modes” on page 14)
Reference divider bits (see ”Reference Divider Ratio” on page 14)
Tuning amplifier control bit:
Bit = 0 : Enable VTUNE
Bit = 1 : Disable VTUNE
PO, P1, P2, P3 NPN ports control bits
Bit = 0 : NPN open-collector output is inactive, TTL inputs at P0, P1
Bit = 1 : NPN open-collector output is active
UHF/VHF bandswitch (see ”UHF/VHF Bandswitch” on page 13)
A0, A1, A2
I0, I1
ADC bits (see ”A/D Converter Levels” on page 14)
Input data from P0/I0, P1/I1
FL
PLL lock flag
Bit = 1 : Loop is locked
POR
x
Power-on reset flag
Flag is set at power-on and reset at the end of READ operation
don‘t care
2.3.3 UHF/VHF Bandswitch
IC is in UHF Mode
Ports Pn
P0
P1
x
P2
1
P3
x
TUA 6026-K
TUA 6026-S
x
x
x
x
1
Semiconductor Group
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1998-09-01
TUA 6026
2.3.4 Address Selection
Voltage at CAS
MA1
MA0
(0...0.1) VVCC
0
0
1
1
0
1
0
1
*
Open circuit
(0.4...0.6) VVCC
*
(0.9...1) VVCC
*
2.3.5 Test Modes
Test Mode
T1
0
T0
0
Normal operation
Charge pump output,
0
1
CHGPMP is in high-impedance state
P1 = Cy output, P0 = fref output
1
1
0
1
TTL-inputs I1/I0 are Cy / fref inputs of phase detector
2.3.6 Reference Divider Ratio
Reference Divider Ratio
RSA
RSB
80
x
0
1
0
1
1
128
64
2.3.7 A/D Converter Levels
Voltage at ADC
A2
0
A1
0
A0
0
(0...0.15) VVCC
*
(0.15...0.3) VVCC
0
0
1
*
(0.3...0.45) VVCC
0
1
0
*
(0.45...0.6) VVCC
0
1
1
*
(0.6...1) VVCC
1
0
0
*
Semiconductor Group
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TUA 6026
2.3.8 I2C-Bus Timing Diagram
Addressing
Ack. 1st Byte Ack. 2nd Byte Ack. 3rd Byte Ack. 4th Byte
SDA
SCL
MA MA R/W
Telegram examples:
Abbreviations:
Start = Start Condition
Addr = Address Byte
Start-Addr-DR1-DR2-CW1-CW2-Stop
Start-Addr-CW1-CW2-DR1-DR2-Stop
Start-Addr-DR1-DR2-Stop
= Prog. Divider Byte 1
= Prog. Divider Byte 2
= Control Byte 1
= Control Byte 2
= Stop Condition
DR1
DR2
CW1
CW2
Stop
Start-Addr-CW1-CW2-Stop
UED10804
Figure 3
Semiconductor Group
15
1998-09-01
TUA 6026
3
Electrical Characteristics
Absolute Maximum Ratings
3.1
Parameter 1)
Symbol
Limit Values
Unit Test Conditions
min.
max.
6
Supply voltage
VVCC
TJ
- 0.3
V
Junction temperature
Storage temperature
150
125
120
°C
°C
K/W
TStg
RthSA
- 40
Thermal resistance
(junction to ambient)
PLL
CHGPMP
VCHGPMP - 0.3
ICHGPMP
VQ
3
V
1
mA
Crystal oscillator pins Q
VVCC
V
IQ
- 5
mA
Bus input/output SDA
Bus output current SDA
Bus input SCL
VSDA
ISDA(L)
VSCL
- 0.3
VVCC
5
V
mA Open collector
- 0.3
- 0.3
- 0.3
VVCC
VVCC
35
V
V
V
Chip address switch CAS VCAS
VCO tuning output
(loop filter)
VTUNE
Port outputs P0...P3
VP
- 0.3
- 1
VVCC
15
V
IP(L)
ΣIP(L)
mA
t
max = 0.1 s at 5.5 V
Total port output current
Mixer-Oscillator
40
mA tmax = 0.1 s at 5.5 V
Mix inputs VHF/HYPER
Mix inputs UHF
VMIXV
VMIXU
IMIXU
VB
- 0.3
3
V
2
V
- 5
6
mA
V
VCO base voltage
- 0.3
3
VCO collector voltage
VC
VVCC
V
Semiconductor Group
16
1998-09-01
TUA 6026
3.1
Absolute Maximum Ratings (cont’d)
Parameter 1)
Symbol
Limit Values
Unit Test Conditions
min.
max.
ESD-Protection 2)
All pins
VESD
1
kV
1) All values are referred to ground (pin), unless stated otherwise.
Currents with a positive sign flows into the pin and currents with a negative sign flows out of pin.
2) According to MIL STD 883D, method 3015.7 and EOS/ESD assn. standard S5.1 - 1993
Ambient Temperature under bias: TA = -20 to 85 °C.
Note: The maximal ratings may not be exceeded under any circumstances, not even
momentary and individual, as permanent damage to the IC will result.
Semiconductor Group
17
1998-09-01
TUA 6026
3.2
Operating Range
Parameter
Symbol
Limit Values
Unit Test Conditions
min.
max.
5.5
Supply voltage
VVCC
4.5
V
Programmable
divider factor
N
256
32767
VHF mixer input
frequency range
fMIXV
fMIXU
fOH
40
500
90
MHz
MHz
MHz
MHz
°C
UHF mixer input
frequency range
350
75
VHF oscillator
frequency range
560
950
85
UHF oscillator
frequency range
fOU
380
- 20
Ambient temperature
Tamb
Note: Within the operational range the IC operates as described in the circuit
description. The AC/DC characteristic limits are not guaranteed..
Semiconductor Group
18
1998-09-01
TUA 6026
3.3
AC/DC Characteristics
Parameter
TA = 25 °C, VVCC
Symbol
Limit Values
min. typ. max.
Unit Test Conditions
Supply
Supply voltage
Current consumption
Digital Unit
PLL
VVCC
IVCC
4.5
66
5
5.5
84
V
70
mA
Crystal Oscillator Connections Q
Crystal frequency
Crystal resistance
Oscillation frequency
Input impedance
fQ
3.2
10
4.0
4.8
MHz Series resonance
RQ
fQ
100
Ω
Series resonance
3.99975 4.000
4.00025
MHz fQ = 4 MHz
ZQ
- 500 - 700 - 900 Ω
fQ = 4 MHz
Charge Pump Output CHGPMP
HIGH output current
LOW output current
Tristate current
ICPH
ICPL
ICPZ
VCP
± 90 ± 220 ± 300 µA
± 22 ± 50 ± 75 µA
5I = 1, VCP = 2 V
5I = 0, VCP = 2 V
T0 = 1, VCP = 2 V
Locked
1
nA
V
Output voltage
1.0
2.5
Drive Output TUNE (open collector)
HIGH output current
LOW output voltage
I2C-Bus
ITH
10
µA
VTH = 33 V, T0 = 1
ITL = 1.0 mA
VTL
0.4
V
Bus Inputs SCL, SDA
HIGH input voltage
LOW input voltage
HIGH input current
LOW input current
VIH
VIL
IIH
IIL
3
0
5.5
1.5
10
V
V
µA VIH = VS
- 10
µA
VIL = 0 V
Bus Output SDA (open collector)
HIGH output current
LOW output voltage
IOH
10
µA
V
OH = 5.5 V
VOL
0.4
V
IOL = 3 mA
Semiconductor Group
19
1998-09-01
TUA 6026
3.3
AC/DC Characteristics (cont’d)
Parameter
Symbol
Limit Values
Unit Test Conditions
TA = 25 °C, VVCC
min. typ.
max.
Edge Speed SCL, SDA
Rise time
tr
tf
300
300
ns
ns
Fall time
Clock Timing SCL
Frequency
fSCL
tH
0
400
kHz
µs
HIGH pulse width
LOW pulse width
Start Condition
Set-up time
0.6
1.3
tL
µs
tsusta
thsta
0.6
0.6
µs
µs
Hold time
Stop Condition
Set-up time
tsusto
tbuf
0.6
1.3
µs
µs
Bus free
Data Transfer
Set-up time
tsudat
thdat
0.1
0
µs
µs
mV
ns
Hold time
Input hysteresis SCL,SDA Vhys
200
Pulse width of spikes
which are suppressed
tsp
0
50
Capacitive load for each
bus line
CL
400
pF
Port Outputs P0, P1, P2, P3 (open collector)
HIGH output current
LOW output voltage
TTL Port Inputs P0, P1
HIGH input voltage
LOW input voltage
HIGH input current
LOW input current
IPOH
1
µA
V
POH = 5 V
VPOL
0.5
V
IPOL = 15 mA
VPIH
VPIL
IPIH
IPIL
2.7
V
0.8
10
V
µA
µA
V
V
PIH = 5.5 V
PIL = 0 V
- 10
Semiconductor Group
20
1998-09-01
TUA 6026
3.3
AC/DC Characteristics (cont’d)
Parameter
TA = 25 °C, VVCC
Symbol
Limit Values
min. typ. max.
Unit Test Conditions
ADC Port Input
HIGH input current
LOW input current
IADCH
IADCL
10
50
µA
µA
- 10
- 50
Address Selection Input CAS
HIGH input current
LOW input current
Analog Unit
ICASH
ICASL
µA
µA
V
CASH = 5 V
CASL = 0 V
V
VHF Low and VHF High Band Section (including IF amplifier)
Voltage gain
GMIXV
20
23
26
dB
fRF = 43.25 to
463.25 MHz, fIF =
33.4 to 58.75 MHz
Mixer noise figure
FMIXV
RMIXV
9
2
11
3
dB
fRF = 43.25 to
463.25 MHz
Mixer input impedance
1
kΩ
Serial equivalent
circuit,
f
MIXV = 100 MHz
CMIXV
2
3
pF Serial equivalent
circuit,
f
MIXV = 100 MHz
Oscillator drift,
PLL unlocked
∆fOscV
400
500
100
kHz VS = 5 V ±10%
kHz ∆T = 25 °C
kHz t = 5 s up to 15 min
after switching on
Oscillator pulling,
PLL unlocked
VMIXV
100
80
108
88
dB
µ
V
∆f = 10 kHz
fRF = 48.25 MHz
dBµ
V
∆f = 10 kHz
fRF = 399.25 MHz
Semiconductor Group
21
1998-09-01
TUA 6026
3.3
AC/DC Characteristics (cont’d)
Parameter
Symbol
Limit Values
Unit Test Conditions
TA = 25 °C, VVCC
min. typ.
max.
N + 5 pulling,
PLL unlocked
VMIXU
- 50
dBc fRF = 48.25 MHz,
RF1 = 82.25 MHz,
f
PRF = PRF1
80 dBµV
=
VMIXU
- 50
dBc fRF = 399.25 MHz,
RF1 = 437.25 MHz,
f
PRF = PRF1
80 dBµV
=
Oscillator phase noise
IF suppression
L(fM)VHF - 80
aIF 15
- 86
20
dBc/ fM = 10 kHz,
Hz
application circuit
dB
V
MIXB = 80 dBµV
UHF Band Section (including IF amplifier)
Voltage gain
GMIXU
31
34
37
dB
fRF = 367.25 to
863.25 MHz, fIF =
33.4 to 58.75 MHz
Mixer noise figure
FMIXU
6
9
dB
dB
Ω
fRF = 367.25 to
615.25 MHz
7
10
26
fRF = 623.25 to
863.25 MHz
Mixer input impedance
RMIXU
LMIXU
∆fOscU
14
6
20
Serial equivalent
circuit,
f
MIXU = 600 MHz
10
14
nH Serial equivalent
circuit,
f
MIXU = 600 MHz
Oscillator drift,
PLL unlocked
400
800
100
kHz VS = 5 V ±10%
kHz ∆T = 25 °C
kHz t = 5 s up to 15 min
after switching on
Oscillator pulling,
PLL unlocked
VMIXU
100
100
108
108
dB
µ
V
V
∆f = 10 kHz
fRF = 375.25 MHz
dBµ
∆f = 10 kHz
fRF = 847.25 MHz
Semiconductor Group
22
1998-09-01
TUA 6026
3.3
AC/DC Characteristics (cont’d)
Parameter
Symbol
Limit Values
Unit Test Conditions
TA = 25 °C, VVCC
min. typ.
max.
N + 5 pulling,
PLL unlocked
VMIXU
- 50
dBc fRF = 471.25 MHz,
RF1 = 510.25 MHz,
f
PRF = PRF1
80 dBµV
=
VMIXU
- 50
dBc fRF = 847.25 MHz,
RF1 = 886.25 MHz,
f
PRF = PRF1
80 dBµV
=
Oscillator phase noise
L(fM)UHF - 80
- 86
20
dBc/ fM = 10 kHz,
Hz
application circuit
IF suppression
aIF
15
dB
VMIXB = 80 dBµV
SAW Preamplifier
IF output impedance
RIFout
LIFout
80
Ω
Serial equivalent
circuit,
fIF = 38.9 MHz
tbf
nH
Rejection at the IF Output
Channel 6 beat
INTCH6 tbf
INTCHA-5 tbf
tbf
tbf
dBc VRFpix = VRFsnd
80 dBµV 1)
dBc VRFpix = 80 dBµV 2)
=
Channel A-5 beat
1) Channel 6 beat is the interfering product of fRFpix, fRFsnd - fOSC of channel 6 at 42 MHz.
2) Channel A-5 beat is the interfering product of fRFpix + fRFsnd - fOSC of channel A-5, fBEAT = 45.5 MHz.
The possible mechanisms are: fOSC - 2 fIF or 2
f
RFpix - fOSC. For the measurement VRF = 80 dBµV.
*
*
Note: AC/DC characteristics involve the spread of values guaranteed in the specified
supply voltage and ambient temperature range. Typical characteristics are the
median of the production.
Semiconductor Group
23
1998-09-01
TUA 6026
4
Test Circuit
4.1
DC and RF Parameter Measurement
RGen = 75
UHF
Ω
SDA
SCL
CAS
4 MHz
P2
P1/I1
P0/I0
VHF
1:1
1:2 2)
68 pF 68 pF 47 nF
18 pF
1)
L3
50
Ω
22 pF 22 pF
2.2 pF
VVCC
1 nF
28
27
26
25
24
23
6
22
21
20
19
18
17
16
13
15
TUA 6026
1
2
3
4
5
7
8
9
10
11
12
14
1.2 pF 1.2 pF 1.2 pF 1.2 pF 2.7 pF 2.2 pF 2.2 pF 2.7 pF
4.7 nF
100 pF
22 nF
4.7 nF
22
k
Ω
L1
L2
4.7 nF
18 pF
82 pF
82 pF
ADC
P3
4.7 nF
BB 565
BB 659C
33
1 k
Ω
k
Ω
IFout
RLoad = 75
4.7 k
Ω
4.7 k
Ω
2.7 k
Ω
2.7 kΩ
Ω
+33 V
1 nF
1)
Not for noise measurement
2)
1:2 transformer for noise measurement
UES10805
Figure 4
Semiconductor Group
24
1998-09-01
TUA 6026
4.2
Measurement of Crystal Oscillator Frequency
VVCC
Test mode: T1 = HIGH
T2 = LOW
5 V
Ι VCC
5 k
5 k
Ω
Ω
fREF
P0
P1
Counter
Counter
fQ = fREF Reference Divider Ratio
*
18 pF
TUA 6026
fCY
4 MHz
fVCO = fCY
N
*
N: Divider Ratio
UES10806
GNDD
Figure 5
Semiconductor Group
25
1998-09-01
TUA 6026
5
Application Circuits
5.1
Application Circuit 1, PAL (evaluation board)
RGen = 75
UHF
Ω
SDA
SCL
CAS
4 MHz
P2
P1/I1
P0/I0
VHF
18 pF
100
pF
100
pF
4.7
nF
4.7
nF
4.7
nF
4.7
nF
68 pF 68 pF 4.7 nF
1:11)
1:2 2)
220
Ω
220 Ω
L4
22 pF 22 pF
2.2 pF
VVCC
1 nF
28
27
26
25
24
23
6
22
21
20
19
18
17
16
15
TUA 6026
1
2
3
4
5
7
8
9
10
11
12
13
14
1.2 pF 1.2 pF 1.2 pF 1.2 pF 2.7 pF 2.2 pF 2.2 pF 2.7 pF
4.7 nF
22 nF
22
ADC
IFout
4.7
nF
k
Ω
100 pF
L1
L2
L3
4.7 nF
RLoad = 75
Ω
P3
1 k
Ω
2.2 pF
BA 892
100
33
kΩ
82 pF
1 k
Ω
3.3 k
Ω
4.7 nF
18 pF
k
Ω
4.7 nF
BB 659C
1 k
Ω
BB 565
4.7 nF
4.7 k
Ω
4.7 k
Ω
2.7 k
Ω
2.7 kΩ
+33 V
1 nF
Transformers:
RF-Bands:
Coils:
1)
TOKO B4F Type 617DB-1023
TOKO B4F Type 617PT-1026
TOKO 7KL 291GCS-1499F
43.25 to 126.25 MHz
133.25 to 423.25 MHz
423.25 to 863.25 MHz
Coil
Turns Wire Size
[mm]
Coil Diameter
2)
3)
[mm]
L1
L2
L3
L4
1.5
2.5
0.4
0.5
0.5
0.3
2
3
3
4
8.5
14.5
UES10807
Figure 6
Semiconductor Group
26
1998-09-01
TUA 6026
5.2
Application Circuit 2, NTSC (evaluation board)
RGen = 75
UHF
Ω
SDA
SCL
CAS
4 MHz
P2/P3
P1/I1
P0/I0
VHF
18 pF
100
pF
100
pF
4.7
nF
4.7
nF
4.7
nF
4.7
nF
68 pF 68 pF 4.7 nF
1:11)
1:2 2)
220
Ω
220 Ω
L4
22 pF 22 pF
2.2 pF
VVCC
1 nF
28
27
26
25
24
23
6
22
21
20
19
18
17
16
15
TUA 6026
4
1
2
3
5
7
8
9
10
11
12
13
14
1.2 pF 1.2 pF 1.2 pF 1.2 pF 2.7 pF 2.2 pF 2.2 pF 2.7 pF
4.7 nF
22 nF
22
ADC
4.7
nF
k
Ω
100 pF
L1
L2
L3
4.7 nF
IFout
RLoad = 75
Ω
P3
1 k
Ω
2.2 pF
BA 892
100
33
kΩ
82 pF
1 k
Ω
3.3 k
Ω
4.7 nF
22 pF
k
Ω
4.7 nF
1 k
Ω
BB 565
BB 659C
4.7 nF
4.7 k
Ω
4.7 k
Ω
2.7 k
Ω
2.7 kΩ
+33 V
1 nF
Transformers:
RF-Bands:
Coils:
1)
TOKO B4F Type 617DB-1023
TOKO B4F Type 617PT-1026
TOKO 7KL 291GCS-1499F
55.25 to 126.25 MHz
139.25 to 423.25 MHz
367.25 to 801.25 MHz
Coil
Turns Wire Size
[mm]
Coil Diameter
2)
3)
[mm]
2
3
3
3.5
L1
L2
L3
L4
1.5
2.5
8.5
12
0.4
0.5
0.5
0.3
UES10808
Figure 7
Semiconductor Group
27
1998-09-01
TUA 6026
6
Electrical Diagrams
6.1
Input Admittance VHF Mixer Input Y0 = 20 ms (single ended)
0.9
1
0.8
0.7
1.5
0.6
2
0.5
0.4
3
0.3
4
0.2
0.1
5
5
10
20
5
3
2
1
0.3 0.2
0.1
0
20
10
0.1
0.2
4
0.3
3
0.4
2
0.5
0.6
1.5
0.7
0.8
0.9
Figure 8
Semiconductor Group
28
1998-09-01
TUA 6026
6.2
Input Impedance UHF Mixer Input Z0 = 50 Ω (symmetrical)
0.9 1
0.8
0.7
1.5
0.6
2
0.5
0.4
3
0.3
4
0.2
0.1
5
5
10
20
0.1
0.2 0.3
1
2
3
5
0
20
10
0.1
0.2
4
0.3
3
0.4
2
0.5
0.6
1.5
0.7
0.8
0.9 1
Figure 9
6.3
Output Impedance IF Output Y0 = 20 ms (single ended)
0.9 1
0.8
0.7
1.5
0.6
2
0.5
0.4
3
0.3
4
0.2
0.1
5
5
10
20
0.1
0.2 0.3
1
2
3
5
0
20
10
0.1
0.2
4
0.3
3
0.4
2
0.5
0.6
1.5
0.7
0.8
0.9 1
UED10811
Figure 10
Semiconductor Group
29
1998-09-01
TUA 6026
7
Package Outlines
P-TSSOP-28-1
(Plastic Thin Shrink Small Outline Package)
GPS05867
Figure 11
Semiconductor Group
30
1998-09-01
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