TUA6024-2 [INFINEON]
2 Band TV Tuner Mixer-Oscillator-PLL with balanced IF-Amplifier; 2波段电视调谐器混频器，振荡器， PLL与平衡IF放大器
| 型号： | TUA6024-2 |
| 厂家： | 
Infineon |
| 描述： | 2 Band TV Tuner Mixer-Oscillator-PLL with balanced IF-Amplifier |
| 文件： | 总40页 (文件大小：663K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Wireless Components
2 Band TV Tuner Mixer-Oscillator-PLL with balanced IF-Amplifier
TUA6024-2 Version 2.0
Specification July 2001
Confidential
Revision History: Current Version: Preliminary Datasheet, V 1.1, August 2000
Previous Version:Target Data Sheet
Page
Page
Subjects (major changes since last revision)
(in previous
Version)
(in current
Version)
all
all
version to 1.1, status to preliminary
5 - 2
5 - 2
Bus input/output SDA max changed to 6V,
Bus input SCL max changed to 6V,
ADC input added
5 - 3
5 - 5
5 - 3
5 - 5
new reference for ESD protection
Current consumption for LOW/MID band and HIGH band added,
tbf’s replaced by data
Charge Pump output voltage VCP = 1.3 V min
5 - 10
5 - 10
Table 5 - 4, Bit Allocation Read/Write in Status Byte A2, A1, A0 added
Revision History: Current Version: Datasheet, V 2.0, July 2001
Previous Version:Preliminary Datasheet V 1.1, August 2000
Page
Page
Subjects (major changes since last revision)
(in previous
Version)
(in current
Version)
all
all
version to 2.0, preliminary deleted
definition of thermal properties changed
current consumtion changed
5 - 2
5 - 5
5- 2
5 - 5
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TUA6024-2
Product Info
Product Info
General Description The TUA6024-2 is a 5 V mixer/oscilla-
tor and synthesizer for TV and VCR
tuners.
Package
Features General
ꢀ Suitable for analog tuners and for
digital CATV tuners
ꢀ Compatible with TUA6024-S and
TUA6024-K in normal mode
ꢀ New features in extended mode
ꢀ Full ESD protection
Mixer/Oscillator
ꢀ High impedance mixer input for
LOW/MID band
PLL
ꢀ Low impedance mixer input for
ꢀ PLL with short lock-in time
HIGH band
ꢀ High voltage VCO tuning output
ꢀ 4 pin oscillator for LOW/MID band
ꢀ 4 pin oscillator for HIGH band
2
ꢀ Fast I C bus
ꢀ 3 NPN bandswitch buffers
ꢀ Internal LOW-MID/HIGH switch
ꢀ Lock-in flag
IF-Amplifier
ꢀ balanced SAW preamplifier
ꢀ Low output impedance
ꢀ Power-down reset
ꢀ 4 programmable reference divider
ratios: 24, 64, 80, 128
ꢀ 4 programmable charge pump cur-
rents
ꢀ The IC is suitable for PAL tuners in TV- and VCR-sets or CATV set-top
Application
receivers for analog TV and digital cable TV.
Ordering Information
Type
Ordering Code
Package
TUA6024-2
P-TSSOP-28-1
Q67037--A1161 ( tape and reel)
Wireless Components
Product Info
Specification, July 2001
1
Table of Contents
1
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
2
Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.3 Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
2.4 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
3
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3.1 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
3.2 Internal Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
3.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
3.4 Circuit Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
4
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
4.1 Evaluation board, PAL application . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
4.2 Evaluation board, low phase noise application. . . . . . . . . . . . . . . . . . 4-3
5
Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
5.1 Electrical Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
5.1.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
5.1.2 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
5.1.3 AC/DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
5.2 Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
5.3 I2C Bus Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14
5.4 Test Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15
5.4.1 Gain (GV) test Set-up in LOW/MID. . . . . . . . . . . . . . . . . . . . . . . . . . 5-15
5.4.2 Gain (GV) test Set-up in HIGH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15
5.4.3 Matching circuit for optimum noise figure in LOW/MID. . . . . . . . . . . 5-16
5.4.4 Noise Figure Test Set-up in LOW/MID . . . . . . . . . . . . . . . . . . . . . . . 5-16
5.4.5 Noise Figure Test Set-up in HIGH . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17
5.4.6 Cross modulation Test Set-up in LOW/MID band. . . . . . . . . . . . . . . 5-17
5.4.7 Cross modulation Test Set-up in HIGH band . . . . . . . . . . . . . . . . . . 5-18
5.4.8 Measurement of fref and fdiv . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-18
5.5 Electrical Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-19
5.5.1 Input admittance (S11) of the LOW/MID band mixer input. . . . . . . . 5-19
5.5.2 Input impedance (S11) of the HIGH band mixer input . . . . . . . . . . . 5-19
5.5.3 Output admittance (S22) of the Mixer output . . . . . . . . . . . . . . . . . . 5-20
5.5.4 Output impedance (S22) of the IF output . . . . . . . . . . . . . . . . . . . . . 5-20
2
Product Description
Contents of this Chapter
2.1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.3 Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
2.4 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
TUA6024-2
Product Description
2.1 General Description
The TUA6024-2 device combines a digitally programmable phase locked loop
(PLL), with a mixer-oscillator block including two balanced mixers and oscilla-
tors for use in TV and VCR tuners.
The PLL block with four selectable chip addresses forms a digitally programm-
able phase locked loop. With a 4 MHz quartz crystal, the PLL permits precise
setting of the frequency of the tuner oscillator up to 1024 MHz in increments of
31.25, 50, 62.5 or 166.7 kHz. The tuning process is controlled by a micropro-
2
cessor via an I C bus. The device has three output ports. A flag is set when the
2
loop is locked. It can be read by the processor via the I C bus.
The mixer-oscillator block includes two balanced mixers (one mixer with high-
impedance input and one mixer with a balanced low-impedance input), two fre-
quency and amplitude-stable balanced oscillators for LOW/MID and HIGH, an
IF amplifier, a low-noise reference voltage source, and a band switch.
2.2 Features
General
ꢀ Suitable for analog tuners and for digital CATV tuners
ꢀ Compatible with TUA6024-S and TUA6024-K in normal mode
ꢀ New features in extended mode
ꢀ Full ESD protection
Mixer/Oscillator
ꢀ High impedance mixer input for LOW/MID band
ꢀ Low impedance mixer input for HIGH band
ꢀ 4 pin oscillator for LOW/MID band
ꢀ 4 pin oscillator for HIGH band
IF-Amplifier
ꢀ balanced SAW preamplifier
ꢀ Low output impedance
PLL
ꢀ PLL with short lock-in time
ꢀ High voltage VCO tuning output
2
ꢀ Fast I C bus
ꢀ 3 NPN bandswitch buffers
ꢀ Internal LOW-MID/HIGH switch
Wireless Components
2 - 2
Specification, July 2001
TUA6024-2
Product Description
ꢀ Lock-in flag
ꢀ Power-down reset
ꢀ 4 programmable reference divider ratios: 24, 64, 80, 128
ꢀ 4 programmable charge pump currents
2.3 Application
ꢀ The IC is suitable for PAL tuners in TV- and VCR-sets or CATV set-top
receivers for analog TV and digital cable TV.
2.4 Package Outlines
P-TSSOP-28-1
Wireless Components
2 - 3
Specification, July 2001
3
Functional Description
Contents of this Chapter
3.1 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
3.2 Internal Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
3.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
3.4 Circuit Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
3.4.1 General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
3.4.2 Mixer-Oscillator block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
3.4.3 PLL block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
3.4.4 I2C-Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
TUA6024-2
Functional Description
3.1 Pin Configuration
OSCHIGHIN
OSCHIGHOUT
OSCHIGHOUT
OSCHIGHIN
1
2
3
4
5
6
7
8
9
28 HIGHIN
27 HIGHIN
26 LOW/MIDIN
25
VCC
OSCLOW/MIDIN
OSCLOW/MIDOUT
24 MIXOUT
23 MIXOUT
22
OSCLOW/MIDOUT
OSCLOW/MIDIN
RFGND
PLLGND
TUA6024-2
21
SDA
20 SCL
ADC 10
IFOUT 11
IFOUT 12
VT 13
19 AS
18 XTAL
17 PHIGH
16 PMID
15 PLOW
CP 14
TUA6024-2_pin_config
Figure 3-1
Pin Configuration
Wireless Components
3 - 2
Specification, July 2001
TUA6024-2
Functional Description
3.2 Internal Pin Configuration
Table 3-1 Pin Definition and Function
Pin No. Symbol
Equivalent I/O-Schematic
Average DC voltage
LOW/MID
HIGH
1
2
3
4
OSCHIGHIN
0.0 V
1.6 V
OSC-
HIGHOUT
0.0 V
0.0 V
0.0 V
2.8 V
2.8 V
1.6 V
OSC-
HIGHOUT
2
1
3
4
OSCHIGHIN
5
6
7
8
OSCLOW/
MIDIN
1.6 V
2.3 V
2.3 V
1.6 V
0.0 V
0.0 V
0.0 V
0.0 V
OSCLOW/
MIDOUT
6
5
7
8
OSCLOW/
MIDOUT
OSCLOW/
MIDIN
Wireless Components
3 - 3
Specification, July 2001
TUA6024-2
Functional Description
Table 3-1 Pin Definition and Function (continued)
Pin No. Symbol Equivalent I/O-Schematic
Average DC voltage
LOW/MID
HIGH
9
RFGND
ADC
analog ground
0.0 V
0.0 V
10
V
V
ADC
ADC
10
11
IFOUT
2.3 V
2.3 V
2.3 V
2.3 V
11
12
12
13
IFOUT
VT
V
V
T
T
14
13
14
CP
2.1 V
2.1 V
Wireless Components
3 - 4
Specification, July 2001
TUA6024-2
Functional Description
Table 3-1 Pin Definition and Function (continued)
Pin No. Symbol Equivalent I/O-Schematic
Average DC voltage
LOW/MID
HIGH
15
16
PLOW
PMID
5 V or V
5 V
CE
15
16
17
5 V or V
5 V
CE
17
18
PHIGH
XTAL
5 V
V
CE
3.0 V
3.0 V
18
19
AS
V
V
AS
AS
19
20
SCL
n.a.
n.a.
20
Wireless Components
3 - 5
Specification, July 2001
TUA6024-2
Functional Description
Table 3-1 Pin Definition and Function (continued)
Pin No. Symbol Equivalent I/O-Schematic
Average DC voltage
LOW/MID
HIGH
21
SDA
n.a.
n.a.
21
22
23
PLLGND
MIXOUT
digital ground
0.0 V
3.8 V
0.0 V
3.8 V
IF Am p.
23
24
24
MIXOUT
3.8 V
3.8 V
O scillator
25
26
VCC
supply voltage
5.0 V
1.8 V
5.0 V
0.0 V
LOW/MIDIN
26
27
28
HIGHIN
HIGHIN
0.0 V
0.0 V
0.9 V
0.9 V
27
28
Wireless Components
3 - 6
Specification, July 2001
TUA6024-2
Functional Description
3.3 Block Diagram
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
I2C Bus
PORTS
LOW
or MID
RF Input
HIGH
RF Input
LOW/MID
HIGH
FL
Lock
Detector
Crystal
Oscillator
LOW
or MID
Mixer
HIGH
Mixer
LOW/MID
HIGH
ADC
Reference
Divider
Prog.
Divider
fref
fdiv
LOW
or MID
Phase/
Frequency
Comparator
Oscillator
HIGH
Oscillator
LOW/MID
SAW
Driver
HIGH
CP,
CM,
OS
Charge
Pump
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Block_diag
Figure 3-2
Block Diagram
Wireless Components
3 - 7
Specification, July 2001
TUA6024-2
Functional Description
3.4 Circuit Description
3.4.1 General
In the normal mode (see Table 5-7 Test modes on page 31) the IC is compatible with
TUA6024-S and TUA6024-K. An extended mode makes a reference divider
ratio of 24 (see Table 5-8 Reference divider ratio on page 31) and two additional charge
pump currents (see Table 5-9 Charge pump current on page 32) available.
3.4.2 Mixer-Oscillator block
The mixer oscillator section includes two balanced mixers (double balanced
mixer), two balanced oscillators for LOW and / or MID band and HIGH band, an
IF amplifier, a reference voltage source and a band switch.
Filters between tuner input and IC separate the TV frequency signals into two
bands. The band switching in the tuner front-end is done by using two or three
port outputs. In the selected band the signal passes a tuner input stage with
MOSFET amplifier, a double-tuned bandpass filter and is then fed to the bal-
anced mixer input of the IC which has in case of LOW / MID a high-impedance
input and in case of HIGH a low-impedance input. The input signal is mixed
there with the signal from the activated on chip oscillator to the IF frequency
which is filtered out at the balanced high-impedance output pair by means of a
parallel tuned circuit. The following SAW preamplifier has a low output imped-
ance to drive the SAW filter directly.
3.4.3 PLL block
The oscillator signal is internally DC-coupled as a differential signal to the pro-
grammable divider inputs. The signal subsequently passes through a program-
mable divider with ratio N = 256 through 32767 and is then compared in a digital
frequency / phase detector to a reference frequency f = 31.25, 50, 62.5 or
ref
166.7 kHz.This frequency is derived from an unbalanced, low-impedance 4
MHz crystal oscillator (pin XTAL) divided by R = 128, 80, 64 or 24.
The phase detector has two outputs that drive two current sources of opposite
polarity as charge pump. If the negative edge of the divided VCO signal appears
prior to the negative edge of the reference signal, the positive current source
pulses for the duration of the phase difference. In the reverse case the negative
current source pulses. If the two signals are in phase, the charge pump output
(CP) goes into the high-impedance state (PLL is locked). An active low-pass fil-
ter integrates the current pulses to generate the tuning voltage for the VCO
(internal amplifier, external pull-up resistor at TUNE and external RC circuitry).
The charge pump output is also switched into the high-impedance state if the
Wireless Components
3 - 8
Specification, July 2001
TUA6024-2
Functional Description
control bits T0 = 1 and T1 = 0. Here it should be noted, however, that the tuning
voltage can alter over a long period in the high-impedance state as a result of
self-discharge in the peripheral circuitry. TUNE may be switched off by the con-
trol bit OS to allow external adjustments.
If the VCO is not oscillating the PLL locks to a tuning voltage of 33 V .
By means of the control bits CP, CM, T0 and T1 the pump current can be
switched between four values by software. This programmability permits alter-
ation of the control response time of the PLL in the locked-in state. In this way
different VCO gains can be compensated, for example.
The software-switched ports PLOW, PMID and PHIGH are general-purpose
open-collector outputs. The test bits T0 = 0 and T1 = 1 switches the test signals
f
(i.e.f
/ 64) and f (divided input signal) to PLOW and PMID respec-
ref
XTAL div
tively.
The lock detector resets the lock flag FL if the width of the charge pump current
pulses is wider than the period of the crystal oscillator (i.e. 250 ns). Hence, if FL
= 1, the maximum deviation of the input frequency from the programmed fre-
quency is given by
∆f = ± I (K
/ f
) (C1+C2) / (C1C2)
P
VCO XTAL
where I is the charge pump current, K
the VCO gain, f
the crystal oscil-
P
VCO
XTAL
lator frequency and C1, C2 the capacitances in the loop filter (see Figure 4-2 Evalu-
ation Board, low phase noise application on page 20). As the charge pump pulses at i.e. 62.5
kHz (= f ), it takes a maximum of 16 µs for FL to be reset after the loop has lost
ref
lock state.
Once FL has been reset, it is set only if the charge pump pulse width is less than
250 ns for eight consecutive f periods. Therefore it takes between 128 and
ref
144 µs for FL to be set after the loop regains lock.
3.4.4 I2C-Bus Interface
2
Data is exchanged between the processor and the PLL via the I C bus. The
clock is generated by the processor (input SCL), while pin SDA functions as an
input or output depending on the direction of the data (open collector, external
pull-up resistor). Both inputs have hysteresis and a low-pass characteristic,
2
which enhance the noise immunity of the I C bus.
2
The data from the processor pass through an I C bus controller. Depending on
their function the data are subsequently stored in registers. If the bus is free,
both lines will be in the marking state (SDA, SCL are HIGH). Each telegram
begins with the start condition and ends with the stop condition. Start condition:
SDA goes LOW, while SCL remains HIGH. Stop condition: SDA goes HIGH
while SCL remains HIGH. All further information transfer takes place during
SCL = LOW, and the data is forwarded to the control logic on the positive clock
edge.
The table ”Bit Allocation” (see Table 5-4 Bit Allocation Read / Write on page 30) should be
referred to the following description. All telegrams are transmitted byte-by-byte,
followed by a ninth clock pulse, during which the control logic returns the SDA
Wireless Components
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Specification, July 2001
TUA6024-2
Functional Description
line to LOW (acknowledge condition). The first byte is comprised of seven
address bits. These are used by the processor to select the PLL from several
peripheral components (chip select). The LSB bit (R/W) determines whether
data are written into (R/W = 0) or read from (R/W = 1) the PLL.
In the data portion of the telegram during a WRITE operation, the MSB bit of the
first or third data byte determines whether a divider ratio or control information
is to follow. In each case the second byte of the same data type has to follow
the first byte.
If the address byte indicates a READ operation, the PLL generates an acknowl-
edge and then shifts out the status byte onto the SDA line. If the processor gen-
erates an acknowledge, a further status byte is output; otherwise the data line
is released to allow the processor to generate a stop condition. The status word
consists the lock flag and the power-on flag.
Four different chip addresses can be set by appropriate DC level at pin AS (see
Table 5-6 Address selection on page 31).
While applying the supply voltage, a power-on reset circuit prevents the PLL
from setting the SDA line to LOW, which would block the bus. The power-on
reset flag POR is set at power-on and when V falls below 3.2 V. It will be reset
CC
at the end of a READ operation.
Wireless Components
3 - 10
Specification, July 2001
4
Applications
Contents of this Chapter
4.1 Evaluation board, PAL application . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
4.2 Evaluation board, low phase noise application. . . . . . . . . . . . . . . . . . 4-3
TUA6024-2
Applications
4.1 Evaluation board, PAL application
SDA SCL
AS
PHIGH
PLOW
4n7
PMID
R
Gen = 75
Ω
RGen = 75 Ω
HIGH
1:1*)
22p
VCC
LOW/
MID
4n7
100p 100p
4n7
4n7
4n7
4 MHz
18p
68p
L4
68p
47n
220
220
1n
22p
2p2
28
27
26
25
24
23
22
21
20
19
10
18
11
17
12
16
13
15
14
TUA6024-2
1
2
3
4
5
6
7
8
9
C1
47n
100p
1p2
1p2
L1
1p2
1p2
2p7
L2
2p2
L3
2p2
2p7
12p
120p
C2
2n2
2:10**)
ADC
1k
100n
1p
15p
1k8
220
BA892
1n
3k3
1k
100k
33k
560
82p
2k7
1k8
BB565
RLoad = 75
Ω
4n7
+ 33 V
IFoutput
BB659C
2k7
10n
TUA6024-2_application-circuit
Figure 4-1
Evaluation Board, PAL application
Table 4-1 Recommended band limits in MHz
RF input Oscillator
Table 4-1 Coils
turns
1.5
E
wire E
0.5 mm
0.5 mm
0.5 mm
0.3 mm
min
48.25
max
min
87.15
max
L1
L2
L3
L4
*)
2.4 mm
3mm
LOW
MID
140.25
179.15
2.5
147.25 423.25 193.15 462.15
431.25 855.25 470.15 894.15
8.5
3.2 mm
4 mm
HIGH
14.5
TOKO B4F Type 617DB-1023
TOKO 7KL600 GCS-A1010DX
**)
Wireless Components
4 - 2
Specification, July 2001
TUA6024-2
Applications
4.2 Evaluation board, low phase noise application
SDA SCL
AS
PHIGH
PLOW
4n7
PMID
R
Gen = 75
Ω
RGen = 75 Ω
HIGH
1:1*)
22p
VCC
LOW/
MID
4n7
100p 100p
4n7
4n7
4n7
4 MHz
18p
68p
L4
68p
47n
220
220
1n
22p
2p2
28
27
26
25
24
23
22
21
20
19
10
18
11
17
12
16
13
15
14
TUA6024-2
1
2
3
4
5
6
7
8
9
C1
100n
100p
1p2
1p2
L1
1p2
1p2
2p7
L2
2p2
L3
2p2
2p7
12p
120p
C2
2n2
2:10**)
ADC
1k
100n
1p
15p
1k8
220
BA892
1n
3k3
1k
100k
33k
560
82p
2k7
1k8
BB565
RLoad = 75
Ω
IFoutput
BB659C
4n7
+ 33 V
22n
560
2k7
47n
TUA6024-2_application-circuit
Figure 4-2
Evaluation Board, low phase noise application
Table 4-1 Recommended band limits in MHz
RF input Oscillator
Table 4-1 Coils
turns
1.5
E
wire E
0.5 mm
0.5 mm
0.5 mm
0.3 mm
min
48.25
max
min
87.15
max
L1
L2
L3
L4
*)
2.4 mm
3mm
LOW
MID
140.25
179.15
2.5
8.5
147.25 423.25 193.15 462.15
431.25 855.25 470.15 894.15
3.2 mm
4 mm
HIGH
14.5
TOKO B4F Type 617DB-1023
TOKO 7KL600 GCS-A1010DX
**)
Wireless Components
4 - 3
Specification, July 2001
5
Reference
Contents of this Chapter
5.1 Electrical Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
5.1.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
5.1.2 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
5.1.3 AC/DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
5.2 Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
Table 5-4 Bit Allocation Read / Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
Table 5-5 Description of symbols. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
Table 5-6 Address selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
Table 5-7 Test modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
Table 5-8 Reference divider ratio. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
Table 5-9 Charge pump current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12
Table 5-10 Bandswitching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12
Table 5-11 A/D converter levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13
5.3 I2C Bus Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14
5.4 Test Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15
5.4.1 Gain (GV) test Set-up in LOW/MID. . . . . . . . . . . . . . . . . . . . . . . . . . 5-15
5.4.2 Gain (GV) test Set-up in HIGH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15
5.4.3 Matching circuit for optimum noise figure in LOW/MID. . . . . . . . . . . 5-16
5.4.4 Noise Figure Test Set-up in LOW/MID . . . . . . . . . . . . . . . . . . . . . . . 5-16
5.4.5 Noise Figure Test Set-up in HIGH . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17
5.4.6 Cross modulation Test Set-up in LOW/MID band. . . . . . . . . . . . . . . 5-17
5.4.7 Cross modulation Test Set-up in HIGH band . . . . . . . . . . . . . . . . . . 5-18
5.4.8 Measurement of fref and fdiv . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-18
5.5 Electrical Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-19
5.5.1 Input admittance (S11) of the LOW/MID band mixer input. . . . . . . . 5-19
5.5.2 Input impedance (S11) of the HIGH band mixer input . . . . . . . . . . . 5-19
5.5.3 Output admittance (S22) of the Mixer output . . . . . . . . . . . . . . . . . . 5-20
5.5.4 Output impedance (S22) of the IF output . . . . . . . . . . . . . . . . . . . . . 5-20
TUA6024-2
Reference
5.1 Electrical Data
5.1.1 Absolute Maximum Ratings
WARNING
The maximum ratings may not be exceeded under any circumstances, not even
momentarily and individually, as permanent damage to the IC may result.
Table 5-1 Absolute Maximum Ratings, Ambient temperature T
= - 20°C ...T
AMB
Limit Values
Amax
Unit
1).
Symbol
Remarks
Parameter
min
-0.3
max
Supply voltage
V
6
V
CC
Ambient temperature
T
-10
T
°C
A
Amax
2).
Junction temperature
Storage temperature
T
T
T
+125
+125
2
°C
°C
K
J
-40
Stg
JC
3).
Temperature difference junction to case
PLL
CP
V
-0.3
3
1
V
CHGPMP
I
mA
V
CHGPMP
Crystal oscillator pin XTAL
V
V
CC
XTAL
XTAL
I
-5
mA
V
Bus input/output SDA
Bus output current SDA
Bus input SCL
V
-0.3
6
5
6
SDA
I
mA
V
open collector
SDA(L)
V
V
V
V
V
-0.3
-0.3
-0.3
-0.3
-0.3
-1
SCL
AS
T
Chip address switch AS
VCO tuning output (loop filter)
ADC input
V
V
CC
35
V
V
V
V
ADC
P
CC
CC
Port outputs PLOW, PMID, PHIGH
V
I
25
mA
t
= 0.1 sec.
P(L)
max
at 5.5 V
t = 0.1 sec.
max
Total port output current
ΣI
40
mA
P(L)
at 5.5 V
Wireless Components
5 - 2
Specification, July 2001
TUA6024-2
Reference
Table 5-1 Absolute Maximum Ratings, Ambient temperature T
= - 20°C ... + 85°C (continued)
AMB
1)
Symbol
Limit Values
Unit
Remarks
Parameter
min
max
Mixer-Oscillator
Mix input LOW/MID
V
V
-0.3
3
2
6
3
V
i
i
Mix inputs HIGH
V
I
-5
mA
V
i
VCO base voltage
V
V
-0.3
B
C
VCO collector voltage
V
V
CC
4).
ESD-Protection
all pins
V
2
kV
ESD
1). All values are referred to ground (pin), unless stated otherwise.
Currents with a positive sign flows into the pin and currents with a negative sign flows out of pin.
2).The maximum ambient temperature depends on the mounting conditions of the package. Any application
mounting must guarantee not to exceed the maximum junction temperature of 125 °C. As reference the tem-
perature difference junction to case is given.
3).Referred to top center of package
4). According to EIA/JESD22-A114-B (HBM incircuit test), as a single device incircuit contact discharge test.
Wireless Components
5 - 3
Specification, July 2001
TUA6024-2
Reference
5.1.2 Operating Range
Within the operational range the IC operates as described in the circuit
description. The AC / DC characteristic limits are not guaranteed.
Table 5-2 Operating Range
Parameter
Symbol
Limit Values
Unit
Test Conditions
L
Item
min
max
+5.5
Supply voltage
V
+4.5
V
CC
Programmable divider factor
N
256
30
32767
500
LOW/MID Mixer input frequency
range
f
f
f
f
MHz
MHz
MHz
i
HIGH Mixer input frequency
range
400
65
900
560
950
i
LOW/MID Oscillator frequency
range
O
HIGH Oscillator frequency range
Ambient temperature
430
-20
MHz
O
T
T
°C
AMB
Amax
1).
1).see 5.1.1 Absolute Maximum Ratings on page 2
Wireless Components
5 - 4
Specification, July 2001
TUA6024-2
Reference
5.1.3 AC/DC Characteristics
AC / DC characteristics involve the spread of values guaranteed in the specified
supply voltage and ambient temperature range. Typical characteristics are the
median of the production.
Table 5-3 AC/DC Characteristics with T
= 25 °C, V
CC
AMB
Symbol
Limit Values
Unit
Test Conditions
L
Item
min
typ
max
5.5
Supply
Supply voltage
V
4.5
5
V
CC
Current consumption
I
48
51
61
65
74
79
mA
mA
LOW/MID band
HIGH band
CC
Digital Unit
PLL
Crystal oscillator connections XTAL
Crystal frequency
Crystal resistance
Oscillation frequency
Input impedance
f
3.2
10
4.0
4.8
100
MHz
Ω
series resonance
series resonance
XTAL
R
XTAL
XTAL
f
3,99975
-500
4,000
-700
4,00025
-900
MHz
Ω
f
f
= 4 MHz
= 4 MHz
XTAL
XTAL
Z
XTAL
Charge pump output CP
Output current,
see Table 5-9 Charge
pump current on page 12
ICPDH
ICPH
ICPDL
ICPL
± 430
± 180
± 90
± 650
± 250
± 125
± 50
± 860
± 360
± 180
± 70
µA
µA
µA
µA
nA
V
VCP = 1.8 V
VCP = 1.8 V
VCP = 1.8 V
VCP = 1.8 V
T0 = 1, T1 = 0
PLL locked
± 35
Tristate current
Output voltage
ICPZ
VCP
± 1
1.3
2.5
Drive output VT (open collector)
HIGH output current
I
10
µA
V
V
= 33 V, T0 = 1,
TH
TH
T1 = 0
LOW output voltage
V
0.4
I
TL
= 1.0 mA
TL
2
I C-Bus
Bus inputs SCL, SDA
HIGH input voltage
V
V
3
0
5.5
1.5
10
V
V
IH
IL
LOW input voltage
HIGH input current
LOW input current
I
I
µA
µA
V
V
= V
CC
IH
IL
IH
IL
-10
= 0 V
Wireless Components
5 - 5
Specification, July 2001
TUA6024-2
Reference
Table 5-3 AC/DC Characteristics with T
= 25 °C, V
(continued)
CC
AMB
Symbol
min
Limit Values
Unit
Test Conditions
L
Item
typ
max
Bus output SDA (open collector)
HIGH output current
LOW output voltage
I
10
µA
V
V
= 5.5 V
OH
OH
V
0.4
I
= 3 mA
OL
OL
Edge speed SCL,SDA
Rise time
t
t
300
300
ns
ns
r
f
Fall time
Clock timing SCL
Frequency
f
t
t
0
400
kHz
µs
SCL
H
HIGH pulse width
LOW pulse width
0.6
1.3
µs
L
Start condition
Set-up time
t
t
0.6
0.6
µs
µs
susta
hsta
Hold time
Stop condition
Set up time
t
t
0.6
1.3
µs
µs
susto
buf
Bus free
Data transfer
Set-up time
t
t
0.1
0
µs
µs
sudat
hdat
Hold time
Input hysteresis
SCL, SDA
V
200
mV
hys
Pulse width of spikes
which are suppressed
t
0
50
ns
sp
Capacitive load for
each bus line
C
400
pF
L
Port outputs PLOW, PMID, PHIGH (open collector)
HIGH output current
LOW output voltage
I
1
µA
V
V
= 5 V
POH
POH
V
0.5
I
= 25 mA
POL
POL
ADC port input
HIGH input current
I
I
10
50
µA
µA
ADCH
ADCL
LOW input current
-10
-50
Address selection input AS
HIGH input current
LOW input current
I
I
µA
µA
V
V
= 5 V
= 0 V
ASH
ASL
ASH
ASL
Wireless Components
5 - 6
Specification, July 2001
TUA6024-2
Reference
Table 5-3 AC/DC Characteristics with T
= 25 °C, V
(continued)
CC
AMB
Symbol
Limit Values
Unit
Test Conditions
L
Item
min
typ
max
Analog Unit
LOW/MID Band Section (including IF amplifier)
Voltage gain
G
20
23
9
26
11
dB
dB
f
= 43.25 to 463.25
RF
V
MHz, f = 33.4 to
IF
58.75 MHz
Mixer noise figure
NF
f
= 43.25 to 463.25
RF
MHz
Output voltage
causing 0.8% of
crossmodulation in
channel, see 5.4.6 on
page 17
Vi
Vi
118
117
dBµV
dBµV
f
= 48.25 MHz
= 399.25 MHz
RFw
f
RFw
Input IP2
IIP2
IIP2
IIP3
IIP3
137
137
119
119
dBµV
dBµV
dBµV
dBµV
f
f
= 48.25 MHz
= 98.50 MHz,
RF1
RF2
P
= P
RF2
RF1
f
f
= 415.25 MHz
= 832.50 MHz,
= P
RF1
RF2
P
RF1
RF2
Input IP3
f
= 48.25 MHz
= 49.25 MHz
RF1
f
RF2
P
= P
RF2
RF1
f
f
= 252.25 MHz
= 253.25 MHz,
= P
RF1
RF2
P
RF1
RF2
Output voltage caus-
ing 1 dB compression
Vo
Vo
121
121
1
dBµV
dBµV
kΩ
f
f
= 48.25 MHz
RF
RF
= 252.25 MHz
Mixer input
impedance
R
0.5
1.5
3
parallel equivalent
circuit,
i
f
= 100 MHz
RF
C
2
pF
parallel equivalent
circuit,
i
f
= 100 MHz
RF
Oscillator frequency
shift, PLL unlocked
∆f
∆f
∆f
400
500
100
kHz
kHz
kHz
V
= 5 V±10%
CC
Osc(V)
Osc(T)
Osc(t)
Oscillator frequency
drift, PLL unlocked
∆T = 25 °C
Oscillator frequency
drift, PLL unlocked
t = 5 s up to 15 min
after switching on
Wireless Components
5 - 7
Specification, July 2001
TUA6024-2
Reference
Table 5-3 AC/DC Characteristics with T
= 25 °C, V
(continued)
CC
AMB
Symbol
Limit Values
Unit
Test Conditions
L
Item
min
typ
max
Oscillator pulling,
PLL unlocked
V
100
108
dBµV
dBµV
∆f = 10 kHz
i
f
= 48.25 MHz
RF
100
108
∆f = 10 kHz
f
= 399.25 MHz
V
RF
i
N + 5 pulling,
PLL unlocked
N+5
-50
-50
dBc
dBc
f
f
= 48.25 MHz,
RF
= 83.25 MHz,
RF1
P
=P
= 80dBµV
RF1
RF
N+5
f
f
= 399.25 MHz,
RF
= 439.25 MHz,
RF1
P
=P
= 80dBµV
RF1
RF
Oscillator
ΦOSC
-58
-88
15
-60
-90
20
dBc/Hz fm = 1kHz
dBc/Hz fm = 10kHz
1).
phase noise
IF suppression
a
dB
V
= 80 dBµV
IF
IF
HIGH Band Section (including IF amplifier)
Voltage gain
G
31
34
37
dB
f
= 367.25 MHz to
V
RF
863.25 MHz,
= 33.4MHz to
f
IF
58.75 MHz
f = 367.25 to
RF
Mixer noise figure
NF
6
7
9
dB
dB
615.25 MHz
f = 623.25 to
RF
10
863.25 MHz
Output voltage
causing 0.8% of
crossmodulation in
channel,
V
V
116
117
dBµV
dBµV
f
= 503.25 MHz
i
i
RFw
f
= 799.25 MHz
RFw
see 5.4.7 on page 18
Input IP2
IIP2
IIP3
IIP3
139
108
108
dBµV
dBµV
dBµV
f
f
= 423.25 MHz
= 848.50 MHz,
RF1
RF2
P
= P
RF2
RF1
Input IP3
f
f
= 503.25 MHz
= 504.25 MHz
RF1
RF2
P
= P
RF2
RF1
f
f
= 799.25 MHz
= 800.25 MHz
RF1
RF2
P
= P
RF2
RF1
Output voltage caus-
ing 1 dB compression
V
V
121
121
dBµV
dBµV
f
f
= 503.25 MHz
= 799.25 MHz
o
o
RF
RF
Wireless Components
5 - 8
Specification, July 2001
TUA6024-2
Reference
Table 5-3 AC/DC Characteristics with T
= 25 °C, V
(continued)
CC
AMB
Symbol
Limit Values
Unit
Test Conditions
L
Item
min
typ
20
max
26
Mixer input
impedance
R
14
Ω
serial equivalent cir-
i
cuit, f = 600 MHz
RF
L
6
10
14
nH
serial equivalent cir-
i
cuit, f = 600 MHz
RF
Oscillator frequency
shift, PLL unlocked
∆f
∆f
∆f
400
800
100
kHz
kHz
V
= 5 V±10%
CC
Osc(V)
Osc(T)
Osc(t)
Oscillator frequency
drift, PLL unlocked
∆T = 25 °C
Oscillator frequency
drift, PLL unlocked
kHz
t = 5 s up to 15 min
after switching on
Oscillator pulling,
PLL unlocked
V
100
100
-50
108
108
dBµV
∆f = 10 kHz
i
f
= 375.25 MHz
RF
dBµV
dBc
∆f = 10 kHz
f
= 847.25 MHz
RF
N + 5 pulling,
PLL unlocked
V
V
f
f
= 471.25 MHz,
i
i
RF
= 511.25 MHz,
RF1
P
=P
= 80dBµV
RF1
RF
-50
dBc
f
f
= 847.25 MHz,
RF
= 887.25 MHz,
RF1
P
=P
= 80 dBµV
RF1
RF
Oscillator
ΦOSC
-58
-88
15
-60
-90
20
dBc/Hz fm = 1kHz
dBc/Hz fm = 10kHz
1.)
phase noise
IF suppression
a
dB
V = 80 dBµV
IF
i
SAW preamplifier
IF output impedance
R
125
10
Ω
serial equivalent
circuit,
IF
L
nH
IF
f
= 38.9 MHz
IF
Rejection at the IF outputs
Divider interference
Vo
30
dBµV
dBc
2).
level
Channel S02 beat
a
66
f
= 76.25 MHz
RF
3).
P
= 80 dBµV
rejection
RF
ꢀꢀ This value is only guaranteed in lab.
1). Measured in the evaluation board (see Chapter 4), worst case in band.
2). This is the level of divider interferences close to the IF frequency. For example channel S3:
fOSC = 158.15 MHz, 1/4 fOSC = 39.5375 MHz. Divider interference is measured in the evaluation
board (see Chapter 4).
3). Channel S02 beat is the interfering product of f , f and f
of channel S02, f
= 37.35 MHz.
RF IF
OSC
beat
The possible mechanisms are f
- 2 x f or 2 x f
- f
. Measured in the evaluation board
OSC
IF
RFpix OSC
(see Chapter 4).
Wireless Components
5 - 9
Specification, July 2001
TUA6024-2
Reference
5.2 Programming
Table 5-4 Bit Allocation Read / Write
Byte
MSB
bit6
bit5
bit4
bit3
bit2
bit1
LSB
Ack
Remark
Write Data
Address Byte
1
0
1
0
0
0
MA1
N10
MA0
N9
0
A
A
Progr. Divider
Byte 1
N14
N13
N12
N11
N8
Progr. Divider
Byte 2
N7
N6
N5
N4
N3
N2
N1
N0
A
Control Byte
1
x
CP
x
T1
x
T0
x
CM
P3
RSA
P2
RSB
P1
OS
P0
A
A
Bandswitch
1).
Byte
Read Data
Address Byte
Status Byte
1
1
0
x
0
x
0
x
MA1
A2
MA0
A1
1
A
A
POR
FL
A0
1). see Table 5-10 Bandswitching on page 12
Table 5-5 Description of symbols
Symbol
Description
MA0, MA1
N14 to N0
Address selection bits (see Table 5-6 Address selection on page 11)
programmable divider bits:
14
13
3
2
1
N = 2 x N14 + 2 x N13 + ..... + 2 x N3 + 2 x N2 + 2 x N1 + N0
CP
charge pump current:
bit = 0: charge pump current = 50 µA
bit = 1: charge pump current = 250µA
T1, T0
CM
test bits (see Table 5-7 Test modes on page 11)
charge pump mode bit (see Table 5-9 Charge pump current on page 12)
reference divider bits (see Table 5-8 Reference divider ratio on page 11)
RSA, RSB
OS
tuning amplifier control bit: bit = 0: enable V
T
bit = 1: disable V
T
PLOW, PMID, PHIGH,
see 5-10 on page 12
NPN ports control bits:
bit = 0: NPN open-collector output is inactive
bit = 1: NPN open-collector output is active
A0, A1, A2
FL
ADC bits (see Table 5-11 A/D converter levels on page 13)
PLL lock flag
bit = 1: loop is locked
POR
Power-on reset flag
flag is set at power-on and reset at the end of READ operation
x
don‘t care
Wireless Components
5 - 10
Specification, July 2001
TUA6024-2
Reference
Table 5-6 Address selection
Voltage at AS
MA1
MA0
(0...0.1) * V
0
0
CC
(0.2...0.3) * VCC or open circuit
(0.4...0.6) * V
0
1
1
0
CC
(0.9...1) * V
1
1
CC
Table 5-7 Test modes
Test mode
Mode
T1
0
T0
0
Normal operation
1).
normal
Charge pump output, CP is in high-impedance state
PMID = fdiv output, PLOW = fref output
Extended operation
0
1
1
0
extended
1
1
1). In this mode the IC is compatible with TUA6024-S and TUA6024-K
Table 5-8 Reference divider ratio
1).
2).
Reference divider ratio
T1
RSA
RSB
T0
Mode
fref
0
0
1
0
0
1
0
0
1
0
1
0
0
1
0
0
1
0
80
x
0
50 kHz
31.25 kHz
62.5 kHz
128
64
0
1
1
1
normal
80
0
0
1
1
0
1
0
1
50 kHz
128
24
31.25 kHz
166.7 kHz
62.5 kHz
extended
1
1
64
1). see Table 5-7 Test modes on page 11
2). With a 4 MHz quartz.
Wireless Components
5 - 11
Specification, July 2001
TUA6024-2
Reference
Table 5-9 Charge pump current
Charge pump current
1).
CP
T1
T0
CM
Mode
50 µA
0
1
0
0
1
1
x
x
0
1
0
1
normal
0
0
250 µA
50 µA
125 µA
extended
1
1
250 µA
600 µA
1). see Table 5-7 Test modes on page 11
Table 5-10 Bandswitching
Bit Designation
P3
P2
P1
P0
Active Port
Pin
1).
17
0
0
0
0
PHIGH
PLOW
15
16
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
PMID
not used
PHIGH
17
15
16
PLOW
PMID
not used
PHIGH
17
15
16
PLOW
PMID
not used
PHIGH
17
15
16
PLOW
PMID
not used
1). Default after power-on
Wireless Components
5 - 12
Specification, July 2001
TUA6024-2
Reference
Table 5-11 A/D converter levels
Voltage at ADC
A2
A1
A0
(0...0.15)*V
0
0
0
CC
(0.15...0.3)*V
(0.3...0.45)*V
(0.45...0.6)*V
0
0
0
1
0
1
1
0
1
0
1
0
CC
CC
CC
(0.6...1)*V
CC
Wireless Components
5 - 13
Specification, July 2001
TUA6024-2
Reference
5.3 I2C Bus Timing Diagram
Wireless Components
5 - 14
Specification, July 2001
TUA6024-2
Reference
5.4 Test Circuits
5.4.1 Gain (GV) test Set-up in LOW/MID
LOW/
IFOUT
MIDIN
Transformer
N1 N2
50
Ω
Device
under
Test
Vmeas
RMS
50
Ω
V0
50
Ω
V
Vi
C
spectrum
analyser
V'meas
Voltmeter
IFOUT
N1 : N2 = 10 : 2 turns
GVHF2
ꢀ Z >> 50 Ω => V = 2 x V = 80 dBµV
meas
i
i
ꢀ V = V
+ 6dB = 80 dBµV
i
meas
ꢀ V = V’
+ 16 dB (transformer ratio N1:N2 and transformer loss)
0
meas
ꢀ G = 20 log(V / V )
v
0
i
5.4.2 Gain (GV) test Set-up in HIGH
HIGHIN IFOUT
Transformer
N1 N2
50
Ω
Device
under
Test
Vmeas
Balun
1:1
Vi
V0
50
spectrum
analyser
Ω
V
50
Ω
C
RMS
Voltmeter
V'meas
HIGHIN
IFOUT
N1 : N2 = 10 : 2 turns
GUHF2
ꢀ V = V
= 70 dBµV
i
meas
ꢀ V = V’
+ 16 dB (transformer ratio N1:N2 and transformer loss)
0
meas
ꢀ G = 20 log(V / V ) + 1 dB (1 dB = insertion loss of balun)
v
0
i
Wireless Components
5 - 15
Specification, July 2001
TUA6024-2
Reference
5.4.3 Matching circuit for optimum noise figure in LOW/MID
15p
1n
22p
1n
In
Out
In
Out
7 turns
22p
wire
coil
⍪
0.5 mm
⍪
5.5 mm
50
τ
semi rigid cable
300 mm long
96 pF/m
33dB/100m
22p
NFM
For f = 150 MHz
For f = 50 MHz
RF
RF
ꢀ loss = 1.3 dB
ꢀ loss = 0 dB
ꢀ image suppression = 13 dB
ꢀ image suppression = 16 dB
5.4.4 Noise Figure Test Set-up in LOW/MID
LOW/
MIDIN
Noise
Source
IFOUT
IN OUT
Noise
Figure
Meter
Transformer
N1 N2
Matching
Circuit
Device
under
Test
C
IFOUT
N1 : N2 = 10 : 2 turns
NF = NFmeas - loss of matching circuit (dB)
NFVHF2
Wireless Components
5 - 16
Specification, July 2001
TUA6024-2
Reference
5.4.5 Noise Figure Test Set-up in HIGH
Noise
Source
HIGHIN IFOUT
Noise
Figure
Meter
Transformer
N1 N2
Device
under
Test
Balun
1:1
C
HIGHIN
IFOUT
N1 : N2 = 10 : 2 turns
loss of balun = 1 dB
NF = NFmeas - loss of balun (dB)
NFUHF2
5.4.6 Cross modulation Test Set-up in LOW/MID band
Vmeas
50
Ω
V
RMS
Voltmeter
unwanted
signal
source
AM = 80 %
18 dB
attenuator
LOW/
MIDIN
A
IFOUT
C
Transformer
N1 N2
50
Ω
Device
under
Test
38.9 MHz
50
Hybrid
V0
Vi
Ω
C
V
modulation
analyser
50
Ω
V'meas
B
D
IFOUT
N1 : N2 = 10 : 2 turns
RMS
Votmeter
wanted
signal
source
50
Ω
XVHF2
ꢀ
Zi >> 50 Ω => Vi = 2 x Vmeas
ꢀ
ꢀ
ꢀ
V’meas = V0 - 16 dB (transformer ratio N1:N2 and transformer loss)
wanted output signal at fpix, Vo = 100 dBµV
unwanted output signal at fsnd , 80 % AM modulated with 1 kHz
Wireless Components
5 - 17
Specification, July 2001
TUA6024-2
Reference
5.4.7 Cross modulation Test Set-up in HIGH band
Vmeas
50
Ω
V
RMS
Voltmeter
unwanted
signal
source
AM = 80 %
18 dB
attenuator
A
C
HIGHIN IFOUT
Transformer
N1 N2
50
Ω
Device
under
Test
Balun
1:1
38.9 MHz
50
Hybrid
Vi
V0
Ω
C
V
modulation
analyser
50
Ω
V'meas
B
D
HIGHIN IFOUT
N1 : N2 = 10 : 2 turns
RMS
Votmeter
wanted
signal
source
50
Ω
XUHF2
ꢀ
ꢀ
ꢀ
V’meas = V0 - 16 dB (transformer ratio N1:N2 and transformer loss)
wanted output signal at fpix, Vo = 100 dBµV
unwanted output signal at fsnd , 80 % AM modulated with 1 kHz
5.4.8 Measurement of fref and fdiv
VVCC
+ 5 V
Test Mode: T1 = 1, T0 = 0
5k
5k
fQ = fref * R
R: reference divider ratio
Counter
Counter
PMID
fref
18p
4 MHz
PLOW
fVCO = fdiv * N
N: divider ratio
fdiv
freq_meas_cof
Wireless Components
5 - 18
Specification, July 2001
TUA6024-2
Reference
5.5 Electrical Diagrams
5.5.1 Input admittance (S11) of the LOW/MID band mixer input
Y = 20mS (single ended)
0
0
48.25 MHz
407.25 MHz
5.5.2 Input impedance (S11) of the HIGH band mixer input
Z = 50 Ω (balanced)
0
855.25 MHz
415.25 MHz
Rdiff
0
Wireless Components
5 - 19
Specification, July 2001
TUA6024-2
Reference
5.5.3 Output admittance (S22) of the Mixer output
Y = 20mS (balanced)
0
0
Rdiff
38.9 MHz
5.5.4 Output impedance (S22) of the IF output
Z = 50 Ω (single/ double ended)
0
0
Rse
Rdiff
Wireless Components
5 - 20
Specification, July 2001
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