TUA6022-K [INFINEON]
Video Tuner, 2-Band, PDSO28, PLASTIC, TSSOP-28;
| 型号： | TUA6022-K |
| 厂家： | 
Infineon |
| 描述： | Video Tuner, 2-Band, PDSO28, PLASTIC, TSSOP-28 放大器 射频 光电二极管 商用集成电路 |
| 文件： | 总25页 (文件大小：266K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Components
for Entertainment Electronics
2 Band TV Tuner
TUA6022, TUA6024
Mixer-Oscillator-PLL
with balanced IF-Amplifier
Preliminary Data Sheet 03.99
Edition 03.99
Ausgabe 03.99
Published by Siemens AG,
Herausgegeben von Siemens AG,
Bereich Halbleiter, Marketing-
Kommunikation, Balanstraße 73,
81541 München
Bereich Halbleiter, Marketing-
Kommunikation, Balanstraße 73,
81541 München
© Siemens AG 1995.
© Siemens AG 1995.
All Rights Reserved.
Alle Rechte vorbehalten.
Attention please!
Wichtige Hinweise!
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components, not for applications, processes
and circuits implemented within components
or assemblies.
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Terms of delivery and rights to change design
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Liefermöglichkeiten und technische Änderun-
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For questions on technology, delivery and
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Fragen über Technik, Preise und Liefermögli-
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turer.
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Packing
Verpackung
Please use the recycling operators known to
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Components used in life-support devices
or systems must be expressly authorized
for such purpose!
1
1
Critical components of the Semiconductor
Kritische Bauelemente des Bereichs Hal-
Group of Siemens AG, may only be used in
life-support devices or systems with the
express written approval of the Semiconductor
Group of Siemens AG.
bleiter der Siemens AG dürfen nur mit aus-
drücklicher schriftlicher Genehmigung des
Bereichs Halbleiter der Siemens AG in leb-
2
2
enserhaltenden Geräten oder Systemen
eingesetzt werden.
1 A critical component is a component used
in a life-support device or system whose
failure can reasonably be expected to
cause the failure of that life-support device
or system, or to affect its safety or effec-
tiveness of that device or system.
1 Ein kritisches Bauelement ist ein in einem
lebenserhaltenden Gerät oder System
eingesetztes Bauelement, bei dessen Aus-
fall berechtigter Grund zur Annahme
besteht, daß das lebenserhaltende Gerät
oder System ausfällt bzw. dessen Sicher-
heit oder Wirksamkeit beeinträchtigt wird.
2 Lebenserhaltende Geräte und Systeme
sind (a) zur chirurgischen Einpflanzung in
den menschlichen Körper gedacht, oder
(b) unterstützen bzw. erhalten das men-
schliche Leben. Sollten sie ausfallen,
besteht berechtigter Grund zur Annahme,
daß die Gesundheit des Anwenders
gefährdet werden kann.
2 Life support devices or systems are
intended (a) to be implanted in the human
body, or (b) to support and/or maintain and
sustain human life. If they fail, it is reasona-
ble to assume that the health of the user
may be endangered.
TUA6022, TUA6024
Revision History:Current Version: 03.99
Previous Version:
old Page
new Page
Subjects (major changes since last revision)
Data Classification
Maximum Ratings
Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to
the integrated circuit.
Characteristics
The listed characteristics are ensured over the operating range of the integrated circuit. Typical characteristics
specify mean values expected over the production spread. If not otherwise specified, typical characteristics
apply at TA = 25 °C and the given supply voltage.
Operating Range
In the operating range the functions given in the circuit description are fulfilled.
For detailed technical information about "Processing Guidelines" and
"Quality Assurance" for ICs, see our "Product Overview".
Preliminary Data Sheet
TUA6022, TUA6024
1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Package Outlines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
2
3
4
5
6
7
8
9
Circuit Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Mixer-Oscillator block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
PLL block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
9.1
9.2
9.3
2
I C-Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
9.3.1 Bit Allocation Read / Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
9.3.2 Description of symbols. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
9.3.3 UHF/VHF Bandswitch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
9.3.4 Address selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
9.3.5 Test modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
9.3.6 Reference divider ratio. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
9.3.7 A/D Converter levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
2
9.3.8 I C Bus Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
10
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
AC/DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
10.1
10.2
10.3
11
11.1
11.2
Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
DC and RF Parameter Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Measurement of Crystal Oscillator Frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . .18
12
Application Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
12.1
Application Circuit (Evaluation Board) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
13
Electrical Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
13.1
13.2
13.3
Input admittance VHF mixer input Y = 20mS (single ended) . . . . . . . . . . . . . . . .20
0
Input impedance UHF mixer input Z = 50 W (symmetrical) . . . . . . . . . . . . . . . . .20
0
Output impedance IF output Y = 20mS (symmetrical). . . . . . . . . . . . . . . . . . . . .21
0
Semiconductor Group
22.3.99
2 Band TV Tuner
TUA6022, TUA6024
Mixer-Oscillator-PLL
with balanced IF-Amplifier
Preliminary Data Sheet
BIPOLAR
1
Features
General
• Suitable for PAL tuners
• Full ESD protection
Mixer/Oscillator
• High impedance mixer input for VHF
• Low impedance mixer input for UHF
• 4 pin oscillator for VHF
P-TSSOP-28-1
• 4 pin oscillator for UHF
IF-Amplifier
• balanced SAW preamplifier
• Low output impedance
PLL
Package
• PLL with short lock-in time;
no asynchronous divider stage
• High voltage VCO tuning output
2
• Fast I C bus
• 3 NPN bandswitch buffers
• Internal VHF/UHF switch
• Lock-in flag
• Power-down reset
• Programmable reference divider ratio
(64, 80, 128)
• Programmable charge pump current
2
Ordering Information
Type
Package
Ordering Code
Q67037-A1079
Q67037-A1080
Q67037-A1081
Q67037-A1082
Q67037-A1055
Q67037-A1056
TUA6022XS
TUA6022-K
TUA6022-S
TUA6024XS
TUA 6024-K
TUA 6024-S
P-TSSOP-28-1
P-TSSOP-28-1
P-TSSOP-28-1
P-TSSOP-28-1
P-TSSOP-28-1
P-TSSOP-28-1
Semiconductor Group
1
22.3.99
Preliminary Data Sheet
TUA6022, TUA6024
3
Functional Description
The TUA6022, TUA6024 device combines a digitally programmable phase locked loop (PLL), with a mixer-
oscillator block including two balanced mixers and oscillators for use in TV tuners.
The PLL block with four hard-switched chip addresses forms a digitally programmable phase locked loop. With
a 4 MHz quartz crystal, the PLL permits precise setting of the frequency of the tuner oscillator up to
2
900 MHz in increments of 62.5 kHz. The tuning process is controlled by a microprocessor via an I C bus. The
device has three output ports, two of them (P0 and P1) can also be used as TTL input ports. A flag is set when
2
the loop is locked. The input ports and lock flag can be read by the processor via the I C bus.
The mixer-oscillator block includes two balanced mixers (one mixer with high-impedance input and one mixer
with a balanced low-impedance input), two frequency and amplitude-stable balanced oscillators for VHF,
HYPER and UHF, a low-noise reference voltage source and a band switch.
4
Application
The IC is suitable for PAL tuners in TV- and VCR-sets or cable set-top receivers for analog TV and Digital
Video Broadcasting.
Semiconductor Group
2
22.3.99
Preliminary Data Sheet
TUA6022, TUA6024
5
Pin Configuration
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
OU-B1
OU-B1
MIXU
MIXUx
MIXV
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
MIXU
MIXUx
MIXV
OU-C2
OU-C2
3
OU-C1
OU-C1
3
4
OU-B2
OU-B2
V
4
V
VCC
VCC
5
OV-B1
OV-B1
MIXout
5
MIXout
6
OV-C2
OV-C2
MIXoutx
6
MIXoutx
7
OV-C1
OV-C1
GND
7
GND
D
D
8
OV-B2
OV-B2
SDA
SCL
CAS
Q
8
SDA
SCL
CAS
Q
9
GND
9
GND
A
A
10
11
12
13
14
ADC
10
11
12
13
14
ADC
IFout
IFoutx
IFout
P2/P3
P1/I1
P0/I0
P2/P3
P1/I1
P0/I0
IFoutx
TUNE
CHGPMP
TUNE
CHGPMP
6
Package Outlines
Semiconductor Group
3
22.3.99
Preliminary Data Sheet
TUA6022, TUA6024
7
Pin Definitions and Functions
Pin No.
Symbol
Function
1
2
3
4
5
6
7
8
9
28 OU-B2
UHF oscillator amplifier, high-impedance base input, symmetrical to OU-B1
UHF oscillator amplifier, high-impedance collector output, symmetrical to OU-C2
UHF oscillator amplifier, high-impedance collector output, symmetrical to OU-C1
UHF oscillator amplifier, high-impedance base input, symmetrical to OU-B2
HYPER oscillator amplifier, high-impedance base input, symmetrical to OV-B1
HYPER oscillator amplifier, high-impedance collector output, symmetrical to OV-C2
HYPER oscillator amplifier, high-impedance collector output, symmetrical to OV-C1
HYPER oscillator amplifier, high-impedance base input, symmetrical to OV-B2
Analog Ground
27 OU-C1
26 OU-C2
25 OU-B1
24 OV-B2
23 OV-C1
22 OV-C2
21 OV-B1
20 GND
A
10 19 ADC
ADC input
11 18 IFout
12 17 IFoutx
13 16 TUNE
14 15 CHGPMP
15 15 P0/I0
16 13 P1/I1
17 12 P2/P3
18 11 Q
IF output, symmetrical to IFoutx
Inverse IF output, symmetrical to IFout
VCO tuning voltage output
Charge pump output / loop filter
Port output / TTL input
Port output / TTL input
Port output (P2 = TUA6022-K, P3 = TUA6024-S)
4 MHz low-impedance crystal oscillator input
Chip address select
19 10 CAS
2
20
21
22
23
24
25
26
27
28
9 SCL
8 SDA
7 GND
Clock input for the I C bus
2
Data input/output for the I C bus
Digital Ground
D
6 MIXoutx
5 MIXout
Inverse Mixer output, symmetrical to MIXout
Mixer output, symmetrical to MIXoutx
Analog supply voltage
4 V
VCC
3 MIXV
2 MIXUx
1 MIXU
VHF mixer input, high-impedance
UHF mixer input, low-impedance, symmetrical to MIXU
UHF mixer input, low-impedance, symmetrical to MIXUx
Semiconductor Group
4
22.3.99
Preliminary Data Sheet
TUA6022, TUA6024
8
Block Diagram
The pin numbers given in parenthesis refer to the TUA 6022
Semiconductor Group
5
22.3.99
Preliminary Data Sheet
TUA6022, TUA6024
9
Circuit Description
9.1 Mixer-Oscillator block
The mixer oscillator section includes two balanced mixers (double balanced mixer), two balanced oscillators
for VHF and / or HYPER band and UHF, a reference voltage source and a band switch.
Filters between tuner input and IC separate the TV frequency signals into two bands. The band switching in
the tuner front-end is done by using two or three port outputs. In the selected band the signal passes a tuner
input stage with MOSFET amplifier, a double-tuned bandpass filter and is then fed to the balanced mixer input
of the IC which has in case of VHF / Hyperband a high-impedance input and in case of UHF a low-impedance
input. The input signal is mixed there with the signal from the activated on chip oscillator to the IF frequency
which is filtered out at the balanced high-impedance output pair by means of a parallel tuned circuit. The fol-
lowing SAW preamplifier has a low output impedance to drive the SAW filter directly.
9.2 PLL block
The mixer-oscillator signal VCO/VCOx is internally DC-coupled as a differential signal at the programmable
divider inputs. The signal subsequently passes through a programmable divider with ratio N = 256 through
32767 and is then compared in a digital frequency / phase detector to a reference frequency f = 62.5 kHz.
ref
This frequency is derived from a unbalanced, low-impedance 4 MHz crystal oscillator (pin Q) divided by
Q = 64.
The phase detector has two outputs UP and DOWN that drive two current sources I+ and I- of a charge pump.
If the negative edge of the divided VCO signal appears prior to the negative edge of the reference signal, the
I+ current source pulses for the duration of the phase difference. In the reverse case the I- current source
pulses. If the two signals are in phase, the charge pump output (CHGPMP) goes into the high-impedance
state (PLL is locked). An active low-pass filter integrates the current pulses to generate the tuning voltage for
the VCO (internal amplifier, external pullup resistor at TUNE and external RC circuitry). The charge pump out-
put is also switched into the high-impedance state when the control bit T0 = 1. Here it should be noted, how-
ever, that the tuning voltage can alter over a long period in the high-impedance state as a result of self-
discharge in the peripheral circuity. TUNE may be switched off by the control bit OS to allow external adjust-
ments.
If the VCO is not working the PLL locks to a tuning voltage of 33V.
By means of control bit 5I the pump current can be switched between two values by software. This program-
mability permits alteration of the control response of the PLL in the locked-in state. In this way different VCO
gains can be compensated, for example.
The software-switched ports P0, P1 and P2 are general-purpose open-collector outputs. The test bit
T1 = 1, switches the test signals f (4 MHz / 64) and C (divided input signal) to P0 and P1 respectively. P0,
ref
y
P1 are bidirectional.
The lock detector resets the lock flag FL when the width of the charge pump current pulses is greater than the
period of the crystal oscillator (i.e. 250 ns). Hence, when FL = 1, the maximum deviation of the input fre-
quency from the programmed frequency is given by
∆f = ± I (K
/ f ) (C +C ) / (C C )
P
VCO
Q
1
2
1 2
where I is the charge pump current, K
the VCO gain, f the crystal oscillator frequency and C , C the
Q 1 2
P
VCO
capacitances in the loop filter (see application circuit). As the charge pump pulses at 62.5 kHz (= f ), it takes
ref
a maximum of 16 µs for FL to be reset after the loop has lost lock state.
Once FL has been reset, it is set only if the charge pump pulse width is less than 250 ns for eight consecutive
f
periods. Therefore it takes between 128 and 144 µs for FL to be set after the loop regains lock.
ref
Semiconductor Group
6
22.3.99
Preliminary Data Sheet
TUA6022, TUA6024
2
9.3 I C-Bus Interface
2
Data is exchanged between the processor and the PLL via the I C bus. The clock is generated by the proces-
sor (input SCL), while pin SDA functions as an input or output depending on the direction of the data (open
collector, external pull-up resistor). Both inputs have hysteresis and a low-pass characteristic, which enhance
2
the noise immunity of the I C bus.
2
The data from the processor pass through an I C bus controller. Depending on their function the data are sub-
sequently stored in registers. If the bus is free, both lines will be in the marking state (SDA, SCL are HIGH).
Each telegram begins with the start condition and ends with the stop condition. Start condition: SDA goes
LOW, while SCL remains HIGH. Stop condition: SDA goes HIGH while SCL remains HIGH. All further infor-
mation transfer takes place during SCL = LOW, and the data is forwarded to the control logic on the positive
clock edge.
The table ”Bit Allocation” (see 9.3.1 Bit Allocation Read / Write on page 8) should be referred to the following
description. All telegrams are transmitted byte-by-byte, followed by a ninth clock pulse, during which the con-
trol logic returns the SDA line to LOW (acknowledge condition). The first byte is comprised of seven address
bits. These are used by the processor to select the PLL from several peripheral components (chip select). The
LSB bit (R/W) determines whether data are written into (R/W = 0) or read from (R/W = 1) the PLL.
In the data portion of the telegram during a WRITE operation, the MSB bit of the first or third data byte deter-
mines whether a divider ratio or control information is to follow. In each case the second byte of the same data
type has to follow the first byte.
If the address byte indicates a READ operation, the PLL generates an acknowledge and then shifts out the
status byte onto the SDA line. If the processor generates an acknowledge, a further status byte is output; oth-
erwise the data line is released to allow the processor to generate a stop condition. The status word consists
of two bits from the TTL input ports, three bits from the A/D converter, the lock flag and the power-on flag.
Four different chip addresses can be set by appropriate DC level at pin CAS (see 9.3.4 Address selection on
page 9).
When the supply voltage is applied, a power-on reset circuit prevents the PLL from setting the SDA line to
LOW, which would block the bus. The power-on reset flag POR is set at power-on and if V
below 3.2 V. It will be reset at the end of a READ operation.
falls
VCC
Semiconductor Group
7
22.3.99
Preliminary Data Sheet
TUA6022, TUA6024
9.3.1 Bit Allocation Read / Write
Byte
Write Data
MSB bit6
bit5
bit4
bit3
bit2
bit1
LSB
Ack
Remarks
Address Byte
1
0
1
n14
n6
5I
0
n13
n5
T1
x
0
n12
n4
T0
x
0
n11
n3
1
MA1 MA0
0
A
A
A
A
A
Progr. Divider Byte 1
Progr. Divider Byte 2
Control Byte 1
Control Byte 2
Read Data
n10
n2
n9
n1
n8
n0
OS
P0
n7
1
RSA RSB
P2 P1
x
x
P3
Address Byte
1
1
0
x
0
0
MA1 MA0
A2 A1
1
A
A
Status Byte
POR
FL
I1
I0
A0
9.3.2 Description of symbols
Symbol
Description
MA0, MA1
n14 to n0
Address selection bits (see 9.3.4 Address selection on page 9)
programmable divider bits:
N = 2 x n14 + 2 x n13 + ..... + 2 x n3 + 2 x n2 + 2 x n1 + n0
14
13
3
2
1
charge pump current:
5I
bit = 0 : charge pump current = 50 µA
bit = 1 : charge pump current = 220µA
T1, T0
test bits (see 9.3.5 Test modes on page 9)
reference divider bits (see 9.3.6 Reference divider ratio on page 9)
tuning amplifier control bit:
RSA, RSB
OS
bit = 0 : enable V
TUNE
bit = 1 : disable V
TUNE
NPN ports control bits
bit = 0 : NPN open-collector output is inactive, TTL inputs at P0, P1
bit = 1 : NPN open-collector output is active
PO, P1, P2/P3
UHF / VHF bandswitch (see 9.3.3 UHF/VHF Bandswitch on page 9)
A0, A1, A2
I0, I1
ADC bits (see 9.3.7 A/D Converter levels on page 9)
input data from P0/I0, P1/I1
PLL lock flag
bit = 1 : loop is locked
FL
Power-on reset flag
flag is set at power-on and reset at the end of READ operation
POR
x
don‘t care
Semiconductor Group
8
22.3.99
Preliminary Data Sheet
TUA6022, TUA6024
9.3.3 UHF/VHF Bandswitch
Ports Pn
IC is in UHF mode
P0
x
P1
1
P2
x
P3
n.a.
n.a.
1
TUA6022XS, TUA6024XS
TUA6022-K, TUA6024-K
TUA6022-S, TUA6024-S
x
x
1
x
x
n.a.
9.3.4 Address selection
Voltage at CAS
MA1
MA0
(0...0.1) * V
open circuit
0
0
1
1
0
1
0
1
VCC
(0.4...0.6) * V
VCC
(0.9...1) * V
VCC
9.3.5 Test modes
Test mode
T1
0
T0
0
Normal operation
Charge pump output, CHGPMP is in high-impedance state
P1 = Cy output, P0 = f output
0
1
1
0
ref
TTL-inputs I1/I0 are Cy/f inputs of phase detector
1
1
ref
9.3.6 Reference divider ratio
Reference divider ratio
RSA
RSB
80
x
0
1
0
1
1
128
64
9.3.7 A/D Converter levels
Voltage at ADC
A2
0
A1
0
A0
0
(0...0.15) * V
VCC
(0.15...0.3) * V
(0.3...0.45) * V
(0.45...0.6) * V
0
0
1
VCC
VCC
VCC
0
1
0
0
1
1
(0.6...1) * V
1
0
0
VCC
Semiconductor Group
9
22.3.99
Addressing
Ack. 1st Byte
Ack. 2nd Byte Ack. 3rd Byte Ack. 4th Byte
MA MA R/W
SCL
Note: SDA
Telegram examples:
Abbreviations:
Start-Addr-DR1-DR2-CW1-CW2-Stop
Start-Addr-CW1-CW2-DR1-DR2-Stop
Start-Addr-DR1-DR2-Stop
Start
Addr
DR1
DR2
CW1
CW2
Stop
= start condition
= address byte
= prog. divider byte 1
= prog. divider byte 2
= control byte 1
Start-Addr-CW1-CW2-Stop
= control byte 2
= stop condition
Preliminary Data Sheet
TUA6022, TUA6024
10 Electrical Characteristics
10.1 Absolute Maximum Ratings
The maximal ratings may not be exceeded under any circumstances, not even momentary and individual, as
permanent damage to the IC will result.
Ambient Temperature under bias: T = -20 to +85° C
A
Limit Values
1
Parameter
Symbol
Unit
Test Conditions
min
max
Supply voltage
V
-0.3
6
V
VCC
Junction temperature
Storage temperature
T
T
+150
+125
°C
°C
J
-40
Stg
Thermal resistance
(junction to ambient)
R
120
K/W
thSA
PLL
V
-0.3
3
1
V
CHGPMP
CHGPMP
I
mA
V
CHGPMP
V
V
V
Q
VCC
Crystal oscillator pins Q
I
-5
mA
V
Q
Bus input/output SDA
Bus output current SDA
Bus input SCL
V
-0.3
SDA
VCC
I
5
mA
V
open collector
SDA(L)
V
V
V
V
-0.3
-0.3
-0.3
-0.3
-1
V
V
SCL
CAS
TUNE
P
VCC
VCC
Chip address switch CAS
VCO tuning output (loop filter)
V
35
V
V
V
VCC
Port outputs P0...P2/P3
I
15
mA
mA
t
t
= 0.1 sec. at 5.5 V
= 0.1 sec. at 5.5 V
P(L)
max
max
Total port output current
Mixer-Oscillator
ΣI
40
P(L)
Mix inputs VHF / Hyper
V
V
-0.3
3
2
6
3
V
MIX V
MIX U
MIX U
V
Mix inputs UHF
I
-5
mA
V
VCO base voltage
VB
VC
-0.3
VCO collector voltage
V
V
VCC
2
ESD-Protection
all pins
V
1
kV
ESD
1. All values are referred to ground (pin), unless stated otherwise.
Currents with a positive sign flows into the pin and currents with a negative sign flows out of pin.
2. according to MIL STD 883D, method 3015.7 and EOS/ESD assn. standard S5.1 - 1993
Semiconductor Group
11
22.3.99
Preliminary Data Sheet
TUA6022, TUA6024
10.2 Operating Range
Within the operational range the IC operates as described in the circuit description.
The AC / DC characteristic limits are not guaranteed.
Limit Values
Parameter
Symbol
Unit
Test Conditions
min
+4.5
256
40
max
+5.5
32767
500
Supply voltage
V
V
VCC
Programmable divider factor
VHF Mixer input frequency range
UHF Mixer input frequency range
VHF Oscillator frequency range
UHF Oscillator frequency range
Ambient temperature
N
f
f
f
f
MHz
MHz
MHz
MHz
°C
MIXV
MIXU
OH
350
75
900
560
380
-20
950
OU
T
+85
amb
Semiconductor Group
12
22.3.99
Preliminary Data Sheet
TUA6022, TUA6024
10.3 AC/DC Characteristics
AC / DC characteristics involve the spread of values guaranteed in the specified supply voltage and ambient
temperature range. Typical characteristics are the median of the production.
Limit Values
Parameter
Symbol
Unit Test conditions
TA = 25 °C,VVCC
min
typ
max
Supply
Supply voltage
Current consumption
Digital Unit
V
4.5
56
5
5.5
84
V
VCC
I
70
mA
VCC
PLL
Crystal oscillator connections Q
Crystal frequency
f
3.2
10
4.0
4.8
MHz series resonance
Q
Crystal resistance
Oscillation frequency
Input impedance
R
100
Ω
series resonance
Q
f
3,99975 4,000 4,00025 MHz f = 4 MHz
Q
Q
Z
-700
-900
-1100
Ω
f = 4 MHz
Q
Q
Charge pump output CHGPMP
HIGH output current
LOW output current
Tristate current
I
I
I
±90
±22
±220
±50
+1
±300 µA
5I = 1, V = 2 V
CP
CPH
CPL
CPZ
±75
µA
nA
V
5I = 0, V = 2 V
CP
T0 = 1, V = 2 V
CP
Output voltage
V
1.0
2.5
locked
CP
Drive output TUNE (open collector)
HIGH output current
LOW output voltage
I
10
µA
V
= 33 V, T0 = 1
TH
TH
V
0.4
V
I
= 1.0 mA
TL
TL
2
I C-Bus
Bus inputs SCL, SDA
HIGH input voltage
LOW input voltage
HIGH input current
LOW input current
Bus output SDA (open collector)
HIGH output current
LOW output voltage
Edge speed SCL,SDA
Rise time
V
V
3
0
5.5
1.5
10
V
IH
IL
V
I
I
µA
µA
V
= V
IH S
IH
-10
V = 0 V
IL
IL
I
10
µA
V
= 5.5 V
OH
OH
V
0.4
V
I
= 3 mA
OL
OL
t
t
300
300
ns
ns
r
f
Fall time
Semiconductor Group
13
22.3.99
Preliminary Data Sheet
TUA6022, TUA6024
Limit Values
Symbol
Parameter
TA = 25 °C,VVCC
Unit Test conditions
min
typ
max
Clock timing SCL
Frequency
f
t
t
0
400
kHz
µs
SCL
H
HIGH pulse width
LOW pulse width
Start condition
Set-up time
0.6
1.3
µs
L
t
t
0.6
0.6
µs
µs
susta
hsta
Hold time
Stop condition
Set up time
t
t
0.6
1.3
µs
µs
susto
buf
Bus free
Data transfer
Set-up time
t
t
0.1
0
µs
µs
sudat
hdat
Hold time
Input hysteresis
SCL, SDA
V
200
mV
hys
Pulse width of spikes which are
suppressed
t
0
50
ns
sp
Capacitive load for each bus line
C
400
pF
L
Port outputs P0, P1, P2/P3 (open collector)
HIGH output current
LOW output voltage
TTL port inputs P0, P1
HIGH input voltage
LOW input voltage
HIGH input current
LOW input current
ADC port input
I
1
µA
V
= 5 V
POH
POH
V
0.5
V
I
= 15 mA
POL
POL
V
V
2.7
-10
-10
-50
V
PIH
PIL
0.8
10
V
I
I
µA
µA
V
V
= 5.5 V
= 0 V
PIH
PIH
PIL
PIL
HIGH input current
LOW input current
Address selection input CAS
HIGH input current
LOW input current
I
I
10
50
µA
µA
ADCH
ADCL
I
I
µA
µA
V
V
= 5 V
= 0 V
CASH
CASL
CASH
CASL
Semiconductor Group
14
22.3.99
Preliminary Data Sheet
TUA6022, TUA6024
Limit Values
Symbol
Parameter
TA = 25 °C,VVCC
Unit Test conditions
min
typ
max
Analog Unit
VHF low and VHF high Band Section (including IF amplifier)
f
= 43.25 to 463.25
RF
Voltage gain
G
20
23
26
dB
MHz, f = 33.4 to
MixV
IF
58.75 MHz
f
= 43.25 to 463.25
RF
Mixer noise figure
F
9
2
2
11
3
dB
kΩ
pF
MixV
MHz
serial equivalent cir-
cuit, f
R
1
MixV
MixV
= 100 MHz
MixV
Mixer input impedance
serial equivalent cir-
cuit, f = 100 MHz
C
3
MixV
400
500
kHz
kHz
V = 5 V±10%
S
∆T = 25 °C
Oscillator drift, PLL unlocked
Oscillator pulling, PLL unlocked
∆f
OscV
t = 5 s up to 15 min
after switching on
100
kHz
∆f = 10 kHz
100
80
108
88
dBµV
dBµV
f
= 48.25 MHz
RF
V
MIXV
∆f = 10 kHz
f
= 399.25 MHz
RF
f
f
P
= 48.25 MHz,
RF
V
V
-50
-50
dBc
dBc
= 82.25 MHz,
MIXV
MIXV
RF1
=P
= 80dBµV
RF1
RF
N + 5 pulling, PLL unlocked
f
f
= 399.25 MHz,
RF
= 437.25 MHz,
RF1
P
=P
= 80dBµV
RF
RF1
dBc/ fm = 10kHz,
Oscillator phase noise
IF suppression
L(fm)
-80
15
-86
20
VHF
Hz
application circuit
V = 80 dBµV
MixB
a
dB
IF
UHF Band Section (including IF amplifier)
f
= 367.25 MHz to
RF
863.25 MHz,
= 33.4MHz to
58.75 MHz
Voltage gain
G
31
34
37
dB
MixU
MixU
f
IF
f
= 367.25 to 615.25
RF
6
7
9
dB
dB
Ω
MHz
Mixer noise figure
F
f
= 623.25 to 863.25
RF
10
26
14
MHz
serial equivalent cir-
R
14
6
20
10
MixU
cuit, f
= 600 MHz
MixU
Mixer input impedance
Semiconductor Group
serial equivalent cir-
cuit, f = 600 MHz
L
nH
MixU
MixU
15
22.3.99
Preliminary Data Sheet
TUA6022, TUA6024
Limit Values
Symbol
Parameter
TA = 25 °C,VVCC
Unit Test conditions
min
typ
max
400
800
kHz
kHz
V = 5 V±10%
S
∆T = 25 °C
Oscillator drift, PLL unlocked
Oscillator pulling, PLL unlocked
∆f
OscU
t = 5 s up to 15 min
after switching on
100
kHz
∆f = 10 kHz
100
100
108
108
dBµV
dBµV
f
= 375.25 MHz
RF
V
MIXU
∆f = 10 kHz
f
= 847.25 MHz
RF
f
f
P
P
= 471.25 MHz,
RF
= 510.25 MHz,
=
RF1
V
-50
-50
dBc
dBc
MIXU
MIXU
RF
= 80dBµV
RF1
N + 5 pulling, PLL unlocked
Oscillator phase noise
f
f
P
P
= 847.25 MHz,
RF
= 886.25 MHz,
RF1
V
=
RF
= 80 dBµV
RF1
dBc/ fm = 10kHz,
L(fm)
-80
15
-86
20
UHF
Hz
application circuit
V = 80 dBµV
MixB
IF suppression
a
dB
IF
SAW preamplifier
R
R
IFout,
80
Ω
serial equivalent
circuit,
IFoutx
IF output impedance
L
L
IFout
f = 38.9 MHz
IF
tbf
nH
IFoutx
Rejection at the IFoutput
V
V
=
RFpix
Channel 6 beat
INT
INT
tbf
tbf
tbf
tbf
dBc
dBc
= 80 dBµV;
CH6
RFsnd
note 1
V
= 80 dBµV;
RFpix
Channel A-5 beat
CHA-5
note 2
Notes:
1.
Channel 6 beat is the interfering product of f
, f
- f
of channel 6 at 42 MHz.
RFpix RFsnd OSC
2.
Channel A-5 beat is the interfering product of f
+ f
- f
of channel A-5,f
= 45.5 MHz.
RFpix
RFsnd OSC
BEAT
The possible mechanisms are: f
- 2 x f or 2 x f
- f
. For the measurement V = 80 dBµV.
OSC
IF
RFpix OSC RF
Semiconductor Group
16
22.3.99
Preliminary Data Sheet
TUA6022, TUA6024
11 Test Circuit
11.1 DC and RF Parameter Measurement
R
= 75Ω
GEN
UHF
VHF
SDA SCL CAS
P2/P3 P1/I1 P0/I0
4MHz
18p
1:1
1:1**)
50*)
68p
L3
68p
47n
V
VCC
22p
2p2
22p
1n
28
27
26
25
24
23
22
21
20
19
18
11
17
16
13
15
14
TUA6024
1
2
3
4
5
6
7
8
9
10
12
22n
4n7
1p2 1p2
L1
1p2
1p2
2p7
2p2
L2
2p2
2p7
100p
27p
ADC
18p
BB565
100p
100p
4k7
4n7
4k7
IF
output
R
=75Ω
BB619C
LOAD
1k
47k
+33V
1n
Coils:
coil turns wire size coil diameter
*) not for noise measurement
**) 1:2 transformer for noise measurement
[mm]
0.4
[mm]
3
3
L1
L2
L3
2
4
0.4
Neosid Part-No. 00503600
0.58µH
Semiconductor Group
17
22.3.99
Preliminary Data Sheet
TUA6022, TUA6024
11.2 Measurement of Crystal Oscillator Frequency
Test mode:
T1 = HIGH
T0 = LOW
V
5V
VCC
I
VCC
5 k
f
Q
ref
f = f * reference divider ratio
Q
ref
Counter
Counter
P0
P1
18 pF
TUA6022,
TUA6024
5 k
f
= f * N
4 MHz
VCO
cy
N: divider ratio
f
cy
GND
D
Semiconductor Group
18
22.3.99
Preliminary Data Sheet
TUA6022, TUA6024
12 Application Circuit
12.1 Application Circuit (Evaluation Board)
R
= 75Ω
GEN
UHF
VHF
SDA SCL CAS
P2/P3 P1/I1 P0/I0
4MHz
18p
1:1*)
1:2**)
100p 100p
68p
L4
68p
47n
V
VCC
22p
2p2
22p
1n
4n7
4n7
4n7
4n7
28
27
26
25
24
23
22
21
20
19
18
17
16
15
TUA6024
1
2
3
4
5
6
7
8
9
10
11
12
13
14
22n
ADC
1p2 1p2
L1
1p2
1p2
2p7
L2
2p2
L3
2p2
2p7
27p
2:10***)
4n7
120p
0p5
18p
1k
BB565
82p
BA 892
4n7
4n7
4k7
1k
4n7
4k7
IF
output
R
=75Ω
BB689
LOAD
2k7
2k7
+33V
1n
Transformers:
RF-Bands:
Coils:
*) TOKO B4F Type 617DB-1023
**) TOKO B4FType 617PT-1026
***) TOKO 7KL 291GCS-1499F
48.25 MHz to 147.25 MHz
154.25 MHz to 423.25 MHz
431.25 MHz to 855.25 MHz
coil turns wire size coil diameter
[mm]
0.4
[mm]
2
L1
L2
L3
1.5
2.5
8.5
0.5
0.5
2.5
3
L4 14.5
0.3
4
Semiconductor Group
19
22.3.99
Preliminary Data Sheet
TUA6022, TUA6024
13 Electrical Diagrams
13.1 Input admittance VHF mixer input Y = 20mS (single ended)
0
0
tbd
13.2 Input impedance UHF mixer input Z = 50 Ω (symmetrical)
0
0
tbd
Semiconductor Group
20
22.3.99
Preliminary Data Sheet
TUA6022, TUA6024
13.3 Output impedance IF output Y = 20mS (symmetrical)
0
0
tbd
Semiconductor Group
21
22.3.99
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