ICS87973DYILFT [IDT]
PLL Based Clock Driver, 13 True Output(s), 0 Inverted Output(s), PQFP52, 10 X 10 MM, 1.40 MM HEIGHT, MS-026, LQFP-52;
| 型号： | ICS87973DYILFT |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | PLL Based Clock Driver, 13 True Output(s), 0 Inverted Output(s), PQFP52, 10 X 10 MM, 1.40 MM HEIGHT, MS-026, LQFP-52 驱动 逻辑集成电路 |
| 文件： | 总17页 (文件大小：249K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS87973I
LOW SKEW, 1-TO-12
LVCMOS / LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
GENERAL DESCRIPTION
FEATURES
The ICS87973I is a LVCMOS/LVTTL clock generator .
The ICS87973I has three selectable inputs and provides
fourteen LVCMOS/LVTTL outputs.
• Fully integrated PLL
• Fourteen LVCMOS/LVTTL outputs; twelve clock outputs,
one feedback, one sync
The ICS87973I is a highly flexible device. The three selectable
inputs (1 differential and 2 single ended inputs) are often used
in systems requiring redundant clock sources. Up to three
different output frequencies can be generated among the
three output banks.
• Selectable LVCMOS/LVTTL or differential CLK, nCLK inputs
• CLK0, CLK1 can accept the following input levels:
LVCMOS or LVTTL
• CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
The three output banks and feedback output each have their
own output dividers which allows the device to generate a
multitude of different bank frequency ratios and output-to-input
frequency ratios. In addition, 2 outputs in Bank C (QC2, QC3)
can be selected to be inverting or non-inverting. The output
frequency range is 8.33MHz to125MHz. The input frequency
range is 5MHz to 120MHz.
• Output frequency range: 8.33MHz to 125MHz
• VCO range: 200MHz to 480MHz
• Output skew: 550ps (maximum)
• Cycle-to-cycle jitter: 100ps (typical)
• Full 3.3V supply voltage
The ICS87973I also has a QSYNC output which can by used
for system synchronization purposes. It monitors Bank A and
Bank C outputs and goes low one period prior to coincident
rising edges of Bank A and Bank C clocks. QSYNC then goes
high again when the coincident rising edges of Bank A and
Bank C occur. This feature is used primarily in applications where
Bank A and Bank C are running at different frequencies, and is
particularly useful when they are running at non-integer
multiples of one another.
• -40°C to 85°C ambient operating temperature
• Available in both standard and lead-free RoHS compliant
packages
• Compatible with PowerPC™ and Pentium™ Microprocessors
PIN ASSIGNMENT
Example Applications:
39 38 37 36 35 34 33 32 31 30 29 28 27
1. System Clock generator: Use a 16.66MHz reference
clock to generate eight 33.33MHz copies for PCI and
four 100MHz copies for the CPU or PCI-X.
FSEL_B1
FSEL_B0
FSEL_A1
FSEL_A0
QA3
40
41
42
43
44
45
46
47
48
49
50
51
52
26
25
24
23
22
21
20
19
18
17
16
15
14
FSEL_FB1
QSYNC
GNDO
QC0
2. Line Card Multiplier: Multiply differential 62.5MHz from
a back plane to single-ended 125MHz for the line Card
ASICs and Gigabit Ethernet Serdes.
VDDO
VDDO
QC1
3. Zero Delay buffer for Synchronous memory: Fan out
up to twelve 100MHz copies from a memory controller
reference clock to the memory chips on a memory module
with zero delay.
QA2
FSEL_C0
FSEL_C1
QC2
ICS87973I
GNDO
QA1
VDDO
VDDO
QA0
QC3
GNDO
VCO_SEL
GNDO
INV_CLK
1
2
3
4
5
6
7
8
9 10 11 12 13
52-Lead LQFP
10mm x 10mm x 1.4mm package body
Y package
Top View
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ICS87973I
LOW SKEW, 1-TO-12
LVCMOS / LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
BLOCK DIAGRAM
VCO_SEL
PLL_SEL
REF_SEL
CLK
1
nCLK
SYNC
FRZ
D
Q
QA0
QA1
QA2
QA3
0
CLK0
0
0
1
SYNC
FRZ
PHASE
DETECTOR
CLK1
1
VCO
SYNC
FRZ
LPF
CLK_SEL
EXT_FB
SYNC
FRZ
SYNC
FRZ
D
Q
QB0
QB1
QB2
QB3
SYNC
FRZ
SYNC
FRZ
SYNC
FRZ
FSEL_FB2
nMR/OE
D
D
D
Q
Q
Q
QC0
QC1
QC2
QC3
QFB
POWER-ON
RESET
SYNC
FRZ
÷4, ÷6, ÷8, ÷12
÷4, ÷6, ÷8, ÷10
÷2, ÷4, ÷6, ÷8
SYNC
FRZ
SYNC
FRZ
2
2
2
3
0
1
÷4, ÷6, ÷8, ÷10
SYNC PULSE
FSEL_A0:1
÷2
FSEL_B0:1
FSEL_C0:1
FSEL_FB0:2
SYNC
SYNC
FRZ
FRZ
D
Q
QSYNC
DATA GENERATOR
FRZ_CLK
OUTPUT DISABLE
CIRCUITRY
12
FRZ_DATA
INV_CLK
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ICS87973I
LOW SKEW, 1-TO-12
LVCMOS / LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
SIMPLIFIED BLOCK DIAGRAM
nMR/OE
FSEL_A[0:1]
2
CLK
1
0
nCLK
CLK0
FSEL_
A1 A0
SYNC
FRZ
QA0
QA1
QA2
QA3
0
1
QAx
÷4
÷6
÷8
PLL
0
0
1
1
0
1
0
1
CLK1
SYNC
FRZ
VCO RANGE
200MHz - 480MHz
SYNC
FRZ
CLK_SEL
REF_SEL
0
1
÷12
SYNC
FRZ
÷2
÷1
0
1
EXT_FB
FSEL_B[0:1]
2
SYNC
FRZ
FSEL_
QB0
QB1
QB2
QB3
B1 B0
QBx
÷4
÷6
÷8
0
0
1
1
0
1
0
1
SYNC
FRZ
VCO_SEL
PLL_SEL
SYNC
FRZ
÷10
SYNC
FRZ
FSEL_C[0:1]
2
FSEL_
QC0
QC1
QC2
QC3
C1 C0 QCx
0
0
1
1
0
1
0
1
÷2
÷4
÷6
÷8
SYNC
FRZ
SYNC
FRZ
0
1
SYNC
FRZ
INV_CLK
FSEL_FB[0:2]
3
FSEL_
FB2 FB1 FB0 QFB
QFB
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
÷4
÷6
÷8
÷10
÷8
÷12
÷16
÷20
O
UTPUT
D
ISABLE
FRZ_CLK
FRZ_DATA
SYNC
FRZ
QSYNC
CIRCUITRY
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ICS87973I
LOW SKEW, 1-TO-12
LVCMOS / LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1
GNDI
Power
Input
Power supply ground.
Master reset and output enable. When HIGH, enables the outputs. When
LOW, resets the outputs to tristate and resets output divide circuitry.
Enables and disables all outputs. LVCMOS / LVTTL interface levels.
2
nMR/OE
Pullup
3
4
FRZ_CLK
Input
Input
Pullup
Pullup
Clock input for freeze circuitry. LVCMOS / LVTTL interface levels.
Configuration data input for freeze circuitry.
LVCMOS / LVTTL interface levels.
FRZ_DATA
FSEL_FB2,
FSEL_FB1, Input
FSEL_FB0
Select pins control Feedback Divide value.
LVCMOS / LVTTL interface levels.
5, 26, 27
Pullup
Pullup
Pullup
Pullup
Selects between the PLL and reference clocks as the input to the output
dividers. When HIGH, selects PLL. When LOW, bypasses the PLL.
LVCMOS / LVTTL interface levels.
Selects between CLK0 or CLK1 and CLK, nCLK inputs.
When HIGH, selects CLK, nCLK. When LOW, selects CLK0 or CLK1.
LVCMOS / LVTTL interface levels.
Clock select input. Selects between CLK0 and CLK1 as phase detector
reference. When LOW, selects CLK0. When HIGH, selects CLK1.
LVCMOS / LVTTL interface levels.
6
7
8
PLL_SEL
REF_SEL
CLK_SEL
Input
Input
Input
9, 10
11
CLK0,CLK1 Input
Pullup Reference clock inputs. LVCMOS / LVTTL interface levels.
CLK
nCLK
Input
Input
Power
Input
Pullup
Non-inverting differential clock input.
Inverting differential clock input. VDD/2 default when left floating.
Analog supply pin.
Pullup/
Pulldown
12
13
14
VDDA
Inverted clock select for QC2 and QC3 outputs.
LVCMOS / LVTTL interface levels.
INV_CLK
Pullup
15, 24, 30,
35, 39, 47, 51
16, 18,
21, 23
17, 22, 33,
37, 45, 49
GNDO
Power
Output
Power
Input
Power supply ground.
QC3, QC2,
QC1, QC0
Bank C clock outputs. 7Ω typical output impedance.
LVCMOS / LVTTL interface levels.
VDDO
Output supply pins.
FSEL_C1,
FSEL_C0
19, 20
25
Pullup
Pullup
Select pins for Bank C outputs. LVCMOS / LVTTL interface levels.
Synchronization output for Bank A and Bank C. Refer to Figure 1,
Timing Diagrams. LVCMOS / LVTTL interface levels.
QSYNC
Output
28
29
31
VDD
QFB
Power
Output
Input
Core supply pins.
Feedback clock output. LVCMOS / LVTTL interface levels.
Extended feedback. LVCMOS / LVTTL interface levels.
EXT_FB
32, 34,
36, 38
QB3, QB2,
QB1, QB0
FSEL_B1,
FSEL_B0
FSEL_A1,
FSEL_A0
QA3, QA2,
QA1, QA0
Bank B clock outputs.7Ω typical output impedance.
Output
Input
LVCMOS / LVTTL interface levels.
40, 41
42, 43
Pullup
Pullup
Select pins for Bank B outputs. LVCMOS / LVTTL interface levels.
Select pins for Bank A outputs. LVCMOS / LVTTL interface levels.
Input
44, 46,
48, 50
Bank A clock outputs.7Ω typical output impedance.
LVCMOS / LVTTL interface levels.
Selects VCO. When HIGH, selects VCO ÷ 1.
When LOW, selects VCO ÷ 2. LVCMOS / LVTTL interface levels.
Output
Input
52
VCO_SEL
Pullup
NOTE: Pullup and Pulldown refer to internal input resistors. See table 2, Pin Characteristics, for typical values.
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ICS87973I
LOW SKEW, 1-TO-12
LVCMOS / LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
CIN
Input Capacitance
4
pF
RPULLUP
RPULLDOWN
/
Input Pullup/Pulldown Resistor
51
kΩ
Power Dissipation Capacitance
(per output)
CPD
VDD, VDDA, VDDO = 3.465V
18
12
pF
ROUT
Output Impedance
5
7
Ω
TABLE 3A. OUTPUT BANK CONFIGURATION SELECT FUNCTION TABLE
Inputs
Outputs
QA
Inputs
Outputs
QB
Inputs
Outputs
QC
÷2
FSEL_A1 FSEL_A0
FSEL_B1
FSEL_B0
FSEL_C1
FSEL_C0
0
0
1
1
0
1
0
1
÷4
0
0
1
1
0
1
0
1
÷4
0
0
1
1
0
1
0
1
÷6
÷6
÷4
÷8
÷8
÷6
÷12
÷10
÷8
TABLE 3B. FEEDBACK CONFIGURATION SELECT FUNCTION TABLE
Inputs
Outputs
FSEL_FB2
FSEL_FB1
FSEL_FB0
QFB
÷4
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
÷6
÷8
÷10
÷8
÷12
÷16
÷20
TABLE 3C. CONTROL INPUT SELECT FUNCTION TABLE
Control Pin
VCO_SEL
REF_SEL
CLK_SEL
PLL_SEL
nMR/OE
Logic 0
VCO/2
Logic 1
VCO
CLK0 or CLK1
CLK0
CLK, nCLK
CLK1
BYPASS PLL
Enable PLL
Enable Outputs
Inverted QC2, QC3
Master Reset/Output Hi Z
Non-Inverted QC2, QC3
INV_CLK
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ICS87973I
LOW SKEW, 1-TO-12
LVCMOS / LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
fVCO
1:1 MODE
2:1 MODE
3:1 MODE
3:2 MODE
4:1 MODE
4:3 MODE
6:1 MODE
QA
QC
QSYNC
QA
QC
QSYNC
QC(÷2)
QA(÷4)
QSYNC
QC(÷2)
QA(÷8)
QSYNC
QC(÷2)
QA(÷8)
QSYNC
QA(÷6)
QC(÷8)
QSYNC
QA(÷12)
QC(÷2)
QSYNC
FIGURE 1. TIMING DIAGRAMS
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ICS87973I
LOW SKEW, 1-TO-12
LVCMOS / LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
Inputs, VI
-0.5V to VDD + 0.5 V
-0.5V to VDDO + 0.5V
Outputs, VO
Package Thermal Impedance, θJA 42.3°C/W (0 lfpm)
Storage Temperature, TSTG -65°C to 150°C
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VDD
VDDA
VDDO
IDD
Core Supply Voltage
3.135
2.935
3.135
3.3
3.3
3.3
3.465
3.465
3.465
225
V
V
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
V
All power pins
mA
mA
IDDA
20
NOTE: Special thermal handling may be required in some configurations.
TABLE 4B. DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VIH
VIL
Input High Voltage
2
3.6
0.8
120
V
V
Input Low Voltage
IIN
Input Current
µA
V
VOH
VOL
VPP
VCMR
Output High Voltage
IOH = -20mA
IOL = 20mA
CLK, nCLK
CLK, nCLK
2.4
Output Low Voltage
0.5
1
V
Peak-to-Peak Input Voltage; NOTE 1, 2
Common Mode Input Voltage; NOTE 1, 2
0.3
V
VDD - 2V
VDD - 0.6V
V
NOTE 1: Common mode voltage is defined as VIH.
NOTE 2. For single ended applications, the maximum input voltage for CLK and nCLK is VDD + 0.3V.
TABLE 5. INPUT FREQUENCY CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
fIN Input Frequency
Test Conditions
Minimum Typical Maximum Units
CLK0, CLK1,
CLK, nCLK; NOTE 1
120
MHz
FRZ_CLK
20
MHz
NOTE 1: Input frequency depends on the feedback divide ratio to ensure "clock * Feedback Divide" is in the VCO range of
200MHz to 480MHz.
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ICS87973I
LOW SKEW, 1-TO-12
LVCMOS / LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
TABLE 6. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
125
Units
MHz
MHz
MHz
÷2
÷4
÷6
÷8
120
fMAX
Output Frequency
80
60
MHz
ps
CLK0
-70
-130
-225
130
70
330
270
175
550
QFB ÷8
In Frequency = 50MHz
Static Phase Offset;
NOTE 1
t(Ø)
CLK1
ps
CLK, nCLK
-25
ps
tsk(o)
tjit(cc)
fVCO
Output Skew; NOTE 2
ps
Cycle-to-Cycle Jitter; NOTE 3, 4
PLL VCO Lock Range
100
ps
200
480
10
MHz
mS
ns
tLOCK
tR / tF
tPW
PLL Lock Time; NOTE 3
Output Rise/Fall Time; NOTE 3
Output Pulse Width
0.8V to 2V
0.15
1.2
tPERIOD/2 - 750 tPERIOD/2 500 tPERIOD/2 + 750
ps
tPZL, tPZH Output Enable Time; NOTE 3
tPLZ, tPHZ Output Disable TIme; NOTE 3
2
2
10
8
ns
ns
NOTE 1: Defined as the time difference between the input reference clock and the average feedback input signal
when the PLL is locked and the input reference frequency is stable.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at VDDO/2.
NOTE 3: These parameters are guaranteed by characterization. Not tested in production.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
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ICS87973I
LOW SKEW, 1-TO-12
LVCMOS / LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
PARAMETER MEASUREMENT INFORMATION
1.65V 5ꢀ
VDD
SCOPE
VDD
,
V
DDA, VDDO
nCLK
Qx
VPP
VCMR
Cross Points
LVCMOS
CLK
GND
GND
-1.65V 5ꢀ
DIFFERENTIAL INPUT LEVEL
3.3V OUTPUT LOAD AC TEST CIRCUIT
VDDO
VDDO
VDDO
2
VDDO
2
Qx
2
2
QA0:QA3,
QB0:QB3,
QC0:QC3,
QSYNC,
QFB
➤
➤
tcycle n
tcycle n+1
➤
➤
VDDO
Qy
2
tjit(cc) = tcycle n –tcycle n+1
1000 Cycles
tsk(o)
OUTPUT SKEW
CYCLE-TO-CYCLE JITTER
nCLK
VDD
2
CLK0,
CLK1
CLK
VDD
2
VDD
2
EXT_FB
EXT_FB
➤
➤
t(Ø)
➤
➤
t(Ø)
t(Ø) mean = Static Phase Offset
t(Ø) mean = Static Phase Offset
(where t(Ø) is any random sample, and t(Ø) mean is the average
of the sampled cycles measured on controlled edges)
(where t(Ø) is any random sample, and t(Ø) mean is the average
of the sampled cycles measured on controlled edges)
STATIC PHASE OFFSET (LVCMOS)
STATIC PHASE OFFSET (DIFFERENTIAL)
VDDO
2
VDDO
2
VDDO
2
2.4V
tF
2.4V
tR
QA0:QA3,
QB0:QB3,
QC0:QC3,
QSYNC,
QFB
tPW
0.5V
0.5V
Clock
tPERIOD
Outputs
tPW
tPERIOD
odc =
OUTPUT RISE/FALL TIME
tPW & tPeriod
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ICS87973I
LOW SKEW, 1-TO-12
LVCMOS / LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
APPLICATION INFORMATION
USING THE OUTPUT FREEZE CIRCUITRY
OVERVIEW
To enable low power states within a system, each output of FRZ_CLK signal. To place an output in the freeze state, a logic
ICS87973I (Except QC0 and QFB) can be individually frozen “0” must be written to the respective freeze enable bit in the shift
(stopped in the logic “0” state) using a simple serial interface register. To unfreeze an output, a logic “1” must be written to the
to a 12 bit shift register. A serial interface was chosen to elimi- respective freeze enable bit. Outputs will not become enabled/
nate the need for each output to have its own Output Enable disabled until all 12 data bits are shifted into the shift register.
pin, which would dramatically increase pin count and package When all 12 data bits are shifted in the register, the next rising
cost. Common sources in a system that can be used to drive edge of FRZ_CLK will enable or disable the outputs. If the bit
the ICS87973I serial interface are FPGA’s and ASICs.
that is following the 12th bit in the register is a logic “0”, it is used
for the start bit of the next cycle; otherwise, the device will wait
and won’t start the next cycle until it sees a logic “0” bit. Freez-
PROTOCOL
The Serial interface consists of two pins, FRZ_Data (Freeze ing and unfreezing of the output clock is synchronous (see the
Data) and FRZ_CLK (Freeze Clock). Each of the outputs which timing diagram below). When going into a frozen state, the out-
can be frozen has its own freeze enable bit in the 12 bit shift put clock will go LOW at the time it would normally go LOW, and
register. The sequence is started by supplying a logic “0” start the freeze logic will keep the output low until unfrozen. Likewise,
bit followed by 12NRZ freeze enable bits. The period of each when coming out of the frozen state, the output will go HIGH
FRZ_DATA bit equals the period of the FRZ_CLK signal. The only when it would normally go HIGH. This logic, therefore, pre-
FRZ_DATA serial transmission should be timed so the ICS87973I vents runt pulses when going into and out of the frozen state.
can sample each FRZ_DATA bit with the rising edge of the
FRZ_DATA
QA0 QA1 QA2 QA3 QB0 QB1 QB2 QB3 QC1 QC2 QC3 QSYNC
FRZ_CLK
FIGURE 2A. FREEZE DATA INPUT PROTOCOL
Qx FREEZE Internal
Qx Internal
Qx Out
FIGURE 2B. OUTPUT DISABLE TIMING
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ICS87973I
LOW SKEW, 1-TO-12
LVCMOS / LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS87973I
providesseparate power supplies to isolate any high switch-
ing noise from the outputs to the internal PLL. VDD, VDDA, and
VDDO should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 3 illustrates how
a 10Ω resistor along with a 10μF and a .01μF bypass
capacitor should be connected to each VDDA pin. The 10Ω
resistor can also be replaced by a ferrite bead.
3.3V
VDD
.01μF
.01μF
10Ω
VDDA
10 μF
FIGURE 3. POWER SUPPLY FILTERING
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 4 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = VDD/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
VDD
R1
1K
Single Ended Clock Input
V_REF
CLK
nCLK
C1
0.1u
R2
1K
FIGURE 4. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
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ICS87973I
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LVCMOS / LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL examples only. Please consult with the vendor of the driver
and other differential signals. Both VSWING and VOH must meet component to confirm the driver termination requirements. For
the VPP and VCMR input requirements. Figures 5A to 5D show example in Figure 5A, the input termination applies for LVHSTL
interface examples for the CLK/nCLK input driven by the most drivers. If you are using an LVHSTL driver from another
common driver types. The input interfaces suggested here are vendor, use their termination recommendation.
3.3V
3.3V
3.3V
1.8V
Zo = 50 Ohm
CLK
Zo = 50 Ohm
CLK
Zo = 50 Ohm
nCLK
Zo = 50 Ohm
HiPerClockS
Input
LVPECL
nCLK
HiPerClockS
Input
LVHSTL
R1
50
R2
50
ICS
HiPerClockS
R1
50
R2
50
LVHSTL Driver
R3
50
FIGURE 5A. CLK/NCLK INPUT DRIVEN BY
LVHSTL DRIVER
FIGURE 5B. CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
3.3V
3.3V
3.3V
3.3V
Zo = 50 Ohm
3.3V
R3
125
R4
125
LVDS_Driver
Zo = 50 Ohm
Zo = 50 Ohm
CLK
CLK
R1
100
nCLK
Receiv er
nCLK
HiPerClockS
Input
Zo = 50 Ohm
LVPECL
R1
84
R2
84
FIGURE 5C. CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 5D. CLK/NCLK INPUT DRIVEN BY
3.3V LVDS DRIVER
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
CLK INPUT:
OUTPUTS:
LVCMOS OUTPUT:
For applications not requiring the use of a clock input, it can All unused LVCMOS output can be left floating. There should
be left floating. Though not required, but for additional be no trace attached.
protection, a 1kΩ resistor can be tied from the CLK input to
ground.
CLK/nCLK INPUT:
For applications not requiring the use of the differential input,
both CLK and nCLK can be left floating. Though not required,
but for additional protection, a 1kΩ resistor can be tied from
CLK to ground.
LVCMOS CONTROL PINS:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
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LVCMOS / LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
RELIABILITY INFORMATION
TABLE 7. θJAVS. AIR FLOW TABLE
θJA by Velocity (Linear Feet per Minute)
0
200
47.1°C/W
36.4°C/W
500
42.0°C/W
34.0°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
58.0°C/W
42.3°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS87973I is: 8364
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ICS87973I
LOW SKEW, 1-TO-12
LVCMOS / LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
PACKAGE OUTLINE - Y SUFFIX FOR 52 LEAD LQFP
TABLE 8. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BCC
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
N
A
52
--
--
1.60
0.15
1.45
0.38
0.20
A1
A2
b
0.05
1.35
0.22
0.09
--
1.40
0.32
c
--
D
12.00 BASIC
10.00 BASIC
12.00 BASIC
10.00 BASIC
0.65 BASIC
--
D1
E
E1
e
L
0.45
0.75
θ
--
0
°
7°
ccc
--
--
0.08
Reference Document: JEDEC Publication 95, MS-026
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ICS87973I
LOW SKEW, 1-TO-12
LVCMOS / LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
TABLE 9. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging Temperature
87973DYI
87973DYIT
ICS87973DYI
ICS87973DYI
52 Lead LQFP
tray
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
52 Lead LQFP
500 tape & reel
tray
87973DYILF
87973DYILFT
ICS87973DYILF
ICS87973DYILF
52 Lead "Lead-Free" LQFP
52 Lead "Lead-Free" LQFP
500 tape & reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Inc. (IDT) assumes no responsibility for either its use or for infringement of
any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial
applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves
the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
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LVCMOS / LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
REVISION HISTORY SHEET
Rev
A
Table
Page
Description of Change
Date
9/9/02
T1
4
2
Pin Description Table - added pins 20 and 21.
A
Block Diagram - added missing dividers to the Data Generator.
10/18/02
DC Characteristics table - updated VCMR values from GND + 1.5V min.,
B
B
B
T4B
7
10/23/02
11/18/02
12/10/02
VDD max. to VDD - 2V min., VDD - 0.6V max.
T1
T8
4
Pin Description Table - corrected CLK Type to read Pullup from Pulldown.
12
Revised Package Drawing. Corrected Package Dimensions table to
correspond with the Package Drawing.
1
Added LVTTL to title.
12
5
Corrected Package Outline to correspond with the Package Dimensions table.
Pin Characteristics - changed the CPD limit from 25pF typical to 18pf max.
Power Supply Table - changed the IDD limit from 215mA max. to 225mA max.
T2
T4A
7
Application Information:
C
3/21/03
11
Added sections, "Power Supply Filtering Techniques" and
"Wiring the Differential Level..."
12
5
Added "Differential Clock Input Interface" section.
Pin Characteristics - changed CIN from 4pF max. to 4pF typical.
T2
C
D
D
5/7/03
6/27/03
7/9/03
10
7
Corrected Freeze Data labeling on Figure 2A.
T4A
Power Supply Table - changed VDDA minimum from 3.135V to 2.935V.
T1
T2
4
5
Pin Characteristics Table - added Pullup/Pulldown to pin 12, nCLK.
Pin Characteristics Table - added to ROUT 5Ω min. and 12Ω max.
1
Features section - added lead-free bullet.
D
D
12
15
Added Recommendations for Unused Input and Output Pins.
Ordering Information Table - added lead-free part number, marking and note.
Updated datasheet's header/footer with IDT from ICS.
Removed ICS"prefix from Part/Order Number column.
Added Contact Page.
5/19/06
8/11/10
T9
T9
15
17
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LOW SKEW, 1-TO-12
LVCMOS / LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
We’ve Got Your Timing Solution.
6024 Silver Creek Valley Road
San Jose, CA 95138
Sales
Tech Support
netcom@idt.com
800-345-7015 (inside USA)
+408-284-8200 (outside USA)
Fax: 408-284-2775
© 2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc.
Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of
their respective owners.
Printed in USA
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