ICS87974AYI [IDT]
PLL Based Clock Driver, 14 True Output(s), 0 Inverted Output(s), CMOS, PQFP52, 10 X 10 MM, 1.40 MM HEIGHT, MS-026, LQFP-52;
| 型号： | ICS87974AYI |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | PLL Based Clock Driver, 14 True Output(s), 0 Inverted Output(s), CMOS, PQFP52, 10 X 10 MM, 1.40 MM HEIGHT, MS-026, LQFP-52 驱动 逻辑集成电路 |
| 文件： | 总14页 (文件大小：169K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS87974I
LOW SKEW, 1-TO-15,
LVCMOS/LVTTLCLOCK GENERATOR
Integrated
Circuit
Systems, Incꢀ
GENERAL DESCRIPTION
FEATURES
• Fully integrated PLL
The ICS87974I is a low skew, low jitter 1-to-15
LVCMOS/LVTTL Clock Generator/Zero Delay
Buffer and is a member of the HiPerClockS family
of high performance clock solutions from ICS. The
device has a fully integrated PLL and three banks
HiPerClockS™
• 15 single ended 3.3V LVCMOS/LVTTLoutputs
• 2 LVCMOS/LVTTL clock inputs for redundant clock applications
• CLK0 and CLK1 accepts the following input levels:
LVCMOS/LVTTL
whose divider ratios can be independently controlled, providing
output frequency relationships of 1:1, 2:1, 3:1, 3:2, 3:2:1. In ad-
dition, the external feedback connection provides for a wide
selection of output-to-input frequency ratios. The CLK0 and CLK1
pins allow for redundant clocking on the input and dynamically
switching the PLL between two clock sources. The ICS87974I
is pin for pin compatible with the MPC974.
• Output frequency range: 8.33MHz to 125MHz
• VCO range: 200MHz to 500MHz
• External feedback for ”zero delay” clock regeneration
• Cycle-to-cycle jitter: ±100ps (typical)
• Output skew: 350ps (maximum)
Guaranteed low jitter and output skew characteristics make the
ICS87974I ideal for those applications demanding well defined
performance and repeatability.
• 3.3V operating supply
• -40°C to 85°C ambient operating temperature
• Pin compatible with the MPC974
PIN ASSIGNMENT
52 51 50 49 48 47 46 45 44 43 42 41 40
GND
nMR/OE
CLK_EN
SEL_B
SEL_C
PLL_SEL
SEL_A
CLK_SEL
CLK0
1
GND
QB1
39
38
37
36
35
34
33
32
31
30
29
28
27
2
3
VDDOB
QB2
4
5
GND
QB3
6
7
VDDOB
QB4
ICS87974I
8
9
FB_IN
GND
QFB
CLK1
10
11
12
13
nc
VDD
VDDOFB
nc
VDDA
14 15 16 17 18 19 20 21 22 23 24 25 26
52-Lead LQFP
10mm x 10mm x 1.4mm package body
Y package
Top View
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REV. B MAY 15, 2003
1
ICS87974I
LOW SKEW, 1-TO-15,
LVCMOS/LVTTLCLOCK GENERATOR
Integrated
Circuit
Systems, Incꢀ
BLOCK DIAGRAM
(Internal Pulldown)
SELA
(Internal Pulldown)
CLK_SEL
CLK0
0
÷2
÷4
(Internal Pulldown) 0
0
1
0
1
÷2
÷4
÷6
5
QA0:QA4
D
Q
(Internal Pullup)
CLK1
1
PLL
1
(Internal Pullup)
FB_IN
0
1
(Internal Pullup)
PLL_SEL
VCO_SEL
5
4
(Internal Pulldown)
QB0:QB4
QC0:QC3
D
D
Q
Q
(Internal Pulldown)
SELB
SELC
0
1
(Internal Pulldown)
0
1
0
1
(Internal Pullup)
QFB
nMR/OE
FB_SEL0
FB_SEL1
D
Q
(Internal Pulldown)
÷2
(Internal Pulldown)
(Internal Pullup)
CLK_EN
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2
ICS87974I
LOW SKEW, 1-TO-15,
LVCMOS/LVTTLCLOCK GENERATOR
Integrated
Circuit
Systems, Incꢀ
SIMPLIFIED BLOCK DIAGRAM
CLK_EN
SEL_A
VCO_SEL
÷2
÷4
0
SEL_A
CLK_SEL
0
1
0
1
÷2
÷4
D
D
D
Q
Q
Q
5
5
CLK0
0
QA0:QA4
QB0:QB4
1
PLL
CLK1
1
SEL_B
FB_IN
0
1
÷2
÷4
PLL_SEL
SEL_B
SEL_C
0
1
÷4
÷6
4
QC0:QC3
SEL_C
FB_1 FB_0
0
0
1
1
0
1
0
÷4
÷6
÷8
Q
D
1 ÷12
QFB
2
FB_SEL(0:1)
nMR/OE
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REV. B MAY 15, 2003
3
ICS87974I
LOW SKEW, 1-TO-15,
LVCMOS/LVTTLCLOCK GENERATOR
Integrated
Circuit
Systems, Incꢀ
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1, 15, 19,
24, 30, 35, 39,
43, 47, 51
GND
Power
Input
Input
Power supply ground.
Active High Master Reset. Active LOW output enable. When logic
HIGH, the internal dividers are reset and the outputs are tri-
stated (HiZ). When logic LOW, the internal dividers and dividers
and the outputs are enabled. LVCMOS / LVTTL interface levels.
Synchronizing clock enable. When HIGH, clock outputs QAx:QCx
are enabled. When LOW, clock outputs QAx:QCx are low.
LVCMOS / LVTTL interface levels.
2
3
nMR/OE
CLK_EN
Pullup
Pullup
Selects divide value for Bank B output as described in Table 3D.
LVCMOS / LVTTL interface levels.
Selects divide value for Bank C output as described in Table 3D.
LVCMOS / LVTTL interface levels.
4
5
SEL_B
SEL_C
Input
Input
Pulldown
Pulldown
Selects between the PLL and the reference clock as the input to
the dividers. When HIGH, selects PLL. When LOW, selects the
reference clock. LVCMOS / LVTTL interface levels.
Selects divide value for Bank A output as described in Table 3D.
LVCMOS / LVTTL interface levels.
6
PLL_SEL
Input
Pullup
7
8
SEL_A
Input
Input
Pulldown
Pulldown
Clock select input. When HIGH, selects CLK1. When LOW,
selects CLK0. LVCMOS / LVTTL interface levels.
CLK_SEL
9
10
CLK0
CLK1
nc
Input
Input
Pulldown Reference clock input. LVCMOS / LVTTL interface levels.
Pullup Reference clock input. LVCMOS / LVTTL interface levels.
11, 27, 42
12
Unused
Power
Power
No connect.
VDD
Core supply pin.
Analog supply pin.
13
VDDA
FB_SEL0,
FB_SEL1
Selects divide value for Bank feedback output as described in
Pulldown
14, 20
Input
Table 3E. LVCMOS / LVTTL interface levels.
16, 18,
21, 23, 25
QA4, QA3,
QA2, QA1, QA0
Bank A clock outputs. 7Ω typical output impedance.
LVCMOS / LVTTL interface levels.
Output
17, 22, 26
VDDOA
VDDOFB
QFB
Power
Power
Output
Output supply pins for Bank A clock outputs.
Output supply pin for QFB clock output.
28
29
Clock output. LVCMOS / LVTTL interface levels.
Feedback input to phase detector for generating clocks with
31
FB_IN
Input
Pullup
"zero delay". Connect to pin 29. LVCMOS / LVTTL interface
levels.
32, 34,
36, 38, 40
QB4, QB3,
QB2, QB1, QB0
Bank B clock outputs. 7Ω typical output impedance.
LVCMOS / LVTTL interface levels.
Output
Power
Output
Power
Input
33, 37, 41
VDDOB
Output supply pins for Bank B clock outputs.
44, 46,
48, 50
QC3, QC2,
QC1, QC0
Bank C clock outputs. 7Ω typical output impedance.
LVCMOS / LVTTL interface levels.
45, 49
VDDOC
Output supply pins for Bank C clock outputs.
Selects VCO ÷ 4 when HIGH. Selects VCO ÷ 2 when LOW.
LVCMOS / LVTTL interface levels.
52
VCO_SEL
Pulldown
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
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ICS87974I
LOW SKEW, 1-TO-15,
LVCMOS/LVTTLCLOCK GENERATOR
Integrated
Circuit
Systems, Incꢀ
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
CIN
Input Capacitance
4
pF
KΩ
KΩ
RPULLUP
Input Pullup Resistor
51
51
RPULLDOWN Input Pulldown Resistor
Power Dissipation Capacitance
(per output); Note 1
CPD
VDD, VDDA, VDDOx = 3.465V
15
pF
NOTE 1: VDDOx denotes VDDOA, VDDOB, VDDOC, VDDOFB
.
TABLE 3A. OUTPUT CONTROL PIN FUNCTION TABLE
Inputs
Outputs
nMR/OE
CLK_EN
QA0:QA4
HiZ
QB0:QB4
HiZ
QC0:QC3
HiZ
QFB
0
1
1
X
0
1
HiZ
LOW
LOW
LOW
Enable
Enable
Enable
Enable
Enable
TABLE 3B. OPERATING MODE FUNCTION TABLE
Inputs
TABLE 3C. PLL INPUT FUNCTION TABLE
Inputs
Operating Mode
PLL_SEL
CLK_SEL
PLL Input
CLK0
0
1
Bypass
PLL
0
1
CLK1
TABLE 3D. SELECT PIN FUNCTION TABLE
SEL_A
QAx
÷ 2
SEL_B
QBx
÷ 2
SEL_C
QCx
÷ 4
0
1
0
1
0
1
÷ 4
÷ 4
÷ 6
TABLE 3E. FB SELECT FUNCTION TABLE
Inputs
TABLE 3F. VCO SELECT FUNCTION TABLE
Inputs
Outputs
VCO_SEL
fVCO
VCO/2
VCO/4
FB_SEL1
FB_SEL0
QFB
÷ 4
0
1
0
0
1
1
0
1
0
1
÷ 6
÷ 8
÷ 12
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ICS87974I
LOW SKEW, 1-TO-15,
LVCMOS/LVTTLCLOCK GENERATOR
Integrated
Circuit
Systems, Incꢀ
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
DD
Inputs, V
-0.5V to VDD + 0.5 V
-0.5V to VDDO + 0.5V
I
Outputs, VO
Package Thermal Impedance, θJA 73.2°C/W (0 lfpm)
StorageTemperature, T -65°C to 150°C
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDOX = 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum Units
VDD
VDDA
VDDOx
IDD
Core Supply Voltage
3.465
3.465
3.465
118
V
V
Analog Supply Voltage
3.135
3.3
Output Supply Voltage; NOTE 1
Power Supply Current
3.135
3.3
V
mA
mA
mA
IDDA
Analog Supply Current
15
IDDOx
Output Supply Current; NOTE 2
22
NOTE 1: VDDOx denotes VDDOA, VDDOB, VDDOC, VDDOFB
NOTE 2: IDDOx denotes IDDOA, IDDOB, IDDOC, IDDOFB
.
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = VDDOX = 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
SEL_A:SEL_C, nMR/OE,
VCO_SEL, PLL_SEL,
CLK_SEL, CLK_EN,
2
2
VDD
VDD
0.8
V
V
V
Input
VIH
High Voltage
FB_SEL0, FB_SEL1, FB_IN
CLK0, CLK1
SEL_A:SEL_C, nMR/OE,
VCO_SEL, PLL_SEL,
CLK_SEL, CLK_EN,
Input
VIL
Low Voltage
FB_SEL0, FB_SEL1, FB_IN
CLK0, CLK1
0.8
V
FB_SEL0, FB_SEL1,
SEL_A:SEL_C, CLK0,
VCO_SEL, CLK_SEL
CLK1, FB_IN, nMR/OE,
PLL_SEL, CLK_EN
FB_SEL0, FB_SEL1,
SEL_A:SEL_C, CLK0,
VCO_SEL, CLK_SEL
CLK1, FB_IN, nMR/OE,
PLL_SEL, CLK_EN
VDD = VIN = 3.465V
VDD = VIN = 3.465V
IN = 0V, VDD = 3.465V
100
µA
Input
IIH
High Current
5
µA
µA
µA
V
-5
Input
IIL
Low Current
VIN = 0V, VDD = 3.465V
-100
2.4
VOH
VOL
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
V
V
0.5
NOTE 1: Outputs terminated with 50Ω to VDDOx/2.
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ICS87974I
LOW SKEW, 1-TO-15,
LVCMOS/LVTTLCLOCK GENERATOR
Integrated
Circuit
Systems, Incꢀ
TABLE 5. AC CHARACTERISTICS, VDD = VDDA = VDDOX = 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Qx ÷ 2, VCO ÷ 2
Qx ÷ 4, VCO ÷ 2
Qx ÷ 6, VCO ÷ 2
Minimum
Typical
Maximum
125
Units
MHz
MHz
MHz
MHz
fMAX
Output Frequency
63
42
fVCO
tPD
PLL VCO Lock Range; NOTE 5
200
500
SYNC to Feedback
Propagation Delay; NOTE 2, 5
PLL_SEL = 3.3V,
fREF = 50MHz
-250
100
350
ps
ps
ps
Measured on rising
edge at VDDO/2
tsk(o)
tjit(cc)
Output Skew; NOTE 4, 5
Cycle-to-Cycle Jitter;
NOTE 5, 6
±100
tL
PLL Lock Time
10
mS
ns
ps
ns
ns
tR / tF
tPW
tEN
Output Rise/Fall Time
Output Pulse Width
Output Enable Time
Output Disable Time
0.8V to 2.0V
0.15
1.5
tPeriod/2 - 800 tPeriod/2 ± 500 tPeriod/2 + 800
2
2
10
10
tDIS
All parameters measured at fMAX unless noted otherwise.
NOTE 1: Measured from the VDD/2 point of the input to theVDDOx/2 of the output.
NOTE 2: Defined as the time difference between the input reference clock and the average feedback input signal
when the PLL is locked and the input reference frequency is stable.
NOTE 3: Defined as skew within a bank with equal load conditions.
NOTE 4: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at VDDOx/2.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 6: Measured as peak-to-peak.
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REV. B MAY 15, 2003
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ICS87974I
LOW SKEW, 1-TO-15,
LVCMOS/LVTTLCLOCK GENERATOR
Integrated
Circuit
Systems, Incꢀ
PARAMETER MEASUREMENT INFORMATION
VDD, VDDA, VDDOx = 1.65V±5%
SCOPE
VDDO
2
x
Qx
Qy
Qx
LVCMOS
VDDO
x
2
tsk(o)
GND = -1.65V±5%
OUTPUT SKEW
3.3V OUTPUT LOAD AC TEST CIRCUIT
VDDO
VDDO
2
VDDO
2V
2V
x
x
x
2
2
QAx,
QBx,
QCx,
QFB
0.8V
0.8V
➤
➤
tcycle n
t
cycle n+1
➤
➤
Clock Outputs
t
t
F
R
tjit(cc) = tcycle n –tcycle n+1
1000 Cycles
CYCLE-TO-CYCLE JITTER
OUTPUT RISE/FALL TIME
VDDO
2
VDDO
x
2
VDDO
x
x
VDD
2
QAx,
2
tPW
QBx,
QCx,
QFB
CLK0,
CLK1
tPERIOD
VDDO
x
2
tPW
tPERIOD
QFB
odc =
t
PD
tPW & tPERIOD
SYNC TO FEEDBACK PROPAGATION DELAY
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REV. B MAY 15, 2003
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ICS87974I
LOW SKEW, 1-TO-15,
LVCMOS/LVTTLCLOCK GENERATOR
Integrated
Circuit
Systems, Incꢀ
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS87974I provides sepa-
rate power supplies to isolate any high switching noise from
the outputs to the internal PLL. VDD, VDDA, and VDDOx should be
individually connected to the power supply plane through
vias, and bypass capacitors should be used for each pin. To
achieve optimum jitter performance, power supply isolation
is required. Figure 1 illustrates how a 10Ω resistor along with
a 10µF and a .01µF bypass capacitor should be connected
to each VDDA pin.
3.3V
VDD
.01µF
.01µF
10Ω
VDDA
10 µF
FIGURE 1. POWER SUPPLY FILTERING
LAYOUT GUIDELINE
The schematic of the ICS87974I layout example used in this lay-
out guideline is shown inFigure 2A. The ICS87974I recommended
PCB board layout for this example is shown in Figure 2B. This
layout example is used as a general guideline. The layout in the
actual system will depend on the selected component types, the
density of the components, the density of the traces, and the
stack up of the P.C. board.
Zo = 50
R8
VDDO
43
Receiver
U3
Zo = 50
R5
43
1
2
3
4
5
6
7
8
9
10
11
12
13
39
38
37
36
35
34
33
32
31
30
29
28
27
Reset
pulse or
pull up
GND
nMR
GND
QB1
VDDOB
QB2
GND
QB3
VDDOB
QB4
FB_IN
GND
QFB
VDDOFB
nc
nMR
CLK_EN
SELB
SELC
CLK_EN
SELB
SELC
PLL_SEL
SELA
CLK_SEL
CLK0
CLK1
nc
VDD
VDDA
3.3V
Receiver
PLL_SEL
SELA
CLK_SEL
Q1
RS
Zo = 50 Ohm
3.3V LVCMOS Driver
VDD
VDD
R7
10
Zo = 50
C11
R3
43
C16
10u
0.01u
87974
VDD
C13
0.01u
Receiver
RU2
1K
RU3
1K
RU4
SP
RU5
SP
RU6
SP
RU7
SP
Zo = 50
R1
43
CLK_EN
PLL_SEL
SELA
SELB
SELC
CLK_SEL
Receiver
VDDO
(U1-17)
(U1-22)
(U1-26)
(U1-28)
(U1-33)
(U1-37)
(U1-41)
(U1-45)
(U1-49)
RD2
SP
RD3
SP
RD4
1K
RD5
1K
RD6
1K
RD7
1K
C3
0.1uF
C4
0.1uF
C5
0.1uF
C6
0.1uF
C7
0.1uF
C8
0.1uF
C9
0.1uF
C10
0.1uF
C12
0.1uF
SP = Space (i.e. not intstalled)
Example of Reconfigurable Logic Control Input
FIGURE 2A. ICS87974I LVCMOS/LVTTL ZERO DELAY BUFFER SCHEMATIC EXAMPLE
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ICS87974I
LOW SKEW, 1-TO-15,
LVCMOS/LVTTLCLOCK GENERATOR
Integrated
Circuit
Systems, Incꢀ
The following component footprints are used in this layout
example:
trace delay might be restricted by the available space on the board
and the component location. While routing the traces, the clock
signal traces should be routed first and should be locked prior to
routing other signal traces.
All the resistors and capacitors are size 0603.
POWER AND GROUNDING
• The differential 50Ω output traces should have same
Place the decoupling capacitors as close as possible to the power
pins. If space allows, placement of the decoupling capacitor on
the component side is preferred. This can reduce unwanted in-
ductance between the decoupling capacitor and the power pin
caused by the via.
length.
• Avoid sharp angles on the clock trace. Sharp angle
turns cause the characteristic impedance to change on
the transmission lines.
• Keep the clock traces on the same layer. Whenever pos-
sible, avoid placing vias on the clock traces. Placement
of vias on the traces can affect the trace characteristic
impedance and hence degrade signal integrity.
Maximize the power and ground pad sizes and number of vias
capacitors. This can reduce the inductance between the power
and ground planes and the component power and ground pins.
• To prevent cross talk, avoid routing other signal traces in
parallel with the clock traces. If running parallel traces is
unavoidable, allow a separation of at least three trace
widths between the differential clock trace and the other
signal trace.
The RC filter consisting of R7, C11, and C16 should be placed
as close to the VDDA pin as possible.
CLOCK TRACES AND TERMINATION
Poor signal integrity can degrade the system performance or
cause system failure. In synchronous high-speed digital systems,
the clock signal is less tolerant to poor signal integrity than other
signals. Any ringing on the rising or falling edge or excessive ring
back can cause system failure. The shape of the trace and the
• Make sure no other signal traces are routed between the
clock trace pair.
• The series termination resistors should be located as
close to the driver pins as possible.
GND
C12
C9
C10
VDDO
VDD
Pin 1
U1
C8
ICS87974
VDDA
VIA
C7
C13
C6
R7
C16
C11
C5
C4
C3
FIGURE 2B. PCB BOARD LAYOUT FOR ICS87974I
87974AYI
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REV. B MAY 15, 2003
10
ICS87974I
LOW SKEW, 1-TO-15,
LVCMOS/LVTTLCLOCK GENERATOR
Integrated
Circuit
Systems, Incꢀ
RELIABILITY INFORMATION
TABLE 6. θJAVS. AIR FLOW TABLE
qJA by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
58.0°C/W
47.1°C/W
42.0°C/W
42.3°C/W
36.4°C/W
34.0°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS87974I is: 4225
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REV. B MAY 15, 2003
11
ICS87974I
LOW SKEW, 1-TO-15,
LVCMOS/LVTTLCLOCK GENERATOR
Integrated
Circuit
Systems, Incꢀ
PACKAGE OUTLINE - Y SUFFIX
TABLE 7. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BCC
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
N
A
52
--
--
1.60
0.15
1.45
0.38
0.20
A1
A2
b
0.05
1.35
0.22
0.09
--
1.40
0.32
c
--
D
12.00 BASIC
10.00 BASIC
12.00 BASIC
10.00 BASIC
0.65 BASIC
--
D1
E
E1
e
L
0.45
0.75
q
--
0°
7°
ccc
--
--
0.08
Reference Document: JEDEC Publication 95, MS-026
87974AYI
www.icst.com/products/hiperclocks.html
REV. B MAY 15, 2003
12
ICS87974I
LOW SKEW, 1-TO-15,
LVCMOS/LVTTLCLOCK GENERATOR
Integrated
Circuit
Systems, Incꢀ
TABLE 8. ORDERING INFORMATION
Part/Order Number
ICS87974AYI
Marking
Package
52 Lead LQFP
Count
160 per tray
500
Temperature
-40°C to 85°C
-40°C to 85°C
ICS87974AYI
ICS87974AYI
ICS87974AYIT
52 Lead LQFP on Tape and Reel
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or
for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial and industrial applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not recommended without
additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices
or critical medical instruments.
87974AYI
www.icst.com/products/hiperclocks.html
REV. B MAY 15, 2003
13
ICS87974I
LOW SKEW, 1-TO-15,
LVCMOS/LVTTLCLOCK GENERATOR
Integrated
Circuit
Systems, Incꢀ
REVISION HISTORY SHEET
Rev
A
Table
Page
Description of Change
Date
4/2/02
4/4/02
10 & 11 Added Layout Guideline and PCB Board Layout.
A
3
Added simplified block diagram.
T7
12
Revised Package Outline drawing. Corrected Package Dimensions table to
correspond with the Package Outline drawing.
A
B
B
11/15/02
3/20/03
5/15/03
Update format throughout datasheet.
Pin Description table - updated nMR/OE and VDDOx pin descriptions.
3V Power Supply table - changed VDD parameter to "Core..." from "Positive...".
T1
4
6
T4A
Changed IDD max. limit from 105mA max. to 118mA max.,
and IDDOx from 20mA max. to 22mA max.
T2
5
5
Pin Characteristics Table - changed CIN 8pF max. to 4pF typical.
T3E
FB Select Function Table - switched FB_SELx headings,
FB_SEL1 heading is in column 1, FB_SEL0 heading is in column 2.
87974AYI
www.icst.com/products/hiperclocks.html
REV. B MAY 15, 2003
14
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