ICS87974AYI-01 [IDT]
PLL Based Clock Driver, 14 True Output(s), 0 Inverted Output(s), PQFP52, 10 X 10 MM, 1.40 MM HEIGHT, MS-026, LQFP-52;
| 型号： | ICS87974AYI-01 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | PLL Based Clock Driver, 14 True Output(s), 0 Inverted Output(s), PQFP52, 10 X 10 MM, 1.40 MM HEIGHT, MS-026, LQFP-52 驱动 逻辑集成电路 |
| 文件： | 总15页 (文件大小：277K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS87974I-01
Integrated
Circuit
Systems, Inc.
LOW
S
KEW, 1-TO-15,
D
IFFERENTIAL
-
TO-LVCMOS / LVTTL CLOCK
GENERATOR
GENERAL DESCRIPTION
FEATURES
The ICS87974I-01 is a low skew, low jitter 1-to-15
Differential-to-LVCMOS / LVTTL Clock Generator/
Zero Delay Buffer and is a member of the
HiPerClockS™family of High Performance Clock
Solutions from ICS. The device has a fully inte-
• Fully integrated PLL
ICS
HiPerClockS™
• 15 single ended 3.3V LVCMOS / LVTTL outputs
• Selectable CLK1 or differential CLK0, nCLK0 inputs
for redundant clock applications
grated PLL and three banks whose divider ratios can be
independently controlled, providing output frequency relation-
ships of 1:1, 2:1, 3:1, 3:2, 3:2:1. In addition, the external feed-
back connection provides for a wide selection of output-to-
input frequency ratios.The CLK1 and CLK0, nCLK0 pins allow
for redundant clocking on the input and dynamically switching
the PLL between two clock sources.
• CLK1 accepts LVCMOS or LVTTL input levels
• CLK0, nCLK0 pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
• Maximum output frequency: 125MHz
• VCO range: 250MHz to 500MHz
• External feedback for ”zero delay” clock regeneration
• Cycle-to-cycle jitter: 50ps (maximum)
• Output skew: 200ps (maximum)
Guaranteed low jitter and output skew characteristics make the
ICS87974I-01 ideal for those applications demanding well de-
fined performance and repeatability.
• Bank skew: 70ps (maximum)
• PLL reference zero delay: CLK1: -150ps to 150ps
CLK0, nCLK0: -475ps to -175ps
• 3.3V operating supply
• -40°C to 70°C ambient operating temperature
PIN ASSIGNMENT
52 51 50 49 48 47 46 45 44 43 42 41 40
GND
nMR
1
39
38
37
36
35
34
33
32
31
30
29
28
27
GND
QB1
2
CLK_EN
SEL_B
SEL_C
PLL_SEL
SEL_A
CLK_SEL
CLK1
3
VDDOB
QB2
4
5
GND
QB3
6
7
VDDOB
QB4
ICS87974I-01
8
9
FB_IN
GND
QFB
CLK0
10
11
12
13
nCLK0
VDD
VDDOFB
nc
VDDA
14 15 16 17 18 19 20 21 22 23 24 25 26
52-Lead LQFP
10mm x 10mm x 1.4mm package body
Y package
Top View
87974AYI-01
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REV. A FEBRUARY 9, 2004
1
ICS87974I-01
Integrated
Circuit
Systems, Inc.
LOW
SKEW, 1-TO-15,
D
IFFERENTIAL
-
TO-LVCMOS / LVTTL CLOCK
GENERATOR
BLOCK DIAGRAM
(Internal Pulldown)
(Internal Pulldown)
(Internal Pulldown)
SEL_A
CLK_SEL
CLK1
0
÷2
÷2
÷4
÷6
5
0
1
QA0:QA4
0
D
Q
0
1
(Internal Pulldown)
(Internal Pullup)
CLK0
nCLK0
1
1
PLL
÷4
(Internal Pullup)
FB_IN
(Internal Pullup)
PLL_SEL
VCO_SEL
0
1
5
4
(Internal Pulldown)
QB0:QB4
QC0:QC3
D
D
Q
Q
(Internal Pulldown)
SEL_B
SEL_C
0
1
(Internal Pulldown)
0
1
0
(Internal Pullup)
QFB
nMR
D
Q
1
(Internal Pulldown)
÷2
FB_SEL1
(Internal Pulldown)
FB_SEL0
(Internal Pullup)
CLK_EN
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REV. A FEBRUARY 9, 2004
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ICS87974I-01
Integrated
Circuit
Systems, Inc.
LOW
S
KEW, 1-TO-15,
D
IFFERENTIAL
-
TO-LVCMOS / LVTTL CLOCK
GENERATOR
SIMPLIFIED BLOCK DIAGRAM
CLK_EN
SEL_A
VCO_SEL
÷2
÷4
0
1
SEL_A
CLK_SEL
0
1
0
1
÷2
÷4
D
D
D
Q
Q
Q
5
5
CLK1
0
QA0:QA4
QB0:QB4
PLL
CLK0
nCLK0
FB_IN
1
SEL_B
0
1
÷2
÷4
PLL_SEL
SEL_B
SEL_C
0
1
÷4
÷6
4
QC0:QC3
SEL_C
FB_0 FB_1
0
0
1
1
0
1
0
÷4
÷6
÷8
Q
1 ÷12
D
QFB
2
FB_SEL(0:1)
nMR/OE
87974AYI-01
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REV. A FEBRUARY 9, 2004
3
ICS87974I-01
Integrated
Circuit
Systems, Inc.
LOW
S
KEW, 1-TO-15,
D
IFFERENTIAL
-
TO-LVCMOS / LVTTL CLOCK
GENERATOR
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1, 15, 19,
24, 30,
35, 39,
GND
Power
Input
Power supply ground.
43, 47, 51
Active LOW Master Reset. When logic LOW, the internal dividers
are reset causing the outputs to go low. when logic HIGH, the internal
dividers and the outputs are enabled.
2
nMR
Pullup
LVCMOS / LVTTL interface levels.
Clock enable. When LOW, all outputs except QFB are low.
LVCMOS / LVTTL interface levels.
Selects divide value for Bank B output as described in Table 3.
LVCMOS / LVTTL interface levels.
Selects divide value for Bank C output as described in Table 3.
LVCMOS / LVTTL interface levels.
3
4
5
CLK_EN
SEL_B
SEL_C
Input
Input
Input
Pullup
Pulldown
Pulldown
Selects between the PLL and the reference clock as the input to the
dividers. When HIGH, selects PLL. When LOW, selects the reference
clock. LVCMOS / LVTTL interface levels.
6
PLL_SEL
Input
Pullup
Selects divide value for Bank A output as described in Table 3.
LVCMOS / LVTTL interface levels.
7
SEL_A
Input
Pulldown
8
9
CLK_SEL
CLK1
CLK0
nCLK0
nc
Input
Input
Pulldown Clock select input. LVCMOS / LVTTL interface levels.
Pulldown Clock input. LVCMOS / LVTTL interface levels.
Pulldown Non-inverting differential clock input.
Pullup Inverting differential clock input
No connect.
10
Input
11
Input
27, 42
12
Unused
Power
Power
VDD
Core supply pin.
13
VDDA
Analog supply pin.
FB_SEL0,
FB_SEL1
QA4, QA3,
Selects divide value for Bank feedback output as described in
Pulldown
14, 20
16, 18,
Input
Table 3. LVCMOS / LVTTL interface levels.
Bank A clock outputs. 7Ω typical output impedance.
LVCMOS / LVTTL interface levels.
Output
21, 23, 25 QA2, QA1, QA0
17, 22, 26
VDDOA
VDDOFB
QFB
Power
Power
Output
Output supply pins for Bank A clock outputs.
Output supply pin for QFB clock output.
28
29
Clock output. LVCMOS / LVTTL interface levels.
Feedback input to phase detector for generating clocks with
Pullup
31
FB_IN
Input
"zero delay". Connect to pin 29. LVCMOS / LVTTL interface levels.
32, 34,
QB4, QB3,
Bank B clock outputs. 7Ω typical output impedance.
Output
Power
Output
Power
Input
36, 38, 40 QB2, QB1, QB0
LVCMOS / LVTTL interface levels.
33, 37, 41
VDDOB
Output supply pins for Bank B clock outputs.
44, 46,
48, 50
QC3, QC2,
QC1, QC0
Bank C clock outputs. 7Ω typical output impedance.
LVCMOS / LVTTL interface levels.
45, 49
VDDOC
Output supply pins for Bank C clock outputs.
Selects VCO ÷ 4 when HIGH. Selects VCO ÷ 2 when LOW.
LVCMOS / LVTTL interface levels.
52
VCO_SEL
Pulldown
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
87974AYI-01
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REV. A FEBRUARY 9, 2004
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ICS87974I-01
Integrated
Circuit
Systems, Inc.
LOW
S
KEW, 1-TO-15,
D
IFFERENTIAL
-
TO-LVCMOS / LVTTL CLOCK
GENERATOR
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
CIN
Input Capacitance
4
pF
KΩ
KΩ
Ω
RPULLUP
Input Pullup Resistor
51
51
7
RPULLDOWN Input Pulldown Resistor
ROUT
Output Impedance
Power Dissipation Capacitance
(per output)
5
12
15
CPD
VDD, VDDA, VDDOx = 3.465V; NOTE 1
pF
NOTE 1: VDDOx denotes VDDOA, VDDOB, VDDOC, VDDOFB
.
TABLE 3A. OUTPUT CONTROL PIN FUNCTION TABLE
Inputs
Outputs
nMR
CLK_EN
QA0:QA4
QB0:QB4
HiZ
QC0:QC3
HiZ
QFB
0
1
1
X
0
1
HiZ
HiZ
LOW
LOW
LOW
Enable
Enable
Enable
Enable
Enable
TABLE 3B. OPERATING MODE FUNCTION TABLE
TABLE 3C. PLL INPUT FUNCTION TABLE
Inputs
Inputs
Operating Mode
PLL_SEL
CLK_SEL
PLL Input
CLK1
0
1
Bypass
PLL
0
1
CLK0, nCLK0
TABLE 3D. SELECT PIN FUNCTION TABLE
SEL_A
QAx
÷ 2
SEL_B
QBx
÷ 2
SEL_C
QCx
÷ 4
0
1
0
1
0
1
÷ 4
÷ 4
÷ 6
TABLE 3E. FB SELECT FUNCTION TABLE
Inputs
TABLE 3F. VCO SELECT FUNCTION TABLE
Inputs
Outputs
VCO_SEL
fVCO
VCO/2
VCO/4
FB_SEL1
FB_SEL0
QFB
÷ 4
0
1
0
0
1
1
0
1
0
1
÷ 6
÷ 8
÷ 12
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REV. A FEBRUARY 9, 2004
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ICS87974I-01
Integrated
Circuit
Systems, Inc.
LOW
S
KEW, 1-TO-15,
D
IFFERENTIAL
-
TO-LVCMOS / LVTTL CLOCK
GENERATOR
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
DD
Inputs, V
-0.5V to VDD + 0.5 V
-0.5V to VDDO + 0.5V
73.2°C/W (0 lfpm)
-65°C to 150°C
I
Outputs, VO
PackageThermal Impedance, θ
JA
StorageTemperature, T
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDOX = 3.3V 5ꢀ, TA = -40°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VDD
VDDA
VDDOx
IDD
Core Supply Voltage
3.135
3.135
3.135
3.3
3.3
3.3
3.465
3.465
3.465
125
V
V
Analog Supply Voltage
Output Supply Voltage; NOTE 1
Power Supply Current
V
mA
mA
mA
IDDO
IDDA
Output Supply Current
Analog Supply Current
25
15
NOTE 1: VDDOx denotes VDDOA, VDDOB, VDDOC, VDDOFB
.
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = VDDOX = 3.3V 5ꢀ, TA = -40°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VIH
VIL
Input High Voltage
2
VDD + 0.3
0.8
V
V
Input Low Voltage
-0.3
FB_SEL0, FB_SEL1,
CLK1, SEL_A:SEL_C,
CLK_SEL, VCO_SEL
FB_IN, nMR,
PLL_SEL, CLK_EN
FB_SEL0, FB_SEL1,
CLK1, SEL_A:SEL_C,
CLK_SEL, VCO_SEL
FB_IN, nMR,
VDD = VIN = 3.465V
150
5
µA
µA
µA
µA
IIH
Input High Current
V
DD = VIN = 3.465V
VIN = 0V, VDD = 3.465V
IN = 0V, VDD = 3.465V
-5
IIL
Input Low Current
V
-150
2.4
PLL_SEL, CLK_EN
VOH
VOL
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
V
V
0.5
NOTE 1: Outputs terminated with 50Ω to VDDOx/2.
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REV. A FEBRUARY 9, 2004
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ICS87974I-01
Integrated
Circuit
Systems, Inc.
LOW
S
KEW, 1-TO-15,
D
IFFERENTIAL
-
TO-LVCMOS / LVTTL CLOCK
GENERATOR
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = VDDA = VDDOX = 3.3V 5ꢀ, TA = -40°C TO 70°C
Symbol Parameter
IIH Input High Current
Test Conditions
VDD = VIN = 3.465V
VDD = VIN = 3.465V
IN = 0V, VDD = 3.465V
Minimum Typical Maximum Units
CLK0
150
5
µA
µA
µA
µA
V
nCLK0
CLK0
V
-5
-150
IIL
Input Low Current
nCLK0
VIN = 0V, VDD = 3.465V
VPP
Peak-to-Peak Input Voltage
0.15
1.3
VCMR
Common Mode Input Voltage; NOTE 1, 2
GND + 0.5
VDD -0.85
V
NOTE 1: Common mode voltage is defined as VIH.
NOTE 2: For single ended applications, the maximum input voltage for CLK0, nCLK0 is VDD + 0.3V.
TABLE 5. AC CHARACTERISTICS, VDD = VDDA = VDDOX = 3.3V 5ꢀ, TA = -40°C TO 70°C
Symbol Parameter
Test Conditions
Qx ÷ 2, VCO ÷ 2
Qx ÷ 4, VCO ÷ 2
Qx ÷ 6, VCO ÷ 2
Minimum Typical Maximum Units
125
62.5
41.67
500
150
-175
70
MHz
MHz
MHz
MHz
ps
fMAX
Output Frequency
fVCO
PLL VCO Lock Range; NOTE 5
250
-150
-475
CLK1
CLK0, nCLK0
0
PLL Reference Zero Delay;
NOTE 2, 5, 6
t(Ø)
PLL_SEL = 1
-325
ps
tsk(b)
tsk(o)
tjit(cc)
tL
Bank Skew; NOTE 3, 5
Output Skew; NOTE 4, 5
Cycle-to-Cycle Jitter; NOTE 5
PLL Lock Time
ps
200
50
ps
VCO = 500MHz, Div 4
20ꢀ to 80ꢀ
ps
10
mS
ps
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
200
45
700
55
ꢀ
tEN
Output Enable Time
Output Disable Time
10
ns
tDIS
10
ns
All parameters measured at fMAX unless noted otherwise.
NOTE 1: Measured from the VDD/2 point of the input to theVDDOx/2 of the output.
NOTE 2: Defined as the time difference between the input reference clock and the averaged feedback
input signal when the PLL is locked and the input reference frequency is stable.
NOTE 3: Defined as skew within a bank with equal load conditions.
NOTE 4: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at VDDOx/2.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 6: Reference frequency of 50MHz used with all banks in DIV4.
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REV. A FEBRUARY 9, 2004
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ICS87974I-01
Integrated
Circuit
Systems, Inc.
LOW
SKEW, 1-TO-15,
D
IFFERENTIAL
-
TO-LVCMOS / LVTTL CLOCK
GENERATOR
PARAMETER MEASUREMENT INFORMATION
1.65V 5ꢀ
VDD
SCOPE
VDD
VDDA
VDDO
,
,
nCLK0
Qx
VPP
VCMR
Cross Points
LVCMOS
CLK0
GND
GND
-1.65V 5ꢀ
3.3V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
VDDOX
2
VDDOX
2
VDDOX
2
VDDOX
QAx,
QBx,
QCx,
QFB
Qx
2
➤
➤
tcycle n+1
tcycle n
➤
➤
VDDOX
Qy
tjit(cc) = tcycle n –tcycle n+1
1000 Cycles
2
tsk(o)
CYCLE-TO-CYCLE JITTER
OUTPUT SKEW
VDD
2
VDDOX
2
QX0:QXx
CLK1
nCLK0
CLK0
VDDOX
2
QX0:QXx
tsk(b)
VDDO
2
QAx, QBx,
QCx, QFB
BANK SKEW (where X denotes outputs in the same bank)
STATIC PHASE OFFSET
VDDOX
80ꢀ
tF
80ꢀ
2
QAx,
QBx,
QCx,
Pulse Width
20ꢀ
20ꢀ
tPERIOD
Clock
Outputs
QFB
tR
tPW
odc =
tPERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
OUTPUT RIS/FALL TIME
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REV. A FEBRUARY 9, 2004
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ICS87974I-01
Integrated
Circuit
Systems, Inc.
LOW
S
KEW, 1-TO-15,
D
IFFERENTIAL
-
TO-LVCMOS / LVTTL CLOCK
GENERATOR
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept of R1 and R2 might need to be adjusted to position theV_REF in
single ended levels. The reference voltage V_REF = VDD/2 is the center of the input voltage swing. For example, if the input
generated by the bias resistors R1, R2 and C1.This bias circuit clock swing is only 2.5V andVDD = 3.3V, V_REF should be 1.25V
should be located as close as possible to the input pin.The ratio and R2/R1 = 0.609.
VDD
R1
1K
Single Ended Clock Input
CLK
V_REF
nCLK
C1
0.1u
R2
1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS87974I-01 provides
separate power supplies to isolate any high switching noise from
the outputs to the internal PLL. VDD, VDDA, and VDDOx should be
individually connected to the power supply plane through
vias, and bypass capacitors should be used for each pin. To
achieve optimum jitter performance, power supply isolation
is required. Figure 2 illustrates how a 10Ω resistor along with
a 10µF and a .01µF bypass capacitor should be connected
to each VDDA pin.
3.3V
VDD
.01µF
.01µF
10Ω
VDDA
10µF
FIGURE 2. POWER SUPPLY FILTERING
87974AYI-01
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REV. A FEBRUARY 9, 2004
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ICS87974I-01
Integrated
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LOW
S
KEW, 1-TO-15,
D
IFFERENTIAL
-
TO-LVCMOS / LVTTL CLOCK
GENERATOR
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL here are examples only. Please consult with the vendor of the
and other differential signals.BothVSWING and VOH must meet the driver component to confirm the driver termination requirements.
VPP and VCMR input requirements. Figures 3A to 3D show inter- For example in Figure 4A, the input termination applies for ICS
face examples for the HiPerClockS CLK/nCLK input driven by HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver
the most common driver types.The input interfaces suggested from another vendor, use their termination recommendation.
3.3V
3.3V
3.3V
1.8V
Zo = 50 Ohm
CLK
Zo = 50 Ohm
CLK
Zo = 50 Ohm
nCLK
Zo = 50 Ohm
HiPerClockS
Input
LVPECL
nCLK
HiPerClockS
Input
LVHSTL
R1
50
R2
50
ICS
HiPerClockS
R1
50
R2
50
LVHSTL Driver
R3
50
FIGURE 3A. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
ICS HIPERCLOCKS LVHSTL DRIVER
FIGURE 3B. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
3.3V
3.3V
3.3V
3.3V
Zo = 50 Ohm
3.3V
R3
125
R4
125
LVDS_Driver
Zo = 50 Ohm
Zo = 50 Ohm
CLK
CLK
R1
100
nCLK
Receiv er
nCLK
HiPerClockS
Input
Zo = 50 Ohm
LVPECL
R1
84
R2
84
FIGURE 3C. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 3D. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVDS DRIVER
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REV. A FEBRUARY 9, 2004
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ICS87974I-01
Integrated
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LOW
S
KEW, 1-TO-15,
D
IFFERENTIAL
-
TO-LVCMOS / LVTTL CLOCK
GENERATOR
S
CHEMATIC
E
XAMPLE
This application note provides general design guide using example of the ICS87974I-01 LVCMOS clock generator. In this
ICS87974I-01 LVCMOS buffer. Figure 4 shows a schematic example, the input is driven by an LVCMOS driver.
R8
43
Zo = 50
VDDO
VDD=3.3V
SP = Space (i.e. not intstalled)
U5
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
39
38
37
36
35
34
33
32
31
30
29
28
27
GND
nMR
CLK_EN
SELB
SELC
PLL_SEL
SELA
CLK_SEL
CLK1
CLK0
nCLK0
VDD
GND
QB1
VDDOB
QB2
GND
QB3
VDDOB
QB4
FB_IN
GND
QFB
VDDOFB
nc
RS
Zo = 50
Driver_LVCMOS_no_Ro
R7
VDD
VDD
VDDA
10 - 15
C16
10u
C11
0.01u
87974I-01
C13
0.01u
Logic Input Pin Examples
Set Logic
Set Logic
Input to
'0'
VDD
VDD
Input to
'1'
R1
43
Zo = 50
RU1
1K
RU2
Not Install
To Logic
Input
To Logic
Input
(U1-17)
VDDO (U1-22)
(U1-26)
(U1-28)
(U1-33)
(U1-37)
(U1-41)
(U1-45)
(U1-49)
pins
pins
RD1
RD2
1K
C3
0.1uF
C4
0.1uF
C5
0.1uF
C6
0.1uF
C7
0.1uF
C8
0.1uF
C9
0.1uF
C10
0.1uF
C12
0.1uF
Not Install
FIGURE 4. EXAMPLE ICS87974I-01 LVCMOS/LVTTL CLOCK OUTPUT BUFFER SCHEMATIC
87974AYI-01
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REV. A FEBRUARY 9, 2004
11
ICS87974I-01
Integrated
Circuit
Systems, Inc.
LOW
S
KEW, 1-TO-15,
D
IFFERENTIAL
-
TO-LVCMOS / LVTTL CLOCK
GENERATOR
RELIABILITY INFORMATION
TABLE 6. θJAVS. AIR FLOW TABLE FOR 52 LEAD LQFP
θJA byVelocity (Linear Feet per Minute)
0
200
47.1°C/W
36.4°C/W
500
42.0°C/W
34.0°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
58.0°C/W
42.3°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS87974I-01 is: 4225
87974AYI-01
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REV. A FEBRUARY 9, 2004
12
ICS87974I-01
Integrated
Circuit
Systems, Inc.
LOW
S
KEW, 1-TO-15,
D
IFFERENTIAL
-
TO-LVCMOS / LVTTL CLOCK
GENERATOR
PACKAGE OUTLINE - Y SUFFIX FOR 52 LEAD LQFP
TABLE 7. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BCC
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
N
A
52
--
--
1.60
0.15
1.45
0.38
0.20
A1
A2
b
0.05
1.35
0.22
0.09
--
1.40
0.32
c
--
D
12.00 BASIC
10.00 BASIC
12.00 BASIC
10.00 BASIC
0.65 BASIC
--
D1
E
E1
e
L
0.45
0.75
θ
--
0
°
7°
ccc
--
--
0.08
Reference Document: JEDEC Publication 95, MS-026
87974AYI-01
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REV. A FEBRUARY 9, 2004
13
ICS87974I-01
Integrated
Circuit
Systems, Inc.
LOW
S
KEW, 1-TO-15,
D
IFFERENTIAL
-
TO-LVCMOS / LVTTL CLOCK
GENERATOR
TABLE 8. ORDERING INFORMATION
Part/Order Number
ICS87974AYI-01
ICS87974AYI-01T
Marking
Package
Count
160 per tray
500
Temperature
-40°C to 70°C
-40°C to 70°C
ICS87974AYI-01
ICS87974AYI-01
52 Lead LQFP
52 Lead LQFP on Tape and Reel
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or
for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without
additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices
or critical medical instruments.
87974AYI-01
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REV. A FEBRUARY 9, 2004
14
ICS87974I-01
Integrated
Circuit
Systems, Inc.
LOW
SKEW, 1-TO-15,
D
IFFERENTIAL
-
TO-LVCMOS / LVTTL CLOCK
GENERATOR
REVISION HISTORY SHEET
Description of Change
Rev
Table
Page
Date
A
11
Added schematic layout.
11/13/03
Swichted labels for FB_SEL0 and FB_SEL1 in the Block Diagram and
Simplified Block Diagram.
A
2 & 3
2/9/04
87974AYI-01
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REV. A FEBRUARY 9, 2004
15
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