ICS87973I-147 [IDT]
LOW SKEW, 1-TO-12 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER; 低偏移， 1到12 LVCMOS / LVTTL时钟乘法器/零延迟缓冲器
| 型号： | ICS87973I-147 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | LOW SKEW, 1-TO-12 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER |
| 文件： | 总19页 (文件大小：1156K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LOW SKEW, 1-TO-12 LVCMOS/LVTTL CLOCK MULTIPLIER/
ZERO DELAY BUFFER
ICS87973I-147
General Description
Features
The ICS87973I-147 is a LVCMOS/LVTTL clock
• Fully integrated PLL
S
IC
generator and a member of the HiPerClockS™family
of High Performance Clock Solutions from IDT. The
ICS87973I-147 has three selectable inputs and
provides 14 LVCMOS/LVTTL outputs.
• Fourteen LVCMOS/LVTTL outputs to include: twelve clocks,
HiPerClockS™
one feedback, one sync
• Selectable differential CLK, nCLK inputs or LVCMOS/LVTTL
reference clock inputs
The ICS87973I-147 is a highly flexible device. The three
selectable inputs (1 differential and 2 single ended inputs) are
often used in systems requiring redundant clock sources. Up to
three different output frequencies can be generated among the
three output banks.
• CLK0, CLK1 can accept the following input levels:
LVCMOS or LVTTL
• CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
• Output frequency range: 10MHz to 150MHz
• VCO range: 240MHz to 500MHz
The three output banks and feedback output each have their own
output dividers which allows the device to generate a multitude of
different bank frequency ratios and output-to-input frequency
ratios. In addition, 2 outputs in Bank C (QC2, QC3) can be
selected to be inverting or non-inverting. The output frequency
range is 10MHz to 150MHz. The input frequency range is 6MHz to
120MHz.
• Output skew: 200ps (maximum)
• Cycle-to-cycle jitter, (all banks ÷4): 55ps (maximum)
• Full 3.3V supply voltage
• -40°C to 85°C ambient operating temperature
• Compatible with PowerPC™and Pentium™Microprocessors
The ICS87973I-147 also has a QSYNC output which can be used
for system synchronization purposes. It monitors Bank A and
Bank C outputs and goes low one period prior to coincident rising
edges of Bank A and Bank C clocks. QSYNC then goes high again
when the coincident rising edges of Bank A and Bank C occur.
This feature is used primarily in applications where Bank A and
Bank C are running at different frequencies, and is particularly
useful when they are running at non-integer multiples of one
another.
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
Pin Assignment
Example Applications:
39 38 37 36 35 34 33 32 31 30 29 28 27
1.System Clock generator: Use a 16.66MHz reference clock to
generate eight 33.33MHz copies for PCI and four 100MHz
copies for the CPU or PCI-X.
26
25
FSEL_B1 40
FSEL_B0 41
FSEL_A1 42
FSEL_FB1
QSYNC
24 GNDO
23
2.Line Card Multiplier: Multiply differential 62.5MHz from a back
plane to single-ended 125MHz for the line Card ASICs and
Gigabit Ethernet Serdes.
QC0
FSEL_A0
QA3
43
44
45
46
22 VDDO
21 QC1
VDDO
QA2
20 FSEL_C0
3.Zero Delay buffer for Synchronous memory: Fanout up to twelve
100MHz copies from a memory controller reference clock to the
memory chips on a memory module with zero delay.
19
18
17
16
GNDO 47
QA1 48
FSEL_C1
QC2
VDDO
VDDO
QA0 50
49
QC3
15 GNDO
51
52
GNDO
VCO_SEL
14 INV_CLK
1
2 3 4 5 6 7 8 9 10 11 12 13
ICS87973I-147
52-Lead LQFP
10mm x 10mm x 1.4mm package body
Y Package
Top View
IDT™ / ICS™ LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
1
ICS87973DYI-147 REV. A DECEMBER 9, 2008
ICS87973I-147
LOW SKEW, 1-TO-12, LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
Block Diagram
Pullup
VCO_SEL
Pullup
PLL_SEL
Pullup
REF_SEL
Pullup
CLK
nCLK
SYNC
FRZ
QA0
Pullup
CLK0
SYNC
FRZ
QA1
QA2
Pullup
CLK1
SYNC
FRZ
Pullup
CLK_SEL
SYNC
FRZ
Pullup
QA3
EXT_FB
SYNC
FRZ
QB0
QB1
QB2
QB3
SYNC
FRZ
SYNC
FRZ
SYNC
FRZ
FSEL_FB2
Pullup
nMR/OE
QC0
QC1
QC2
SYNC
FRZ
SYNC
FRZ
SYNC
FRZ
QC3
QFB
2
2
2
3
Pullup
Pullup
Pullup
FSEL_A[0:1]
FSEL_B[0:1]
FSEL_C[0:1]
FSEL_FB[0:2]
SYNC
FRZ
QSYNC
Pullup
Pullup
Pullup
Pullup
FRZ_CLK
FRZ_DATA
INV_CLK
IDT™ / ICS™ LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
2
ICS87973DYI-147 REV. A DECEMBER 9, 2008
ICS87973I-147
LOW SKEW, 1-TO-12, LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
Simplified Block Diagram
nMR/OE
Pullup
FSEL_A[0:1]
2
CLK
nCLK
1
0
FSEL_
A1 A0 QAx
SYNC
FRZ
Pullup
Pullup
QA0
CLK0
CLK1
0
1
PLL
0
0
1
1
0
1
0
1
÷4
÷6
÷8
SYNC
FRZ
QA1
QA2
VCO RANGE
240MHz - 500MHz
Pullup
Pullup
CLK_SEL
REF_SEL
EXT_FB
SYNC
FRZ
0
1
÷12
SYNC
FRZ
QA3
÷2
÷1
0
1
Pullup
FSEL_B[0:1]
2
SYNC
FRZ
FSEL_
B1 B0 QBx
QB0
QB1
QB2
QB3
Pullup
Pullup
0
0
1
1
0
1
0
1
÷4
÷6
÷8
SYNC
FRZ
VCO_SEL
PLL_SEL
SYNC
FRZ
÷10
SYNC
FRZ
FSEL_C[0:1]
2
FSEL_
C1 C0 QCx
QC0
QC1
QC2
QC3
0
0
1
1
0
1
0
1
÷2
÷4
÷6
÷8
SYNC
FRZ
SYNC
FRZ
0
1
SYNC
FRZ
Pullup
INV_CLK
FSEL_FB[0:2]
3
FSEL_
FB2 FB1 FB0 QFB
QFB
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
÷4
÷6
÷8
÷10
÷8
÷12
÷16
÷20
Pullup
Pullup
FRZ_CLK
FRZ_DATA
O
UTPUT
D
ISABLE
SYNC
FRZ
QSYNC
C
IRCUITRY
IDT™ / ICS™ LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
3
ICS87973DYI-147 REV. A DECEMBER 9, 2008
ICS87973I-147
LOW SKEW, 1-TO-12, LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
Table 1. Pin Descriptions
Number
Name
Type
Description
1
GNDI
Power
Input
Power supply ground.
Master reset and output enable. When HIGH, enables the outputs.
When LOW, resets the outputs in a high-impedance state and resets output divide
circuitry. Enables and disables all outputs. LVCMOS / LVTTL interface levels.
2
nMR/OE
Pullup
3
4
FRZ_CLK
FRZ_DATA
Input
Input
Pullup
Pullup
Clock input for freeze circuitry. LVCMOS / LVTTL interface levels.
Configuration data input for freeze circuitry. LVCMOS / LVTTL interface levels.
5,
26,
27
FSEL_FB2,
FSEL_FB1,
FSEL_FB0
Select pins control Feedback Divide value. LVCMOS / LVTTL interface levels.
See Table 3B.
Input
Input
Pullup
Pullup
Selects between the PLL and reference clocks as the input to the output dividers.
When HIGH, selects PLL. When LOW, bypasses the PLL and reference clocks.
LVCMOS / LVTTL interface levels.
6
PLL_SEL
Selects between CLK0 or CLK1 and CLK, nCLK inputs. When LOW, selects CLK0
or CLK1. When HIGH, CLK, nCLK inputs. LVCMOS / LVTTL interface levels.
7
8
REF_SEL
CLK_SEL
Input
Input
Pullup
Pullup
Clock select input. When LOW, selects CLK0. When HIGH, selects CLK1.
LVCMOS / LVTTL interface levels.
9, 10
11
CLK0, CLK1
CLK
Input
Input
Input
Power
Input
Pullup
Pullup
Single-ended reference clock inputs. LVCMOS/LVTTL interface levels.
Non-inverting differential clock input.
12
nCLK
Inverting differential clock input. VDD/2 default when left floating.
Analog supply pin.
13
VDDA
14
INV_CLK
Pullup
Inverted clock select for QC2 and QC3 outputs. LVCMOS / LVTTL interface levels.
15, 24, 30,
35, 39, 47,
51
GNDO
Power
Power supply ground.
16, 18,
21, 23
QC3, QC2,
QC1, QC0
Output
Power
Input
Single-ended Bank C clock outputs. LVCMOS/ LVTTL interface levels.
Output power supply pins.
17, 22, 33,
37, 45, 49
VDDO
19,
20
FSEL_C1,
FSEL_C0
Pullup
Pullup
Select pins for Bank C outputs. LVCMOS / LVTTL interface levels. See Table 3A.
Synchronization output for Bank A and Bank C. Refer to Figure 1, Timing Diagrams.
LVCMOS / LVTTL interface levels.
25
QYSNC
Output
28
29
31
VDD
QFB
Power
Output
Input
Power supply pin.
Single-ended feedback clock output. LVCMOS / LVTTL interface levels.
External feedback. LVCMOS / LVTTL interface levels.
EXT_FB
32, 34,
36, 38
QB3, QB2,
QB1, QB0
Output
Input
Single-ended Bank B clock outputs. LVCMOS/ LVTTL interface levels.
Select pins for Bank B outputs. LVCMOS / LVTTL interface levels. See Table 3A.
Select pins for Bank A outputs. LVCMOS / LVTTL interface levels. See Table 3A.
Single-ended Bank A clock outputs. LVCMOS/ LVTTL interface levels.
40,
41
FSEL_B1,
FSEL_B0
Pullup
Pullup
42,
43
FSEL_A1,
FSEL_A0
Input
44, 46
48, 50
QA3, QA2,
QA1, QA0
Output
Input
Selects VCO. When HIGH, selects VCO ÷ 1. When LOW, selects VCO ÷ 2.
LVCMOS / LVTTL interface levels.
52
VCO_SEL
Pullup
NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
IDT™ / ICS™ LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
4
ICS87973DYI-147 REV. A DECEMBER 9, 2008
ICS87973I-147
LOW SKEW, 1-TO-12, LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
Table 2. Pin Characteristics
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
pF
CIN
Input Capacitance
4
RPULLUP Input Pullup Resistor
51
kΩ
Power Dissipation Capacitance
(per output)
CPD
VDD, VDDA, VDDO = 3.465V
18
12
pF
ROUT
Output Impedance
5
7
Ω
Function Tables
Table 3A. Output Bank Configuration Select Function Table
Inputs
Outputs
QA
Inputs
Outputs
QB
Inputs
Outputs
QC
FSEL_A1
FSEL_A0
FSEL_B1
FSEL_B0
FSEL_C1
FSEL_C0
0
0
1
1
0
1
0
1
÷4
0
0
1
1
0
1
0
1
÷4
0
0
1
1
0
1
0
1
÷2
÷6
÷6
÷4
÷8
÷8
÷6
÷12
÷10
÷8
Table 3B. Feedback Configuration Select Function Table
Inputs
Outputs
QFB
÷4
FSEL_FB2
FSEL_FB1
FSEL_FB0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
÷6
÷8
÷10
÷8
÷12
÷16
÷20
Table 3C. Control Input Select Function Table
Control Pin
VCO_SEL
REF_SEL
CLK_SEL
PLL_SEL
nMR/OE
Logic 0
VCO/2
Logic 1
VCO
CLK0 or CLK1
CLK0
XTAL
CLK1
BYPASS PLL
Enable PLL
Enable Outputs
Inverted QC2, QC3
Master Reset/Output High-Impedance
Non-Inverted QC2, QC3
INV_CLK
IDT™ / ICS™ LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
5
ICS87973DYI-147 REV. A DECEMBER 9, 2008
ICS87973I-147
LOW SKEW, 1-TO-12, LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
fVCO
1:1 Mode
QA
QC
QSYNC
2:1 Mode
QA
QC
QSYNC
3:1 Mode
QC(÷2)
QA(÷4)
QSYNC
3:2 Mode
QC(÷2)
QA(÷8)
QSYNC
4:1 Mode
QC(÷2)
QA(÷8)
QSYNC
4:3 Mode
QA(÷6)
QC(÷8)
QSYNC
6:1 Mode
QA(÷12)
QC(÷2)
QSYNC
Figure 1. Timing Diagrams
IDT™ / ICS™ LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
6
ICS87973DYI-147 REV. A DECEMBER 9, 2008
ICS87973I-147
LOW SKEW, 1-TO-12, LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VDD
Inputs, VI
4.6V
-0.5V to VDD + 0.5V
-0.5V to VDDO + 0.5V
42.3°C/W (0 lfpm)
-65°C to 150°C
Outputs, VO
Package Thermal Impedance, θJA
Storage Temperature, TSTG
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VDD = VDDA = VDDO = 3.3V 5ꢀ, TA = -40°C to 85°C
Symbol
VDD
Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum
3.465
3.465
3.465
225
Units
V
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
VDDA
VDDO
IDD
3.135
3.3
V
3.135
3.3
V
mA
mA
IDDA
20
Table 4B. DC Characteristics, VDD = VDDA = VDDO = 3.3V 5ꢀ, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
VDD + 0.3
0.8
Units
V
VIH
VIL
Input High Voltage
2
Input Low Voltage
-0.3
V
IIN
Input Current
120
µA
V
VOH
VOL
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
IOH = -20mA
IOL = 20mA
2.4
0.3
0.5
1
V
Peak-to-Peak Input Voltage;
NOTE 2, 3
VPP
CLK, nCLK
CLK, nCLK
V
V
Common Mode Input Voltage;
NOTE 2, 3
VCMRP
V
DD - 2
VDD - 0.6
NOTE 1: Outputs terminated with 50Ω to VDDO/2. See Parameter Measurement Information section. Load Test Circuit diagram.
NOTE 2: VIL should not be less than -0.3V.
NOTE 3: Common mode input voltage is defined as VIH.
IDT™ / ICS™ LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
7
ICS87973DYI-147 REV. A DECEMBER 9, 2008
ICS87973I-147
LOW SKEW, 1-TO-12, LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
Table 5. Input Frequency Characteristics, VDD = VDDA = VDDO = 3.3V 5ꢀ, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
120
Units
MHz
MHz
CLK0, CLK1; NOTE 1
FRZ_CLK
FIN Input Frequency
20
NOTE 1: Input frequency depends on the feedback divide ratio to ensure "clock * feedback divide" is in the VCO range of 240MHz to
500MHz.
AC Electrical Characteristics
Table 6. AC Characteristics, VDD = VDDA = VDDO = 3.3V 5ꢀ, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
150
125
83.33
62.5
300
245
165
200
55
Units
MHz
MHz
MHz
MHz
ps
÷2
÷4
÷6
÷8
fMAX
Output Frequency
CLK0
-10
-65
145
90
Static Phase Offset;
NOTE 1
QFB ÷ 8,
In Frequency = 50MHz
t(Ø)
CLK1
ps
CLK, nCLK
-130
18
ps
tsk(o)
tjit(cc)
fVCO
Output Skew; NOTE 2, 3
Cycle-to-Cycle Jitter; NOTE 3
PLL VCO Lock Range
ps
All Banks ÷ 4
0.8V to 2V
ps
240
500
10
MHz
ms
ps
tLOCK
tR / tF
odc
PLL Lock Time; NOTE 4
Output Rise/Fall Time
150
45
700
55
Output Duty Cycle
ꢀ
tPZL, PZH
t
Output Enable Time; NOTE 4
Output Disable Time; NOTE 4
10
ns
tPLZL, PHZ
t
8
ns
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the
device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after
thermal equilibrium has been reached under these conditions.
NOTE 1: Defined as the time difference between the input reference clock and the average feedback input signal when the PLL is locked
and the input reference frequency is stable.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: These parameters are guaranteed by characterization. Not tested in production.
IDT™ / ICS™ LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
8
ICS87973DYI-147 REV. A DECEMBER 9, 2008
ICS87973I-147
LOW SKEW, 1-TO-12, LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
Parameter Measurement Information
1.65V 5ꢀ
V
DD
SCOPE
V
V
DD,
nCLK
CLK
DDA,
V
DDO
Qx
VPP
VCMR
Cross Points
LVCMOS
GND
GND
-1.65V 5ꢀ
LVCMOS Output Load AC Test Circuit
Differential Input Level
VDDO
2
VDDO
2
VDDO
2
QA[0:3],
QB[0:3],
QC[0:3],
QSYNC,
QFB
Qx
➤
➤
tcycle n
tcycle n+1
➤
➤
tjit(cc) = tcycle n – tcycle n+1
|
|
Qy
1000 Cycles
tsk(o)
Cycle-to-Cycle Jitter
Output Skew
nCLK
nCLK
VDD
VDD
2
CLK0,
CLK1
2
VDD
2
VDD
2
EXT_FB
EXT_FB
➤
➤
➤
t(Ø)
➤
t(Ø)
t(Ø) mean = Static Phase Offset
Where t(Ø) is any random sample, and t(Ø) mean is the
average of the sampled cycles measured on controlled edges
t(Ø) mean = Static Phase Offset
Where t(Ø) is any random sample, and t(Ø) mean is the
average of the sampled cycles measured on controlled edges
LVCMOS Static Phase Offset
Differential Static Phase Offset
IDT™ / ICS™ LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
9
ICS87973DYI-147 REV. A DECEMBER 9, 2008
ICS87973I-147
LOW SKEW, 1-TO-12, LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
Parameter Measurement Information, continued
VDDO
2
QA[0:3],
QA[0:3],
QB[0:3],
QC[0:3],
QSYNC,
QFB
2V
tPW
2V
QB[0:3],
QC[0:3],
QSYNC,
QFB
tPERIOD
0.8V
0.8V
tR
tF
tPW
x 100ꢀ
odc =
tPERIOD
Output Duty Cycle/Pulse Width Period
Output Rise/Fall Time
Application Information
Recommendations for Unused Input and Output Pins
Inputs:
Outputs:
CLK/nCLK Inputs
LVCMOS Outputs
All unused LVCMOS output can be left floating. There should be no
trace attached.
For applications not requiring the use of the differential input, both
CLK and nCLK can be left floating. Though not required, but for
additional protection, a 1kΩ resistor can be tied from CLK to
ground.
CLK Inputs
For applications not requiring the use of the clock input, it can be
left floating. Though not required, but for additional protection, a
1kΩ resistor can be tied from the CLK to ground.
LVCMOS Control Pins
All control pins have internal pull-ups; additional resistance is not
required but can be added for additional protection. A 1kΩ resistor
can be used.
IDT™ / ICS™ LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
10
ICS87973DYI-147 REV. A DECEMBER 9, 2008
ICS87973I-147
LOW SKEW, 1-TO-12, LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
Power Supply Filtering Technique
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter perform-
ance, power supply isolation is required. The ICS87973I-147
provides separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. VDD, VDDA and VDDO
should be individually connected to the power supply plane
through vias, and 0.01µF bypass capacitors should be used for
each pin. Figure 2 illustrates this for a generic VDD pin and also
shows that VDDA requires that an additional 10Ω resistor along with
a 10µF bypass capacitor be connected to the VDDA pin.
3.3V
VDD
.01µF
.01µF
10Ω
VDDA
10µF
Figure 2. Power Supply Filtering
Wiring the Differential Input to Accept Single Ended Levels
Figure 3 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_BIAS = VDD/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to position the V_BIAS in the
center of the input voltage swing. For example, if the input clock
swing is only 2.5V and VDD = 3.3V, V_BIAS should be 1.25V and
VDD
R1
1K
Single Ended Clock Input
R2/R1 = 0.609.
CLK
V_Bias
nCLK
C1
0.1u
R2
1K
Figure 3. Single-Ended Signal Driving Differential Input
IDT™ / ICS™ LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
11
ICS87973DYI-147 REV. A DECEMBER 9, 2008
ICS87973I-147
LOW SKEW, 1-TO-12, LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
Differential Clock Input Interface
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both signals must meet the VPP and
VCMR input requirements. Figures 4A to 4E show interface
examples for the HiPerClockS CLK/nCLK input driven by the most
common driver types. The input interfaces suggested here are
examples only. Please consult with the vendor of the driver
component to confirm the driver termination requirements. For
example, in Figure 4A, the input termination applies for IDT
HiPerClockS open emitter LVHSTL drivers. If you are using an
LVHSTL driver from another vendor, use their termination
recommendation.
3.3V
3.3V
3.3V
1.8V
Zo = 50Ω
Zo = 50Ω
CLK
CLK
Zo = 50Ω
nCLK
Zo = 50Ω
HiPerClockS
Input
nCLK
LVPECL
HiPerClockS
LVHSTL
R1
50
R2
50
Input
R1
50
R2
50
IDT
HiPerClockS
LVHSTL Driver
R2
50
Figure 4A. HiPerClockS CLK/nCLK Input
Driven by an IDT Open Emitter
HiPerClockS LVHSTL Driver
Figure 4B. HiPerClockS CLK/nCLK Input
Driven by a 3.3V LVPECL Driver
3.3V
3.3V
3.3V
3.3V
R3
125
R4
125
3.3V
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
CLK
CLK
R1
100
nCLK
nCLK
Zo = 50Ω
HiPerClockS
Input
LVPECL
Receiver
LVDS
R1
84
R2
84
Figure 4C. HiPerClockS CLK/nCLK Input
Driven by a 3.3V LVPECL Driver
Figure 4D. HiPerClockS CLK/nCLK Input
Driven by a 3.3V LVDS Driver
2.5V
3.3V
Zo = 50Ω
*R3
*R4
33
33
CLK
Zo = 50Ω
nCLK
HiPerClockS
Input
HCSL
R1
50
R2
50
*Optional – R3 and R4 can be 0Ω
Figure 4E. HiPerClockS CLK/nCLK Input
Driven by a 3.3V HCSL Driver
IDT™ / ICS™ LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
12
ICS87973DYI-147 REV. A DECEMBER 9, 2008
ICS87973I-147
LOW SKEW, 1-TO-12, LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
Using the Output Freeze Circuitry
each FRZ_DATA bit with the rising edge of the FRZ_CLK signal. To
OVERVIEW
place an output in the freeze state, a logic “0” must be written to the
respective freeze enable bit in the shift register. To unfreeze an
output, a logic “1” must be written to the respective freeze enable
bit. Outputs will not become enabled/disabled until all 12 data bits
are shifted into the shift register. When all 12 data bits are shifted
in the register, the next rising edge of FRZ_CLK will enable or
disable the outputs. If the bit that is following the 12th bit in the
register is a logic “0”, it is used for the start bit of the next cycle;
otherwise, the device will wait and won’t start the next cycle until it
sees a logic “0” bit. Freezing and unfreezing of the output clock is
synchronous (see the timing diagram below). When going into a
frozen state, the output clock will go LOW at the time it would
normally go LOW, and the freeze logic will keep the output low until
unfrozen. Likewise, when coming out of the frozen state, the output
will go HIGH only when it would normally go HIGH. This logic,
therefore, prevents runt pulses when going into and out of the
frozen state.
To enable low power states within a system, each output of
ICS87973I-147 (Except QC0 and QFB) can be individually frozen
(stopped in the logic “0” state) using a simple serial interface to a
12 bit shift register. A serial interface was chosen to eliminate the
need for each output to have its own Output Enable pin, which
would dramatically increase pin count and package cost. Common
sources in a system that can be used to drive the ICS87973I-147
serial interface are FPGA’s and ASICs.
PROTOCOL
The Serial interface consists of two pins, FRZ_Data (Freeze Data)
and FRZ_CLK (Freeze Clock). Each of the outputs which can be
frozen has its own freeze enable bit in the 12 bit shift register. The
sequence is started by supplying a logic “0” start bit followed by
12NRZ freeze enable bits. The period of each FRZ_DATA bit
equals the period of the FRZ_CLK signal. The FRZ_DATA serial
transmission should be timed so the ICS87973I-147 can sample
FRZ_DATA
QA0 QA1 QA2 QA3 QB0 QB1 QB2 QB3 QC1 QC2 QC3 QSYNC
FRZ_CLK
Figure 5A. Freeze Data Input Protocol
Qx FREEZE Internal
Qx Internal
Qx Out
Figure 5. Output Disable Timing Diagram
IDT™ / ICS™ LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
13
ICS87973DYI-147 REV. A DECEMBER 9, 2008
ICS87973I-147
LOW SKEW, 1-TO-12, LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
Schmatic Example
Figure 6 shows a schematic example of using ICS87973I-147. This
example shows general design of input, output termination, logic
control input pull up/down and power supply filtering. In this
example, the clock input is driven by an LVCMOS driver.
R1
43
Zo = 50
VDD
U1
VDD
R9
1K
Serial Clcok
R8
1K
1
2
39
38
37
36
35
34
33
32
31
30
29
28
27
GNDI
GNDO
QB0
nMR/OE
FRZ_CLK
FRZ_DATA
FSEL_FB2
PLL_SEL
REF_SEL
CLK_SEL
CLK0
R10 1K
Zo = 50
3
VDDO
QB1
Serial Data
RS
VDD
4
5
GNDO
QB2
6
7
VDDO
QB3
8
9
EXT_FB
GNDO
QFB
10
11
12
13
CLK1
CLK
LVCMOS CLOCK
nCLK
VDD
VDDA
FSEL_FB0
R7
VDD
10 - 15
C16
10u
R5
1K
R6
1K
C11
0.01u
ICS87973I-147
R2
43
Zo = 50
Logic Input Pin Examples
Set Logic
R4
1K
Set Logic
Input to
'0'
VDD
VDD
Input to
'1'
RU1
1K
RU2
Not Install
R3
43
Zo = 50
To Logic
Input
To Logic
(U1-17)
C3
(U1-22)
(U1-28)
(U1-33)
(U1-37)
(U1-45)
(U1-49)
VDD
Input
pins
pins
RD1
RD2
1K
C4
0.1uF
C5
0.1uF
C6
0.1uF
C7
0.1uF
C8
0.1uF
C9
0.1uF
VDD=3.3V
Not Install
0.1uF
ICS87973I-147 Schematic Layout
IDT™ / ICS™ LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
14
ICS87973DYI-147 REV. A DECEMBER 9, 2008
ICS87973I-147
LOW SKEW, 1-TO-12, LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
Reliability Information
Table 7. θJA vs. Air Flow Table for a 52 Lead LQFP
θJA by Velocity
Linear Feet per Minute
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
58.0°C/W
42.3°C/W
47.1°C/W
36.4°C/W
42.0°C/W
34.0°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
Transistor Count
The transistor count for ICS87973I-147: 8364
Pin Compatible with MPC973
IDT™ / ICS™ LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
15
ICS87973DYI-147 REV. A DECEMBER 9, 2008
ICS87973I-147
LOW SKEW, 1-TO-12, LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
Package Outline and Package Dimensions
Package Outline - Y Suffix for 52 Lead LQFP
Table 8. Package Dimensions for 52 Lead LQFP
JEDEC Variation: BCC
All Dimensions in Millimeters
Symbol
Minimum
Nominal
Maximum
N
52
A
1.60
0.15
1.45
0.38
0.20
A1
0.05
1.35
0.22
0.09
0.10
1.40
A2
b
c
D & E
D1 & E1
D2 & E2
e
12.00 Basic
10.00 Basic
7.80 Ref.
0.65 Basic
0.60
L
0.45
0°
0.75
7°
θ
ccc
0.10
Reference Document: JEDEC Publication 95, MS-026
IDT™ / ICS™ LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
16
ICS87973DYI-147 REV. A DECEMBER 9, 2008
ICS87973I-147
LOW SKEW, 1-TO-12, LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
Ordering Information
Table 9. Ordering Information
Part/Order Number
87973DYI-147
87973DYI-147T
87973DYI-147LF
87973DYI-147LFT
Marking
Package
52 Lead LQFP
52 Lead LQFP
Shipping Packaging
Tray
1000 Tape & Reel
Tray
Temperature
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
ICS7973DYI-147
ICS87973DYI-147
ICS87973DI147L
ICS87973DI147L
“Lead-Free” 52 Lead LQFP
“Lead-Free” 52 Lead LQFP
1000 Tape & Reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
IDT™ / ICS™ LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
17
ICS87973DYI-147 REV. A DECEMBER 9, 2008
ICS87973I-147
LOW SKEW, 1-TO-12, LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
Revision History Sheet
Rev
Table
Page
Description of Change
Date
T4B
T6
7
Differential DC Characteristics Table - updated NOTES.
AC Characteristics Table - added thermal note.
8
10
12
16
17
Added Recommendations for Unused Input and Output Pins section.
Updated Differetnial Clock Input Interface section.
A
12/9/08
T8
T9
UpdatePackage Outline and Package Dimensions Table.
Ordering Information Table - added lead-free part number and marking.
IDT™ / ICS™ LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
18
ICS87973DYI-147 REV. A DECEMBER 9, 2008
ICS87973I-147
LOW SKEW, 1-TO-12, LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
Contact Information:
www.IDT.com
Corporate Headquarters
Sales
Technical Support
Integrated Device Technology, Inc.
800-345-7015 (inside USA)
+408-284-8200 (outside USA)
Fax: 408-284-2775
netcom@idt.com
+480-763-2056
6024 Silver Creek Valley Road
San Jose, CA 95138
United States
800-345-7015 (inside USA)
+408-284-8200 (outside USA)
www.IDT.com/go/contactIDT
© 2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device
Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered
trademarks used to identify products or services of their respective owners.
www.IDT.com
Printed in USA
相关型号：
ICS87974AY
PLL Based Clock Driver, 15 True Output(s), 0 Inverted Output(s), PQFP52, 10 X 10 MM, 1.40 MM HEIGHT, MS-026, LQFP-52
IDT
ICS87974AY-01
PLL Based Clock Driver, 15 True Output(s), 0 Inverted Output(s), PQFP52, 10 X 10 MM, 1.40 MM HEIGHT, MS-026, LQFP-52
IDT
ICS87974AY-01LF
PLL Based Clock Driver, 15 True Output(s), 0 Inverted Output(s), PQFP52, 10 X 10 MM, 1.40 MM HEIGHT, MS-026, LQFP-52
IDT
ICS87974AY-01LFT
PLL Based Clock Driver, 15 True Output(s), 0 Inverted Output(s), PQFP52, 10 X 10 MM, 1.40 MM HEIGHT, MS-026, LQFP-52
IDT
ICS87974AY-01T
PLL Based Clock Driver, 15 True Output(s), 0 Inverted Output(s), PQFP52, 10 X 10 MM, 1.40 MM HEIGHT, MS-026, LQFP-52
IDT
ICS87974AY-T
PLL BASED CLOCK DRIVER, 14 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52, 10 X 10 MM, 1.40 MM HEIGHT, MS-026, LQFP-52
IDT
ICS87974AY-T-LF
PLL Based Clock Driver, 14 True Output(s), 0 Inverted Output(s), PQFP52, 10 X 10 MM, 1.40 MM HEIGHT, MS-026, LQFP-52
IDT
ICS87974AYI
PLL Based Clock Driver, 14 True Output(s), 0 Inverted Output(s), CMOS, PQFP52, 10 X 10 MM, 1.40 MM HEIGHT, MS-026, LQFP-52
IDT
ICS87974AYI-01
PLL Based Clock Driver, 14 True Output(s), 0 Inverted Output(s), PQFP52, 10 X 10 MM, 1.40 MM HEIGHT, MS-026, LQFP-52
IDT
ICS87974AYI-01LF
PLL Based Clock Driver, 14 True Output(s), 0 Inverted Output(s), PQFP52, 10 X 10 MM, 1.40 MM HEIGHT, MS-026, LQFP-52
IDT
ICS87974AYI-01LFT
PLL Based Clock Driver, 14 True Output(s), 0 Inverted Output(s), PQFP52, 10 X 10 MM, 1.40 MM HEIGHT, MS-026, LQFP-52
IDT
ICS87974AYILF
PLL Based Clock Driver, 14 True Output(s), 0 Inverted Output(s), PQFP52, 10 X 10 MM, 1.40 MM HEIGHT, MS-026, LQFP-52
IDT
©2020 ICPDF网 联系我们和版权申明