ICS87974AY-01T [IDT]
PLL Based Clock Driver, 15 True Output(s), 0 Inverted Output(s), PQFP52, 10 X 10 MM, 1.40 MM HEIGHT, MS-026, LQFP-52;
| 型号： | ICS87974AY-01T |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | PLL Based Clock Driver, 15 True Output(s), 0 Inverted Output(s), PQFP52, 10 X 10 MM, 1.40 MM HEIGHT, MS-026, LQFP-52 驱动 逻辑集成电路 |
| 文件： | 总14页 (文件大小：131K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
ICS87974-01
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-15,
DIFFERENTIAL-TO-LVCMOS CLOCK GENERATOR
GENERAL DESCRIPTION
FEATURES
• Fully integrated PLL
The ICS87974-01 is a low skew, low jitter 1-to-15
Differential-to-LVCMOS clock generator/zero
delay buffer and is a member of the HiPerClockS
family of High Performance Clock Solutions from
ICS. The device has a fully integrated PLLand three
HiPerClockS™
• 15 single ended 3.3V LVCMOS outputs
• Selectable LVCMOS_CLK or differential CLK0, nCLK0 inputs
for redundant clock applications
banks whose divider ratios can be independently controlled,
providing output frequency relationships of 1:1, 2:1, 3:1, 3:2,
3:2:1. In addition, the external feedback connection provides
for a wide selection of output-to-input frequency ratios. The
LVCMOS_CLK and CLK0, nCLK0 pins allow for redundant
clocking on the input and dynamically switching the PLL
between two clock sources.
• LVCMOS_CLK accepts LVCMOS or LVTTL input levels
• CLK0, nCLK0 pair can accept the following differential input
levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
• Maximum output frequency up to 125MHz
• External feedback for ”zero delay” clock regeneration
• Cycle-to-cycle jitter: ±100ps (typical)
• Output skew: 350ps (maximum)
Guaranteed low jitter and output skew characteristics make the
ICS87974-01 ideal for those applications demanding well de-
fined performance and repeatability.
• Bank skew: ±50ps (typical)
• PLLreference zero delay: TBD
• 3.3V operating supply
• 0°C to 70°C ambient operating temperature
• Industrial temperature information available upon request
PIN ASSIGNMENT
52 51 50 49 48 47 46 45 44 43 42 41 40
GND
nMR
1
GND
39
38
37
36
35
34
33
32
31
30
29
28
27
2
QB1
CLK_EN
SELB
3
VDDOB
QB2
4
SELC
5
GND
QB3
PLL_SEL
SELA
6
7
VDDOB
QB4
ICS87974-01
CLK_SEL
LVCMOS_CLK
CLK0
8
9
FB_IN
GND
QFB
10
11
12
13
nCLK0
VDD
VDDOFB
nc
VDDA
14 15 16 17 18 19 20 21 22 23 24 25 26
52-Lead LQFP
10mm x 10mm x 1.4mm package body
Y package
Top View
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
87974AY-01
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REV. A FEBRUARY 13, 2002
1
PRELIMINARY
ICS87974-01
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-15,
DIFFERENTIAL-TO-LVCMOS CLOCK GENERATOR
BLOCK DIAGRAM
(Internal Pulldown)
(Internal Pulldown)
(Internal Pulldown)
SELA
CLK_SEL
0
÷2
LVCMOS_CLK
÷2
÷4
÷6
5
QA0 - QA4
0
1
0
1
D
Q
0
1
(Internal Pulldown)
(Internal Pullup)
CLK0
nCLK0
1
PLL
÷4
(Internal Pullup)
FB_IN
(Internal Pullup)
PLL_SEL
VCO_SEL
0
1
5
4
QB0 - QB4
(Internal Pulldown)
D
D
Q
Q
(Internal Pulldown)
SELB
SELC
0
1
QC0 - QC3
(Internal Pulldown)
0
1
0
(Internal Pullup)
QFB
nMR
FB_SEL0
FB_SEL1
D
Q
1
(Internal Pulldown)
÷2
(Internal Pulldown)
(Internal Pullup)
CLK_EN
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REV. A FEBRUARY 13, 2002
2
PRELIMINARY
ICS87974-01
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-15,
DIFFERENTIAL-TO-LVCMOS CLOCK GENERATOR
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1, 15, 19,
24, 30,
35, 39,
GND
Power
Power supply ground. Connect to ground.
43, 47, 51
Master reset. When HIGH, outputs are enabled.
When LOW, outputs are disabled and dividers are reset.
LVCMOS / LVTTL interface levels.
2
nMR
Input
Pullup
3
4
CLK_EN
SELB
Input
Input
Pullup
Clock enable. When LOW, all outputs except QFB are low.
Selects divide value for Bank B output as described in Table 3.
LVCMOS / LVTTL interface levels.
Pulldown
Selects divide value for Bank C output as described in Table 3.
LVCMOS / LVTTL interface levels.
Selects between the PLL and the reference clock as the input to the
dividers. When HIGH, selects PLL. When LOW, selects the reference
clock. LVCMOS / LVTTL interface levels.
5
6
7
SELC
PLL_SEL
SELA
Input
Input
Input
Pulldown
Pullup
Selects divide value for Bank A output as described in Table 3.
LVCMOS / LVTTL interface levels.
Pulldown
8
9
CLK_SEL
LVCMOS_CLK
CLK0
Input
Input
Pulldown Clock select input. LVCMOS / LVTTL interface levels.
Pulldown Clock input. LVCMOS / LVTTL interface levels.
Pulldown Non-inverting differential clock input.
Pullup Inverting differential clock input
No connect.
10
Input
11
nCLK0
nc
Input
27, 42
12
Unused
Power
Power
VDD
Positive supply pin. Connect to 3.3V.
13
VDDA
Analog supply pin. Connect to 3.3V.
FB_SEL0,
FB_SEL1
QA4, QA3,
Selects divide value for Bank feedback output as described in
Pulldown
14, 20
16, 18,
Input
Table 3. LVCMOS / LVTTL interface levels.
Bank A clock outputs. 7Ω typical output impedance.
LVCMOS / LVTTL interface levels.
Output
21, 23, 25 QA2, QA1, QA0
17, 22, 26
VDDOA
VDDOFB
QFB
Power
Power
Output
Output supply pins. Connect to 3.3V.
28
29
Output supply pins. Connect to 3.3V.
Clock output. LVCMOS / LVTTL interface levels.
Feedback input to phase detector for generating clocks with
Pullup
31
FB_IN
Input
"zero delay". Connect to pin 29. LVCMOS / LVTTL interface levels.
32, 34,
QB4, QB3,
Bank B clock outputs. 7Ω typical output impedance.
LVCMOS interface levels.
Output
Power
Output
Power
Input
36, 38, 40 QB2, QB1, QB0
33, 37, 41
VDDOB
Output supply pins. Connect to 3.3V.
44, 46,
48, 50
QC3, QC2,
QC1, QC0
Bank C clock outputs. 7Ω typical output impedance.
LVCMOS interface levels.
45, 49
VDDOC
Output supply pins. Connect to 3.3V.
Selects VCO ÷ 4 when HIGH. Selects VCO ÷ 2 when LOW.
LVCMOS / LVTTL interface levels.
52
VCO_SEL
Pulldown
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
87974AY-01
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REV. A FEBRUARY 13, 2002
3
PRELIMINARY
ICS87974-01
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-15,
DIFFERENTIAL-TO-LVCMOS CLOCK GENERATOR
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
CIN
Input Capacitance
4
pF
KΩ
KΩ
RPULLUP
Input Pullup Resistor
51
51
RPULLDOWN Input Pulldown Resistor
Power Dissipation Capacitance
(per output)
CPD
VDD, VDDA, *VDDOx = 3.465V
15
pF
*NOTE: VDDOx denotes VDDOA, VDDOB, VDDOC, VDDOFB
.
TABLE 3A. OUTPUT CONTROL PIN FUNCTION TABLE
Inputs
Outputs
nMR
CLK_EN
QA0 - QA4
HiZ
QB0 - QB4
HiZ
QC0 - QC3
HiZ
QFB
0
1
1
X
0
1
HiZ
LOW
LOW
LOW
Enable
Enable
Enable
Enable
Enable
TABLE 3B. OPERATING MODE FUNCTION TABLE
Inputs
TABLE 3C. PLL INPUT FUNCTION TABLE
Inputs
Operating Mode
PLL_SEL
CLK_SEL
PLL Input
0
1
Bypass
PLL
0
1
LVCMOS_CLK
CLK0, nCLK0
TABLE 3D. SELECT PIN FUNCTION TABLE
SELA
QAx
÷ 2
SELB
QBx
÷ 2
SELC
QCx
÷ 4
0
1
0
1
0
1
÷ 4
÷ 4
÷ 6
TABLE 3E. FB SELECT FUNCTION TABLE
Inputs
TABLE 3F. VCO SELECT FUNCTION TABLE
Inputs
Outputs
VCO_SEL
fVCO
VCO/2
VCO/4
FB_SEL0
FB_SEL1
QFB
÷ 4
0
1
0
0
1
1
0
1
0
1
÷ 6
÷ 8
÷ 12
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REV. A FEBRUARY 13, 2002
4
PRELIMINARY
ICS87974-01
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-15,
DIFFERENTIAL-TO-LVCMOS CLOCK GENERATOR
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDDx
Inputs, VI
4.6V
-0.5V to VDD + 0.5V
-0.5V to VDDO + 0.5V
Outputs, VO
Package Thermal Impedance, θJA
Storage Temperature, TSTG
73.2°C/W (0 lfpm)
-65°C to 150°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings
are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in
the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDOX = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum Units
VDD
VDDA
*VDDOx
IDD
Positive Supply Voltage
3.465
3.465
3.465
V
V
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
Analog Supply Current
3.135
3.3
3.135
3.3
V
90
mA
mA
mA
IDDO
IDDA
10
290
*NOTE: VDDOx denotes VDDOA, VDDOB, VDDOC, VDDOFB
.
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = VDDOX = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VIH
VIL
Input High Voltage
2
VDD + 0.3
0.8
V
V
Input Low Voltage
-0.3
FB_SEL0, FB_SEL1,
SELA, SELB, SELC,
CLK_SEL, VCO_SEL
LVCMOS_CLK
VDD = VIN = 3.465V
150
5
µA
µA
µA
µA
IIH
Input High Current
FB_IN, nMR,
VDD = VIN = 3.465V
PLL_SEL, CLK_EN
FB_SEL0, FB_SEL1,
SELA, SELB, SELC,
CLK_SEL, VCO_SEL
LVCMOS_CLK
VIN = 0V, VDD = 3.465V
-5
IIL
Input Low Current
FB_IN, nMR,
PLL_SEL, CLK_EN
V
IN = 0V, VDD = 3.465V
-150
2.4
VOH
VOL
IOZL
IOZH
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Output Tristate Current Low
Output Tristate Current High
V
V
0.5
TBD
TBD
µA
µA
NOTE 1: Outputs terminated with 50Ω to VDDOx/2.
87974AY-01
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REV. A FEBRUARY 13, 2002
5
PRELIMINARY
ICS87974-01
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-15,
DIFFERENTIAL-TO-LVCMOS CLOCK GENERATOR
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = VDDA = VDDOX = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
CLK0
V
DD = VIN = 3.465V
150
5
µA
µA
µA
µA
V
IIH
Input High Current
nCLK0
CLK0
VDD = VIN = 3.465V
VIN = 0V, VDD = 3.465V
VIN = 0V, VDD = 3.465V
-5
-150
IIL
Input Low Current
nCLK0
VPP
Peak-to-Peak Input Voltage
0.15
1.3
VCMR
Common Mode Input Voltage; NOTE 1, 2
GND + 0.5
VDD -0.85
V
NOTE 1: Common mode voltage is defined as VIH.
NOTE 2: For single ended applications, the maximum input voltage for CLK0, nCLK0 is VDD + 0.3V.
TABLE 5. AC CHARACTERISTICS, VDD = VDDA = VDDOX = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Qx ÷ 2, VCO ÷ 2
Qx ÷ 4, VCO ÷ 2
Qx ÷ 6, VCO ÷ 2
Minimum Typical Maximum Units
125
63
MHz
MHz
MHz
MHz
fMAX
Output Frequency
42
fVCO
tPLH
PLL VCO Lock Range; NOTE 5
200
700
Propagation Delay,
Low to High; NOTE 1
Propagation Delay,
High to Low; NOTE 1
PLL_SEL = 0V,
0MHz ≤ f ≤ MHz
PLL_SEL = 0V,
0MHz ≤ f ≤ MHz
ns
ns
tPHL
PLL Reference Zero Delay;
NOTE 2, 5
PLL_SEL = 3.3V, fREF = TBD,
fVCO = TBD
t(Ø)
X - 150ps TBD X X + 150ps
ps
Bank A
±50
±50
±50
350
±100
10
ps
ps
ps
ps
ps
mS
ps
ps
ps
ns
ns
Bank Skew;
NOTE 3, 5
tsk(b)
Bank B
Measured on rising edge at VDDO/2
Measured on rising edge at VDDO/2
Bank C
Output Skew; NOTE 4, 5
Cycle-to-Cycle Jitter; NOTE 5
PLL Lock Time
tsk(o)
tjit(cc)
tL
tR
Output Rise Time
20% to 80% @ 50MHz
20% to 80% @ 50MHz
450
400
tF
Output Fall Time
tPW
Output Pulse Width
tEN
Output Enable Time
Output Disable Time
10
10
tDIS
All parameters measured at fMAX unless noted otherwise.
NOTE 1: Measured from the VDD/2 point of the input to theVDDOx/2 of the output.
NOTE 2: Defined as the time difference between the input reference clock and the averaged feedback
input signal when the PLL is locked and the input reference frequency is stable.
NOTE 3: Defined as skew within a bank with equal load conditions.
NOTE 4: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at VDDOx/2.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
87974AY-01
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REV. A FEBRUARY 13, 2002
6
PRELIMINARY
ICS87974-01
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-15,
DIFFERENTIAL-TO-LVCMOS CLOCK GENERATOR
PARAMETER MEASUREMENT INFORMATION
1.65V±5%
SCOPE
VDD,
VDDA,
VDDOx
Qx
LVCMOS
GND
-1.65V±5%
3.3V OUTPUT LOAD TEST CIRCUIT
VDD
nCLK0
CLK0
VPP
VCMR
Cross Points
GND
DIFFERENTIAL INPUT LEVEL
87974AY-01
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REV. A FEBRUARY 13, 2002
7
PRELIMINARY
ICS87974-01
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-15,
DIFFERENTIAL-TO-LVCMOS CLOCK GENERATOR
VDDOx
2
Qx
Qy
VDDOx
2
tsk(o)
OUTPUT SKEW
V
V
V
DDOx
2
DDOx
2
DDOx
2
QAx, QBx, QCx, QFB
➤
➤
tcycle n+1
tcycle n
➤
➤
tjit(cc) = tcycle n –tcycle n+1
Cycle-to-Cycle Jitter
80%
80%
VSWING
20%
20%
Clock Inputs
and Outputs
tR
tF
INPUT AND OUTPUT RISE AND FALL TIME
87974AY-01
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REV. A FEBRUARY 13, 2002
8
PRELIMINARY
ICS87974-01
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-15,
DIFFERENTIAL-TO-LVCMOS CLOCK GENERATOR
nCLK0
LVCMOS_CLK, CLK0
VDDO
2
x
QAx, QBx, QCx, QFB
tpLH
FIGURE 6 - PROPAGATION DELAY
V
V
V
DDOx
2
DDO x
2
DDO x
2
QAx, QBx, QCx, QFB
tPW
tPERIOD
tPW
tPERIOD
odc =
FIGURE 7 - tPW & tPERIOD
87974AY-01
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REV. A FEBRUARY 13, 2002
9
PRELIMINARY
ICS87974-01
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-15,
DIFFERENTIAL-TO-LVCMOS CLOCK GENERATOR
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock
swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VDD
R1
1K
CLK_IN
+
V_REF
-
C1
0.1uF
R2
1K
FIGURE 1 - SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
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REV. A FEBRUARY 13, 2002
10
PRELIMINARY
ICS87974-01
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-15,
DIFFERENTIAL-TO-LVCMOS CLOCK GENERATOR
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS87974-01 provides sepa-
rate power supplies to isolate any high switching noise from
the outputs to the internal PLL. VDD, VDDA, and VDDOx should be
individually connected to the power supply plane through
vias, and bypass capacitors should be used for each pin. To
achieve optimum jitter performance, power supply isolation
is required. Figure 2 illustrates how a 10Ω resistor along with
a 10µF and a .01µF bypass capacitor should be connected
to each VDDA pin.
3.3V
VDD
.01µF
.01µF
10Ω
VDDA
10 µF
FIGURE 2 - POWER SUPPLY FILTERING
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REV. A FEBRUARY 13, 2002
11
PRELIMINARY
ICS87974-01
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-15,
DIFFERENTIAL-TO-LVCMOS CLOCK GENERATOR
RELIABILITY INFORMATION
TABLE 6. θJAVS. AIR FLOW TABLE
qJA by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
58.0°C/W
47.1°C/W
42.0°C/W
42.3°C/W
36.4°C/W
34.0°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS87974-01 is: 4225
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REV. A FEBRUARY 13, 2002
12
PRELIMINARY
ICS87974-01
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-15,
DIFFERENTIAL-TO-LVCMOS CLOCK GENERATOR
PACKAGE OUTLINE - Y SUFFIX
TABLE 7. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BCC
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
N
A
52
--
--
1.60
0.15
1.45
0.38
0.33
A1
A2
b
0.05
1.35
0.22
0.22
--
1.40
0.32
b1
D
0.30
12.00 BASIC
10.00 BASIC
12.00 BASIC
10.00 BASIC
0.65 BASIC
--
D1
E
E1
e
ccc
ddd
0.45
--
0.10
0.13
--
Reference Document: JEDEC Publication 95, MS-026
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REV. A FEBRUARY 13, 2002
13
PRELIMINARY
ICS87974-01
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-15,
DIFFERENTIAL-TO-LVCMOS CLOCK GENERATOR
TABLE 8. ORDERING INFORMATION
Part/Order Number
ICS87974AY-01
Marking
Package
52 Lead LQFP
Count
160 per tray
500
Temperature
0°C to 70°C
0°C to 70°C
ICS87974AY-01
ICS87974AY-01
ICS87974AY-01T
52 Lead LQFP on Tape and Reel
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or
for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for
use in life support devices or critical medical instruments.
87974AY-01
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REV. A FEBRUARY 13, 2002
14
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IDT
ICS87974AYIT
PLL Based Clock Driver, 14 True Output(s), 0 Inverted Output(s), PQFP52, 10 X 10 MM, 1.40 MM HEIGHT, MS-026, LQFP-52
IDT
ICS87974AYLF
PLL Based Clock Driver, 15 True Output(s), 0 Inverted Output(s), PQFP52, 10 X 10 MM, 1.40 MM HEIGHT, MS-026, LQFP-52
IDT
ICS87974AYLFT
PLL Based Clock Driver, 15 True Output(s), 0 Inverted Output(s), PQFP52, 10 X 10 MM, 1.40 MM HEIGHT, MS-026, LQFP-52
IDT
ICS87974AYT
PLL Based Clock Driver, 15 True Output(s), 0 Inverted Output(s), PQFP52, 10 X 10 MM, 1.40 MM HEIGHT, MS-026, LQFP-52
IDT
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