ICS8745BYT_技术文档

ICS8745B

1:5 DIFFERENTIAL-TO-LVDS

ZERO DELAY CLOCK GENERATOR

Integrated

Circuit

Systems, Inc.

GENERAL DESCRIPTION

FEATURES

The ICS8745B is a highly versatile 1:5 LVDS Clock • 5 differential LVDS outputs designed to meet

ICS

Generator and a member of the HiPerClockS™

family of High Performance Clock Solutions from

ICS. The ICS8745B has a fully integrated PLL

and can be configured as zero delay buffer, multi-

or exceed the requirements of ANSITIA/EIA-644

HiPerClockS™

• Selectable differential clock inputs

• CLKx, nCLKx pairs can accept the following differential

input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL

plier or divider, and has an output frequency range of 31.25MHz

to 700MHz. The Reference Divider, Feedback Divider and

Output Divider are each programmable, thereby allowing for

the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1,

1:2, 1:4, 1:8.The external feedback allows the device to achieve

“zero delay” between the input clock and the output clocks.

The PLL_SEL pin can be used to bypass the PLL for system

test and debug purposes. In bypass mode, the reference clock

is routed around the PLL and into the internal output dividers.

• Output frequency range: 31.25MHz to 700MHz

• Input frequency range: 31.25MHz to 700MHz

• VCO range: 250MHz to 700MHz

• External feedback for “zero delay” clock regeneration

with configurable frequencies

• Programmable dividers allow for the following output-to-input

frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8

• Cycle-to-cycle jitter: 30ps (maximum)

• Output skew: 35ps (maximum)

• Static phase offset: 25ps 125ps

• 3.3V supply voltage

• 0°C to 70°C ambient operating temperature

• Lead-Free package fully RoHS compliant

BLOCK DIAGRAM

PIN ASSIGNMENT

Q0

nQ0

PLL_SEL

Q1

nQ1

÷1, ÷2, ÷4, ÷8,

÷16, ÷32, ÷64

0

CLK0

nCLK0

32 31 30 29 28 27 26 25

Q2

nQ2

0

SEL0

SEL1

1

2

3

4

5

6

7

8

24

23

22

21

20

19

18

17

1

Q3

CLK1

1

Q3

nQ3

V^DDO

Q2

nQ3

nCLK1

CLK0

PLL

Q4

nQ4

nCLK0

CLK1

CLK_SEL

ICS8745B

nQ2

GND

Q1

8:1, 4:1, 2:1, 1:1,

1:2, 1:4, 1:8

nCLK1

CLK_SEL

FB_IN

nFB_IN

MR

nQ1

9

10 11 12 13 14 15 16

SEL0

SEL1

SEL2

SEL3

MR

32-Lead LQFP

7mm x 7mm x 1.4mm package body

Y Package

TopView

8745BY

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REV. B DECEMBER 2, 2004

1

ICS8745B

1:5 DIFFERENTIAL-TO-LVDS

ZERO DELAY CLOCK GENERATOR

Integrated

Circuit

Systems, Inc.

TABLE 1. PIN DESCRIPTIONS

Number

Name

SEL0

Type

Description

1

2

3

4

5

6

Input Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels.

Input Pulldown Non-inverting differential clock input.

SEL1

CLK0

nCLK0

CLK1

nCLK1

Input

Pullup Inverting differential clock input.

Input Pulldown Non-inverting differential clock input.

Input

Pullup Inverting differential clock input.

Clock select input. When HIGH, selects CLK1, nCLK1.

7

CLK_SEL Input Pulldown

When LOW, selects CLK0, nCLK0. LVCMOS / LVTTL interface levels.

Active HIGH Master Reset. When logic HIGH, the internal dividers are reset

causing the true outputs Qx to go low and the inverted outputs nQx to go

high. When logic LOW, the internal dividers and the outputs are enabled.

LVCMOS / LVTTL interface levels.

8

MR

Input Pulldown

Power

9, 32

10

V_DD

Core supply pins.

nFB_IN

FB_IN

SEL2

GND

Input

Pullup

Feedback input to phase detector for regenerating clocks with "zero delay".

11

Input Pulldown Feedback input to phase detector for regenerating clocks with "zero delay".

Input Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels.

12

13, 19, 25

14, 15

16, 22, 28

17, 18

20, 21

23, 24

26, 27

29

Power

Power supply ground.

nQ0, Q0 Output

V_DDOPower

Differential output pair. LVDS interface levels.

Output supply pins.

nQ1, Q1 Output

nQ2, Q2 Output

nQ3, Q3 Output

nQ4, Q4 Output

Differential output pair. LVDS interface levels.

SEL3

V_DDA

Input Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels.

30

Power

Input

Analog supply pin.

Selects between the PLL and reference clock as the input to the dividers.

When LOW, selects reference clock. LVCMOS / LVTTL interface levels.

31

PLL_SEL

Pullup

NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

TABLE 2. PIN CHARACTERISTICS

Symbol

C_IN

Parameter

Test Conditions

Minimum Typical Maximum Units

Input Capacitance

Input Pullup Resistor

Input Pulldown Resistor

4

pF

kΩ

R_PULLUP

R_PULLDOWN

51

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REV. B DECEMBER 2, 2004

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ICS8745B

1:5 DIFFERENTIAL-TO-LVDS

ZERO DELAY CLOCK GENERATOR

Integrated

Circuit

Systems, Inc.

TABLE 3A. CONTROL INPUT FUNCTION TABLE

Outputs

Inputs

SEL0

PLL_SEL = 1

PLL Enable Mode

Q0:Q4, nQ0:nQ4

SEL3

SEL2

SEL1

Reference Frequency Range (MHz)*

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

250 - 700

125 - 350

62.5 - 175

31.25 - 87.5

250 - 700

125 - 350

62.5 - 175

250 -700

÷ 1

÷ 2

÷ 4

÷ 8

x 2

x 4

x 8

125 - 350

250 - 700

125 - 350

62.5 - 175

31.25 - 87.5

62.5 - 175

31.25 - 87.5

*NOTE: VCO frequency range for all configurations above is 250MHz to 700MHz.

TABLE 3B. PLL BYPASS FUNCTION TABLE

Inputs

Outputs

PLL_SEL = 0

PLL Bypass Mode

SEL3

SEL2

SEL1

SEL0

Q0:Q4, nQ0:nQ4

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

÷ 4

÷ 8

÷ 16

÷ 32

÷ 64

÷ 2

÷ 4

÷ 1

÷ 2

÷ 1

8745BY

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REV. B DECEMBER 2, 2004

3

ICS8745B

1:5 DIFFERENTIAL-TO-LVDS

ZERO DELAY CLOCK GENERATOR

Integrated

Circuit

Systems, Inc.

ABSOLUTE MAXIMUM RATINGS

SupplyVoltage, V

4.6V

NOTE: Stresses beyond those listed under Absolute

Maximum Ratings may cause permanent damage to the

device.These ratings are stress specifications only.Functional

operation of product at these conditions or any conditions be-

yond those listed in the DC Characteristics or AC Character-

istics is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect product reliability.

DD

Inputs, V

-0.5V to V_DD+ 0.5V

I

Outputs, I_O

Continuous Current

Surge Current

10mA

15mA

PackageThermal Impedance, θ_JA47.9°C/W (0 lfpm)

StorageTemperature,T -65°C to 150°C

STG

TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, V_DD= V_DDA= V_DDO= 3.3V 5ꢀ, TA = 0°C TO 70°C

Symbol Parameter Test Conditions Minimum Typical Maximum Units

V_DD

V_DDA

V_DDO

I_DD

Core Supply Voltage

3.135

3.3

3.465

125

V

Analog Supply Voltage

Output Supply Voltage

Power Supply Current

Analog Supply Current

Output Supply Current

V

mA

I_DDA

I_DDO

17

59

TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, V_DD= V_DDA= V_DDO= 3.3V 5ꢀ, TA = 0°C TO 70°C

Symbol Parameter Test Conditions Minimum Typical Maximum Units

V_IH

V_IL

Input High Voltage

2

V_DD+ 0.3

0.8

V

Input Low Voltage

-0.3

CLK_SEL, MR, SEL0,

SEL1, SEL2, SEL3

V

_DD= V_IN= 3.465V

150

5

µA

I_IH

Input High Current

PLL_SEL

V_DD= V_IN= 3.465V

CLK_SEL, MR, SEL0,

SEL1, SEL2, SEL3

-5

V

_DD= 3.465V, V_IN= 0V

I_IL

Input Low Current

PLL_SEL

-150

µA

V_DD= 3.465V, V_IN= 0V

TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, V_DD= V_DDA= V_DDO= 3.3V 5ꢀ, TA = 0°C TO 70°C

Symbol Parameter

Test Conditions

Minimum Typical Maximum Units

CLK0, CLK1, FB_IN

nCLK0, nCLK1, nFB_IN

CLK0, CLK1, FB_IN

nCLK0, nCLK1, nFB_IN

V

_DD= V_IN= 3.465V

150

5

µA

V

Input

I_IH

High Current

V

_DD= 3.465V, V_IN= 0V

-5

-150

Input

I_IL

Low Current

V

V_PP

Peak-to-Peak Input Voltage

0.15

1.3

V_CMR

Common Mode Input Voltage; NOTE 1, 2

GND + 0.5

V_DD- 0.85

V

NOTE 1: Common mode voltage is defined as V_IH.

NOTE 2: For single ended applications, the maximum input voltage for CLK0, nCLK0 and CLK1, nCLK1 is V_DD+ 0.3V.

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REV. B DECEMBER 2, 2004

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ICS8745B

1:5 DIFFERENTIAL-TO-LVDS

ZERO DELAY CLOCK GENERATOR

Integrated

Circuit

Systems, Inc.

TABLE 4D. LVDS DC CHARACTERISTICS, V_DD= V_DDA= V_DDO= 3.3V 5ꢀ, TA = 0°C TO 70°C

Symbol Parameter

Test Conditions

Minimum

Typical

440

0

Maximum Units

V_OD

Differential Output Voltage

320

550

50

mV

V

Δ V_OD

V_OS

V_ODMagnitude Change

Offset Voltage

1.05

1.2

1.35

25

Δ V_OS

V_OSMagnitude Change

mV

TABLE 5. INPUT FREQUENCY CHARACTERISTICS, V_DD= V_DDA= V_DDO= 3.3V 5ꢀ, TA = 0°C TO 70°C

Symbol Parameter

f_INInput Frequency

Test Conditions

PLL_SEL = 1

PLL_SEL = 0

Minimum Typical Maximum Units

31.25

700

MHz

CLK0, nCLK0,

CLK1, nCLK1

TABLE 6. AC CHARACTERISTICS, V_DD= V_DDA= V_DDO= 3.3V 5ꢀ, TA = 0°C TO 70°C

Symbol Parameter

Test Conditions

Minimum

Typical

Maximum

Units

MHz

ns

f_MAX

Output Frequency

700

3.7

150

35

t_PD

Propagation Delay; NOTE 1

Static Phase Offset; NOTE 2, 5

Output Skew; NOTE 3, 5

Cycle-to-Cycle Jitter; NOTE 5, 6

Phase Jitter; NOTE 4, 5, 6

Output Duty Cycle

PLL_SEL = 0V, f ≤ 700MHz

3.1

3.4

25

tsk(Ø)

tsk(o)

tjit(cc)

tjit(θ)

odc

PLL_SEL = 3.3V

-100

ps

30

ps

52

ps

46

50

54

ꢀ

t_L

PLL Lock Time

1

ms

ps

t_R/ t_F

Output Rise/Fall Time; NOTE 7

200

700

NOTE 1: Measured from the differential input crossing point to the differential output crossing point.

NOTE 2: Defined as the time difference between the input reference clock and the averaged feedback

input signal across all conditions, when the PLL is locked and the input reference frequency is stable.

NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions.

Measured at the output differential cross points.

NOTE 4: Phase jitter is dependent on the input source used.

NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.

NOTE 6: Characterized at VCO frequency of 622MHz.

NOTE 7: Measured from the 20ꢀ to 80ꢀ points. Guaranteed by characterization. Not production tested.

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REV. B DECEMBER 2, 2004

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ICS8745B

1:5 DIFFERENTIAL-TO-LVDS

ZERO DELAY CLOCK GENERATOR

Integrated

Circuit

Systems, Inc.

PARAMETER MEASUREMENT INFORMATION

V_DD

3.3V

SCOPE

Qx

nCLK0,

nCLK1

Power Supply

Float GND

V_PP

V_CMR

Cross Points

LVDS

+

-

CLK0,

CLK1

nQx

GND

3.3V OUTPUT LOAD AC TEST CIRCUIT

DIFFERENTIAL INPUT LEVEL

nCLK0,

nCLK1

V_OH

V_OL

nQx

Qx

CLK0,

CLK1

V_OH

V_OL

nFB_IN

nQy

FB_IN

Qy

➤

t(Ø)

➤

tsk(o)

tjit(Ø) = t(Ø) — t(Ø) mean = Phase Jitter

t(Ø) mean = Static Phase Offset

(where t(Ø) is any random sample, and t(Ø) mean is the average

of the sampled cycles measured on controlled edges)

PHASE JITTER AND STATIC PHASE OFFSET

OUTPUT SKEW

nQ0:nQ4

Q0:Q4

80ꢀ

t_F

80ꢀ

V_OD

➤

Clock

20ꢀ

tcycle n

tcycle n+1

➤

Outputs

t_R

tjit(cc) = tcycle n –tcycle n+1

1000 Cycles

CYLE-TO-CYCLE JITTER

OUTPUT RISE/FALL TIME

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REV. B DECEMBER 2, 2004

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ICS8745B

1:5 DIFFERENTIAL-TO-LVDS

ZERO DELAY CLOCK GENERATOR

Integrated

Circuit

Systems, Inc.

nCLK0,

nCLK1

nQ0:nQ4

Q0:Q4

CLK0,

CLK1

Pulse Width

t_PERIOD

nQ0:nQ4

Q0:Q4

t_PW

odc =

t_PD

t_PERIOD

PROPAGATION DELAY

OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD

V_DD

out

➤

out

DC Input

LVDS

DC Input

100

V

_OD/Δ V_OD

V_OS/Δ V_OS

➤

OFFSET VOLTAGE SETUP

DIFFERENTIAL OUTPUT VOLTAGE SETUP

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REV. B DECEMBER 2, 2004

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ICS8745B

1:5 DIFFERENTIAL-TO-LVDS

ZERO DELAY CLOCK GENERATOR

Integrated

Circuit

Systems, Inc.

APPLICATION INFORMATION

WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS

Figure 1 shows how the differential input can be wired to accept of R1 and R2 might need to be adjusted to position theV_REF in

single ended levels. The reference voltage V_REF ~ V_DD/2 is the center of the input voltage swing. For example, if the input

generated by the bias resistors R1, R2 and C1.This bias circuit clock swing is only 2.5V andV_DD= 3.3V, V_REF should be 1.25V

should be located as close as possible to the input pin.The ratio and R2/R1 = 0.609.

VDD

R1

1K

Single Ended Clock Input

CLKx

V_REF

nCLKx

C1

0.1u

R2

1K

FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT

LVDS DRIVER TERMINATION

A general LVDS interface is shown in Figure 2. In a 100Ω differ-

ential transmission line environment, LVDS drivers require a

matched load termination of 100Ω across near the receiver in-

put. For a multiple LVDS outputs buffer, if only partial outputs

are used, it is recommended to terminate the un-used outputs.

3.3V

LVDS_Driv er

+

R1

100

-

100 Ohm Differiential Transmission Line

FIGURE 2. TYPICAL LVDS DRIVER TERMINATION

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REV. B DECEMBER 2, 2004

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ICS8745B

1:5 DIFFERENTIAL-TO-LVDS

ZERO DELAY CLOCK GENERATOR

Integrated

Circuit

Systems, Inc.

POWER SUPPLY FILTERING TECHNIQUES

As in any high speed analog circuitry, the power supply pins

are vulnerable to random noise.The ICS8745B provides sepa-

rate power supplies to isolate any high switching

noise from the outputs to the internal PLL.V_DD, V_DDA, and V_DDO

should be individually connected to the power supply

plane through vias, and bypass capacitors should be

used for each pin. To achieve optimum jitter performance,

power supply isolation is required. Figure 3 illustrates how

a 10Ω resistor along with a 10μF and a .01μF bypass

capacitor should be connected to each V_DDApin.

3.3V

V_DD

.01μF

10Ω

V_DDA

10 μF

FIGURE 3. POWER SUPPLY FILTERING

DIFFERENTIAL CLOCK INPUT INTERFACE

The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL here are examples only. Please consult with the vendor of the

and other differential signals. Both V_SWINGandV_OHmust meet the driver component to confirm the driver termination requirements.

V_PPand V_CMRinput requirements. Figures 4A to 4D show inter- For example in Figure 4A, the input termination applies for ICS

face examples for the HiPerClockS CLK/nCLK input driven by HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver

the most common driver types.The input interfaces suggested from another vendor, use their termination recommendation.

3.3V

1.8V

Zo = 50 Ohm

CLK

Zo = 50 Ohm

CLK

Zo = 50 Ohm

nCLK

Zo = 50 Ohm

HiPerClockS

Input

LVPECL

nCLK

HiPerClockS

Input

LVHSTL

R1

50

R2

50

ICS

HiPerClockS

R1

50

R2

50

LVHSTL Driver

R3

50

FIGURE 4A. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY

ICS HIPERCLOCKS LVHSTL DRIVER

FIGURE 4B. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY

3.3V LVPECL DRIVER

3.3V

Zo = 50 Ohm

3.3V

R3

125

R4

125

LVDS_Driver

Zo = 50 Ohm

CLK

R1

100

nCLK

Receiv er

nCLK

HiPerClockS

Input

Zo = 50 Ohm

LVPECL

R1

84

R2

84

FIGURE 4C. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY

3.3V LVPECL DRIVER

FIGURE 4D. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY

3.3V LVDS DRIVER

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REV. B DECEMBER 2, 2004

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ICS8745B

1:5 DIFFERENTIAL-TO-LVDS

ZERO DELAY CLOCK GENERATOR

Integrated

Circuit

Systems, Inc.

LAYOUT GUIDELINE

The schematic of the ICS8745B layout example is shown in

Figure 5A. The ICS8745B recommended PCB board layout

tem will depend on the selected component types, the den-

sity of the components, the density of the traces, and the

for this example is shown in Figure 5B. This layout example stack up of the P.C. board.

is used as a general guideline. The layout in the actual sys-

VDD

SP = Space (i.e. not intstalled)

R7

VDD

VDDA

RU2

SP

RU3

1K

RU4

1K

RU5

SP

RU6

1K

RU7

SP

10

C11

0.01u

CLK_SEL

PLL_SEL

SEL0

C16

10u

SEL1

SEL2

SEL3

Zo = 50 Ohm

(77.76 MHz)

+

-

RD2

1K

RD3

SP

RD4

SP

RD5

1K

RD6

SP

RD7

1K

R4

100

VDD

VDDO

LVDS_input

U3

3.3V

(155.5 MHz)

SEL0

SEL1

Zo = 50 Ohm

1

24

SEL0

SEL1

Q3

nQ3

VDDO

Q2

nQ2

GND

Q1

2

3

4

5

6

7

8

23

22

21

20

19

18

17

CLK0

nCLK0

CLK1

nCLK1

CLK_SEL

MR

Zo = 50 Ohm

CLK_SEL

VDD=3.3V

3.3V PECL Driver

nQ1

VDDO=3.3V

R8A

50

R9

50

8745

SEL[3:0] = 0101,

Divide by 2

R10

50

SEL2

R2

100

Decoupling capacitor located near the power pins

VDD

VDDO

(U1-9)

(U1-32)

(U1-22)

(U1-28)

(U1-16)

C1

0.1uF

C6

0.1uF

C4

0.1uF

C5

0.1uF

C2

0.1uF

FIGURE 5A. ICS8745B LVDS ZERO DELAY BUFFER SCHEMATIC EXAMPLE

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1:5 DIFFERENTIAL-TO-LVDS

ZERO DELAY CLOCK GENERATOR

Integrated

Circuit

Systems, Inc.

The following component footprints are used in this layout

example:

trace delay might be restricted by the available space on the board

and the component location.While routing the traces, the clock

signal traces should be routed first and should be locked prior to

routing other signal traces.

All the resistors and capacitors are size 0603.

POWER AND GROUNDING

• The differential 50Ω output traces should have same

Place the decoupling capacitors C1, C6, C2, C4, and C5, as

close as possible to the power pins. If space allows, placement

of the decoupling capacitor on the component side is preferred.

This can reduce unwanted inductance between the decoupling

capacitor and the power pin caused by the via.

length.

• Avoid sharp angles on the clock trace.Sharp angle

turns cause the characteristic impedance to change on

the transmission lines.

• Keep the clock traces on the same layer.Whenever pos-

sible, avoid placing vias on the clock traces. Placement

of vias on the traces can affect the trace characteristic

impedance and hence degrade signal integrity.

Maximize the power and ground pad sizes and number of vias

capacitors.This can reduce the inductance between the power

and ground planes and the component power and ground pins.

• To prevent cross talk, avoid routing other signal traces in

parallel with the clock traces. If running parallel traces is

unavoidable, allow a separation of at least three trace

widths between the differential clock trace and the other

signal trace.

The RC filter consisting of R7, C11, and C16 should be placed

as close to the V_DDApin as possible.

CLOCK TRACES AND TERMINATION

Poor signal integrity can degrade the system performance or

cause system failure. In synchronous high-speed digital systems,

the clock signal is less tolerant to poor signal integrity than other

signals. Any ringing on the rising or falling edge or excessive ring

back can cause system failure. The shape of the trace and the

• Make sure no other signal traces are routed between the

clock trace pair.

• The matching termination resistors should be located as

close to the receiver input pins as possible.

GND

VDDO

VDD

R7

C16

C11

C5

C6

U1

Pin 1

C4

VDDA

VIA

50 Ohm

Traces

C1

C2

FIGURE 5B. PCB BOARD LAYOUT FOR ICS8745B

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REV. B DECEMBER 2, 2004

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ICS8745B

1:5 DIFFERENTIAL-TO-LVDS

ZERO DELAY CLOCK GENERATOR

Integrated

Circuit

Systems, Inc.

RELIABILITY INFORMATION

TABLE 7. θ_JAVS. AIR FLOW TABLE FOR 32 LEAD LQFP

θ_JAbyVelocity (Linear Feet per Minute)

0

200

500

Single-Layer PCB, JEDEC Standard Test Boards

Multi-Layer PCB, JEDEC Standard Test Boards

67.8°C/W

55.9°C/W

50.1°C/W

47.9°C/W

42.1°C/W

39.4°C/W

NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.

TRANSISTOR COUNT

The transistor count for ICS8745B is: 2772

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REV. B DECEMBER 2, 2004

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ICS8745B

1:5 DIFFERENTIAL-TO-LVDS

ZERO DELAY CLOCK GENERATOR

Integrated

Circuit

Systems, Inc.

PACKAGE OUTLINE - Y SUFFIX FOR 32 LEAD LQFP

TABLE 8. PACKAGE DIMENSIONS

JEDEC VARIATION

ALL DIMENSIONS IN MILLIMETERS

BBA

SYMBOL

MINIMUM

NOMINAL

MAXIMUM

N

A

32

--

1.60

0.15

1.45

0.45

0.20

A1

A2

b

0.05

1.35

0.30

0.09

1.40

0.37

c

--

D

9.00 BASIC

7.00 BASIC

5.60 Ref.

9.00 BASIC

7.00 BASIC

5.60 Ref.

0.80 BASIC

0.60

D1

D2

E

E1

E2

e

L

0.45

0.75

θ

--

0°

7°

ccc

--

0.10

Reference Document: JEDEC Publication 95, MS-026

8745BY

www.icst.com/products/hiperclocks.html

REV. B DECEMBER 2, 2004

13

ICS8745B

1:5 DIFFERENTIAL-TO-LVDS

ZERO DELAY CLOCK GENERATOR

Integrated

Circuit

Systems, Inc.

TABLE 9. ORDERING INFORMATION

Part/Order Number

ICS8745BY

Marking

Package

Shipping Packaging Temperature

ICS8745BY

32 Lead LQFP

tray

0°C to 70°C

ICS8745BYT

32 Lead LQFP

1000 tape & reel

tray

ICS8745BYLF

ICS8745BYLFT

ICS8745BYLF

32 Lead "Lead-Free" LQFP

1000 tape & reel

NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.

The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.

While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or

for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal

commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not

recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for

use in life support devices or critical medical instruments.

8745BY

www.icst.com/products/hiperclocks.html

REV. B DECEMBER 2, 2004

14

ICS8745B

1:5 DIFFERENTIAL-TO-LVDS

ZERO DELAY CLOCK GENERATOR

Integrated

Circuit

Systems, Inc.

REVISION HISTORY SHEET

Rev

Table

Page

Description of Change

Date

LVDS DC Characteristics Table - modified V_OS0.90V min. to 1.05V min,

1.15V typical to 1.2V typical, and 1.4V max. to 1.35V max.

Added Lead-Free bullet.

Ordering Information Table - added Lead-Free part.

Features Section - delete bullet, "Industrial temperature available upon

request."

B

T4D

5

3/17/04

1

14

1

B

12/2/04

3/18/05

T9

14

Ordering Information Table - added Lead-Free note.

8745BY

www.icst.com/products/hiperclocks.html

REV. B DECEMBER 2, 2004

15


型号：	ICS8745BYT
厂家：	INTEGRATED CIRCUIT SOLUTION INC
描述：	1:5 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR 1 ： 5差分至LVDS零延迟时钟发生器时钟发生器逻辑集成电路驱动
文件：	总15页 (文件大小：185K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ICS8745BYT [ICSI]

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