ICS8752BYLF [IDT]
Low Skew Clock Driver, 8 True Output(s), 0 Inverted Output(s), CMOS, PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, MS-026, LQFP-32;
| 型号： | ICS8752BYLF |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Low Skew Clock Driver, 8 True Output(s), 0 Inverted Output(s), CMOS, PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, MS-026, LQFP-32 驱动 逻辑集成电路 |
| 文件： | 总9页 (文件大小：105K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
ICS8752
Integrated
Circuit
Systems, Incꢀ
LOW SKEW 1-TO-8
LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
GENERAL DESCRIPTION
FEATURES
The ICS8752 is a low voltage, low skew clock
• Fully integrated PLL
,&6
generator and a member of the HiPerClockS™
• 8 LVCMOS outputs, 7Ω typical output impedance
• External feedback for ”zero delay” clock regeneration
• Output frequency up to 240MHz
HiPerClockS™
family of High Performance Clock Solutions
from ICS. With output frequencies up to 240MHz
the ICS8752 is targeted for high performance
clock applications. Along with a fully integrated PLL the
ICS8752 contains frequency configurable outputs and an
external feedback input for regenerating clocks with “zero de-
lay”.
• VCO range 220MHz to 480MHz
• Dual LVCMOS clock inputs for redundant clock applications
• LVCMOS control inputs
Dual clock inputs, REF_CLK1 and REF_CLK2, support
redundant clock applications. The CLK_SEL input determines
which reference clock is used. The output divider values of
Bank A and B are controlled by the DIV_SELA0:1, and
DIV_SELB0:1, respectively.
• Bank skew, tsk(b), 100ps
• Output skew, tsk(o), 150ps
• Multiple-frequency skew, tsk(w), 200ps
• Cycle-to-cycle jitter, tjit(cc), 100ps, typical
• PLL reference zero delay, t(Ø), ±150ps, typical
• Full 3.3V
For test and system debug purposes the PLL_SEL input
allows the PLL to be bypassed. When HIGH the MR/nOE
input resets the internal dividers and forces the outputs to
the high impedance state.
The low impedance LVCMOS outputs of the ICS8752 are
designed to drive terminated transmission lines. The effec-
tive fanout of each output can be doubled by utilizing the
ability of each output to drive two series terminated trans-
mission lines.
• 32 lead low-profile QFP (LQFP)
• 7mm x 7mm x 1.4mm package body, 0.8mm lead pitch
• 0°C to 70°C ambient operating temperature
• Functionally compatible with the MPC952 in some applications
BLOCK DIAGRAM
PIN ASSIGNMENT
PLL_SEL
PLL
FB_IN
PHASE
÷2
÷4
00
01
10
11
VCO
0
32 31 30 29 28 27 26 25
DETECTOR
REF_CLK1
REF_CLK2
CLK_SEL
1
0
QA0
QA1
QA2
QA3
1
÷6
DIV_SELB0
DIV_SELB1
DIV_SELA0
DIV_SELA1
MR/nOE
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
GND
QB1
÷8
÷12
QB0
DIV_SELA1
DIV_SELA0
VDDO
VDDO
QA3
ICS8752
00
01
10
11
REF_CLK1
GND
QB0
QB1
QB2
QB3
QA2
FB_IN
GND
DIV_SELB1
DIV_SELB0
9
10 11 12 13 14 15 16
32-Lead LQFP
Y package
Top View
MR/nOE
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
8752
www.icst.com/products/hiperclocks.html
REV. B MAY 4, 2001
1
PRELIMINARY
ICS8752
Integrated
Circuit
Systems, Incꢀ
LOW SKEW 1-TO-8
LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Pulldown
Description
DIV_SELB0,
DIV_SELB1
DIV_SELA0,
DIV_SELA1
Determines output divider values for bank B as described in Table 3.
LVCMOS / LVTTL interface levels.
Determines output divider values for bank A as described in Table 3.
LVCMOS / LVTTL interface levels.
When HIGH, resets dividers and forces output into high impedance state.
LVCMOS / LVTTL interface levels.
1, 2
Input
Input
3, 4
Pulldown
Pulldown
5
6
MR/nOE
Input
Input
REF_CLK1
Pulldown Reference clock input. LVCMOS interface levels.
7, 13
17, 24,
28, 29
GND
FB_IN
Power
Input
Input
Ground pin. Connect to ground.
Feedback input to phase detector for regenerating clocks with "zero delay".
LVCMOS / LVTTL interface levels.
Selects between REF_CLK1 or REF_CLK2 as phase detector reference.
Pulldown When LOW selects REF_CLK1. When HIGH selects REF_CLK2.
LVCMOS / LVTTL interface levels.
8
Pulldown
9
CLK_SEL
10
11, 32
12
VDDA
VDDI
Power
Power
Input
PLL power supply pin. Connect to 3.3V.
Input and core power supply pin. Connect to 3.3V.
Pulldown Reference clock input. LVCMOS interface levels.
REF_CLK2
14, 15,
18, 19
16, 20,
21, 25
22, 23,
26, 27
QA0, QA1,
QA2, QA3
Bank A clock outputs.7Ω typical output impedance.
LVCMOS interface levels.
Output
Power
VDDO
Output power supply pins. Connect to 3.3V.
QB0, QB1,
QB2, QB3
Bank B clock outputs.7Ω typical output impedance.
LVCMOS interface levels.
Output
30
31
32
nc
Unused
Unused pin.
Selects between the PLL and the reference clock as the input to the
dividers. When HIGH select PLL. When LOW selects reference clock.
LVCMOS / LVTTL interface levels.
PLL_SEL
VDDI
Input
Pullup
Power
Input power supply pin. Connect to 3.3V.
8752
www.icst.com/products/hiperclocks.html
REV. B MAY 4, 2001
2
PRELIMINARY
ICS8752
Integrated
Circuit
Systems, Incꢀ
LOW SKEW 1-TO-8
LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
Test Conditions
Minimum Typical Maximum Units
REF_CLK1,
REF_CLK2
PLL_SEL,
FB_IN,
TBD
pF
Input
Capacitance
CIN
CLK_SEL
DIV_SELA1,
DIV_SELA0,
DIV_SELB1,
DIV_SELB0
TBD
pF
Input
Pullup Resistor
Input
RPULLUP
51
51
KΩ
KΩ
RPULLDOWN Pulldown
Resistor
Power Dissipation
CPD
Capacitance
(per output)
Output
VDDA, VDDI, VDDO = 3.47V
TBD
7
pF
ROUT
Ω
Impedance
TABLE 3. CONTROL INPUTS FUNCTION TABLE
Inputs
Outputs
DIV_
SELA1
DIV_
SELA0
DIV_
SELB1
DIV_
SELB0
MR/nOE PLL_SEL CLK_SEL
QAx
QBx
1
0
0
0
0
0
0
0
0
0
0
0
0
X
1
1
1
1
0
0
0
0
0
0
0
0
X
X
X
X
X
0
0
0
0
1
1
1
1
X
0
0
1
1
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
0
1
0
1
X
0
0
1
1
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
0
1
0
1
Hi-Z
Hi-Z
fVCO/2
fVCO/4
fVCO/6
fVCO/8
fVCO/4
fVCO/6
fVCO/8
fVCO/12
fREF_CLK1/2
fREF_CLK1/4
fREF_CLK1/6
fREF_CLK1/8
fREF_CLK2/2
fREF_CLK2/4
fREF_CLK2/6
fREF_CLK2/8
fREF_CLK1/4
fREF_CLK1/6
fREF_CLK1/8
fREF_CLK1/12
fREF_CLK2/4
fREF_CLK2/6
fREF_CLK2/8
fREF_CLK2/12
NOTE: For normal operation MR/nOE is LOW. When MR/nOE is HIGH all ouputs are disabled.
8752
www.icst.com/products/hiperclocks.html
REV. B MAY 4, 2001
3
PRELIMINARY
ICS8752
Integrated
Circuit
Systems, Incꢀ
LOW SKEW 1-TO-8
LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
TABLE 4A. QA OUTPUT FREQUENCY W/FB_IN = QB
QB
OUPUT
FB_IN DIV_SELB1 DIV_SELB0
DIVIDER
INPUTS
OUTPUT
REF_CLK1,
REF_CLK2
(MHz)
QA
QA
Multiplier
(NOTE 1)
OUPUT
DIVIDER
MODE
DIV_SELA1 DIV_SELA0
MODE
MIN
MAX
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
0
1
÷2
÷4
÷6
÷8
÷2
÷4
÷6
÷8
÷2
÷4
÷6
÷8
÷2
÷4
÷6
÷8
2
1
QB
QB
QB
QB
0
0
1
1
0
1
0
1
÷4
62.5
41.67
31.25
20.83
125
0.667
0.5
3
1.5
1
÷6
÷8
83.33
62.5
0.75
4
2
1.33
1
6
3
÷12
41.67
2
1.5
NOTE 1: NOTE 1: VCO frequency range is 250MHz to 500MHz.
NOTE 2: QA output frequency equal to reference clock frequency times the multiplier;
QB output frequency equal to reference clock.
8752
www.icst.com/products/hiperclocks.html
REV. B MAY 4, 2001
4
PRELIMINARY
ICS8752
Integrated
Circuit
Systems, Incꢀ
LOW SKEW 1-TO-8
LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
TABLE 4B. QB OUTPUT FREQUENCY W/FB_IN = QA
QA
OUPUT
FB_IN DIV_SELA1 DIV_SELA0
DIVIDER
INPUTS
OUTPUT
REF_CLK1,
REF_CLK2
(MHz)
QB
QB
Multiplier
(NOTE 2)
OUPUT
DIVIDER
MODE
DIV_SELB1 DIV_SELB0
MODE
MIN
MAX
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
0
1
÷4
÷6
0.5
0.333
0.25
0.083
1
QA
QA
QA
QA
0
0
1
1
0
1
0
1
÷2
÷4
÷6
÷8
125
250
÷8
÷12
÷4
÷6
0.667
0.5
62.5
125
÷8
÷12
÷4
0.333
1.5
÷6
1
41.67 83.33
÷8
0.75
0.5
÷12
÷4
2
÷6
1.333
1
31.25
62.5
÷8
÷12
0.667
NOTE 1: VCO frequency range is 250MHz to 500MHz.
NOTE 2: QB output frequency equal to reference clock frequency times the multiplier;
QA output frequency equal to reference clock.
TABLE 5. PLL INPUT REFERENCE CHARACTERISTICS, VDDI=VDDA=3.3V±5%, TA=0°C TO 70°C
Symbol
fREF
tR
Parameter
Test Conditions
Minimum Typical Maximum Units
Input Reference Frequency
Input Rise Time
20
240
TBD
TBD
TBD
MHz
ns
Measured at 20% to 80% points
Measured at 20% to 80% point
tF
Input Fall Time
ns
tDC
Input Reference Duty Cycle
TBD
%
8752
www.icst.com/products/hiperclocks.html
REV. B MAY 4, 2001
5
PRELIMINARY
ICS8752
Integrated
Circuit
Systems, Incꢀ
LOW SKEW 1-TO-8
LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
Inputs
Outputs
4.6V
-0.5V to VDD+0.5 V
-0.5V to VDD+0.5V
Ambient Operating Temperature 0°C to 70°C
Storage Temperature -65°C to 150°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any conditions beyond those listed in the DC Character-
istics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product
reliability.
TABLE 6A. POWER SUPPLY DC CHARACTERISTICS, VDDI=VDDA=VDDO=3.3V±5%, TA=0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VDDI
VDDA
VDDO
IDD
Input Power Supply Voltage
3.135
3.135
3.135
3.3
3.3
3.3
3.465
3.465
3.465
70
V
V
Analog Power Supply Voltage
Output Power Supply Voltage
Input Power Supply Current
V
mA
TABLE 6B. LVCMOS/LVTTL DC CHARACTERISTICS, VDDI=VDDA=VDDO=3.3V±5%, TA=0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VIH
VIL
Input High Voltage
2
3.765
0.8
V
V
Input Low Voltage
-0.3
REF_CLK1, REF_CLK2
FB_IN, CLK_SEL,
DIV_SELA1, DIV_SELA0,
DIV_SELB1, DIV_SELB0,
MR/nOE
VIN = 3.465V
VIN = 3.465V
VIN = 0V
150
5
µA
µA
µA
IIH
IIL
Input High Current
PLL_SEL
REF_CLK1, REF_CLK2
FB_IN, CLK_SEL,
DIV_SELA1, DIV_SELA0,
DIV_SELB1, DIV_SELB0,
MR/nOE
-5
Input Low Current
PLL_SEL
VIN = 0V
-150
2.6
µA
V
VDDO = 3.135V
IOH = -36mA
VDDO = 3.135V
IOL = 36mA
VOH
VOL
Output High Voltage
Output Low Voltage
0.5
V
8752
www.icst.com/products/hiperclocks.html
REV. B MAY 4, 2001
6
PRELIMINARY
ICS8752
Integrated
Circuit
Systems, Incꢀ
LOW SKEW 1-TO-8
LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
TABLE 7. AC CHARACTERISTICS, VDDI=VDDA=VDDO=3.3V±5%, TA=0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
÷2
÷4
240
120
80
MHz
MHz
MHz
MHz
MHz
MHz
fMAX
Maximum Output Frequency
÷6
÷8
60
÷12
40
fVCO
tpLH
PLL VCO Lock Range
240
480
PLL_SEL=0V,
0MHz ≤ f ≤ 240MHz
PLL_SEL=0V,
Propagation Delay, Low-to-High
TBD
TBD
TBD
ns
ns
ps
tpHL
Propagation Delay, High-to-Low
TBD
0MHz ≤ f ≤ 240MHz
PLL_SEL=3.3V, fREF=TBD,
fVCO=TBD
PLL Reference Zero Delay;
NOTE 2
t(Ø)
±150
Bank A
Bank Skew; NOTE 3
Bank B
75
ps
ps
Measured on rising edge at
VDDO/2
tsk(b)
100
Measured on rising edge at
VDDO/2
Measured on rising edge at
VDDO/2
tsk(o)
tsk(w)
Output Skew; NOTE 4
150
200
ps
ps
Multiple Frequency Skew;
NOTE 5
tjit(cc)
tjit(Ø)
tL
Cycle-to-Cycle Jitter; NOTE 6
Phase Jitter
100
150
ps
ps
PLL Lock Time
1
mS
ps
tR
Output Rise Time
Output Fall Time
20% to 80%
20% to 80%
300
300
800
800
tF
ps
tCYCLE/2
-500
tCYCLE/2
+500
0MHz ≤ f ≤ 240MHz
tCYCLE/2
4.0
ps
tPW
Output Pulse Width
f = 120MHz
3.65
4.35
TBD
TBD
ns
ns
ns
tEN
Output Enable Time
Output Disable Time
tDIS
NOTE 1: All parameters measured at fMAX unless noted otherwise. All outputs terminated with 50Ω to VDDO/2.
NOTE 2: Defined as the time difference between the input reference clock and the averaged feedback input signal
when the PLL is locked and the input reference frequency is stable.
NOTE 3: Defined as skew within a bank of outputs at the same supply voltages and with equal load conditions.
NOTE 4: Defined as skew across banks of outputs at the same supply voltages and with equal load conditions.
NOTE 5: Defined as skew across banks of outputs operating at different frequency with the same supply voltages
and equal load conditions.
NOTE 6: Defined as the variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent
pairs of cycles.
8752
www.icst.com/products/hiperclocks.html
REV. B MAY 4, 2001
7
PRELIMINARY
ICS8752
Integrated
Circuit
Systems, Incꢀ
LOW SKEW 1-TO-8
LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
PACKAGE OUTLINE - Y SUFFIX
D
D2
θ
32
25
24
1
2
3
L
E
E1
E2
N
8
17
16
9
e
D1
A
C
A2
SEATING
PLANE
-C-
ccc
b
A1
c
TABLE 8. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BBA
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
N
A
32
--
--
--
1.60
0.15
1.45
0.45
0.20
A1
A2
b
0.05
1.35
0.30
0.09
1.40
0.37
c
--
D
9.00 BASIC
7.00 BASIC
5.60 Ref.
9.00 BASIC
7.00 BASIC
5.60 Ref.
0.80 BASIC
0.60
D1
D2
E
E1
E2
e
L
0.45
0.75
--
0
°
7°
ccc
--
--
0.10
Reference Document: JEDEC Publication 95, MS-026
8752
www.icst.com/products/hiperclocks.html
REV. B MAY 4, 2001
8
PRELIMINARY
ICS8752
Integrated
Circuit
Systems, Incꢀ
LOW SKEW 1-TO-8
LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
TABLE 9. ORDERING INFORMATION
Part/Order Number
ICS8752BY
Marking
Package
32 Lead LQFP
Count
250 per tray
1000
Temperature
0°C to 70°C
0°C to 70°C
ICS8752BY
ICS8752BY
ICS8752BYT
32 Lead LQFP on Tape and Reel
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or
for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for
use in life support devices or critical medical instruments.
8752
www.icst.com/products/hiperclocks.html
REV. B MAY 4, 2001
9
相关型号：
ICS8752BYT
Low Skew Clock Driver, 8 True Output(s), 0 Inverted Output(s), CMOS, PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, MS-026, LQFP-32
IDT
ICS8752CYI
PLL Based Clock Driver, 8752 Series, 8 True Output(s), 0 Inverted Output(s), CMOS, PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-32
IDT
ICS8752CYIT
PLL Based Clock Driver, 8752 Series, 8 True Output(s), 0 Inverted Output(s), CMOS, PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-32
IDT
ICS8752CYLF
PLL Based Clock Driver, 8752 Series, 8 True Output(s), 0 Inverted Output(s), CMOS, PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, MS-026, LQFP-32
IDT
ICS8752CYLFT
PLL Based Clock Driver, 8752 Series, 8 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, MS-026, LQFP-32
IDT
ICS8752YLF
Low Skew Clock Driver, 8 True Output(s), 0 Inverted Output(s), CMOS, PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, MS-026, LQFP-32
IDT
ICS87604AGI
Processor Specific Clock Generator, 166.67MHz, PDSO28, 6.10 X 9.70 MM, 0.92 MM HEIGHT, MO-153, TSSOP-28
IDT
ICS87604AGILF
Processor Specific Clock Generator, 166.67MHz, PDSO28, 6.10 X 9.70 MM, 0.92 MM HEIGHT, LEAD FREE, MO-153, TSSOP-28
IDT
©2020 ICPDF网 联系我们和版权申明