ICS87604AGILF [IDT]
Processor Specific Clock Generator, 166.67MHz, PDSO28, 6.10 X 9.70 MM, 0.92 MM HEIGHT, LEAD FREE, MO-153, TSSOP-28;
| 型号： | ICS87604AGILF |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Processor Specific Clock Generator, 166.67MHz, PDSO28, 6.10 X 9.70 MM, 0.92 MM HEIGHT, LEAD FREE, MO-153, TSSOP-28 时钟 光电二极管 外围集成电路 晶体 |
| 文件： | 总13页 (文件大小：202K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Low Voltage/Low Skew, 1:4 PCI/PCI-X
Zero Delay Clock Generator
87604I
GENERAL DESCRIPTION
FEATURES
The ICS87604I is a 1:4 PCI/PCI-X Clock Generator.
The ICS87604I has a selectable REF_IN or crystal
input. The REF_IN input accepts LVCMOS or LVTTL
input levels.The ICS87604I has a fully integrated PLL
along with frequency configurable clock and feedback
• Fully integrated PLL
ICS
HiPerClockS™
• Four LVCMOS/LVTTL outputs, 15Ω typical output impedance
• Selectable crystal oscillator interface or
LVCMOS/LVTTL REF_IN clock input
• Maximum output frequency: 166.67MHz
• Maximum crystal input frequency: 38MHz
• Maximum REF_IN input frequency: 41.67MHz
outputs for multiply-ing and regenerating clocks with “zero delay”.
The PLL’s VCO has an operating range of 250MHz - 500MHz,
allowing this device to be used in a variety of general purpose
clocking applications. For PCI/PCI-X applications in particular,
the VCO frequency should be set to 400MHz. This can be
accomplished by supplying 33.33MHz, 25MHz, 20MHz, or
16.66MHz on the reference clock or crystal input and by selecting
÷12, ÷16, ÷20, or ÷24, respectively as the feedback divide value.
The divider on the output bank can then be configured to generate
33.33MHz (÷12), 66.66MHz (÷6), 100MHz (÷4), or 133.33MHz
(÷3).
• Individual banks with selectable output dividers for
generating 33.333MHz, 66.66MHz, 100MHz and
133.333MHz
• Separate feedback control for generating PCI / PCI-X
frequencies from a 16.66MHz or 20MHz crystal, or 25MHz
or 33.33MHz reference frequency
• VCO range: 250MHz to 500MHz
• Cycle-to-cycle jitter: 120ps (maximum)
• Period jitter, RMS: 20ps (maximum)
• Output skew: 65ps (maximum)
• Static phase offset: 160ps 160ps
• Voltage Supply Modes:
The ICS87604I is characterized to operate with its core
supply at 3.3V and the bank supply at 3.3V or 2.5V. The
ICS87604I is packaged in a small 6.1mm x 9.7mm TSSOP
body, making it ideal for use in space-constrained applications.
V /V /V
DDO
DD
DDA
3.3/3.3/3.3
3.3/3.3/2.5
• -40°C to 85°C ambient operating temperature
BLOCK DIAGRAM
• Available in both standard (RoHS 5 and lead-free (RoHS 6)
packages
DIV_SEL0
DIV_SEL1
PIN ASSIGNMENT
XTAL_SEL
1
2
3
4
VDD
FB_IN
GND
28
27
26
FBDIV_SEL1
FBDIV_SEL0
DIV_SEL1
Q0
Q1
Q2
Q3
0 0
0 1
1 0
÷3
÷4
REF_IN
0
1
FB_OUT
REF_OUT
VDDO
25
DIV_SEL0
nc
0
1
24
23
22
5
6
7
8
XTAL_IN
÷6
MR
nc
OSC
÷12
1 1
Q3
Q2
XTAL_OUT
PLL
21
20
19
18
17
16
15
GND
GND
nc
GND
Q1
Q0
9
FB_IN
10
11
12
13
REF_IN
XTAL_OUT
XTAL_IN
VDDO
PLL_SEL
VDDA
÷12
÷16
÷20
0 0
0 1
1 0
PLL_SEL
REF_OUT
FB_OUT
14
XTAL_SEL
÷24
1 1
ICS87604I
28-Lead TSSOP, 240MIL
6.1mm x 9.7mm x 0.92mm
body package
FBDIV_SEL1
FBDIV_SEL0
MR
G Package
Top View
ICS87601AGI REVISION B APRIL 1, 2010
1
©2010 Integrated Device Technology, Inc.
ICS87604I
LOW VOLTAGE/LOW SKEW, 1:4 PCI/PCI-X ZERO DELAY CLOCK GENERATOR
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1
VDD
Power
Input
Core supply pin.
Feedback input to phase detector for generating clocks with
"zero delay". LVCMOS / LVTTL interface levels.
2
FB_IN
Pulldown
3, 9, 20, 21
GND
FB_OUT
REF_OUT
VDDO
Power
Output
Output
Power
Power supply ground.
4
5
Feedback output. Connect to FB_IN. LVCMOS / LVTTL interface levels.
Reference clock output. LVCMOS / LVTTL interface levels.
Output supply pin
6, 12
7, 8,
10, 11
Q3, Q2,
Q1, Q0
Clock outputs. 15Ω typical output impedance.
LVCMOS / LVTTL interface levels.
Output
Selects between PLL and bypass mode. When HIGH, selects PLL.
When LOW, selects reference clock. LVCMOS / LVTTL interface levels.
13
14
PLL_SEL
VDDA
Input
Pullup
Pullup
Power
Analog supply pin. See Applications Note for filtering.
Selects between crystal oscillator or reference clock as the PLL
reference source. Selects XTAL inputs when HIGH. Selects REF_IN
when LOW. LVCMOS / LVTTL interface levels.
Crystal oscillator interface. XTAL_IN is the input.
XTAL_OUT is the output.
15
XTAL_SEL
Input
16,
17
XTAL_IN,
XTAL_OUT
Input
18
REF_IN
nc
Input
Pulldown Reference clock input. LVCMOS / LVTTL interface levels.
No connect.
19, 22, 24
Unused
Active HIGH Master Reset. When logic HIGH, the internal dividers
Pulldown are reset causing the outputs go low. When logic LOW, the internal
dividers and the outputs are enabled. LVCMOS / LVTTL interface levels.
23
MR
Input
25,
26
27,
28
DIV_SEL0,
DIV_SEL1
FBDIV_SEL0,
FBDIV_SEL1
Selects divide value for clock outputs as described in Table 3.
LVCMOS / LVTTL interface levels.
Selects divide value for reference clock output and feedback output.
LVCMOS / LVTTL interface levels.
Input
Input
Pulldown
Pulldown
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
CIN
Input Capacitance
Input Pullup Resistor
4
pF
kΩ
kΩ
pF
pF
Ω
RPULLUP
51
51
9
RPULLDOWN Input Pulldown Resistor
VDD, VDDA, VDDO = 3.465V
Power Dissipation Capacitance
(per output); NOTE 1
CPD
VDD, VDDA = 3.465V; VDDO = 2.625V
11
ROUT
Output Impedance
15
ICS87601AGI REVISION B APRIL 1, 2010
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©2010 Integrated Device Technology, Inc.
ICS87604I
LOW VOLTAGE/LOW SKEW, 1:4 PCI/PCI-X ZERO DELAY CLOCK GENERATOR
TABLE 3A. OUTPUT CONTROL PIN FUNCTION TABLE
Inputs
Outputs
MR
1
Q0:Q3
LOW
FB_OUT, REF_OUT
LOW
0
Active
Active
TABLE 3C. PLL INPUT FUNCTION TABLE
Inputs
TABLE 3B. OPERATING MODE FUNCTION TABLE
Inputs
Operating Mode
PLL_SEL
XTAL_SEL
PLL Input
REF_IN
0
1
Bypass
PLL
0
1
XTAL Oscillator
TABLE 3D. CONTROL FUNCTION TABLE
Outputs
Frequency
Inputs
PLL_SEL=1
Reference
Frequency
Range (MHz)
FB_OUT
(MHz)
FBDIV_SEL1 FBDIV_SEL0 DIV_SEL1 DIV_SEL0
Q0:Q3
Q0:Q3 (MHz)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
16.67 - 41.67
16.67 - 41.67
16.67 - 41.67
16.67 - 41.67
12.5 - 31.25
12.5 - 31.25
12.5 - 31.25
12.5 - 31.25
10 - 25
x 4
x 3
66.68 - 166.68
50 - 125
16.67 - 41.67
16.67 - 41.67
16.67 - 41.67
16.67 - 41.67
12.5 - 31.25
12.5 - 31.25
12.5 - 31.25
12.5 - 31.25
10 - 25
x 2
33.34 - 83.34
16.67 - 41.67
66.63 - 166.56
50 - 125
x 1
x 5.33
x 4
x 2.667
x 1.33
x 6.667
x 5
33.34 - 83.34
16.63 - 41.56
66.67 - 166.68
50 - 125
10 - 25
10 - 25
10 - 25
x 3.33
x 1.66
x 8
33.30 - 83.25
16.60 - 41.50
66.64 - 166.64
50 - 125
10 - 25
10 - 25
10 - 25
8.33 - 20.83
8.33 - 20.83
8.33 - 20.83
8.33 - 20.83
8.33 - 20.83
8.33 - 20.83
8.33 - 20.83
8.33 - 20.83
x 6
x 4
33.32 - 83.32
16.66 - 41.66
x 2
NOTE: VCO frequency range for all configurations above is 250MHz to 500MHz.
ICS87601AGI REVISION B APRIL 1, 2010
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©2010 Integrated Device Technology, Inc.
ICS87604I
LOW VOLTAGE/LOW SKEW, 1:4 PCI/PCI-X ZERO DELAY CLOCK GENERATOR
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only. Functional op-
eration of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
Inputs, VI
XTAL_IN
Other Inputs
0V to VDD
-0.5V to VDD + 0.5V
Outputs,VO
-0.5V to VDDO + 0.5V
Package Thermal Impedance, θJA 64.5°C/W (0 mps)
Storage Temperature, TSTG -65°C to 150°C
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 3.3V 5ꢀ, VDDO = 3.3V 5ꢀ OR 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VDD
VDDA
VDDO
IDD
Core Supply Voltage
3.135
3.135
3.135
3.3
3.3
3.3
3.465
3.465
3.465
185
V
V
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
V
mA
mA
mA
IDDA
IDDO
15
20
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = 3.3V 5ꢀ, VDDO = 3.3V 5ꢀ OR 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
MR, DIV_ SEL0, DIV_SEL1,
FBDIV_SEL0, FBDIV_SEL1,
XTAL_SEL, FB_IN, PLL_SEL
2
VDD + 0.3
V
V
Input
VIH
High Voltage
REF_IN
2
V
DD + 0.3
0.8
MR, DIV_ SEL0, DIV_SEL1,
FBDIV_SEL0, FBDIV_SEL1,
XTAL_SEL, FB_IN, PLL_SEL
-0.3
-0.3
V
Input
VIL
Low Voltage
REF_IN
1.3
V
DIV_ SEL0, DIV_SEL1,
FBDIV_SEL0, FBDIV_SEL1,
MR, FB_IN
VDD = VIN = 3.465V
VDD = VIN = 3.465V
150
5
µA
µA
µA
Input
IIH
High Current
XTAL_SEL, PLL_SEL
DIV_ SEL0, DIV_SEL1,
FBDIV_SEL0, FBDIV_SEL1,
MR, FB_IN
V
DD = 3.465V,
VIN = 0V
-5
Input
IIL
Low Current
VDD = 3.465V,
VIN = 0V
XTAL_SEL, PLL_SEL
-150
µA
V
DD = VIN = 3.465V
2.6
1.8
V
V
VOH
VOL
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
VDD = VIN = 2.625V
VDD = VIN = 3.465V or
2.625V
0.5
V
NOTE 1: Outputs terminated with 50Ω to VDDO/2. See Parameter Measurement Information section,
"3.3V Output Load Test Circuit".
ICS87601AGI REVISION B APRIL 1, 2010
4
©2010 Integrated Device Technology, Inc.
ICS87604I
LOW VOLTAGE/LOW SKEW, 1:4 PCI/PCI-X ZERO DELAY CLOCK GENERATOR
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum Typical Maximum
Units
Mode of Oscillation
Frequency
Fundamental
10
38
50
MHz
Ω
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
7
pF
1
mW
TABLE 6. PLL INPUT REFERENCE CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
fREF Reference Frequency 8.33 41.67 MHz
TABLE 7A. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
Typical Maximum Units
fMAX
Output Frequency
166.67
325
65
MHz
ps
t(Ø)
Static Phase Offset; NOTE 1
Output Skew; NOTE 2, 5
Cycle-to-Cycle Jitter; 5
Period Jitter, RMS; NOTE 3, 5, 6
Slew Rate
FREF = 25MHz
0
160
tsk(o)
tjit(cc)
tjit(per)
tsl(o)
tL
ps
120
20
ps
ps
1
4
V/ns
ms
ps
PLL Lock Time
10
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle; NOTE 4
20ꢀ to 80ꢀ
200
48
700
52
ꢀ
NOTE: All parameters measured with feedback and output dividers set to DIV by 12 unless otherwise noted.
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established
when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet
specifications after thermal equilibrium has been reached under these conditions.
NOTE 1: Defined as the time difference between the input reference clock and the average feedback input signal when the
PLL is locked and the input reference frequency is stable. Measured at VDD/2.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at VDDO/2.
NOTE 3: Jitter performance using LVCMOS inputs.
NOTE 4: Measured using REF_IN. For XTAL input, refer to Application Note.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 6: This parameter is defined as an RMS value.
TABLE 7B. AC CHARACTERISTICS, VDD = VDDA = 3.3V 5ꢀ, VDDO = 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
Typical Maximum Units
fMAX
Output Frequency
166.67
160
50
MHz
ps
t(Ø)
Static Phase Offset; NOTE 1
Output Skew; NOTE 2, 5
Cycle-to-Cycle Jitter; 5
Period Jitter, RMS; NOTE 3, 5, 6
Slew Rate
FREF = 25MHz
-365
-105
tsk(o)
tjit(cc)
tjit(per)
tsl(o)
tL
ps
170
20
ps
ps
1
4
V/ns
ms
ps
PLL Lock Time
10
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle; NOTE 4
20ꢀ to 80ꢀ
200
48
700
52
ꢀ
See Table 7A for notes.
ICS87601AGI REVISION B APRIL 1, 2010
5
©2010 Integrated Device Technology, Inc.
ICS87604I
LOW VOLTAGE/LOW SKEW, 1:4 PCI/PCI-X ZERO DELAY CLOCK GENERATOR
PARAMETER MEASUREMENT INFORMATION
1.65V 5ꢀ
2.05V 5ꢀ
1.25V 5ꢀ
2.05V 5ꢀ
1.65V 5ꢀ
SCOPE
VDD
,
VDDO
VDD
VDDA
SCOPE
Qx
VDDO
LVCMOS
GND
VDDA
Qx
LVCMOS
GND
-1.65V 5ꢀ
-1.25V 5ꢀ
3.3V/2.5V OUTPUT LOAD AC TEST CIRCUIT
3.3V OUTPUT LOAD AC TEST CIRCUIT
VDDO
VDDO
2
VDDO
2
VDDO
2
Qx
Qy
2
Qx
➤
➤
tcycle n
tcycle n+1
➤
➤
VDDO
2
tjit(cc) = tcycle n – tcycle n+1
1000 Cycles
tsk(o)
CYCLE-TO-CYCLE JITTER
OUTPUT SKEW
VDD
2
REF_IN
FB_IN
80ꢀ
80ꢀ
VDD
2
20ꢀ
20ꢀ
Qx
tR
tF
➤
➤
t(Ø)
OUTPUT RISE/FALL TIME
STATIC PHASE OFFSET
VDDO
2
VDDO
VDDO
2
2
Qx,
FB_OUT,
REF_OUT
tPW
tPERIOD
tPW
tPERIOD
odc =
OUTPUT PULSE WIDTH/PULSE WIDTH PERIOD
ICS87601AGI REVISION B APRIL 1, 2010
6
©2010 Integrated Device Technology, Inc.
ICS87604I
LOW VOLTAGE/LOW SKEW, 1:4 PCI/PCI-X ZERO DELAY CLOCK GENERATOR
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
3.3V
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. To achieve optimum jitter per-
formance, power supply isolation is required. The ICS87604I pro-
vides separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. VDD, VDDA, and VDDO
should be individually connected to the power supply
plane through vias, and 0.01μF bypass capacitors should be
used for each pin. Figure 1 illustrates this for a generic VDD pin
and also shows that VDDA requires that an additional10Ω resistor
along with a 10µF bypass capacitor be connected to the VDDA pin.
The 10Ω resistor can also be replaced by a ferrite bead.
VDD
.01μF
.01μF
10Ω
VDDA
10μF
FIGURE 1. POWER SUPPLY FILTERING
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
OUTPUTS:
LVCMOS OUTPUTS
CRYSTAL INPUT
For applications not requiring the use of the crystal oscillator
input, both XTAL_IN and XTAL_OUT can be left floating. Though
not required, but for additional protection, a 1kΩ resistor can be
tied from XTAL_IN to ground.
All unused LVCMOS output can be left floating. There should be
no trace attached.
REF_CLK INPUT
For applications not requiring the use of the reference clock, it
can be left floating. Though not required, but for additional
protection, a 1kΩ resistor can be tied from the REF_CLK to
ground.
LVCMOS CONTROL PINS
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
CRYSTAL INPUT INTERFACE
The ICS87604I has been characterized with 18pF parallel
resonant crystals. The capacitor values, C1 and C2, shown in
Figure 2 below were determined using a 25MHz, 18pF parallel
resonant crystal and were chosen to minimize the frequency ppm
error. The optimum C1 and C2 values can be slightly adjusted for
optimum frequency accuracy.
XTAL_IN
C1
22p
X1
18pF Parallel Crystal
XTAL_OUT
C2
22p
FIGURE 2. CRYSTAL INPUt INTERFACE
ICS87601AGI REVISION B APRIL 1, 2010
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©2010 Integrated Device Technology, Inc.
ICS87604I
LOW VOLTAGE/LOW SKEW, 1:4 PCI/PCI-X ZERO DELAY CLOCK GENERATOR
OVERDRIVING THE CRYSTAL INTERFACE
The XTAL_IN input can be overdriven by an LVCMOS driver or by
one side of a differential driver through an AC coupling capacitor.
The XTAL_OUT pin can be left floating.The amplitude of the input
signal should be between 500mV and 1.8V and the slew rate
should not be less than .2V/nS. For 3.3V LVCMOS inputs, the
amplitude must be reduced from full swing to at least half the
swing in order to prevent signal interference with the power rail
and to reduce internal noise. Figure 3A shows an example of the
interface diagram for a high speed 3.3V LVCMOS driver. This
configuration requires that the sum of the output impedance of
the driver (Ro) and the series resistance (Rs) equals the
transmission line impedance. In addition, matched termination at
the crystal input will attenuate the signal in half.This can be done
in one of two ways. First, R1 and R2 in parallel should equal the
transmission line impedance. For most 50 applications, R1 and
R2 can be 100Ω. This can also be accomplished by removing R1
and changing R2 to 50Ω. The values of the resistors can be
increased to reduce the loading for slower and weaker LVCMOS
driver. Figure 2 shows an example of the interface diagram for an
LVPECL driver. This is a standard LVPECL termination with one
side of the driver feeding the XTAL_IN input. It is recommended
that all components in the schematics be placed in the layout.
Though some components might not be used, they can be utilized
for debugging purposes. The datasheet specifications are
characterized and guaranteed by using a quartz crystal as the
input.
3.3V
3.3V
R1
100
C1
Ro
~ 7 Ohm
Zo = 50 Ohm
XTAL_IN
RS
43
0.1uF
R2
Driver_LVCMOS
100
XTAL_OUT
Crystal Input Interf ace
FIGURE 3A. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE
VCC=3.3V
C1
Zo = 50 Ohm
XTAL_IN
0.1uF
R1
Zo = 50 Ohm
50
XTAL_OU T
LVPECL
Cry stal Input Interface
R2
50
R3
50
FIGURE 3B. GENERAL DIAGRAM FOR LVPECL DRIVER TO XTAL INPUT INTERFACE
ICS87601AGI REVISION B APRIL 1, 2010
8
©2010 Integrated Device Technology, Inc.
ICS87604I
LOW VOLTAGE/LOW SKEW, 1:4 PCI/PCI-X ZERO DELAY CLOCK GENERATOR
SCHEMATIC EXAMPLE
Figure 4 shows a schematic example of the ICS87604I.
Series termination is shown in this schematic. Additional
LVCMOS termination approaches are shown in the LVCMOS
Termination Application Note. In this example, an 18 pF
parallel resonant 25MHz crystal is used.The C1=22pF and
C2=22pF are recommended for frequency accuracy. For
different board layout, the C1 and C2 values may be slightly
adjusted for optimizing frequency accuracy.The logic control
inputs are either pull up or pull down depending on the
application requirement. If there is space available, it is
recommended to provide spare footprints as shown in the
schematic for flexibility of choosing pull up or pull down.
FIGURE 4. ICS87604I SCHEMATIC EXAMPLE
ICS87601AGI REVISION B APRIL 1, 2010
9
©2010 Integrated Device Technology, Inc.
ICS87604I
LOW VOLTAGE/LOW SKEW, 1:4 PCI/PCI-X ZERO DELAY CLOCK GENERATOR
RELIABILITY INFORMATION
TABLE 8. θ VS. AIR FLOW TABLE FOR 28 LEAD TSSOP
JA
θ by Velocity (Linear Feet per Minute)
JA
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
64.5°C/W
60.4°C/W
58.5°C/W
TRANSISTOR COUNT
The transistor count for ICS87604I is: 5495
PACKAGE OUTLINE AND PACKAGE DIMENSIONS
TABLE 9. PACKAGE DIMENSIONS
PACKAGE OUTLINE - G SUFFIX FOR 28 LEAD TSSOP
Millimeters
SYMBOL
Minimum
Maximum
N
A
28
--
1.20
0.15
1.05
0.30
0.20
9.80
A1
A2
b
0.05
0.80
0.19
0.09
9.60
c
D
E
8.10 BASIC
0.65 BASIC
E1
e
6.00
6.20
L
0.45
0°
0.75
8°
α
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
ICS87601AGI REVISION B APRIL 1, 2010
10
©2010 Integrated Device Technology, Inc.
ICS87604I
LOW VOLTAGE/LOW SKEW, 1:4 PCI/PCI-X ZERO DELAY CLOCK GENERATOR
TABLE 10. ORDERING INFORMATION
Part/Order Number
87604AGI
Marking
Package
Shipping Packaging
tube
Temperature
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
ICS87604AGI
ICS87604AGI
28 Lead TSSOP
87604AGIT
28 Lead TSSOP
1000 tape & reel
tube
87604AGILF
87604AGILFT
ICS87604AGILF
ICS87604AGILF
28 Lead "Lead-Free" TSSOP
28 Lead "Lead-Free" TSSOP
1000 tape & reel
NOTE: Parts that are with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and
industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT
reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
ICS87601AGI REVISION B APRIL 1, 2010
11
©2010 Integrated Device Technology, Inc.
ICS87604I
LOW VOLTAGE/LOW SKEW, 1:4 PCI/PCI-X ZERO DELAY CLOCK GENERATOR
REVISION HISTORY SHEET
Rev
A
Table
T7A & T7B
10
Page
Description of Change
Date
5
AC Characteristics Tables - corrected note sequence.
3/18/05
4/12/05
A
10
1
Ordering Information Table - added marking.
Pin Assignment and General Description - corrected package dimension.
Crystal Characteristics - added Drive Level.
T5
5
6
Updated Output Load AC Test Circuit Diagrams.
B
3/8/06
8
Application Information - added LVCMOS to XTAL Interface and
Recommendations for Unused Input and Output Pins sections.
T9
T9
10
1
10
Package Dimensions - corrected "E" and "E1" dimensions.
Pin Assignment and General Description - corrected package dimension.
B
B
8/18/06
1/11/08
Package Dimensions - corrected "E" and "E1" dimensions.
Absolute Maximum Ratings - updated Package Thermal Impedance.
Added Schematic Layout.
4
9
10
1
5
8
Reliability Information - updated Package Thermal Impedance.
Pin Assignment, corrected 173-MIL to 240-MIL.
AC Characteristics Table, added Thermal Note.
Updated the Overdriving the Crystal Interface section.
Ordering Information Table - deleted "ICS" prefix from Part/Order Number
column.
T7A
T10
B
4/1/10
11
Added new Header/Footer in datasheet.
ICS87601AGI REVISION B APRIL 1, 2010
12
©2010 Integrated Device Technology, Inc.
ICS87604I
LOW VOLTAGE/LOW SKEW, 1:4 PCI/PCI-X ZERO DELAY CLOCK GENERATOR
www.IDT.com
6024 Silver Creek Valley Road
San Jose, CA 95138
Sales
Techical Support
netcom@idt.com
+480-763-2056
800-345-7015 (inside USA)
+408-284-8200 (outside
USA)
Fax: 408-284-2775
www.IDT.com/go/contactIDT
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All
information in this document, including descriptions of product features and performace, is subject to change without notice. Performance specifications and the operating parameters of the
described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided
without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitablity of IDT’s products for any particular purpose, an implied warranty of merchantabil-
ity, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third
parties.
IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or
safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.
Integrated Device Techology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property
of IDT or their respective third party owners.
Copyright 2010. All rights reserved.
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