ICS8752CYLF [IDT]
PLL Based Clock Driver, 8752 Series, 8 True Output(s), 0 Inverted Output(s), CMOS, PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, MS-026, LQFP-32;
| 型号： | ICS8752CYLF |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | PLL Based Clock Driver, 8752 Series, 8 True Output(s), 0 Inverted Output(s), CMOS, PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, MS-026, LQFP-32 驱动 逻辑集成电路 |
| 文件： | 总14页 (文件大小：132K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS8752
LOW SKEW, 1-TO-8
LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
GENERAL DESCRIPTION
FEATURES
The ICS8752 is a low voltage, low skew LVCMOS clock
generator. With output frequencies up to 240MHz, the
ICS8752 is targeted for high performance clock applcations.
Along with a fully integrated PLL, the ICS8752 contains
frequency configurable outputs and an external feedback
input for regenerating clocks with “zero delay”.
• Fully integrated PLL
• Eight LVCMOS outputs, 7Ω typical output impedance
• Selectable LVCMOS CLK0 or CLK1 inputs for
redundant clock applications
• Input/Output frequency range: 18.33MHz to 240MHz
at VCC = 3.3V 5ꢀ
Dual clock inputs, CLK0 and CLK1, support redundant clock
applications. The CLK_SEL input determines which refer-
ence clock is used. The output divider values of Bank A and
B are controlled by the DIV_SELA0:1, and DIV_SELB0:1,
respectively.
• VCO range: 220MHz to 480MHz
• External feedback for “zero delay” clock regeneration
• Cycle-to-cycle jitter: 75ps (maximum),
(all outputs are the same frequency)
For test and system debug purposes, the PLL_SEL input
allows the PLL to be bypassed. When HIGH, the MR/nOE
input resets the internal dividers and forces the outputs to
the high impedance state.
• Output skew: 100ps (maximum)
• Bank skew: 55ps (maximum)
The low impedance LVCMOS outputs of the ICS8752 are
designed to drive terminated transmission lines. The
effective fanout of each output can be doubled by
utilizing the ability of each output to drive two series
terminated transmission lines.
• Full 3.3V or 2.5V supply voltage
• 0°C to 70°C ambient operating temperature
• Available in both standard and lead-free RoHS-compliant
packages
BLOCK DIAGRAM
PIN ASSIGNMENT
PLL_SEL
PLL
FB_IN
PHASE
÷2
÷4
00
01
10
11
VCO
CLK0
0
32 31 30 29 28 27 26 25
DETECTOR
1
0
CLK1
QA0
QA1
QA2
QA3
1
÷6
DIV_SELB0
DIV_SELB1
DIV_SELA0
DIV_SELA1
MR/nOE
CLK0
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
GND
QB1
QB0
VDDO
VDDO
QA3
QA2
GND
CLK_SEL
÷8
÷12
DIV_SELA1
DIV_SELA0
ICS8752
00
01
10
11
QB0
QB1
QB2
QB3
GND
FB_IN
DIV_SELB1
DIV_SELB0
9
10 11 12 13 14 15 16
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y package
TopView
MR/nOE
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ICS8752
LOW SKEW, 1-TO-8
LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Pulldown
Description
DIV_SELB0,
DIV_SELB1
DIV_SELA0,
DIV_SELA1
Determines output divider values for Bank B as described in Table 3.
LVCMOS / LVTTL interface levels.
Determines output divider values for Bank A as described in Table 3.
LVCMOS / LVTTL interface levels.
1, 2
Input
Input
3, 4
Pulldown
When logic HIGH, the internal dividers are reset and the outputs are
5
6
MR/nOE
Input
Pulldown disabled. When logic LOW, the master reset is disabled and the outputs
are enabled. LVCMOS / LVTTL interface levels.
CLK0
GND
Input
Pulldown Clock input. LVCMOS / LVTTL interface levels.
7, 13, 17,
24, 28, 29
Power
Power supply ground.
Feedback input to phase detector for generating clocks with "zero delay".
LVCMOS / LVTTL interface levels.
Clock select input. Selects between CLK0 or CLK1 as phase detector
Pulldown reference. When LOW, selects CLK0. When HIGH, selects CLK1.
LVCMOS / LVTTL interface levels.
8
FB_IN
Input
Input
Pulldown
9
CLK_SEL
10
11, 32
12
VDDA
VDD
Power
Power
Input
Analog supply pin.
Core supply pins.
CLK1
Pulldown Clock input. LVCMOS / LVTTL interface levels.
14, 15,
18, 19
16, 20,
21, 25
22, 23,
26, 27
QA0, QA1,
QA2, QA3
Bank A clock outputs. 7Ω typical output impedance.
Output
Power
LVCMOS / LVTTL interface levels.
VDDO
Output supply pins.
QB0, QB1,
QB2, QB3
Bank B clock outputs. 7Ω typical output impedance.
LVCMOS / LVTTL interface levels.
Output
30
nc
Unused
No connect.
Selects between the PLL and CLK0 or CLK1 as the input to the dividers.
31
PLL_SEL
Input
Pullup
When HIGH selects PLL. When LOW selects CLK0 or CLK1.
LVCMOS / LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
Parameter
Test Conditions
Minimum Typical Maximum Units
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
4
pF
kΩ
kΩ
RPULLUP
RPULLDOWN
51
51
Power Dissipation Capacitance
(per output)
Output Impedance
CPD
VDDA, VDD, VDDO = 3.465V
23
7
pF
ROUT
Ω
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ICS8752
LOW SKEW, 1-TO-8
LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
TABLE 3. CONTROL INPUT FUNCTION TABLE
Inputs
DIV_
SELA1
Outputs
DIV_
SELA0
DIV_
SELB1
DIV_
SELB0
MR/nOE PLL_SEL CLK_SEL
QAx
QBx
1
0
0
0
0
0
0
0
0
0
0
0
0
X
1
1
1
1
0
0
0
0
0
0
0
0
X
X
X
X
X
0
0
0
0
1
1
1
1
X
X
0
1
0
1
0
1
0
1
0
1
0
1
X
0
0
1
1
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
0
1
0
1
Hi-Z
Hi-Z
0
0
1
1
0
0
1
1
0
0
1
1
fVCO/2
fVCO/4
fVCO/6
fVCO/8
fCLK0/2
fCLK0/4
fCLK0/6
fCLK0/8
fCLK1/2
fCLK1/4
fCLK1/6
fCLK1/8
fVCO/4
fVCO/6
fVCO/8
fVCO/12
fCLK0/4
fCLK0/6
fCLK0/8
fCLK0/12
fCLK1/4
fCLK1/6
fCLK1/8
fCLK1/12
NOTE: For normal operation, MR/nOE is LOW. When MR/nOE is HIGH, all ouputs are disabled.
TABLE 4A. QA OUTPUT FREQUENCY W/FB_IN = QB
Inputs
Outputs
CLK0, CLK1 (MHz)
(NOTE 1)
Minimum Maximum
QB Output
Divider Mode
(NOTE 2)
DIV_
SELB1 SELB0
DIV_
DIV_
DIV_
QA Output
QA Multiplier
(NOTE 2)
FB_IN
SELA1 SELA0 Divider Mode
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
0
1
÷2
÷4
÷6
÷8
÷2
÷4
÷6
÷8
÷2
÷4
÷6
÷8
÷2
÷4
÷6
÷8
2
1
QB
0
0
1
1
0
1
0
1
÷4
÷6
55
120
80
0.667
0.5
3
1.5
1
QB
QB
QB
36.66
27.5
0.75
4
2
÷8
60
1.33
1
6
3
÷12
18.33
40
2
1.5
NOTE 1: VCO frequency range is 220MHz to 480MHz.
NOTE 2: QA output frequency equal to CLKx frequency times the multiplier;
QB output frequency equal to CLKx.
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ICS8752
LOW SKEW, 1-TO-8
LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
TABLE 4B. QB OUTPUT FREQUENCY W/FB_IN = QA
Inputs
Outputs
CLK0, CLK1 (MHz)
QA Output
Divider Mode
(NOTE 2)
QB Output
Divider Mode
DIV_
DIV_
DIV_
SELB1
DIV_
SELB0
QB Multiplier
(NOTE 2)
(NOTE 1)
FB_IN
SELA1 SELA0
Minimum Maximum
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
0
1
÷4
÷6
0.5
0.333
0.25
0.167
1
QA
0
0
110
240
÷2
(NOTE 3)
÷8
÷12
÷4
÷6
0.667
0.5
QA
QA
QA
0
1
1
1
0
1
÷4
÷6
÷8
55
120
80
÷8
÷12
÷4
0.333
1.5
÷6
1
36.66
27.5
÷8
0.75
0.5
÷12
÷4
2
÷6
1.333
1
60
÷8
÷12
0.667
NOTE 1: VCO frequency range is 220MHz to 480MHz.
NOTE 2: QB output frequency equal to CLKx frequency times the multiplier;
QA output frequency equal to CLKx.
NOTE 3: Maximum frequency of 240MHz valid for VCC = 3.3V 5ꢀ only.
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ICS8752
LOW SKEW, 1-TO-8
LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
DD
Inputs, V
-0.5V to VDD + 0.5V
-0.5V to VDDO + 0.5V
47.9°C/W (0 lfpm)
-65°C to 150°C
I
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
Outputs, VO
PackageThermal Impedance, θ
JA
StorageTemperature, T
STG
TABLE 5A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VDD
VDDA
VDDO
IDD
Core Supply Voltage
3.135
3.135
3.135
3.3
3.3
3.3
3.465
3.465
3.465
105
V
V
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
V
mA
mA
mA
IDDA
IDDO
15
20
TABLE 5B. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 2.5V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VDD
VDDA
VDDO
IDD
Core Supply Voltage
2.375
2.375
2.375
2.5
2.5
2.5
2.625
2.625
2.625
100
V
V
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
V
mA
mA
mA
IDDA
IDDO
15
20
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ICS8752
LOW SKEW, 1-TO-8
LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
TABLE 5B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V 5ꢀ OR 2.5V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
DD = 3.3V
VDD = 2.5V
DD = 3.3V
Minimum Typical Maximum Units
V
2
VDD + 0.3
VDD + 0.3
0.8
V
V
V
V
VIH
VIL
Input High Voltage
1.7
-0.3
-0.3
V
Input Low Voltage
DIV_ SELx0,
VDD = 2.5V
0.7
VDD = VIN = 3.465V
DIV_SELx1, CLK0,
CLK1, FB_IN, CLK_SEL,
MR/nOE
150
5
µA
µA
µA
or 2.625V
Input
High Current
IIH
VDD = VIN = 3.465V
or 2.625V
PLL_SEL
DIV_ SELx0,
V
DD = 3.465V or 2.625V,
VIN = 0V
DIV_SELx1, CLK0,
CLK1, FB_IN, CLK_SEL,
MR/nOE
-5
Input
Low Current
IIL
VDD = 3.465V or 2.625V,
VIN = 0V
PLL_SEL
-150
µA
V
DDO = VIN = 3.465V
DDO = VIN = 2.625V
2.6
1.8
V
V
V
VOH
VOL
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
V
0.5
NOTE 1: Outputs terminated with 50Ω to VDDO/2. See Parameter Measurement Information section,
"Output Load Test Circuit" diagrams.
TABLE 6A. PLL INPUT REFERENCE CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Input Reference Frequency
Test Conditions
Minimum Typical Maximum Units
20 240 MHz
fREF
NOTE: Input reference frequency is limited by
the divider selection and the VCO lock range.
TABLE 6B. PLL INPUT REFERENCE CHARACTERISTICS, VDD = VDDA = VDDO = 2.5V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
Input Reference Frequency
fREF
NOTE: Input reference frequency is limited by
the divider selection and the VCO lock range.
20
120
MHz
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ICS8752
LOW SKEW, 1-TO-8
LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
TABLE 7A. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
÷2
÷4
110
55
240
120
80
MHz
MHz
MHz
MHz
MHz
MHz
fOUT
Output Frequency (PLL Mode)
÷6
36.67
27.5
18.33
220
÷8
60
÷12
40
fVCO
PLL VCO Lock Range
480
fVCO = 400MHz,
Feedback ÷ 8
Measured on rising edge
at VDDO/2
t(Ø)
Static Phase Offset; NOTE 1
-30
70
170
55
ps
ps
tsk(b)
tsk(o)
Bank Skew; NOTE 2, 4
Output Skew; NOTE 3, 4
Measured on rising edge
at VDDO/2
100
400
75
ps
ps
ps
Different Frequencies
on Different Banks
All Outputs at
Cycle-to-Cycle
Jitter; NOTE 4
tjit(cc)
Same Frequency
tL
PLL Lock Time
1
950
53
mS
ps
ꢀ
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20ꢀ to 80ꢀ
400
47
50
All parameters measured at fMAX unless noted otherwise.
NOTE 1: Defined as the time difference between the input clock and the average feedback input signal,
when the PLL is locked and the input reference frequency is stable.
NOTE 2: Defined as skew within a bank of outputs at the same supply voltages and with equal load conditions.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at VDDO/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
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ICS8752
LOW SKEW, 1-TO-8
LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
TABLE 7B. AC CHARACTERISTICS, VDD = VDDA = VDDO = 2.5V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
÷2
÷4
110
55
240
120
80
MHz
MHz
MHz
MHz
MHz
MHz
fOUT
Output Frequency (PLL Mode)
÷6
36.67
27.5
18.33
220
÷8
60
÷12
40
fVCO
PLL VCO Lock Range
480
fVCO = 400MHz
Feedback ÷ 8
Measured on rising edge
at VDDO/2
t(Ø)
Static Phase Offset; NOTE 1
-90
50
190
55
ps
ps
ps
ps
ps
tsk(b)
tsk(o)
Bank Skew; NOTE 2, 4
Output Skew; NOTE 3, 4
Measured on rising edge
at VDDO/2
90
Different Frequencies
400
75
on Different Banks
All Outputs at
Cycle-to-Cycle
Jitter; NOTE 4
tjit(cc)
Same Frequency
tL
PLL Lock Time
1
950
55
mS
ps
ꢀ
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20ꢀ to 80ꢀ
400
45
50
All parameters measured at fMAX unless noted otherwise.
NOTE 1: Defined as the time difference between the input clock and the average feedback input signal,
when the PLL is locked and the input reference frequency is stable.
NOTE 2: Defined as skew within a bank of outputs at the same supply voltages and with equal load conditions.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at VDDO/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
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ICS8752
LOW SKEW, 1-TO-8
LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
PARAMETER MEASUREMENT INFORMATION
1.25V 5ꢀ
1.65V 5ꢀ
SCOPE
SCOPE
VDD
VDDA,VDDO
,
VDD
VDDA,VDDO
,
Qx
Qx
LVCMOS
LVCMOS
GND
GND
-1.65V 5ꢀ
-1.25V 5ꢀ
3.3V OUTPUT LOAD AC TEST CIRCUIT
2.5V OUTPUT LOAD AC TEST CIRCUIT
(Where X denotes outputs in the same Bank)
VDDO
2
VDDO
QX0:QX3
Qx
Qy
2
VDDO
2
VDDO
2
QX0:QX3
tsk(b)
tsk(o)
OUTPUT SKEW
BANK SKEW
VDD
2
VDDO
2
VDDO
2
VDDO
2
CLK0,
CLK1
QA0:QA3,
QB0:QB3
➤
➤
tcycle n
tcycle n+1
➤
➤
VDD
2
FB_IN
➤
tjit(cc) = tcycle n –tcycle n+1
1000 Cycles
➤
t(Ø)
STATIC PHASE OFFSET
CYCLE-TO-CYCLE JITTER
VDDO
2
80ꢀ
tF
80ꢀ
QA0:QA3,
QB0:QB3
tPW
20ꢀ
20ꢀ
tPERIOD
Clock
Outputs
tR
tPW
x 100ꢀ
odc =
tPERIOD
OUTPUT DUTY CYLCLE/PULSE WIDTH/PERIOD
OUTPUT RISE/FALL TIME
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ICS8752
LOW SKEW, 1-TO-8
LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
APPLICATION INFORMATION
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
OUTPUTS:
CLK INPUT:
LVCMOS OUTPUT:
For applications not requiring the use of a clock input, it can All unused LVCMOS output can be left floating. We
be left floating. Though not required, but for additional recommend that there is no trace attached.
protection, a 1kΩ resistor can be tied from the CLK input to
ground.
LVCMOS CONTROL PINS:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
RELIABILITY INFORMATION
TABLE 7. θJAVS. AIR FLOW TABLE FOR 32 LEAD LQFP
θJA byVelocity (Linear Feet per Minute)
0
200
55.9°C/W
42.1°C/W
500
50.1°C/W
39.4°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
47.9°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS8752 is: 1546
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ICS8752
LOW SKEW, 1-TO-8
LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
PACKAGE OUTLINE - Y SUFFIX FOR 32 LEAD LQFP
TABLE 8. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BBA
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
N
A
32
--
--
--
1.60
0.15
1.45
0.45
0.20
A1
A2
b
0.05
1.35
0.30
0.09
1.40
0.37
c
--
D
9.00 BASIC
7.00 BASIC
5.60 Ref.
9.00 BASIC
7.00 BASIC
5.60 Ref.
0.80 BASIC
0.60
D1
D2
E
E1
E2
e
L
0.45
0.75
θ
--
0°
7°
ccc
--
--
0.10
Reference Document: JEDEC Publication 95, MS-026
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ICS8752
LOW SKEW, 1-TO-8
LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
TABLE 9. ORDERING INFORMATION
Part/Order Number
8752CY
Marking
Package
Shipping Packaging
tray
Temperature
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
ICS8752CY
ICS8752CY
32 Lead LQFP
8752CYT
32 Lead LQFP
1000 tape & reel
tray
8752CYLF
ICS8752CYLF
ICS8752CYLF
32 Lead "Lead-Free" LQFP
32 Lead "Lead-Free" LQFP
8752CYLFT
1000 tape & reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated DeviceTechnology, Inc.(IDT) assumes no responsibility for either its use or for infringement of
any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial
applications.Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves
the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
8752CY
www.idt.com
REV.C JULY 2, 2010
12
ICS8752
LOW SKEW, 1-TO-8
LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
REVISION HISTORY SHEET
Rev
Table
Page
Description of Change
Date
A
T1
2
1
Pin Descriptions Table. Revised MR/nOE description.
8/19/02
Features Section - delete bullet, "Industrial temperature available upon
request." Added Lead-Free bullet.
B
T2
T9
2
12
Pin Characteristics table - changed CIN 4pF max. to 4pF typical.
Ordering Information Table -added Lead-Free part number and note.
Updated data sheet format.
3/31/05
B
B
T1
2
Pin Description Table - correct Pin 5, MR/nOE.
5/2/05
10
12
Added Recommendations for Unused Input and Output Pins.
Ordering Information Table - added lead-free marking.
10/19/05
T9
T9
Updated datasheet's header/footer with IDT from ICS.
Removed ""ICS"" prefix from Part/Order Number column.
Added Contact Page.
C
12
14
7/2/10
8752CY
www.idt.com
REV. C JULY 2, 2010
13
ICS8752
LOW SKEW, 1-TO-8
LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
We’ve Got Your Timing Solution.
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© 2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc.
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Printed in USA
8752CY
www.idt.com
REV.C JULY 2, 2010
14
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