ICS874S02BMILF [IDT]
PLL Based Clock Driver, 874S Series, 1 True Output(s), 0 Inverted Output(s), PDSO20, 7.50 X 12.80 MM, 2.30 MM HEIGHT, ROHS COMPLIANT, MS-013, MO-119, SOIC-20;
| 型号： | ICS874S02BMILF |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | PLL Based Clock Driver, 874S Series, 1 True Output(s), 0 Inverted Output(s), PDSO20, 7.50 X 12.80 MM, 2.30 MM HEIGHT, ROHS COMPLIANT, MS-013, MO-119, SOIC-20 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总16页 (文件大小：685K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
ICS874S02I
General Description
Features
The ICS874S02I is a highly versatile 1:1 Differential-
• One differential LVDS output pair and
one differential feedback output pair
S
IC
to-LVDS Clock Generator and a member of the
HiPerClockS™ family of High Performance Clock
Solutions from IDT. The ICS874S02I has a fully
integrated PLL and can be configured as a zero
HiPerClockS™
• One differential clock input pair
• CLK/nCLK can accept the following differential input levels:
LVPECL, LVDS, LVHSTL, SSTL
delay buffer, multiplier or divider, and has an output frequency
range of 62.5MHz to 1GHz. The reference divider, feedback
divider and output divider are each programmable, thereby
allowing for the following output-to-input frequency ratios: 8:1, 4:1,
2:1, 1:1, 1:2, 1:4, 1:8. The external feedback allows the device to
achieve “zero delay” between the input clock and the output
clocks. The PLL_SEL pin can be used to bypass the PLL for
system test and debug purposes. In bypass mode, the reference
clock is routed around the PLL and into the internal output
dividers.
• Input frequency range: 62.5MHz to 1GHz
• Output frequency range: 62.5MHz to 1GHz
• VCO range: 500MHz - 1GHz
• External feedback for "zero delay" clock regeneration with
configurable frequencies
• Programmable dividers allow for the following output-to-input
frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8
• Cycle-to-cycle jitter: 35ps (maximum)
• Static phase offset: 100ps
• Full 3.3V supply mode
• -40°C to 85°C ambient operating temperature
• Available in standard (RoHS 5) package
Block Diagram
Pin Assignment
Pullup
CLK
nCLK
MR
1
2
20 SEL1
19
SEL0
PLL_SEL
Q
nQ
÷1, ÷2, ÷4, ÷8,
3
4
18 VDD
17 PLL_SEL
0
÷16, ÷32, ÷64
nFB_IN
B
nQFB
QF
FB_IN
SEL2
VDDO
5
6
7
16
15
14
13
VDDA
SEL3
GND
Pulldown
CLK
nCLK
1
Pullup
nQFB
QFB
GND
8
Q
PLL
9
10
12 nQ
VDDO
11
8:1, 4:1, 2:1, 1:1,
1:2, 1:4, 1:8
Pulldown
Pullup
ICS874S02I
FB_IN
nFB_IN
20-Lead SOIC
7.5mm x 12.8mm x 2.3mm package body
M Package
Top View
Pulldown
Pulldown
Pulldown
Pulldown
Pulldown
SEL0
SEL1
SEL2
SEL3
MR
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Table 1. Pin Descriptions
Number
Name
CLK
Type
Description
1
2
Input
Input
Pulldown Non-inverting differential clock input.
nCLK
Pullup
Inverting differential clock input.
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset
causing the true outputs Q and QFB to go low and the inverted outputs nQ and
nQFB to go high. When logic LOW, the internal dividers and the outputs are
enabled. LVCMOS / LVTTL interface levels.
3
MR
Input
Pulldown
Inverting differential feedback input to phase detector for regenerating clocks
with “Zero Delay.” Connect to pin 8.
4
5
nFB_IN
FB_IN
Input
Input
Input
Pullup
Non-inverted differential feedback input to phase detector for regenerating
clocks with “Zero Delay.” Connect to pin 9.
Pulldown
6, 15,
19, 20
SEL2, SEL3,
SEL0, SEL1
Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels.
7, 11
8, 9
VDDO
nQFB, QFB
GND
Power
Output
Power
Output
Power
Output supply pins.
Differential feedback output pair. HSTL interface levels.
Power supply ground.
10, 14
12, 13
16
nQ, Q
Differential clock output pair. HSTL interface levels.
Analog supply pin.
VDDA
PLL select. Selects between the PLL and reference clock as the input to the
17
18
PLL_SEL
Input
Pullup
dividers. When LOW, selects reference clock. When HIGH, selects PLL.
LVCMOS/LVTTL interface levels.
VDD
Power
Core supply pin.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
CIN
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
pF
Input Capacitance
Input Pullup Resistor
2
RPULLUP
50
50
kΩ
RPULLDOWN Input Pulldown Resistor
kΩ
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1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
Function Tables
Table 3A. Control Input Function Table
Inputs
Outputs
PLL_SEL = 1
PLL Enable Mode
SEL3
SEL2
SEL1
SEL0
Reference Frequency Range (MHz)*
500 - 1000
250 - 500
Q/nQ
÷1
÷1
÷1
÷1
÷2
÷2
÷2
÷4
÷4
÷8
x2
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
125 - 250
62.5 - 125
500 - 1000
250 - 500
125 - 250
500 - 1000
250 - 500
500 - 1000
250 - 500
125 - 250
x2
62.5 - 125
x2
125 - 250
x4
62.5 - 125
x4
62.5 - 125
x8
*NOTE: VCO frequency range for all configurations above is 500MHz to 1GHz.
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Table 3B. PLL Bypass Function Table
Inputs
Outputs
PLL_SEL = 0
PLL Bypass Mode
SEL3
SEL2
SEL1
SEL0
Q/nQ
÷4
0z
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
÷4
÷4
÷8
÷8
÷8
÷16
÷16
÷32
÷64
÷2
÷2
÷4
÷1
÷2
÷1
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Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VDD
Inputs, VI
4.6V
-0.5V to VDD + 0.5V
Outputs, IO (LVDS)
Continuos Current
Surge Current
10mA
15mA
Package Thermal Impedance, θJA
64.7°C/W (0 lfpm)
Storage Temperature, TSTG
-65°C to 150°C
DC Electrical Characteristics
Table 4A. LVDS Power Supply DC Characteristics, VDD = VDDO = 3.3V 5ꢀ, TA = -40°C to 85°C
Symbol
VDD
Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum
3.465
VDD
Units
V
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
VDDA
VDDO
IDD
VDD – 0.20
3.135
3.3
V
3.3
3.465
97
V
mA
mA
mA
IDDA
20
IDDO
40
Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = VDDO = 3.3V 5ꢀ, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
2.2
Typical
Maximum
VDD + 0.3
0.8
Units
V
VIH
VIL
Input High Voltage
Input Low Voltage
-0.3
V
MR, SEL[0:3]
PLL_SEL
V
DD = VIN = 3.465V
150
µA
µA
µA
µA
IIH
Input High Current
VDD = VIN = 3.465V
10
MR, SEL[0:3]
PLL_SEL
V
DD = 3.465V, VIN = 0V
-10
IIL
Input Low Current
VDD = 3.465V, VIN = 0V
-150
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1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
Table 4C. Differential DC Characteristics, VDD = VDDO = 3.3V 5ꢀ, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
150
Units
µA
µA
µA
µA
V
CLK, FB_IN
V
DD = VIN = 3.465V
VDD = VIN = 3.465V
DD = 3.465V, VIN = 0V
IIH Input High Current
nCLK, nFB_IN
CLK, FB_IN
10
V
-10
-150
IIL
Input Low Current
nCLK, nFB_IN
VDD = 3.465V, VIN = 0V
VPP
Peak-to-Peak Input Voltage; NOTE 1
0.15
1.3
VCMR
Common Mode Input Voltage; NOTE 1, 2
GND + 0.5
VDD – 0.85
V
NOTE 1: VIL should not be less than -0.3V.
NOTE 2: Common mode input voltage is defined as VIH.
Table 4D. LVDS DC Characteristics, VDD = VDDO = 3.3V 5ꢀ, TA = -40°C to 85°C
Symbol
VOD
Parameter
Test Conditions
Minimum
Typical
Maximum
550
Units
mV
mV
V
Differential Output Voltage
VOD Magnitude Change
Offset Voltage
350
450
∆VOD
VOS
50
1.20
1.33
1.45
50
∆VOS
VOS Magnitude Change
mV
Table 5. Input Frequency Characteristics, VDD = VDDO = 3.3V 5ꢀ, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
PLL_SEL = 1
PLL_SEL = 0
Minimum
Typical
Maximum
1000
Units
MHz
MHz
62.5
FIN
Input Frequency
CLK/nCLK
1000
Table 6. AC Characteristics, VDD = VDDO = 3.3V 5ꢀ, TA = -40°C to 85°C
Parameter
fOUT
Symbol
Test Conditions
Minimum
62.5
Typical
Maximum
Units
MHz
ps
Output Frequency
1000
100
35
tsk(Ø)
tjit(cc)
tL
Static Phase Offset; NOTE 1, 2
Cycle-to-Cycle Jitter; NOTE 2
PLL Lock Time
PLL_SEL = 1
-100
ps
1
ms
ps
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20ꢀ to 80ꢀ
50
47
250
53
ꢀ
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when device
is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. Device will meet specifications after thermal
equilibrium has been reached under these conditions.
NOTE 1: Defined as the time difference between the input reference clock and the average feedback input signal, when the PLL is locked
and the input reference frequency is stable.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
IDT™ / ICS™ LVDS CLOCK GENERATOR
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1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
Parameter Measurement Information
V
DD
nCLK
CLK
SCOPE
Qx
V
VPP
VCMR
Cross Points
DD,
3.3V 5ꢀ
V
POWER SUPPLY
DDO
V
+
Float GND –
LVDS
DDA
nQx
GND
3.3V LVDS Output Load AC Test Circuit
Differential Input Level
nCLK
CLK
VOH
VOL
nQ, nQFB
nFB_IN
VOH
VOL
Q, QFB
➤
➤
FB_IN
tcycle n
tcycle n+1
➤
➤
➤
t(Ø)
➤
tjit(cc) = tcycle n – tcycle n+1
|
|
tjit(Ø) = t(Ø) – t(Ø) mean= Phase Jitter
t(Ø) mean = Static Phase Offset
1000 Cycles
Where t(Ø) is any random sample, and t(Ø) mean is the average
of the sampled cycles measured on the controlled edges)
Static Phase Offset
Cycle-to-Cycle Jitter
nQ, nQFB
Q, QFB
nQ, nQFB
Q, QFB
80ꢀ
tF
80ꢀ
tR
tPW
VOD
20ꢀ
tPERIOD
20ꢀ
tPW
odc =
x 100ꢀ
tPERIOD
Output Duty Cycle/Pulse Width/Period
Output Rise/Fall Time
IDT™ / ICS™ LVDS CLOCK GENERATOR
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1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
Parameter Measurement Information, continued
VDD
VDD
out
out
➤
out
out
➤
DC Input
LVDS
LVDS
DC Input
100
V
OD/∆ VOD
➤
VOS/∆ VOS
➤
Differential Output Voltage Setup
Offset Voltage Setup
Application Information
Recommendations for Unused Input and Output Pins
Inputs:
Outputs:
LVCMOS Control Pins
LVDS Outputs
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
All unused LVDS output pairs can be either left floating or
terminated with 100Ω across. If they are left floating, there should
be no trace attached.
IDT™ / ICS™ LVDS CLOCK GENERATOR
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1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
Power Supply Filtering Technique
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter perform-
ance, power supply isolation is required. The ICS874S02I provides
separate power supplies to isolate any high switching noise from
the outputs to the internal PLL. VDD, VDDA and VDDO should be
individually connected to the power supply plane through vias, and
0.01µF bypass capacitors should be used for each pin. Figure 1
illustrates this for a generic VDD pin and also shows that VDDA
requires that an additional 10Ω resistor along with a 10µF bypass
capacitor be connected to the VDDA pin.
3.3V
VDD
.01µF
.01µF
10Ω
VDDA
10µF
Figure 1. Power Supply Filtering
Wiring the Differential Input to Accept Single-Ended Levels
Figure 2 shows how the differential input can be wired to accept
single-ended levels. The reference voltage V_REF = VDD/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to position the V_REF in the
center of the input voltage swing. For example, if the input clock
swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and
VDD
R1
1K
Single Ended Clock Input
R2/R1 = 0.609.
CLK
V_REF
nCLK
C1
0.1u
R2
1K
Figure 2. Single-Ended Signal Driving Differential Input
IDT™ / ICS™ LVDS CLOCK GENERATOR
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1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
Differential Clock Input Interface
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, and
other differential signals. Both signals must meet the VPP and
VCMR input requirements. Figures 3A to 3E show interface
examples for the HiPerClockS CLK/nCLK input driven by the most
common driver types. The input interfaces suggested here are
examples only. Please consult with the vendor of the driver
component to confirm the driver termination requirements. For
example, in Figure 3A, the input termination applies for IDT
HiPerClockS open emitter LVHSTL drivers. If you are using an
LVHSTL driver from another vendor, use their termination
recommendation.
3.3V
3.3V
3.3V
1.8V
Zo = 50Ω
Zo = 50Ω
CLK
CLK
Zo = 50Ω
nCLK
Zo = 50Ω
HiPerClockS
Input
nCLK
LVPECL
HiPerClockS
LVHSTL
R1
50
R2
50
Input
R1
50
R2
50
IDT
HiPerClockS
LVHSTL Driver
R2
50
3A. HiPerClockS CLK/nCLK Input Driven by an IDT
Open Emitter HiPerClockS LVHSTL Driver
Figure 3B. HiPerClockS CLK/nCLK Input
Driven by a 3.3V LVPECL Driver
3.3V
3.3V
3.3V
3.3V
3.3V
R3
125
R4
125
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
CLK
CLK
R1
100
nCLK
nCLK
Zo = 50Ω
Receiver
HiPerClockS
Input
LVPECL
LVDS
R1
84
R2
84
Figure 3D. HiPerClockS CLK/nCLK Input
Driven by a 3.3V LVDS Driver
Figure 3C. HiPerClockS CLK/nCLK Input
Driven by a 3.3V LVPECL Driver
2.5V
3.3V
2.5V
R3
R4
120
120
Zo = 60Ω
Zo = 60Ω
CLK
nCLK
HiPerClockS
SSTL
R1
120
R2
120
Figure 3E. HiPerClockS CLK/nCLK Input
Driven by a 2.5V SSTL Driver
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1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
3.3V LVDS Driver Termination
A general LVDS interface is shown in Figure 4. In a 100Ω
differential transmission line environment, LVDS drivers require a
matched load termination of 100Ω across near the receiver input.
For a multiple LVDS outputs buffer, if only partial outputs are used,
it is recommended to terminate the unused outputs.
3.3V
50Ω
3.3V
LVDS Driver
+
–
R1
100Ω
50Ω
100Ω Differential Transmission Line
Figure 4. Typical LVDS Driver Termination
Schematic Example
The schematic of the ICS874S02I layout example is shown in
Figure 5A. The ICS874S02I recommended PCB board layout for
this example is shown in Figure 5B. This layout example is used as
a general guideline. The layout in the actual system will depend on
the selected component types and the density of the P.C. board.
3.3V
(155.52 MHz)
U1
Zo = 50 Ohm
SEL1
SEL0
1
2
3
20
19
18
17
16
15
14
13
12
11
C1
0.1uF
CLK
SEL1
SEL0
VDDI
PLL_SEL
VDDA
SEL3
GND
nCLK
MR
VDD
PLL_SEL
VDDA
Zo = 50 Ohm
3.3V PECL Driv er
4
5
R7
VDD
nFB_IN
FB_IN
SEL2
VDDO
nQFB
QFB
SEL2
VDDO
6
SEL3
7
10
C16
8
C11
Q
9
0.01u
nQ
R8
50
R9
50
10
VDDO
10u
GND
VDDO
R2
100
ICS8745B-21
ICS874S02I
SP = Space (i.e. not intstalled)
(77.76 MHz)
R10
50
VDD
+
-
RU3
1K
RU4
1K
RU5
SP
RU6
1K
RU7
SP
Bypass capacitors located
near the power pins
R4
PLL_SEL
SEL0
100
LVDS_input
VDD=3.3V
VDDO=3.3V
SEL1
(U1-7)
(U1-11)
SEL2
VDDO
SEL3
C4
0.1uF
C2
0.1uF
Zo = 100 Ohm Dif ferential
RD3
SP
RD4
SP
RD5
1K
RD6
SP
RD7
1K
SEL[3:0] = 0101,
Divide by 2
Figure 5A. ICS874S02I LVDS Zero Delay Buffer Schematic Example
IDT™ / ICS™ LVDS CLOCK GENERATOR
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The following component footprints are used in this layout
example.
trace delay might be restricted by the available space on the board
and the component location. While routing the traces, the clock
signal traces should be routed first and should be locked prior to
routing other signal traces.
All the resistors and capacitors are size 0603.
• The 100Ω differential output traces should have the same
length.
Power and Grounding
Place the decoupling capacitors as close as possible to the power
pins. If space allows, placement of the decoupling capacitor on the
component side is preferred. This can reduce unwanted
inductance between the decoupling capacitor and the power pin
caused by the via.
• Avoid sharp angles on the clock trace. Sharp angle turns
cause the characteristic impedance to change on the
transmission lines.
• Keep the clock traces on the same layer. Whenever possible,
avoid placing vias on the clock traces. Placement of vias on
the traces can affect the trace characteristic impedance and
hence degrade signal integrity.
Maximize the power and ground pad sizes and number of vias
capacitors. This can reduce the inductance between the power and
ground planes and the component power and ground pins.
• To prevent cross talk, avoid routing other signal traces in
parallel with the clock traces. If running parallel traces is
unavoidable, allow a separation of at least three trace widths
between the differential clock trace and the other signal trace.
The RC filter consisting of R7, C11, and C16 should be placed as
close to the VDDA pin as possible.
Clock Traces and Termination
• Make sure no other signal traces are routed between the
clock trace pair.
Poor signal integrity can degrade the system performance or cause
system failure. In synchronous high-speed digital systems, the
clock signal is less tolerant to poor signal integrity than other
signals. Any ringing on the rising or falling edge or excessive ring
back can cause system failure. The shape of the trace and the
• The series termination resistors should be located as close to
the driver pins as possible.
U1
ICS874S02I
ICS8745B-21
GND
VDDO
C1
VDD
C16
VDDA
VIA
C11
C4
R7
100 Ohm
Differential
Traces
C2
Figure 5B. PCB Board Layout for ICS874S02I
IDT™ / ICS™ LVDS CLOCK GENERATOR
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Power Considerations
This section provides information on power dissipation and junction temperature for the ICS874S02I.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS874S02I is the sum of the core power plus the analog power plus the power dissipated in the load(s).
The following is the power dissipation for VDD = 3.3V + 5ꢀ = 3.465V, which gives worst case results.
•
The maximum current at 85°C is as follows:
IDD_MAX = 93mA
IDDA_MAX = 19mA
IDDO_MAX = 36mA
•
•
Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX) = 3.465V * (93mA + 19mA) = 388.08mW
Power (outputs)MAX = VDDO_MAX* IDDO_MAX = 3.465V * 36mA = 124.74mW
Total Power_MAX = 388.08mW + 124.74mW = 512.82mW
•
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device.
The maximum recommended junction temperature for HiPerClockS devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow
and a multi-layer board, the appropriate value is 64.7°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.513W * 64.7°C/W = 118.2°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type
of board (single layer or multi-layer).
Table 7. Thermal Resistance θJA for 20 Lead SOIC, Forced Convection
θJA by Velocity
Linear Feet per Minute
0
200
500
Multi-Layer PCB, JEDEC Standard Test Boards
64.7°C/W
56.7°C/W
53.5°C/W
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Reliability Information
Table 8. θJA vs. Air Flow Table for a 20 Lead SOIC
θJA by Velocity
Linear Feet per Minute
0
200
500
Multi-Layer PCB, JEDEC Standard Test Boards
64.7°C/W
56.7°C/W
53.5°C/W
Transistor Count
The transistor count for ICS874S02I is: 1358
Package Outline and Package Dimensions
Package Outline - M Suffix for 20 Lead SOIC
Table 9. Package Dimensions for 20 Lead SOIC
300 Millimeters
All Dimensions in Millimeters
Symbol
Minimum
Maximum
N
A
A1
A2
B
C
D
E
20
2.65
0.10
2.05
0.33
0.18
12.60
7.40
2.55
0.51
0.32
13.00
7.60
e
1.27 Basic
H
h
10.00
0.25
0.40
0°
10.65
0.75
1.27
8°
L
α
Reference Document: JEDEC Publication 95, MS-013, MS-119
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Ordering Information
Table 10. Ordering Information
Part/Order Number
874S02BMI
874S02BMIT
874S02BMILF
874S02BMILFT
Marking
Package
20 Lead SOIC
20 Lead SOIC
Shipping Packaging
Tube
1000 Tape & Reel
Tube
Temperature
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
ICS874S02BMI
ICS874S02BMI
ICS874S02BMILF
ICS874S02BMILF
Lead-Free, 20 Lead SOIC
Lead-Free, 20 Lead SOIC
1000 Tape & Reel
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for
the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT
product for use in life support devices or critical medical instruments.
IDT™ / ICS™ LVDS CLOCK GENERATOR
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Contact Information:
www.IDT.com
Corporate Headquarters
Sales
Technical Support
Integrated Device Technology, Inc.
800-345-7015 (inside USA)
+408-284-8200 (outside USA)
Fax: 408-284-2775
netcom@idt.com
+480-763-2056
6024 Silver Creek Valley Road
San Jose, CA 95138
United States
800-345-7015 (inside USA)
+408-284-8200 (outside USA)
www.IDT.com/go/contactIDT
© 2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device
Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered
trademarks used to identify products or services of their respective owners.
www.IDT.com
Printed in USA
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