ICS874S02BMI_技术文档

1:1 Differential-to-LVDS Zero Delay

Clock Generator

874S02I

Data Sheet

General Description

Features

The 874S02I is a highly versatile 1:1 Differential- to-LVDS Clock

Generator and a member of the family of High Performance Clock

Solutions from IDT. The 874S02I has a fully integrated PLL and

can be configured as a zero delay buffer, multiplier or divider, and

has an output frequency range of 62.5MHz to 1GHz. The

reference divider, feedback divider and output divider are each

programmable, thereby allowing for the following output-to-input

frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8. The external

feedback allows the device to achieve “zero delay” between the

input clock and the output clocks. The PLL_SEL pin can be used

to bypass the PLL for system test and debug purposes. In bypass

mode, the reference clock is routed around the PLL and into the

internal output dividers.

• One differential LVDS output pair and

one differential feedback output pair

• One differential clock input pair

• CLK/nCLK can accept the following differential input levels:

LVPECL, LVDS, LVHSTL, SSTL

• Input frequency range: 62.5MHz to 1GHz

• Output frequency range: 62.5MHz to 1GHz

• VCO range: 500MHz - 1GHz

• External feedback for "zero delay" clock regeneration with

configurable frequencies

• Programmable dividers allow for the following output-to-input

frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8

• Cycle-to-cycle jitter: 35ps (maximum)

• Static phase offset: 100ps

• Full 3.3V supply mode

• -40°C to 85°C ambient operating temperature

• Available in lead-free packages

Block Diagram

Pin Assignment

Pullup

CLK

nCLK

MR

1

2

20 SEL1

PLL_SEL

19

SEL0

Q

nQ

÷1, ÷2, ÷4, ÷8,

3

4

18

V^DD

0

÷16, ÷32, ÷64

nFB_IN

17 PLL_SEL

B

nQFB

QF

FB_IN

SEL2

V^DDO

5

6

7

16

15

14

13

V^DDA

SEL3

GND

Pulldown

CLK

nCLK

1

Pullup

nQFB

QFB

GND

8

Q

PLL

9

10

12 nQ

V^DDO

11

8:1, 4:1, 2:1, 1:1,

1:2, 1:4, 1:8

Pulldown

Pullup

874S02I

FB_IN

nFB_IN

20-Lead SOIC

7.5mm x 12.8mm x 2.3mm package body

M Package

Top View

Pulldown

SEL0

SEL1

SEL2

SEL3

MR

1

January 26, 2016

874S02I Data Sheet

Table 1. Pin Descriptions

Number

Name

CLK

Type

Description

1

2

Input

Pulldown Non-inverting differential clock input.

nCLK

Pullup

Inverting differential clock input.

Active HIGH Master Reset. When logic HIGH, the internal dividers are reset

causing the true outputs Q and QFB to go low and the inverted outputs nQ and

nQFB to go high. When logic LOW, the internal dividers and the outputs are

enabled. LVCMOS / LVTTL interface levels.

3

MR

Input

Pulldown

Inverting differential feedback input to phase detector for regenerating clocks

with “Zero Delay.” Connect to pin 8.

4

5

nFB_IN

FB_IN

Input

Pullup

Non-inverted differential feedback input to phase detector for regenerating

clocks with “Zero Delay.” Connect to pin 9.

Pulldown

6, 15,

19, 20

SEL2, SEL3,

SEL0, SEL1

Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels.

7, 11

8, 9

V_DDO

nQFB, QFB

GND

Power

Output

Power

Output

Power

Output supply pins.

Differential feedback output pair. HSTL interface levels.

Power supply ground.

10, 14

12, 13

16

nQ, Q

Differential clock output pair. HSTL interface levels.

Analog supply pin.

V_DDA

PLL select. Selects between the PLL and reference clock as the input to the

17

PLL_SEL

Input

Pullup

dividers. When LOW, selects reference clock. When HIGH, selects PLL.

LVCMOS/LVTTL interface levels.

18

V_DD

Power

Core supply pin.

NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

Table 2. Pin Characteristics

Symbol

C_IN

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

pF

Input Capacitance

Input Pullup Resistor

2

R_PULLUP

50

k

R_PULLDOWNInput Pulldown Resistor

k

2

January 26, 2016

874S02I Data Sheet

Function Tables

Table 3A. Control Input Function Table

Inputs

Outputs

PLL_SEL = 1

PLL Enable Mode

SEL3

SEL2

SEL1

SEL0

Reference Frequency Range (MHz)*

500 - 1000

250 - 500

Q/nQ

÷1

÷2

÷4

÷8

x2

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

125 - 250

62.5 - 125

500 - 1000

250 - 500

125 - 250

500 - 1000

250 - 500

500 - 1000

250 - 500

125 - 250

x2

62.5 - 125

x2

125 - 250

x4

62.5 - 125

x4

62.5 - 125

x8

*NOTE: VCO frequency range for all configurations above is 500MHz to 1GHz.

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January 26, 2016

874S02I Data Sheet

Table 3B. PLL Bypass Function Table

Inputs

Outputs

PLL_SEL = 0

PLL Bypass Mode

SEL3

SEL2

SEL1

SEL0

Q/nQ

÷4

0z

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

÷4

÷8

÷16

÷32

÷64

÷2

÷4

÷1

÷2

÷1

4

January 26, 2016

874S02I Data Sheet

Absolute Maximum Ratings

NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.

These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond

those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for

extended periods may affect product reliability.

Item

Rating

Supply Voltage, V_DD

Inputs, V_I

4.6V

-0.5V to V_DD+ 0.5V

Outputs, I_O(LVDS)

Continuous Current

Surge Current

10mA

15mA

Package Thermal Impedance, _JA

64.7°C/W (0 lfpm)

Storage Temperature, T_STG

-65C to 150C

DC Electrical Characteristics

Table 4A. LVDS Power Supply DC Characteristics, V_DD= V_DDO= 3.3V 5ꢀ, T_A= -40°C to 85°C

Symbol

V_DD

Parameter

Test Conditions

Minimum

3.135

Typical

3.3

Maximum

3.465

V_DD

Units

V

Core Supply Voltage

Analog Supply Voltage

Output Supply Voltage

Power Supply Current

Analog Supply Current

Output Supply Current

V_DDA

V_DDO

I_DD

V_DD– 0.20

3.135

3.3

V

3.3

3.465

97

V

mA

I_DDA

20

I_DDO

40

Table 4B. LVCMOS/LVTTL DC Characteristics, V_DD= V_DDO= 3.3V 5ꢀ, T_A= -40°C to 85°C

Symbol Parameter

Test Conditions

Minimum

2.2

Typical

Maximum

V_DD+ 0.3

0.8

Units

V

V_IH

V_IL

Input High Voltage

Input Low Voltage

-0.3

V

MR, SEL[0:3]

PLL_SEL

V

_DD= V_IN= 3.465V

150

µA

I_IH

Input High Current

V

_DD= V_IN= 3.465V

10

MR, SEL[0:3]

PLL_SEL

V

_DD= 3.465V, V_IN= 0V

-10

I_IL

Input Low Current

V_DD= 3.465V, V_IN= 0V

-150

5

January 26, 2016

874S02I Data Sheet

Table 4C. Differential DC Characteristics, V_DD= V_DDO= 3.3V 5ꢀ, T_A= -40°C to 85°C

Symbol Parameter

Test Conditions

Minimum

Typical

Maximum

Units

µA

V

CLK, FB_IN

V

_DD= V_IN= 3.465V

V_DD= V_IN= 3.465V

_DD= 3.465V, V_IN= 0V

150

10

I_IHInput High Current

nCLK, nFB_IN

CLK, FB_IN

V

-10

-150

I_IL

Input Low Current

nCLK, nFB_IN

V_DD= 3.465V, V_IN= 0V

V_PP

Peak-to-Peak Input Voltage; NOTE 1

0.15

1.3

V_CMR

Common Mode Input Voltage; NOTE 1, 2

GND + 0.5

V_DD– 0.85

V

NOTE 1: V_ILshould not be less than -0.3V.

NOTE 2: Common mode input voltage is defined as V_IH.

Table 4D. LVDS DC Characteristics, V_DD= V_DDO= 3.3V 5ꢀ, T_A= -40°C to 85°C

Symbol

V_OD

Parameter

Test Conditions

Minimum

Typical

Maximum

550

Units

mV

V

Differential Output Voltage

V_ODMagnitude Change

Offset Voltage

350

450

V_OD

V_OS

50

1.20

1.33

1.45

50

V_OS

V_OSMagnitude Change

mV

Table 5. Input Frequency Characteristics, V_DD= V_DDO= 3.3V 5ꢀ, T_A= -40°C to 85°C

Symbol

Parameter

Test Conditions

PLL_SEL = 1

PLL_SEL = 0

Minimum

Typical

Maximum

1000

Units

MHz

62.5

F_IN

Input Frequency

CLK/nCLK

1000

Table 6. AC Characteristics, V_DD= V_DDO= 3.3V 5ꢀ, T_A= -40°C to 85°C

Parameter

f_OUT

Symbol

Test Conditions

Minimum

62.5

Typical

Maximum

Units

MHz

ps

Output Frequency

1000

100

35

tsk(Ø)

tjit(cc)

t_L

Static Phase Offset; NOTE 1, 2

Cycle-to-Cycle Jitter; NOTE 2

PLL Lock Time

PLL_SEL = 1

-100

ps

1

ms

ps

t_R/ t_F

odc

Output Rise/Fall Time

Output Duty Cycle

20ꢀ to 80ꢀ

50

47

250

53

ꢀ

NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when device

is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. Device will meet specifications after thermal

equilibrium has been reached under these conditions.

NOTE 1: Defined as the time difference between the input reference clock and the average feedback input signal, when the PLL is locked

and the input reference frequency is stable.

NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.

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January 26, 2016

874S02I Data Sheet

Parameter Measurement Information

V

DD

nCLK

CLK

V_PP

V_CMR

V

Cross Points

DD,

3.3V 5ꢀ

V

DDO

V

DDA

GND

3.3V LVDS Output Load AC Test Circuit

Differential Input Level

nCLK

CLK

V_OH

V_OL

nQ, nQFB

Q, QFB

nFB_IN

V_OH

V_OL

FB_IN

tcycle n

tcycle n+1

➤

t(Ø)

➤

tjit(cc) = tcycle n – tcycle n+1

|

tjit(Ø) = ⎪ t(Ø) – t(Ø) mean⎪= Phase Jitter

t(Ø) mean = Static Phase Offset

1000 Cycles

Where t(Ø) is any random sample, and t(Ø) mean is the average

of the sampled cycles measured on the controlled edges)

Static Phase Offset

Cycle-to-Cycle Jitter

nQ, nQFB

Q, QFB

nQ, nQFB

Q, QFB

80ꢀ

t_F

80ꢀ

t_R

V_OD

20ꢀ

Output Duty Cycle/Pulse Width/Period

Output Rise/Fall Time

7

January 26, 2016

874S02I Data Sheet

Parameter Measurement Information, continued

Differential Output Voltage Setup

Offset Voltage Setup

Application Information

Recommendations for Unused Input and Output Pins

Inputs:

Outputs:

LVCMOS Control Pins

LVDS Outputs

All control pins have internal pull-ups or pull-downs; additional

resistance is not required but can be added for additional

protection. A 1k resistor can be used.

All unused LVDS output pairs can be either left floating or

terminated with 100 across. If they are left floating, there should

be no trace attached.

8

January 26, 2016

874S02I Data Sheet

Power Supply Filtering Technique

As in any high speed analog circuitry, the power supply pins are

vulnerable to random noise. To achieve optimum jitter perform-

ance, power supply isolation is required. The 874S02I provides

separate power supplies to isolate any high switching noise from

the outputs to the internal PLL. V_DD,V_DDAand V_DDOshould be

individually connected to the power supply plane through vias, and

0.01µF bypass capacitors should be used for each pin. Figure 1

illustrates this for a generic V_DDpin and also shows that V_DDA

requires that an additional 10 resistor along with a 10F bypass

capacitor be connected to the V_DDApin.

3.3V

V_DD

.01µF

10Ω

V_DDA

10µF

Figure 1. Power Supply Filtering

Wiring the Differential Input to Accept Single-Ended Levels

Figure 2 shows how the differential input can be wired to accept

single-ended levels. The reference voltage V_REF = V_DD/2 is

generated by the bias resistors R1, R2 and C1. This bias circuit

should be located as close as possible to the input pin. The ratio

of R1 and R2 might need to be adjusted to position the V_REF in

the center of the input voltage swing. For example, if the input

V_DD

R1

1K

Single Ended Clock Input

clock swing is only 2.5V and V_DD= 3.3V, V_REF should be 1.25V

and R2/R1 = 0.609.

CLK

V_REF

nCLK

C1

0.1u

R2

1K

Figure 2. Single-Ended Signal Driving Differential Input

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January 26, 2016

874S02I Data Sheet

Differential Clock Input Interface

The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, and

other differential signals. Both signals must meet the V_PPand

V_CMRinput requirements. Figures 3A to 3E show interface

examples for the HiPerClockS CLK/nCLK input driven by the most

common driver types. The input interfaces suggested here are

examples only. Please consult with the vendor of the driver

component to confirm the driver termination requirements. For

example, in Figure 3A, the input termination applies for IDT

HiPerClockS open emitter LVHSTL drivers. If you are using an

LVHSTL driver from another vendor, use their termination

recommendation.

3.3V

1.8V

Zo = 50Ω

CLK

Zo = 50Ω

nCLK

Differential

Input

LVHSTL

R1

50Ω

R2

50Ω

IDT

LVHSTL Driver

3A. HiPerClockS CLK/nCLK Input Driven by an IDT

Open Emitter HiPerClockS LVHSTL Driver

Figure 3B. HiPerClockS CLK/nCLK Input

Driven by a 3.3V LVPECL Driver

Figure 3D. HiPerClockS CLK/nCLK Input

Driven by a 3.3V LVDS Driver

Figure 3C. HiPerClockS CLK/nCLK Input

Driven by a 3.3V LVPECL Driver

2.5V

3.3V

2.5V

R3

R4

120Ω

Zo = 60Ω

CLK

nCLK

Differential

Input

SSTL

R1

R2

120Ω

Figure 3E. HiPerClockS CLK/nCLK Input

Driven by a 2.5V SSTL Driver

10

January 26, 2016

874S02I Data Sheet

3.3V LVDS Driver Termination

A general LVDS interface is shown in Figure 4. In a 100

differential transmission line environment, LVDS drivers require a

matched load termination of 100 across near the receiver input.

For a multiple LVDS outputs buffer, if only partial outputs are used,

it is recommended to terminate the unused outputs.

3.3V

50Ω

3.3V

LVDS Driver

+

–

R1

100Ω

50Ω

100Ω Differential Transmission Line

Figure 4. Typical LVDS Driver Termination

Schematic Example

The schematic of the 874S02I layout example is shown in Figure

5A. The 874S02I recommended PCB board layout for this example

is shown in Figure 5B. This layout example is used as a general

guideline. The layout in the actual system will depend on the

selected component types and the density of the P.C. board.

3.3V

(155.52 MHz)

U1

Zo = 50 Ohm

SEL1

SEL0

VDD

PLL_SEL

VDDA

1

2

3

4

5

6

7

8

9

20

19

18

17

16

15

14

13

12

11

C1

0.1uF

CLK

nCLK

MR

nFB_IN

FB_IN

SEL2

VDDO

nQFB

QFB

SEL1

SEL0

VDDI

PLL_SEL

VDDA

SEL3

GND

Q

nQ

VDDO

Zo = 50 Ohm

R7

VDD

SEL2

VDDO

SEL3

3.3V PECL Driv er

10

C11

0.01u

C16

10u

R8

50

R9

50

10

VDDO

GND

R2

100

ICS8745B-21

ICS874S02I

SP = Space (i.e. not intstalled)

(77.76 MHz)

R10

50

VDD

+

-

RU3

1K

RU4

1K

RU5

SP

RU6

1K

RU7

SP

Bypass capacitors located

near the power pins

R4

100

PLL_SEL

SEL0

SEL1

SEL2

SEL3

LVDS_input

VDD=3.3V

(U1-7)

(U1-11)

VDDO

VDDO=3.3V

C4

0.1uF

C2

0.1uF

Zo = 100 Ohm Dif ferential

RD3

SP

RD4

SP

RD5

1K

RD6

SP

RD7

1K

SEL[3:0] = 0101,

Divide by 2

Figure 5A. 874S02I LVDS Zero Delay Buffer Schematic Example

The following component footprints are used in this layout

example.

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January 26, 2016

874S02I Data Sheet

All the resistors and capacitors are size 0603.

trace delay might be restricted by the available space on the

board and the component location. While routing the traces, the

clock signal traces should be routed first and should be locked

prior to routing other signal traces.

Power and Grounding

Place the decoupling capacitors as close as possible to the power

pins. If space allows, placement of the decoupling capacitor on

the component side is preferred. This can reduce unwanted

inductance between the decoupling capacitor and the power pin

caused by the via.

• The 100 differential output traces should have the same

length.

• Avoid sharp angles on the clock trace. Sharp angle turns

cause the characteristic impedance to change on the

transmission lines.

Maximize the power and ground pad sizes and number of vias

capacitors. This can reduce the inductance between the power

and ground planes and the component power and ground pins.

• Keep the clock traces on the same layer. Whenever possible,

avoid placing vias on the clock traces. Placement of vias on

the traces can affect the trace characteristic impedance and

hence degrade signal integrity.

The RC filter consisting of R7, C11, and C16 should be placed as

close to the V_DDApin as possible.

Clock Traces and Termination

• To prevent cross talk, avoid routing other signal traces in

parallel with the clock traces. If running parallel traces is

unavoidable, allow a separation of at least three trace widths

between the differential clock trace and the other signal trace.

Poor signal integrity can degrade the system performance or

cause system failure. In synchronous high-speed digital systems,

the clock signal is less tolerant to poor signal integrity than other

signals. Any ringing on the rising or falling edge or excessive ring

back can cause system failure. The shape of the trace and the

• Make sure no other signal traces are routed between the

clock trace pair.

• The series termination resistors should be located as close to

the driver pins as possible.

U1

ICS874S02I

ICS8745B-21

GND

VDDO

C1

VDD

C16

VDDA

VIA

C11

C4

R7

100 Ohm

Differential

Traces

C2

Figure 5B. PCB Board Layout for 874S02I

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January 26, 2016

874S02I Data Sheet

Power Considerations

This section provides information on power dissipation and junction temperature for the 874S02I.

Equations and example calculations are also provided.

1. Power Dissipation.

The total power dissipation for the 874S02I is the sum of the core power plus the analog power plus the power dissipated in the load(s).

The following is the power dissipation for V_DD= 3.3V + 5ꢀ = 3.465V, which gives worst case results.

•

The maximum current at 85°C is as follows:

I_{DD_MAX}= 93mA

I_{DDA_MAX}= 19mA

I_{DDO_MAX}= 36mA

•

Power (core)_MAX= V_{DD_MAX}* (I_{DD_MAX}+ I_{DDA_MAX}) = 3.465V * (93mA + 19mA) = 388.08mW

Power (outputs)_MAX= V_{DDO_MAX}* I_{DDO_MAX}= 3.465V * 36mA = 124.74mW

Total Power__MAX= 388.08mW + 124.74mW = 512.82mW

•

2. Junction Temperature.

Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device.

The maximum recommended junction temperature for HiPerClockS devices is 125°C.

The equation for Tj is as follows: Tj = _JA* Pd_total + T_A

Tj = Junction Temperature

_JA= Junction-to-Ambient Thermal Resistance

Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)

T_A= Ambient Temperature

In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance _JAmust be used. Assuming no air flow

and a multi-layer board, the appropriate value is 64.7°C/W per Table 7 below.

Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:

85°C + 0.513W * 64.7°C/W = 118.2°C. This is well below the limit of 125°C.

This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type

of board (single layer or multi-layer).

Table 7. Thermal Resistance _JAfor 20 Lead SOIC, Forced Convection

_JAby Velocity

Linear Feet per Minute

0

200

500

Multi-Layer PCB, JEDEC Standard Test Boards

64.7°C/W

56.7°C/W

53.5°C/W

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January 26, 2016

874S02I Data Sheet

Reliability Information

Table 8. _JAvs. Air Flow Table for a 20 Lead SOIC

_JAby Velocity

Linear Feet per Minute

0

200

500

Multi-Layer PCB, JEDEC Standard Test Boards

64.7°C/W

56.7°C/W

53.5°C/W

Transistor Count

The transistor count for 874S02I is: 1358

Package Outline and Package Dimensions

Package Outline - M Suffix for 20 Lead SOIC

Table 9. Package Dimensions for 20 Lead SOIC

300 Millimeters

All Dimensions in Millimeters

Symbol

Minimum

Maximum

N

A

A1

A2

B

C

D

E

20

2.65

0.10

2.05

0.33

0.18

12.60

7.40

2.55

0.51

0.32

13.00

7.60

e

1.27 Basic

H

h

10.00

0.25

0.40

0°

10.65

0.75

1.27

8°

L



Reference Document: JEDEC Publication 95, MS-013, MS-119

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January 26, 2016

874S02I Data Sheet

Ordering Information

Table 10. Ordering Information

Part/Order Number

874S02BMILF

874S02BMILFT

Marking

ICS874S02BMILF

Package

Lead-Free, 20 Lead SOIC

Shipping Packaging

Tube

Temperature

-40C to 85C

Tape & Reel

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January 26, 2016

874S02I Data Sheet

Revision History]

Revision Date

Description of Change

▪ Removed ICS from the part number where needed.

January 26, 2016

▪ General Description - Removed ICS Chip and HiPerClockS.

▪ Ordering Information - removed quantity from tape and reel.

▪ Updated data sheet header and footer.

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January 26, 2016

874S02I Data Sheet

Corporate Headquarters

6024 Silver Creek Valley Road

San Jose, CA 95138 USA

www.IDT.com

Sales

Tech Support

www.idt.com/go/support

1-800-345-7015 or 408-284-8200

Fax: 408-284-2775

www.IDT.com/go/sales

DISCLAIMER Integrated Device Technology, Inc. (IDT) reserves the right to modify the products and/or specifications described herein at any time, without notice, at IDT's sole discretion. Performance specifications

and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein

is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability,

or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties.

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型号：	ICS874S02BMI
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	PLL Based Clock Driver, 874S Series, 1 True Output(s), 0 Inverted Output(s), PDSO20, 7.50 X 12.80 MM, 2.30 MM HEIGHT, MS-013, MO-119, SOIC-20 驱动光电二极管逻辑集成电路
文件：	总17页 (文件大小：395K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ICS874S02BMI [IDT]

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