ICS874S02AMILFT [IDT]
PLL Based Clock Driver, 874S Series, 1 True Output(s), 0 Inverted Output(s), PDSO20, 7.50 X 12.80 MM, 2.30 MM HEIGHT, ROHS COMPLIANT, MS-013, MO-119, SOIC-20;
| 型号： | ICS874S02AMILFT |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | PLL Based Clock Driver, 874S Series, 1 True Output(s), 0 Inverted Output(s), PDSO20, 7.50 X 12.80 MM, 2.30 MM HEIGHT, ROHS COMPLIANT, MS-013, MO-119, SOIC-20 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总15页 (文件大小：200K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
ICS874S02I
1:1 DIFFERENTIAL-TO-LVDS
ZERO DELAY CLOCK GENERATOR
Integrated
Circuit
Systems, Inc.
GENERAL DESCRIPTION
FEATURES
The ICS874S02I is a highly versatile 1:1 LVDS • One differential LVDS output pair designed to meet
ICS
Clock Generator and a member of the
HiPerClockS™family of High Performance Clock
Solutions from ICS. The ICS874S02I has a fully
integrated PLL and can be configured as zero
or exceed the requirements of ANSI TIA/EIA-644,
One differential feedback output pair
HiPerClockS™
• Differential CLK, nCLK input pair
delay buffer, multiplier or divider, and has an output frequency
range of 62.5MHz to 1GHz. The Reference Divider, Feed-
back Divider and Output Divider are each programmable,
thereby allowing for the following output-to-input frequency
ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8. The external feedback
allows the device to achieve “zero delay” between the input
clock and the output clock. The PLL_SEL pin can be used
to bypass the PLL for system test and debug purposes. In
bypass mode, the reference clock is routed around the PLL
and into the internal output dividers.
• CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, SSTL
• Output frequency range: 62.5MHz to 1GHz
• Input frequency range: 62.5MHz to 1GHz
• VCO range: 500MHz to 1GHz
• External feedback for “zero delay” clock regeneration
with configurable frequencies
• Programmable dividers allow for the following output-to-input
frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8
• Cycle-to-cycle jitter: 26ps (typical)
• Output skew: 4ps (typical)
• Static phase offset: 98ps (typical)
• 3.3V supply voltage
• -40°C to 85°C ambient operating temperature
• Available in both standard and lead-free RoHS-compliant
packages
BLOCK DIAGRAM
PIN ASSIGNMENT
PLL_SEL
CLK
nCLK
MR
nFB_IN
FB_IN
SEL2
VDDO
nQFB
QFB
GND
1
2
3
4
5
6
7
8
20
19
18
17
16
15
14
13
12
11
SEL1
SEL0
VDD
PLL_SEL
VDDA
SEL3
GND
Q
÷1, ÷2, ÷4, ÷8,
Q
0
1
÷16, ÷32, ÷64
nQ
CLK
nCLK
QFB
nQFB
PLL
9
10
nQ
VDDO
8:1, 4:1, 2:1, 1:1,
1:2, 1:4, 1:8
FB_IN
nFB_IN
ICS874S02I
20-Lead, 300-MIL SOIC
7.5mm x 12.8mm x 2.3mm body package
M Package
Top View
SEL0
SEL1
SEL2
SEL3
MR
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on
initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications
without notice.
874S02AMI
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REV.A APRIL 27, 2006
1
PRELIMINARY
ICS874S02I
1:1 DIFFERENTIAL-TO-LVDS
ZERO DELAY CLOCK GENERATOR
Integrated
Circuit
Systems, Inc.
TABLE 1. PIN DESCRIPTIONS
Number
Name
CLK
Type
Description
1
2
Input Pulldown Non-inverting differential clock input.
nCLK
Input
Pullup Inverting differential clock input.
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset
causing the true outputs Qx to go low and the inverted outputs nQx to go
high. When logic LOW, the internal dividers and the outputs are enabled.
LVCMOS / LVTTL interface levels.
3
MR
Input Pulldown
4
5
nFB_IN
FB_IN
SEL2
VDDO
Input
Pullup Feedback input to phase detector for regenerating clocks with "zero delay".
Input Pulldown Feedback input to phase detector for regenerating clocks with "zero delay".
Input Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels.
6
7, 11
8, 9
10, 14
12, 13
15
Power
Output supply pins.
nQFB, QFB Output
Differential feedback outputs. LVDS interface levels.
Power supply ground.
GND
nQ, Q
SEL3
VDDA
Power
Output
Differential clock outputs. LVDS interface levels.
Input Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels.
16
Power
Analog supply pin.
Selects between the PLL and reference clock as the input to the dividers.
When HIGH, selects PLL. When LOW, selects the reference clock.
LVCMOS / LVTTL interface levels.
17
PLL_SEL
Input
Pullup
18
19
20
VDD
Power
Core supply pin.
SEL0
SEL1
Input Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels.
Input Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
Parameter
Test Conditions
Minimum Typical Maximum Units
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
4
pF
kΩ
kΩ
RPULLUP
RPULLDOWN
51
51
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2
PRELIMINARY
ICS874S02I
1:1 DIFFERENTIAL-TO-LVDS
ZERO DELAY CLOCK GENERATOR
Integrated
Circuit
Systems, Inc.
TABLE 3A. CONTROL INPUT FUNCTION TABLE
Outputs
Inputs
PLL_SEL = 1
PLL Enable Mode
SEL3
SEL2
SEL1
SEL0
Reference Frequency Range (MHz)*
500 - 1000
Q, nQ
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
÷ 1
÷ 1
÷ 1
÷ 1
÷ 2
÷ 2
÷ 2
÷ 4
÷ 4
÷ 8
x 2
x 2
x 2
x 4
x 4
x 8
250 - 500
125 - 250
62.5 - 125
500 - 1000
250 - 500
125 - 250
500 - 1000
250 - 500
500 - 1000
250 - 500
125 - 250
62.5 - 125
125 - 250
62.5 - 125
62.5 - 125
*NOTE: VCO frequency range for all configurations above is 500MHz to 1GHz.
TABLE 3B. PLL BYPASS FUNCTION TABLE
Inputs
Outputs
PLL_SEL = 0
PLL Bypass Mode
SEL3
SEL2
SEL1
SEL0
Q, nQ
÷ 4
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
÷ 4
÷ 4
÷ 8
÷ 8
÷ 8
÷ 16
÷ 16
÷ 32
÷ 64
÷ 2
÷ 2
÷ 4
÷ 1
÷ 2
÷ 1
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3
PRELIMINARY
ICS874S02I
1:1 DIFFERENTIAL-TO-LVDS
ZERO DELAY CLOCK GENERATOR
Integrated
Circuit
Systems, Inc.
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
DD
Inputs, V
-0.5V to VDD + 0.5V
I
Outputs, IO
Continuous Current
Surge Current
10mA
15mA
PackageThermal Impedance, θJA 46.2°C/W (0 lfpm)
StorageTemperature,T -65°C to 150°C
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VDD
VDDA
VDDO
IDD
Core Supply Voltage
3.135
VDD - 0.18
3.135
3.3
3.3
3.3
84
3.465
3.465
3.465
V
V
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
V
mA
mA
mA
IDDA
IDDO
18
30
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VIH
VIL
Input High Voltage
2
VDD + 0.3
0.8
V
V
Input Low Voltage
-0.3
CLK_SEL, MR, SEL0,
SEL1, SEL2, SEL3
V
DD = VIN = 3.465V
150
5
µA
µA
µA
IIH
Input High Current
PLL_SEL
VDD = VIN = 3.465V
CLK_SEL, MR, SEL0,
SEL1, SEL2, SEL3
-5
V
DD = 3.465V, VIN = 0V
IIL
Input Low Current
PLL_SEL
-150
µA
VDD = 3.465V, VIN = 0V
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
CLK, FB_IN
V
DD = VIN = 3.465V
150
5
µA
µA
µA
µA
V
IIH
Input High Current
nCLK, nFB_IN
CLK, FB_IN
VDD = VIN = 3.465V
V
DD = 3.465V, VIN = 0V
DD = 3.465V, VIN = 0V
-5
-150
IIL
Input Low Current
nCLK0, nFB_IN
V
VPP
Peak-to-Peak Input Voltage
0.15
1.3
VCMR
Common Mode Input Voltage; NOTE 1, 2
GND + 0.5
VDD - 0.85
V
NOTE 1: Common mode voltage is defined as VIH.
NOTE 2: For single ended applications, the maximum input voltage for CLK, nCLK is VDD + 0.3V.
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PRELIMINARY
ICS874S02I
1:1 DIFFERENTIAL-TO-LVDS
ZERO DELAY CLOCK GENERATOR
Integrated
Circuit
Systems, Inc.
TABLE 4D. LVDS DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum
Typical
440
Maximum Units
VOD
Differential Output Voltage
mV
Δ VOD
VOS
VOD Magnitude Change
Offset Voltage
0
50
25
mV
V
1.27
Δ VOS
VOS Magnitude Change
mV
TABLE 5. INPUT FREQUENCY CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
fIN Input Frequency
Test Conditions
PLL_SEL = 1
PLL_SEL = 0
Minimum Typical Maximum Units
62.5
1000
1000
MHz
MHz
CLK,
nCLK
TABLE 6. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
62.5
Typical
Maximum
Units
MHz
ns
fMAX
Output Frequency
1000
tPD
Propagation Delay; NOTE 1
Static Phase Offset; NOTE 2, 4
Output Skew; NOTE 3, 4
Cycle-to-Cycle Jitter; NOTE 4, 5
Output Duty Cycle
1.85
98
4
tsk(Ø)
tsk(o)
tjit(cc)
odc
PLL_SEL = 3.3V
ps
ps
26
50
ps
ꢀ
tL
PLL Lock Time
1
ms
ps
tR / tF
Output Rise/Fall Time; NOTE 6
180
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as the time difference between the input reference clock and the averaged feedback
input signal across all conditions, when the PLL is locked and the input reference frequency is stable.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 5: Characterized at VCO frequency of 800MHz.
NOTE 6: Measured from the 20ꢀ to 80ꢀ points.
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PRELIMINARY
ICS874S02I
1:1 DIFFERENTIAL-TO-LVDS
ZERO DELAY CLOCK GENERATOR
Integrated
Circuit
Systems, Inc.
PARAMETER MEASUREMENT INFORMATION
VDD
3.3V 3.3V
nCLK
CLK
SCOPE
VDD
Qx
3.3V 5ꢀ
POWER SUPPLY
Float GND
VDDA
VPP
VCMR
Cross Points
LVDS
+
–
nQx
GND
3.3V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nCLK
CLK
VOH
VOL
nQx
Qx
VOH
VOL
nFB_IN
nQy
FB_IN
Qy
➤
t(Ø)
➤
tsk(o)
t(Ø) mean = Static Phase Offset
(where t(Ø) mean is the average of the sampled cycles
measured on controlled edges)
STATIC PHASE OFFSET
OUTPUT SKEW
nQ, nQFB
Q, QFB
80ꢀ
tF
80ꢀ
VOD
➤
➤
Clock
20ꢀ
20ꢀ
tcycle n
tcycle n+1
➤
➤
Outputs
tR
tjit(cc) = tcycle n –tcycle n+1
1000 Cycles
CYLE-TO-CYCLE JITTER
OUTPUT RISE/FALL TIME
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PRELIMINARY
ICS874S02I
1:1 DIFFERENTIAL-TO-LVDS
ZERO DELAY CLOCK GENERATOR
Integrated
Circuit
Systems, Inc.
nCLK
CLK
nQ, nQFB
Q, QFB
tPW
tPERIOD
nQ, nQFB
Q, QFB
tPW
tPD
odc =
x 100ꢀ
tPERIOD
PROPAGATION DELAY
OUPUT DUTY/CYCLE/PULSE WIDTH/PERIOD
VDD
VDD
out
out
➤
➤
out
out
DC Input
LVDS
LVDS
DC Input
100
V
OD/Δ VOD
VOS/Δ VOS
➤
➤
OFFSET VOLTAGE SETUP
DIFFERENTIAL OUTPUT VOLTAGE SETUP
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REV.A APRIL 27, 2006
7
PRELIMINARY
ICS874S02I
1:1 DIFFERENTIAL-TO-LVDS
ZERO DELAY CLOCK GENERATOR
Integrated
Circuit
Systems, Inc.
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept of R1 and R2 might need to be adjusted to position theV_REF in
single ended levels. The reference voltage V_REF ~ VDD/2 is the center of the input voltage swing. For example, if the input
generated by the bias resistors R1, R2 and C1.This bias circuit clock swing is only 2.5V andVDD = 3.3V, V_REF should be 1.25V
should be located as close as possible to the input pin.The ratio and R2/R1 = 0.609.
VDD
R1
1K
Single Ended Clock Input
CLK
V_REF
nCLK
C1
0.1u
R2
1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
POWER SUPPLY FILTERINGT ECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS874S02I provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL.VDD, VDDA, and VDDO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 2 illustrates how
a 10Ω resistor along with a 10μF and a .01μF bypass
capacitor should be connected to each VDDA pin. The 10Ω
resistor can also be replaced by a ferrite bead.
3.3V
.01μF
.01μF
10Ω
VDDA
10 μF
FIGURE 2. POWER SUPPLY FILTERING
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PRELIMINARY
ICS874S02I
1:1 DIFFERENTIAL-TO-LVDS
ZERO DELAY CLOCK GENERATOR
Integrated
Circuit
Systems, Inc.
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL here are examples only. Please consult with the vendor of the
and other differential signals. Both VSWING andVOH must meet the driver component to confirm the driver termination requirements.
VPP and VCMR input requirements. Figures 3A to 3D show inter- For example in Figure 3A, the input termination applies for ICS
face examples for the HiPerClockS CLK/nCLK input driven by HiPerClockS LVHSTL drivers.If you are using an LVHSTL driver
the most common driver types.The input interfaces suggested from another vendor, use their termination recommendation.
3.3V
3.3V
3.3V
1.8V
Zo = 50 Ohm
CLK
Zo = 50 Ohm
CLK
Zo = 50 Ohm
nCLK
Zo = 50 Ohm
HiPerClockS
Input
LVPECL
nCLK
HiPerClockS
Input
LVHSTL
R1
50
R2
50
ICS
HiPerClockS
R1
50
R2
50
LVHSTL Driver
R3
50
FIGURE 4A. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
ICS HIPERCLOCKS LVHSTL DRIVER
FIGURE 4B. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
3.3V
3.3V
3.3V
3.3V
Zo = 50 Ohm
3.3V
R3
125
R4
125
LVDS_Driver
Zo = 50 Ohm
Zo = 50 Ohm
CLK
CLK
R1
100
nCLK
Receiv er
nCLK
HiPerClockS
Input
Zo = 50 Ohm
LVPECL
R1
84
R2
84
FIGURE 3C. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 3D. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVDS DRIVER
RECOMMENDATIONS FOR UNUSED INPUT PINS
INPUTS:
LVCMOS CONTROL PINS:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
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9
PRELIMINARY
ICS874S02I
1:1 DIFFERENTIAL-TO-LVDS
ZERO DELAY CLOCK GENERATOR
Integrated
Circuit
Systems, Inc.
LVDS DRIVER TERMINATION
A general LVDS interface is shown in Figure 4. In a 100Ω
differential transmission line environment, LVDS drivers re-
quire a matched load termination of 100Ω across near the
receiver input. For a multiple LVDS outputs buffer, if only par-
tial outputs are used, it is recommended to terminate the un-
used outputs.
3.3V
3.3V
LVDS_Driv er
+
R1
100
-
100 Ohm Differiential Transmission Line
FIGURE 4. TYPICAL LVDS DRIVERT ERMINATION
LAYOUT GUIDELINE
The schematic of the ICS874S02I layout example is shown in depend on the selected component types and the density of
Figure 5A. The ICS874S02I recommended PCB board layout
for this example is shown in Figure 5B. This layout example is
used as a general guideline.The layout in the actual system will
the P.C. board.
3.3V
U1
Zo = 50 Ohm
SEL1
SEL0
VDD
PLL_SEL
VDDA
1
20
C1
0.1uF
CLK
2
SEL1
19
nCLK
3
4
5
6
7
8
9
10
SEL0
18
MR
VDDI
17
Zo = 50 Ohm
R7
VDD
nFB_IN
FB_IN
SEL2
VDDO
nQFB
QFB
PLL_SEL
16
VDDA
15
SEL2
VDDO
SEL3
SEL3
14
3.3V PECL Driver
10
GND
13
C11
Q
nQ
VDDO
12
11
0.01u
C16
10u
R8
50
R9
50
VDDO
GND
R2
100
ICS8745B-21
SP = Space (i.e. not intstalled)
R10
50
VDD
+
-
RU3
1K
RU4
1K
RU5
SP
RU6
1K
RU7
SP
Bypass capacitors located
near the power pins
R4
100
PLL_SEL
SEL0
SEL1
SEL2
SEL3
LVDS_input
VDD=3.3V
(U1-7)
(U1-11)
VDDO
VDDO=3.3V
C4
0.1uF
C2
0.1uF
Zo = 100 Ohm Dif f erential
RD3
SP
RD4
SP
RD5
1K
RD6
SP
RD7
1K
SEL[3:0] = 0101,
Divide by 2
FIGURE 5A. ICS874S02I LVDS ZERO DELAY BUFFER SCHEMATIC EXAMPLE
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PRELIMINARY
ICS874S02I
1:1 DIFFERENTIAL-TO-LVDS
ZERO DELAY CLOCK GENERATOR
Integrated
Circuit
Systems, Inc.
The following component footprints are used in this layout
example:
trace delay might be restricted by the available space on the board
and the component location.While routing the traces, the clock
signal traces should be routed first and should be locked prior to
routing other signal traces.
All the resistors and capacitors are size 0603.
POWER AND GROUNDING
• The 100Ω differential output traces should have equal
Place the decoupling capacitors as close as possible to the power
pins. If space allows, placement of the decoupling capacitor on
the component side is preferred.This can reduce unwanted in-
ductance between the decoupling capacitor and the power pin
caused by the via.
length.
• Avoid sharp angles on the clock trace.Sharp angle
turns cause the characteristic impedance to change on
the transmission lines.
• Keep the clock traces on the same layer.Whenever pos-
sible, avoid placing vias on the clock traces. Placement
of vias on the traces can affect the trace characteristic
impedance and hence degrade signal integrity.
Maximize the power and ground pad sizes and number of vias
capacitors.This can reduce the inductance between the power
and ground planes and the component power and ground pins.
• To prevent cross talk, avoid routing other signal traces in
parallel with the clock traces. If running parallel traces is
unavoidable, allow a separation of at least three trace
widths between the differential clock trace and the other
signal trace.
The RC filter consisting of R7, C11, and C16 should be placed
as close to the VDDA pin as possible.
CLOCK TRACES AND TERMINATION
Poor signal integrity can degrade the system performance or
cause system failure. In synchronous high-speed digital systems,
the clock signal is less tolerant to poor signal integrity than other
signals. Any ringing on the rising or falling edge or excessive ring
back can cause system failure. The shape of the trace and the
• Make sure no other signal traces are routed between the
clock trace pair.
• The series termination resistors should be located as
close to the driver pins as possible.
U1
GND
VDDO
C1
VDD
C16
VDDA
C11
VIA
C4
R7
100 Ohm
Differential
Traces
C2
FIGURE 5B. PCB BOARD LAYOUT FOR ICS874S02I
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874S02AMI
REV.A APRIL 27, 2006
11
PRELIMINARY
ICS874S02I
1:1 DIFFERENTIAL-TO-LVDS
ZERO DELAY CLOCK GENERATOR
Integrated
Circuit
Systems, Inc.
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS874S02I.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS874S02I is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VDD = 3.3V + 5ꢀ = 3.465V, which gives worst case results.
•
•
Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX) = 3.465V * (84mA + 18mA) = 353.43mW
Power (outputs)MAX = VDDO_MAX * IDDO_MAX = 3.465V * 30mA = 103.95mW
Total Power_MAX = 353.43mW + 103.95mW = 457.38mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of
the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
qJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used.
Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 39.7°C/W per
Table 7 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.457W * 39.7°C/W = 103.1°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air
flow, and the type of board (single layer or multi-layer).
TABLE 7. THERMAL RESISTANCE θJA FOR 20-LEAD SOIC, FORCED CONVECTION
θ
JA by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
83.2°C/W
65.7°C/W
57.5°C/W
46.2°C/W
39.7°C/W
36.8°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
874S02AMI
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REV.A APRIL 27, 2006
12
PRELIMINARY
ICS874S02I
1:1 DIFFERENTIAL-TO-LVDS
ZERO DELAY CLOCK GENERATOR
Integrated
Circuit
Systems, Inc.
RELIABILITY INFORMATION
TABLE 8. θJAVS. AIR FLOWT ABLE FOR 20 LEAD SOIC
θJA byVelocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
83.2°C/W
65.7°C/W
57.5°C/W
46.2°C/W
39.7°C/W
36.8°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS874S02I is: 1358
874S02AMI
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REV.A APRIL 27, 2006
13
PRELIMINARY
ICS874S02I
1:1 DIFFERENTIAL-TO-LVDS
ZERO DELAY CLOCK GENERATOR
Integrated
Circuit
Systems, Inc.
PACKAGE OUTLINE - M SUFFIX FOR 20 LEAD SOIC
TABLE 9. PACKAGE DIMENSIONS
Millimeters
Minimum Maximum
SYMBOL
N
A
20
--
2.65
A1
A2
B
0.10
2.05
0.33
0.18
12.60
7.40
--
2.55
0.51
0.32
13.00
7.60
C
D
E
e
1.27 BASIC
H
h
10.00
0.25
0.40
0°
10.65
0.75
1.27
8°
L
α
Reference Document: JEDEC Publication 95, MS-013, MO-119
874S02AMI
www.icst.com/products/hiperclocks.html
REV.A APRIL 27, 2006
14
PRELIMINARY
ICS874S02I
1:1 DIFFERENTIAL-TO-LVDS
ZERO DELAY CLOCK GENERATOR
Integrated
Circuit
Systems, Inc.
TABLE 10. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging
tube
Temperature
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
ICS874S02AMI
ICS874S02AMIT
ICS874S02AMILF
ICS874S02AMILFT
ICS874S02AMI
ICS874S02AMI
TBD
20 Lead SOIC
20 Lead SOIC
1000 tape & reel
tube
20 Lead "Lead-Free" SOIC
20 Lead "Lead-Free" SOIC
TBD
1000 tape & reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademark, HiPerClockS is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or
for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without
additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices
or critical medical instruments.
874S02AMI
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REV.A APRIL 27, 2006
15
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