MB90V340E-103CR [FUJITSU]
16-bit Proprietary Microcontroller; 16位微控制器专有
| 型号： | MB90V340E-103CR |
| 厂家： | 
FUJITSU |
| 描述： | 16-bit Proprietary Microcontroller |
| 文件： | 总64页 (文件大小：1797K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FUJITSU MICROELECTRONICS
DATA SHEET
DS07-13746-3E
16-bit Proprietary Microcontroller
CMOS
F2MC-16LX MB90360E Series
MB90362E, MB90362ES, MB90362TE, MB90362TES,
MB90F362E, MB90F362ES, MB90F362TE, MB90F362TES,
MB90367E, MB90367ES, MB90367TE, MB90367TES,
MB90F367E, MB90F367ES, MB90F367TE, MB90F367TES,
MB90V340E-101, MB90V340E-102, MB90V340E-103, MB90V340E-104
■ DESCRIPTION
The MB90360E-series, loaded 1 channel FULL-CAN* interface and Flash ROM, is general-purpose FUJITSU
16-bit microcontroller designing for automotive and industrial applications. Its main feature is the on-board CAN
Interfaces, which conform to Ver 2.0 Part A and Part B, while supporting a very flexible message buffer scheme
and so offering more functions than a normal FULL-CAN approach. With the new 0.35 µm CMOS technology,
Fujitsu now offers on-chip Flash ROM program memory up to 64 Kbytes.
The power supply (3 V) is supplied to the MCU core from an internal regulator circuit. This creates a major
advantage in terms of EMI and power consumption.
The internal PLL clock frequency multiplier provides an internal 42 ns instruction execution time from an external
4 MHz clock. Also, main and sub clock can be monitored independently using the clock supervisor function.
The unit features a 4-channel input capture unit 1 channel 16-bit free running timer, 2-channel LIN-UART, and
16-channel 8/10-bit A/D converter as the peripheral resource.
* : Controller Area Network (CAN) - License of Robert Bosch GmbH
Note : F2MC is the abbreviation of FUJITSU Flexible Microcontroller.
The information for microcontroller supports is shown in the following homepage.
Be sure to refer to the "Check Sheet" for the latest cautions on development.
"Check Sheet" is seen at the following support page
"Check Sheet" lists the minimal requirement items to be checked to prevent problems beforehand in
system development.
http://edevice.fujitsu.com/micom/en-support/
Copyright©2006-2008 FUJITSU MICROELECTRONICS LIMITED All rights reserved
2008.8
MB90360E Series
■ FEATURES
• Clock
• Built-in PLL clock frequency multiplication circuit
• Selection of machine clocks (PLL clocks) is allowed among frequency division by 2 on oscillation clock and
multiplication of 1 to 6 times of oscillation clock (for 4 MHz oscillation clock, 4 MHz to 24 MHz)
• Operation by sub clock : internal operating clock frequency: up to 50 kHz (for operating with 100 kHz oscillation
clock divided two and devices without S-suffix only) is available
• Minimum execution time of instruction : 42 ns (when operating with 4-MHz oscillation clock and 6-time multiplied
PLL clock)
• Clock supervisor (MB90x367x only)
• Main clock or sub clock is monitored independently
• Instruction system best suited to controller
• 16 Mbytes CPU memory space
• 24-bit internal addressing
• Wide choice of data types (bit, byte, word, and long word)
• Wide choice of addressing modes (23 types)
• Enhanced multiply-divide instructions with sign and RETI instructions
• Enhanced high-precision computing with 32-bit accumulator
• Instruction system compatible with high-level language (C language) and multitask
• Employing system stack pointer
• Enhanced various pointer indirect instructions
• Barrel shift instructions
• Increased processing speed
4-byte instruction queue
• Powerful interrupt function
• Powerful 8-level, 34-condition interrupt feature
• Up to 8 channels external interrupts are supported
• Automatic data transfer function independent of CPU
Expanded intelligent I/O service function (EI2OS) : up to 16 channels
• Low power consumption (standby) mode
• Sleep mode (a mode that halts CPU operating clock)
• Main timer mode (timebase timer mode that is transferred from main clock mode)
• PLL timer mode (timebase timer mode that is transferred from PLL clock mode)
• Watch mode (a mode that operates sub clock and watch timer only, devices without S-suffix)
• Stop mode (a mode that stops oscillation clock and sub clock)
• CPU blocking operation mode
• Process
CMOS technology
• I/O port
General purpose input/output port (CMOS output) :
- 34 ports (devices without S-suffix)
- 36 ports (devices with S-suffix)
• Sub clock pin (X0A and X1A)
• Provided (used for external oscillation), devices without S-suffix
• Not provided, devices with S-suffix
(Continued)
2
DS07-13746-3E
MB90360E Series
(Continued)
• Timer
• Timebase timer, watch timer (device without S-suffix) , watchdog timer : 1 channel
• 8/16-bit PPG timer : 8-bit × 4 channels or 16-bit × 2 channels
• 16-bit reload timer : 2 channels
• 16- bit input/output timer
- 16-bit free-run timer : 1 channel (FRT0 : ICU 0/1/2/3)
- 16- bit input capture : (ICU) : 4 channels
• FULL-CAN interface : 1 channel
• Compliant with CAN specifications Version 2.0 Part A and B
• 16 message buffers are built in
• CAN wake-up function
• LIN-UART : 2 channels
• Equipped with full-duplex double buffer
• Clock-asynchronous or clock-synchronous serial transmission is available
• DTP/External interrupt : up to 8 channels, CAN wakeup : up to 1 channel
Module for activation of expanded intelligent I/O service (EI2OS) and generation of external interrupt by external
input
• Delay interrupt generator module
Generates interrupt request for task switching
• 8/10-bit A/D converter : 16 channels
• Resolution is selectable between 8-bit and 10-bit
• Activation by external trigger input is allowed
• Conversion time : 3 µs (at 24-MHz machine clock, including sampling time)
• Address matching detection (program patch) function
Address matching detection for 6 address pointers
• Low voltage/CPU operation detection reset (devices with T-suffix)
• Detects low voltage (4.0 V 0.3 V) and resets automatically
• Resets automatically when program is runaway and counter is not cleared within interval time
(approx. 262 ms : external 4 MHz)
• Capable of changing input voltage for port
Automotive/CMOS-Schmitt input level (initial level is Automotive in single-chip mode)
• Flash memory security function
Protects the content of Flash memory (MB90F362x, MB90F367x only)
DS07-13746-3E
3
MB90360E Series
■ PRODUCT LINEUP
MB90V340E- MB90V340E-
Features
Type
MB90362E MB90362TE MB90362ES MB90362TES
MASK ROM product
F2MC-16LX CPU
101
102
Evaluation product
CPU
PLL clock multiplier ( × 1, × 2, × 3, × 4, × 6, 1/2 when PLL stops)
Minimum instruction execution time : 42 ns (4 MHz oscillation clock, PLL × 6)
System clock
Sub clock pin
(X0A, X1A)
Yes
No
No
No
Yes
Clock supervisor
ROM
MASK ROM, 64 Kbytes
3 Kbytes
External
30 Kbytes
3 channels
RAM capacitance
CAN interface
LIN-UART
1 channel
2 channels
Yes
Low voltage/CPU
operation
No
Yes
No
No
detection reset
Package
LQFP-48P
PGA-299C
Yes
Emulator-specific
power supply *
⎯
Corresponding
evaluation product
MB90V340E-102
MB90V340E-101
⎯
* : It is setting of Jumper switch (TOOL VCC) when emulator (MB2147-01) is used. Please refer to the Emulator
hardware manual for the details.
Features
MB90F362E
MB90F362TE
MB90F362ES
MB90F362TES
Type
CPU
Flash memory product
F2MC-16LX CPU
PLL clock multiplier
( × 1, × 2, × 3, × 4, × 6, 1/2 when PLL stops)
Minimum instruction execution time : 42 ns
(4 MHz oscillation clock, PLL × 6)
System clock
Sub clock pin
(X0A, X1A)
Yes
No
Clock supervisor
ROM
No
Flash memory, 64 Kbytes
3 Kbytes
RAM capacitance
CAN interface
LIN-UART
1 channel
2 channels
Low voltage/CPU opera-
tion detection reset
No
Yes
No
Yes
Package
LQFP-48P
Corresponding
evaluation product
MB90V340E-102
MB90V340E-101
4
DS07-13746-3E
MB90360E Series
MB90V340E- MB90V340E-
Features
Type
MB90367E MB90367TE MB90367ES
MB90367TES
103
104
MASK ROM product
Evaluation product
CPU
F2MC-16LX CPU
PLL clock multiplier ( × 1, × 2, × 3, × 4, × 6, 1/2 when PLL stops)
Minimum instruction execution time : 42 ns (4 MHz oscillation clock, PLL × 6)
System clock
Sub clock pin
(X0A, X1A)
Yes
No
Yes
Clock supervisor
ROM
Yes
MASK ROM, 64 Kbytes
3 Kbytes
External
30 Kbytes
3 channels
RAM capacitance
CAN interface
LIN-UART
1 channel
2 channels
Low voltage/CPU
operation
detection reset
No
Yes
No
LQFP-48P
Yes
No
Package
PGA-299C
Yes
Emulator-specific
power supply *
⎯
Corresponding
EVA product
MB90V340E-104
MB90V340E-103
⎯
* : It is setting of Jumper switch (TOOL VCC) when emulator (MB2147-01) is used. Please refer to the Emulator
hardware manual for the details.
Features
MB90F367E
MB90F367TE
MB90F367ES
MB90F367TES
Type
CPU
Flash memory product
F2MC-16LX CPU
PLL clock multiplier
( × 1, × 2, × 3, × 4, × 6, 1/2 when PLL stops)
Minimum instruction execution time : 42 ns
(4 MHz oscillation clock, PLL × 6)
System clock
Sub clock pin
(X0A, X1A)
Yes
No
Clock supervisor
ROM
Yes
Flash memory, 64 Kbytes
3 Kbytes
RAM capacitance
CAN interface
LIN-UART
1 channel
2 channels
Low voltage/CPU
operation detection reset
No
Yes
No
Yes
Package
LQFP-48P
Corresponing EVA
product
MB90V340E-104
MB90V340E-103
DS07-13746-3E
5
MB90360E Series
■ PIN ASSIGNMENT
• MB90F362E/TE/ES/TES, MB90362E/TE/ES/TES, MB90F367E/TE/ES/TES, MB90367E/TE/ES/TES
(TOP VIEW)
P20 *2
1
2
36
35
34
33
32
31
30
29
28
27
26
25
AVcc
AVR
P21 *2
P22/PPGD(C) *2
P60/AN0
3
P61/AN1
4
P23/PPGF(E) *2
P24/IN0
P25/IN1
P26/IN2
P27/IN3
X1
P62/AN2
5
P63/AN3
6
7
P64/AN4
8
P65/AN5
9
P66/AN6/PPGC(D)
P67/AN7/PPGE(F)
P80/ADTG/INT12R
P50/AN8
10
11
12
X0
C
Vss
(FPT-48P-M26)
*1 : MB90F362E/TE, MB90362E/TE, MB90F367E/TE, MB90367E/TE
: X0A, X1A
MB90F362ES/TES, MB90362ES/TES, MB90F367ES/TES, MB90367ES/TES : P40, P41
*2 : High current output port
6
DS07-13746-3E
MB90360E Series
■ PIN DESCRIPTION
I/O circuit
type*
Pin No.
Pin name
AVCC
Function
1
2
I
VCC power input pin for analog circuit.
Power (Vref+) input pin for A/D converter.
AVR
⎯
It should be below VCC.
P60 to P65
AN0 to AN5
P66, P67
General-purpose I/O port.
3 to 8
9, 10
H
H
Analog input pins for A/D converter.
General-purpose I/O port.
AN6, AN7
Analog input pins for A/D converter.
PPGC (D) ,
PPGE (F)
Output pins for PPG.
P80
General-purpose I/O port.
11
12 to 14
15
ADTG
INT12R
F
H
H
Trigger input pin for A/D converter.
External interrupt request input pin for INT12.
General-purpose I/O port (P50 has different I/O circuit type from
MB90V340E) .
P50 to P52
AN8 to AN10
P53
Analog input pins for A/D converter.
General-purpose I/O port.
AN11
Analog input pin for A/D converter.
Event input pin for reload timer 3.
General-purpose I/O port.
TIN3
P54
AN12
Analog input pin for A/D converter.
Output pin for reload timer 3
16
H
H
TOT3
INT8
External interrupt request input pin for INT8.
General-purpose I/O port.
P55 to P57
AN13 to AN15
Analog input pins for A/D converter.
17 to 19
INT10, INT11,
INT13
External interrupt request input pins for INT10, INT11, INT13.
Input pin for operation mode specification.
20
MD2
D
C
MD1,
MD0
21, 22
Input pins for operation mode specification.
23
24
25
RST
VCC
VSS
E
Reset input pin.
⎯
⎯
Power input pin (3.5 V to 5.5 V) .
Power input pin (0 V) .
Power supply stabilization capacitor pin. It should be connected
to a higher than or equal to 0.1 µF ceramic condenser.
26
C
I
(Continued)
DS07-13746-3E
7
MB90360E Series
I/O circuit
type*
Pin No.
Pin name
Function
27
28
X0
X1
Oscillation input pin.
A
Oscillation output pin.
General-purpose I/O port.
P27 to P24
IN3 to IN0
The register can be set to select whether to use a pull-up
resistor. This function is enabled in single-chip mode.
29 to 32
G
Event input pins for input capture 0 to 3.
General-purpose I/O port.
The register can be set to select whether to use a pull-up
resistor. This function is enabled in single-chip mode.
High current output port.
P23, P22
33, 34
35, 36
J
J
PPGF (E) ,
PPGD (C)
Output pins for PPG.
General-purpose I/O port.
The register can be set to select whether to use a pull-up
resistor. This function is enabled in single-chip mode.
High current output port.
P21, P20
P85
SIN1
P87
General-purpose I/O port.
37
38
39
40
K
F
F
F
Serial data input pin for LIN-UART1.
General-purpose I/O port.
SCK1
P86
Clock I/O pin for LIN-UART1.
General-purpose I/O port.
SOT1
P43
Serial data output pin for LIN-UART1.
General-purpose I/O port.
TX1
TX output pin for CAN1 interface.
General-purpose I/O port.
P42
41
42
43
RX1
F
F
F
RX input pin for CAN1 interface.
External interrupt request input pin for INT9 (Sub) .
General-purpose I/O port.
INT9R
P83
SOT0
TOT2
P84
Serial data output pin for LIN-UART0.
Output pin for reload timer 2.
General-purpose I/O port.
SCK0
INT15R
Clock I/O pin for LIN-UART0.
External interrupt request input pin for INT15.
(Continued)
8
DS07-13746-3E
MB90360E Series
(Continued)
I/O circuit
type*
Pin No.
Pin name
Function
P82
SIN0
General-purpose I/O port.
Serial data input pin for LIN-UART0.
External interrupt request input pin for INT14.
Event input pin for reload timer 2.
44
45
K
INT14R
TIN2
General-purpose I/O port
(Different I/O circuit type from MB90V340E) .
P44
F
F
FRCK0
P40, P41
Free-run timer 0 clock pin.
General-purpose I/O port
(Devices with S-suffix and MB90V340E-101/103 only) .
46, 47
48
Oscillation pins for sub clock
(Devices without S-suffix and MB90V340E-102/104 only) .
X0A, X1A
AVSS
B
I
VSS power input pin for analog circuit.
* : For the I/O circuit type, refer to “■ I/O CIRCUIT TYPE”.
DS07-13746-3E
9
MB90360E Series
■ I/O CIRCUIT TYPE
Type
Circuit
Remarks
Oscillation circuit :
High-speed oscillation feedback resistor =
approx. 1 MΩ
X1
X0
Xout
A
Standby control signal
Oscillation circuit :
Low-speed oscillation feedback resistor =
approx. 10 MΩ
X1A
X0A
Xout
B
Standby control signal
• MASK ROM product :
CMOS hysteresis input pin
• Flash memory product :
CMOS input pin
R
CMOS hysteresis
inputs
C
D
• MASK ROM product :
CMOS hysteresis input pin
• Flash memory product :
- CMOS input pin
R
CMOS hysteresis
inputs
Pull-down
resistor
- No Pull-down
CMOS hysteresis input pin
Pull-up
resistor
E
R
CMOS hysteresis
inputs
(Continued)
10
DS07-13746-3E
MB90360E Series
Type
Circuit
Remarks
• CMOS level output
P-ch
N-ch
• CMOS hysteresis inputs (With the
standby-time input shutdown function)
• Automotive input (With the standby-
time input shutdown function)
Pout
Nout
R
F
CMOS hysteresis inputs
Automotive inputs
Standby control for
input shutdown
• CMOS level output
Pull-up control
Pout
• CMOS hysteresis inputs (With the
standby-time input shutdown function)
• Automotive input (With the standby-
time input shutdown function)
Pull-up
resistor
P-ch
P-ch
N-ch
Nout
G
R
CMOS hysteresis inputs
Automotive inputs
Standby control for
input shutdown
• CMOS level output
P-ch
N-ch
• CMOS hysteresis inputs (With the
standby-time input shutdown function)
• Automotive input (With the standby-
time input shutdown function)
• A/D analog input
Pout
Nout
R
H
CMOS hysteresis inputs
Automotive inputs
Standby control for
input shutdown
Analog input
(Continued)
DS07-13746-3E
11
MB90360E Series
(Continued)
Type
Circuit
Remarks
Protection circuit for power supply input
P-ch
N-ch
I
• CMOS level output
• CMOS hysteresis inputs (With the
standby-time input shutdown function)
• Automotive input (With the standby-
time input shutdown function)
Pull-up control
Pull-up
resistor
P-ch
P-ch
Pout high current output
Nout high current output
N-ch
J
R
CMOS hysteresis inputs
Automotive inputs
Standby control for
input shutdown
• CMOS level output
• CMOS input (With standby-time input
shutdown function)
• Automotive input (With standby-time in-
put shutdown function)
P-ch
N-ch
Pout
Nout
R
K
CMOS inputs
Automotive inputs
Standby control for
input shutdown
12
DS07-13746-3E
MB90360E Series
■ HANDLING DEVICES
1. Preventing latch-up
CMOS IC chips may suffer latch-up under the following conditions :
• A voltage higher than VCC pin or lower than VSS pin is applied to an input or output pin.
• A voltage higher than the rated voltage is applied between VCC pin and VSS pin.
• The AVCC power supply is applied before the VCC voltage.
Latch-up may increase the power supply current drastically, causing thermal damage to the device.
Use meticulous care not to exceed the rating.
For the same reason, also be careful not to let the analog power-supply voltage (AVCC, AVR) exceed the digital
power-supply voltage.
2. Treatment of unused pins
Leaving unused input pins open may result in permanent damage of the device due to misbehavior or latch-up.
Therefore, they must be pulled up or pulled down through resistors. In this case, those resistors should be more
than 2 kΩ .
Unused bidirectional pins should be set to the output state and can be left open, or the input state with the above
described connection.
3. Using external clock
To use external clock, drive the X0 pin and leave X1 pin open.
MB90360E Series
X0
X1
Open
4. Precautions for when not using a sub clock signal
If you do not connect pins X0A and X1A to an oscillator, use pull-down handling on the X0A pin and leave the
X1A pin open.
5. Notes on during operation of PLL clock mode
On this microcontroller, if in case the crystal oscillator breaks off or an external reference clock input stops while
the PLL clock mode is selected, a self-oscillator circuit contained in the PLL may continue its operation at its
self-running frequency. However, Fujitsu will not guarantee results of operations if such failure occurs.
6. Power supply pins (VCC/VSS)
• If there are multiple VCC and VSS pins, from the point of view of device design, pins to be of the same potential
are connected the inside of the device to prevent malfunction such as latch-up.
To reduce unnecessary radiation, prevent malfunctioning of the strobe signal due to the rise of ground level,
and oerve the standard for total output current, be sure to connect the VCC and VSS pins to the power supply
and ground externally.
• Connect VCC and VSS pins to the device from the current supply source at a low impedance.
DS07-13746-3E
13
MB90360E Series
• As a measure against power supply noise, connect a capacitor of about 0.1 µF as a bypass capacitor between
VCC pin and VSS pin in the vicinity of VCC and VSS pins of the device.
VCC
VSS
VCC
VSS
VSS
MB90360E
Series
VCC
VCC
VSS
VCC
VSS
7. Pull-up/down resistors
The MB90360E Series does not support internal pull-up/down resistors (Port 2 : built-in pull-up resistors) . Use
external components where needed.
8. Crystal oscillator circuit
Noises around X0 or X1 pin may be possible causes of abnormal operations. Make sure to provide bypass
capacitors via shortest distance from X0, X1 pins, crystal oscillator (or ceramic resonator) and ground lines, and
make sure, to the utmost effort, that lines of oscillation circuit do not cross the lines of other circuits.
It is highly recommended to provide a printed circuit board artwork surrounding X0 and X1 pins with a ground
area for stabilizing the operation. Please ask the crystal maker to evaluate the oscillational characteristics of the
crystal and this device.
9. Turning-on sequence of power supply to A/D converter and analog inputs
Make sure to turn on the A/D converter power supply (AVCC and AVR) and analog inputs (AN0 to AN15) after
turning-on the digital power supply (VCC) .
Turn-off the digital power after turning off the A/D converter power supply and analog inputs. In this case, make
sure that the voltage does not exceed AVRH or AVCC (turning on/off the analog and digital power supplies
simultaneously is acceptable).
10. Connection of unused pins of A/D converter if A/D converter is not used
Connect unused pins of A/D converter to AVCC = VCC, AVSS = AVR = VSS.
11. Notes on energization
To prevent the internal regulator circuit from malfunctioning, set the voltage rise time during energization at
50 µs or more (0.2 V to 2.7 V) .
14
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MB90360E Series
12. Stabilization of power supply voltage
A sudden change in the power supply voltage may cause the device to malfunction even within the specified
VCC power supply voltage operating guarantee range. Therefore, the VCC power supply voltage should be
stabilized.
For reference, the power supply voltage should be controlled so that VCC ripple variations (peak-to-peak value)
at commercial frequencies (50 Hz/60 Hz) fall below 10% of the standard VCC power supply voltage and the
coefficient of transient fluctuation does not exceed 0.1 V/ms at instantaneous power switching.
13. Initialization
Inthedevice, thereareinternalregisterswhichareinitializedonlybyapower-onreset. Toinitializetheseregisters,
turn on the power again.
14. Notes on using CAN function
To use CAN function, please set ’1’ to DIRECT bit of CAN direct mode register (CDMR) .
If DIRECT bit is set to ’0’ (initial value) , wait states will be performed when accessing CAN registers.
Note : Please refer to Hardware Manual of “MB90360E series for detail of CAN Direct Mode Register”.
15. Flash security function
The security bit is located in the area of the Flash memory.
If protection code 01H is written in the security bit, the Flash memory is in the protected state by security.
Therefore, please do not write 01H in this address if you do not use the security function.
Please refer to following table for the address of the security bit.
Flash memory size
Address for security bit
MB90F362E
MB90F362ES
MB90F362TE
MB90F362TES
MB90F367E
Embedded 512 Kbits Flash Memory
FF0001H
MB90F367ES
MB90F367TE
MB90F367TES
16. Correspondence with TA = +105 °C or more
There is a restriction of reliability if the product is used exceeding TA = +105 °C.
Contact the sales or support representative.
It is ensured to write/erase data to the Flash memory between TA = − 40 °C and +105 °C.
17. Serial communication
There is a possibility to receive wrong data due to the noise or other causes on the serial communication.
Therefore, design a printed circuit board so as to avoid noise.
Retransmit the data if an error occurs because of applying the checksum to the last data in consideration of
receiving wrong data due to the noise.
DS07-13746-3E
15
MB90360E Series
■ BLOCK DIAGRAMS
• MB90V340E-101/102
X0, X1
Clock
F2MC-16LX
core
∗
X0A, X1A
controller
RST
16-bit
Free-run
timer 0
FRCK0
Input
capture
IN7 to IN0
8 channels
RAM
30 Kbytes
Output
compare
8 channels
OUT7 to OUT0
FRCK1
Prescaler
(5 channels)
16-bit
free-run
timer 1
SOT4 to SOT0
SCK4 to SCK0
SIN4 to SIN0
CAN
controller
3 channels
RX2 to RX0
TX2 to TX0
LIN-UART
5 channels
16-bit
reload timer
4 channels
AVCC
AVSS
AN23 to AN0
TIN3 to TIN0
TOT3 to TOT0
8/10-bit
A/D
converter
24 channels
AVRH
AVRL
ADTG
AD15 to AD00
A23 to A16
ALE
RD
WRL
WRH
HRQ
10-bit
D/A converter
2 channels
External
bus
DA01, DA00
8/16-bit
PPG
16/8 channels
HAK
RDY
CLK
PPGF to PPG0
I2C
interface
2 channels
SDA1, SDA0
SCL1, SCL0
INT15 to INT8
(INT15R to INT8R)
INT7 to INT0
DTP/
External
interrupt
DMA
Clock
monitor
CKOT
* : Only for MB90V340E-102
16
DS07-13746-3E
MB90360E Series
• MB90V340E-103/104
X0, X1
X0A, X1A*
Clock
controller/
monitor
F2MC-16LX
Core
RST
16-bit
Free-run
FRCK0
CR
oscillator
circuit
timer 0
Input
capture
IN7 to IN0
8 channels
RAM
30 Kbytes
Output
compare
8 channels
OUT7 to OUT0
FRCK1
Prescaler
(5 channels)
16-bit
free-run
timer 1
SOT4 to SOT0
SCK4 to SCK0
SIN4 to SIN0
CAN
controller
3 channels
RX2 to RX0
TX2 to TX0
LIN-UART
5 channels
16-bit
reload timer
4 channels
AVCC
TIN3 to TIN0
TOT3 to TOT0
AVSS
AN23 to AN0
8/10-bit
A/D
converter
24 channels
AVRH
AVRL
ADTG
AD15 to AD00
A23 to A16
ALE
RD
WRL
WRH
HRQ
10-bit
D/A converter
2 channels
External
bus
DA01, DA00
8/16-bit
PPG
16/8 channels
HAK
RDY
CLK
PPGF to PPG0
I2C
interface
2 channels
SDA1, SDA0
SCL1, SCL0
INT15 to INT8
(INT15R to INT8R)
INT7 to INT0
DTP/
External
interrupt
DMA
Clock
monitor
CKOT
* : Only for MB90V340E-104
DS07-13746-3E
17
MB90360E Series
• MB90F362E/TE/ES/TES, MB90362E/TE/ES/TES
X0, X1
F2MC-16LX
core
Clock
controller
1
∗
X0A, X1A
RST
Input
capture
4 channels
IN0 to IN3
Low voltage/CPU
operation detection *2
16-bit
free-run
timer 0
FRCK0
RAM
3 Kbytes
CAN
RX1
TX1
controller
1 channel
ROM
64 Kbytes
16-bit
reload
TIN2, TIN3
TOT2, TOT3
timer
2 channels
Prescaler
(2 channels)
SOT0, SOT1
SCK0, SCK1
SIN0, SIN1
LIN-UART
2 channels
AVCC
AVSS
AN15 to AN0
8/10-bit
A/D
converter
16 channels
AVR
ADTG
INT8, INT9R
DTP/
External
interrupt
INT10, INT11
INT12R, INT13
INT14R, INT15R
8/16-bit
PPG
4/2 channels
PPGF(E), PPGD(C),
PPGC(D), PPGE(F)
*1 : Only for devices without S-suffix
*2 : Only for devices with T-suffix
18
DS07-13746-3E
MB90360E Series
• MB90F367E/TE/ES/TES, MB90367E/TE/ES/TES
X0, X1
Clock
controller/
monitor
F2MC-16LX
Core
X0A, X1A*1
RST
CR
oscillator
circuit
Input
capture
4 channels
IN0 to IN3
16-bit
free-run
timer 0
Low voltage/CPU
operation detection *2
FRCK0
RAM
3 Kbytes
CAN
RX1
TX1
controller
1 channel
ROM
64 Kbytes
16-bit
reload
TIN2, TIN3
TOT2, TOT3
timer
2 channels
Prescaler
(2 channels)
SOT0, SOT1
SCK0, SCK1
SIN0, SIN1
LIN-UART
2 channels
AVCC
AVSS
AN15 to AN0
8/10-bit
A/D
converter
16 channels
AVR
ADTG
INT8, INT9R
INT10, INT11
INT12R, INT13
INT14R, INT15R
DTP/
External
interrupt
8/16-bit
PPG
4/2 channels
PPGF(E), PPGD(C),
PPGC(D), PPGE(F)
*1 : Only for devices without S-suffix
*2 : Only for devices with T-suffix
DS07-13746-3E
19
MB90360E Series
■ MEMORY MAP
MB90F362E/TE/ES/TES
MB90362E/TE/ES/TES
MB90F367E/TE/ES/TES
MB90367E/TE/ES/TES
MB90V340E-101/102
MB90V340E-103/104
FFFFFF
H
FFFFFF
H
ROM (FF bank)
ROM (FE bank)
ROM (FD bank)
ROM (FC bank)
ROM (FB bank)
ROM (FA bank)
ROM (F9 bank)
ROM (FF bank)
FF0000
FEFFFF
H
FF0000
H
H
FEFFFF
H
FE0000
H
FDFFFF
H
H
H
H
H
H
FD0000
H
FCFFFF
FC0000
H
FBFFFF
FB0000
H
FAFFFF
FA0000
H
F9FFFF
F90000
H
F8FFFF
ROM (F8 bank)
F80000
H
010000
00FFFF
H
External access area
H
00FFFF
H
ROM (image
ROM (image
of FF bank)
of FF bank)
008000
H
008000
H
007FFF
H
007FFF
H
Peripheral
Peripheral
007900
H
007900
H
0078FF
H
RAM 30 Kbytes
000CFF
H
H
RAM 3 Kbytes
000100
000100
H
0000FF
0000F0H
H
External access area
Peripheral
0000EF
000000
H
0000EF
H
H
Peripheral
000000
H
: No access
Note : The high-order portion of bank 00 gives the image of the FF bank ROM to make the small model of the C
compiler effective. Since the low-order 16 bits are the same, the table in ROM can be referred without using
the far specification in the pointer declaration.
For example, an attempt to access 00C000H practically accesses the value at FFC000H in ROM.
The ROM area in bank FF exceeds 32 Kbytes, and its entire image cannot be shown in bank 00.
The image between FF8000H and FFFFFFH is visible in bank 00, while the image between FF0000H and
FF7FFFH is visible only in bank FF.
20
DS07-13746-3E
MB90360E Series
■ I/O MAP
Abbrevia-
tion
Address
Register
Access
Resource name Initial value
000000H,
000001H
Reserved
000002H Port 2 Data Register
000003H
PDR2
R/W
Port 2
XXXXXXXXB
Reserved
PDR4
000004H Port 4 Data Register
000005H Port 5 Data Register
000006H Port 6 Data Register
000007H
R/W
R/W
R/W
Port 4
Port 5
Port 6
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
PDR5
PDR6
Reserved
PDR8
000008H Port 8 Data Register
R/W
Port 8
XXXXXXXXB
000009H,
00000AH
Reserved
00000BH Port 5 Analog Input Enable Register
00000CH Port 6 Analog Input Enable Register
00000DH
ADER5
ADER6
Reserved
ILSR0
R/W
R/W
Port 5, A/D
Port 6, A/D
11111111B
11111111B
00000EH Input Level Select Register
00000FH Input Level Select Register
R/W
R/W
Ports
Ports
XXXX0XXXB
XXXXXXXXB
ILSR1
000010H,
000011H
Reserved
000012H Port 2 Direction Register
000013H
DDR2
R/W
Port 2
00000000B
Reserved
DDR4
000014H Port 4 Direction Register
000015H Port 5 Direction Register
000016H Port 6 Direction Register
000017H
R/W
R/W
R/W
Port 4
Port 5
Port 6
XXX00000B
00000000B
00000000B
DDR5
DDR6
Reserved
DDR8
000018H Port 8 Direction Register
000019H
R/W
W
Port 8
Port A
000000X0B
Reserved
DDRA
00001AH Port A Direction Register
XXX00XXXB
00001BH
to
Reserved
00001DH
00001EH Port 2 Pull-up Control Register
00001FH
PUCR2
R/W
Port 2
00000000B
Reserved
(Continued)
DS07-13746-3E
21
MB90360E Series
Abbrevia-
tion
Address
Register
Access
Resource name Initial value
000020H Serial Mode Register 0
000021H Serial Control Register 0
SMR0
SCR0
W, R/W
W, R/W
00000000B
00000000B
RDR0/
TDR0
000022H Reception/Transmission Data Register 0
000023H Serial Status Register 0
R/W
00000000B
SSR0
R, R/W
00001000B
LIN-UART0
Extended Communication Control
R, W,
R/W
000024H
ECCR0
000000XXB
Register 0
000025H Extended Status/Control Register 0
000026H Baud Rate Generator Register 00
000027H Baud Rate Generator Register 01
000028H Serial Mode Register 1
ESCR0
BGR00
BGR01
SMR1
R/W
00000100B
00000000B
00000000B
00000000B
00000000B
R/W, R
R/W, R
W, R/W
W, R/W
000029H Serial Control Register 1
SCR1
RDR1/
TDR1
00002AH Reception/Transmission Data Register 1
R/W
00000000B
00002BH Serial Status Register 1
SSR1
R, R/W
00001000B
LIN-UART1
Extended Communication Control
R, W,
R/W
00002CH
ECCR1
000000XXB
Register 1
00002DH Extended Status/Control Register 1
00002EH Baud Rate Generator Register 10
00002FH Baud Rate Generator Register 11
ESCR1
BGR10
BGR11
R/W
00000100B
00000000B
00000000B
R/W, R
R/W, R
000030H
to
00003AH
Reserved
PACSR1
Address Match
00000000B
00003BH Address Detect Control Register 1
R/W
Detection 1
00003CH
to
Reserved
000047H
000048H PPG C Operation Mode Control Register PPGCC
000049H PPG D Operation Mode Control Register PPGCD
PPG C/PPG D Count Clock Select
W, R/W
W, R/W
0X000XX1B
0X000001B
16-bit PPG C/D
00004AH
PPGCD
R/W
000000X0B
Register
00004BH
Reserved
00004CH PPG E Operation Mode Control Register PPGCE
00004DH PPG F Operation Mode Control Register PPGCF
PPG E/PPG F Count Clock Select
W, R/W
W, R/W
0X000XX1B
0X000001B
16-bit PPG E/F
00004EH
PPGEF
R/W
000000X0B
Register
00004FH
Reserved
(Continued)
22
DS07-13746-3E
MB90360E Series
Abbrevia-
tion
Address
Register
Access
Resource name
Initial value
000050H Input Capture Control Status 0/1
000051H Input Capture Edge 0/1
ICS01
ICE01
ICS23
ICE23
R/W
R/W, R
R/W
R
00000000B
XXX0X0XXB
00000000B
Input Capture 0/1
000052H Input Capture Control Status 2/3
000053H Input Capture Edge 2/3
Input Capture 2/3
XXXXXXXXB
000054H
to
Reserved
000063H
000064H Timer Control Status 2
000065H Timer Control Status 2
000066H Timer Control Status 3
000067H Timer Control Status 3
000068H A/D Control Status 0
000069H A/D Control Status 1
00006AH A/D Data 0
TMCSR2
TMCSR2
TMCSR3
TMCSR3
ADCS0
ADCS1
ADCR0
ADCR1
ADSR0
ADSR1
R/W
R/W
R/W
R/W
R/W
R/W, W
R
00000000B
XXXX0000B
00000000B
XXXX0000B
000XXXX0B
0000000XB
00000000B
XXXXXX00B
00000000B
00000000B
16-bit Reload Timer
2
16-bit Reload Timer
3
A/D Converter
00006BH A/D Data 1
R
00006CH ADC Setting 0
R/W
R/W
00006DH ADC Setting 1
Low voltage/CPU
R/W, W operation detection
reset
Low Voltage/CPU Operation Detection
00006EH
LVRC
00111000B
Reset Control Register
00006FH ROM Mirror Function Select
ROMM
W
ROM Mirror
XXXXXXX1B
000070H
to
Reserved
00007FH
000080H
to
Reserved for CAN Interface 1. Refer to “■ CAN CONTROLLERS”
00008FH
000090H
to
Reserved
00009DH
Address Match
Detection 0
00009EH Address Detect Control Register 0
00009FH Delayed Interrupt/Release Register
PACSR0
DIRR
R/W
R/W
00000000B
Delayed Interrupt
generation module
XXXXXXX0B
Low-Power
consumption
Control Circuit
Low-power Consumption Mode
0000A0H
LPMCR
CKSCR
W, R/W
R, R/W
00011000B
11111100B
Control Register
Low-Power
consumption
Control Circuit
0000A1H Clock Selection Register
DS07-13746-3E
(Continued)
23
MB90360E Series
Abbrevia-
tion
Address
Register
Access
Resource name
Initial value
0000A2H
to
Reserved
0000A7H
0000A8H Watchdog Control Register
0000A9H Timebase Timer Control Register
0000AAH Watch Timer Control register
WDTC
TBTC
WTC
R, W
Watchdog Timer
Timebase Timer
Watch Timer
XXXXX111B
1XX00100B
1X001000B
W, R/W
R, R/W
0000ABH
to
Reserved
0000ADH
Flash Control Status
0000AEH (Flash Devices only.
Otherwise reserved)
FMCS
R, R/W
Flash Memory
000X0000B
0000AFH
Reserved
0000B0H Interrupt Control Register 00
0000B1H Interrupt Control Register 01
0000B2H Interrupt Control Register 02
0000B3H Interrupt Control Register 03
0000B4H Interrupt Control Register 04
0000B5H Interrupt Control Register 05
0000B6H Interrupt Control Register 06
0000B7H Interrupt Control Register 07
0000B8H Interrupt Control Register 08
0000B9H Interrupt Control Register 09
0000BAH Interrupt Control Register 10
0000BBH Interrupt Control Register 11
0000BCH Interrupt Control Register 12
0000BDH Interrupt Control Register 13
0000BEH Interrupt Control Register 14
0000BFH Interrupt Control Register 15
ICR00
ICR01
ICR02
ICR03
ICR04
ICR05
ICR06
ICR07
ICR08
ICR09
ICR10
ICR11
ICR12
ICR13
ICR14
ICR15
W, R/W
W, R/W
W, R/W
W, R/W
W, R/W
W, R/W
W, R/W
W, R/W
W, R/W
W, R/W
W, R/W
W, R/W
W, R/W
W, R/W
W, R/W
W, R/W
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
Interrupt Control
0000C0H
to
Reserved
0000C9H
0000CAH External Interrupt Enable 1
0000CBH External Interrupt Source 1
ENIR1
EIRR1
R/W
R/W
00000000B
XXXXXXXXB
00000000B
00000000B
00000000B
XXXX0000B
(Continued)
0000CCH
External Interrupt 1
PLL
Detection Level Setting 1
0000CDH
ELVR1
R/W
0000CEH xternal Interrupt Source Select
0000CFH PLL/Sub clock Control Register
EISSR
R/W
W
PSCCR
24
DS07-13746-3E
MB90360E Series
Abbrevia-
tion
Address
Register
Access
Resource name
Initial value
0000D0H
to
Reserved
0000FFH
007900H
to
007917H
Reserved
PRLLC
007918H Reload Register LC
007919H Reload Register HC
00791AH Reload Register LD
00791BH Reload Register HD
00791CH Reload Register LE
00791DH Reload Register HE
00791EH Reload Register LF
00791FH Reload Register HF
007920H Input Capture 0
007921H Input Capture 0
007922H Input Capture 1
007923H Input Capture 1
007924H Input Capture 2
007925H Input Capture 2
007926H Input Capture 3
007927H Input Capture 3
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
PRLHC
PRLLD
PRLHD
PRLLE
PRLHE
PRLLF
PRLHF
IPCP0
IPCP0
IPCP1
IPCP1
IPCP2
IPCP2
IPCP3
IPCP3
16-bit PPG C/D
16-bit PPG E/F
Input Capture 0/1
Input Capture 2/3
R
R
R
R
R
R
R
007928H
to
Reserved
00793FH
007940H Timer Data 0
TCDT0
TCDT0
R/W
R/W
R/W
R/W
00000000B
00000000B
00000000B
0XXXXXXXB
007941H Timer Data 0
Free-run Timer 0
007942H Timer Control Status 0
007943H Timer Control Status 0
TCCSL0
TCCSH0
007944H
to
Reserved
00794BH
00794CH
R/W
R/W
R/W
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
TMR2/
TMRLR2
16-bit Reload
Timer 2
Timer 2/Reload 2
00794DH
00794EH
TMR3/
TMRLR3
16-bit Reload
Timer 3
Timer 3/Reload 3
00794FH
007950H
to
Reserved
00795FH
(Continued)
DS07-13746-3E
25
MB90360E Series
Abbrevia-
tion
Address
Register
Access
Resource name
Initial value
Clock Supervisor Control
Register
007960H
CSVCR
R, R/W
Clock supervisor
00011100B
007961H
to
Reserved
00796DH
CAN Direct Mode Register
(MB90V340E only)
00796EH
CDMR
R/W
CAN clock sync
XXXXXXX0B
00796FH
to
Reserved
0079DFH
0079E0H Detect Address Setting 0
0079E1H Detect Address Setting 0
0079E2H Detect Address Setting 0
0079E3H Detect Address Setting 1
0079E4H Detect Address Setting 1
0079E5H Detect Address Setting 1
0079E6H Detect Address Setting 2
0079E7H Detect Address Setting 2
0079E8H Detect Address Setting 2
PADR0
PADR0
PADR0
PADR1
PADR1
PADR1
PADR2
PADR2
PADR2
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
Address Match
Detection 0
0079E9H
to
Reserved
0079EFH
0079F0H Detect Address Setting 3
0079F1H Detect Address Setting 3
0079F2H Detect Address Setting 3
0079F3H Detect Address Setting 4
0079F4H Detect Address Setting 4
0079F5H Detect Address Setting 4
0079F6H Detect Address Setting 5
0079F7H Detect Address Setting 5
0079F8H Detect Address Setting 5
PADR3
PADR3
PADR3
PADR4
PADR4
PADR4
PADR5
PADR5
PADR5
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
Address Match
Detection 1
0079F9H
to
Reserved
007BFFH
007C00H
to
Reserved for CAN Interface 1. Refer to “■ CAN CONTROLLERS”
Reserved for CAN Interface 1. Refer to “■ CAN CONTROLLERS”
007CFFH
007D00H
to
007DFFH
(Continued)
26
DS07-13746-3E
MB90360E Series
(Continued)
Abbrevia-
tion
Address
Register
Access
Resource name
Initial value
007E00H
to
Reserved
007FFFH
Notes : • Initial value of “X” represents unknown value.
• Any write access to reserved addresses in I/O map should not be performed. A read access to reserved
addresses results in reading “X”.
DS07-13746-3E
27
MB90360E Series
■ CAN CONTROLLERS
• Conforms to CAN Specification Ver 2.0 Part A and Part B
• Supports transmission/reception in standard frame and extended frame formats
• Supports transmitting of data frames by receiving remote frames
• 16 transmitting/receiving message buffers
• 29-bit ID and 8-byte data
• Multi-level message buffer configuration
• Provides full-bit comparison, full-bit mask, acceptance register 0/acceptance register 1 for each message
buffer as ID acceptance mask
• 2 acceptance mask registers in either standard frame format or extended frame formats
• Bit rate programmable from 10 kbps/s to 2 Mbps/s (when input clock is at 16 MHz)
List of Control Registers (1)
Address
Register
Abbreviation
BVALR
TREQR
TCANR
TCR
Access
R/W
R/W
W
Initial Value
CAN1
000080H
000081H
000082H
000083H
000084H
000085H
000086H
000087H
000088H
000089H
00008AH
00008BH
00008CH
00008DH
00008EH
00008FH
Message buffer valid register
Transmit request register
Transmit cancel register
Transmission complete register
Receive complete register
00000000 00000000B
00000000 00000000B
00000000 00000000B
00000000 00000000B
00000000 00000000B
00000000 00000000B
00000000 00000000B
00000000 00000000B
R/W
R/W
R/W
R/W
R/W
RCR
Remote request receiving
register
RRTRR
ROVRR
RIER
Receive overrun register
Reception interrupt enable
register
28
DS07-13746-3E
MB90360E Series
List of Control Registers (2)
Abbreviation
Address
CAN1
Register
Access
Initial Value
007D00H
007D01H
007D02H
007D03H
007D04H
007D05H
007D06H
007D07H
007D08H
007D09H
007D0AH
007D0BH
007D0CH
007D0DH
007D0EH
007D0FH
007D10H
007D11H
007D12H
007D13H
007D14H
007D15H
007D16H
007D17H
007D18H
007D19H
007D1AH
007D1BH
R/W, W
R/W, R
Control status register
CSR
LEIR
0XXXX0X1 00XXX000B
000X0000 XXXXXXXXB
00000000 00000000B
Last event indicator register
R/W
R
Receive and transmit error
counter
RTEC
BTR
Bit timing register
IDE register
R/W
R/W
R/W
R/W
R/W
11111111 X1111111B
XXXXXXXX XXXXXXXXB
00000000 00000000B
IDER
Transmit RTR register
TRTRR
RFWTR
TIER
Remote frame receive
waiting register
XXXXXXXX XXXXXXXXB
00000000 00000000B
Transmit interrupt enable
register
XXXXXXXX XXXXXXXXB
XXXXXXXX XXXXXXXXB
XXXXXXXX XXXXXXXXB
XXXXXXXX XXXXXXXXB
XXXXXXXX XXXXXXXXB
XXXXXXXX XXXXXXXXB
Acceptance mask select
register
AMSR
AMR0
AMR1
R/W
R/W
R/W
Acceptance mask register 0
Acceptance mask register 1
DS07-13746-3E
29
MB90360E Series
List of Message Buffers (ID Registers)
Address
CAN1
Register
Abbreviation
Access
Initial Value
007C00H
to
007C1FH
XXXXXXXXB
to
XXXXXXXXB
General-purpose RAM
⎯
R/W
007C20H
007C21H
007C22H
007C23H
007C24H
007C25H
007C26H
007C27H
007C28H
007C29H
007C2AH
007C2BH
007C2CH
007C2DH
007C2EH
007C2FH
007C30H
007C31H
007C32H
007C33H
007C34H
007C35H
007C36H
007C37H
007C38H
007C39H
007C3AH
007C3BH
007C3CH
007C3DH
007C3EH
007C3FH
XXXXXXXX XXXXXXXXB
XXXXXXXX XXXXXXXXB
XXXXXXXX XXXXXXXXB
XXXXXXXX XXXXXXXXB
XXXXXXXX XXXXXXXXB
XXXXXXXX XXXXXXXXB
XXXXXXXX XXXXXXXXB
XXXXXXXX XXXXXXXXB
XXXXXXXX XXXXXXXXB
XXXXXXXX XXXXXXXXB
XXXXXXXX XXXXXXXXB
XXXXXXXX XXXXXXXXB
XXXXXXXX XXXXXXXXB
XXXXXXXX XXXXXXXXB
XXXXXXXX XXXXXXXXB
ID register 0
ID register 1
ID register 2
ID register 3
ID register 4
ID register 5
ID register 6
ID register 7
IDR0
IDR1
IDR2
IDR3
IDR4
IDR5
IDR6
IDR7
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
XXXXXXXX XXXXXXXXB
(Continued)
30
DS07-13746-3E
MB90360E Series
(Continued)
Address
Register
Abbreviation
Access
Initial Value
CAN1
007C40H
007C41H
007C42H
007C43H
007C44H
007C45H
007C46H
007C47H
007C48H
007C49H
007C4AH
007C4BH
007C4CH
007C4DH
007C4EH
007C4FH
007C50H
007C51H
007C52H
007C53H
007C54H
007C55H
007C56H
007C57H
007C58H
007C59H
007C5AH
007C5BH
007C5CH
007C5DH
007C5EH
007C5FH
XXXXXXXX XXXXXXXXB
XXXXXXXX XXXXXXXXB
XXXXXXXX XXXXXXXXB
XXXXXXXX XXXXXXXXB
XXXXXXXX XXXXXXXXB
XXXXXXXX XXXXXXXXB
XXXXXXXX XXXXXXXXB
XXXXXXXX XXXXXXXXB
XXXXXXXX XXXXXXXXB
XXXXXXXX XXXXXXXXB
XXXXXXXX XXXXXXXXB
XXXXXXXX XXXXXXXXB
XXXXXXXX XXXXXXXXB
XXXXXXXX XXXXXXXXB
XXXXXXXX XXXXXXXXB
XXXXXXXX XXXXXXXXB
ID register 8
IDR8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ID register 9
ID register 10
ID register 11
ID register 12
ID register 13
ID register 14
ID register 15
IDR9
IDR10
IDR11
IDR12
IDR13
IDR14
IDR15
DS07-13746-3E
31
MB90360E Series
List of Message Buffers (DLC Registers and Data Registers)
Address
CAN1
Register
Abbreviation
DLCR0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
007C60H
007C61H
007C62H
007C63H
007C64H
007C65H
007C66H
007C67H
007C68H
007C69H
007C6AH
007C6BH
007C6CH
007C6DH
007C6EH
007C6FH
007C70H
007C71H
007C72H
007C73H
007C74H
007C75H
007C76H
007C77H
007C78H
007C79H
007C7AH
007C7BH
007C7CH
007C7DH
007C7EH
007C7FH
DLC register 0
DLC register 1
DLC register 2
DLC register 3
DLC register 4
DLC register 5
DLC register 6
DLC register 7
DLC register 8
DLC register 9
DLC register 10
DLC register 11
DLC register 12
DLC register 13
DLC register 14
DLC register 15
DLCR1
DLCR2
DLCR3
DLCR4
DLCR5
DLCR6
DLCR7
DLCR8
DLCR9
DLCR10
DLCR11
DLCR12
DLCR13
DLCR14
DLCR15
(Continued)
32
DS07-13746-3E
MB90360E Series
Address
CAN1
Register
Abbreviation
Access
Initial Value
007C80H
to
007C87H
XXXXXXXXB
to
XXXXXXXXB
Data register 0
(8 bytes)
DTR0
R/W
007C88H
to
007C8FH
XXXXXXXXB
to
XXXXXXXXB
Data register 1
(8 bytes)
DTR1
DTR2
DTR3
DTR4
DTR5
DTR6
DTR7
DTR8
DTR9
DTR10
DTR11
DTR12
DTR13
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
007C90H
to
007C97H
XXXXXXXXB
to
XXXXXXXXB
Data register 2
(8 bytes)
007C98H
to
007C9FH
XXXXXXXXB
to
XXXXXXXXB
Data register 3
(8 bytes)
007CA0H
to
007CA7H
XXXXXXXXB
to
XXXXXXXXB
Data register 4
(8 bytes)
007CA8H
to
007CAFH
XXXXXXXXB
to
XXXXXXXXB
Data register 5
(8 bytes)
007CB0H
to
007CB7H
XXXXXXXXB
to
XXXXXXXXB
Data register 6
(8 bytes)
007CB8H
to
007CBFH
XXXXXXXXB
to
XXXXXXXXB
Data register 7
(8 bytes)
007CC0H
to
007CC7H
XXXXXXXXB
to
XXXXXXXXB
Data register 8
(8 bytes)
007CC8H
to
007CCFH
XXXXXXXXB
to
XXXXXXXXB
Data register 9
(8 bytes)
007CD0H
to
007CD7H
XXXXXXXXB
to
XXXXXXXXB
Data register 10
(8 bytes)
007CD8H
to
007CDFH
XXXXXXXXB
to
XXXXXXXXB
Data register 11
(8 bytes)
007CE0H
to
007CE7H
XXXXXXXXB
to
XXXXXXXXB
Data register 12
(8 bytes)
007CE8H
to
007CEFH
XXXXXXXXB
to
XXXXXXXXB
Data register 13
(8 bytes)
(Continued)
DS07-13746-3E
33
MB90360E Series
(Continued)
Address
Register
CAN1
Abbreviation
Access
Initial Value
007CF0H
Data register 14
to
XXXXXXXXB
to
XXXXXXXXB
DTR14
R/W
(8 bytes)
007CF7H
007CF8H
Data register 15
to
XXXXXXXXB
to
XXXXXXXXB
DTR15
R/W
(8 bytes)
007CFFH
34
DS07-13746-3E
MB90360E Series
■ INTERRUPT FACTORS, INTERRUPT VECTORS, INTERRUPT CONTROL REGISTER
Interrupt control
Interrupt vector
Number Address
EI2OS
corresponding
register
Interrupt cause
Number
Address
Reset
N
N
#08
#09
#10
#11
#12
#13
#14
#15
#16
#17
#18
#19
#20
#21
#22
#23
#24
#25
#26
#27
#28
#29
#30
#31
#32
#33
#34
#35
#36
#37
#38
FFFFDCH
FFFFD8H
FFFFD4H
FFFFD0H
FFFFCCH
FFFFC8H
FFFFC4H
FFFFC0H
FFFFBCH
FFFFB8H
FFFFB4H
FFFFB0H
FFFFACH
FFFFA8H
FFFFA4H
FFFFA0H
FFFF9CH
FFFF98H
FFFF94H
FFFF90H
FFFF8CH
FFFF88H
FFFF84H
FFFF80H
FFFF7CH
FFFF78H
FFFF74H
FFFF70H
FFFF6CH
FFFF68H
FFFF64H
⎯
⎯
⎯
⎯
⎯
⎯
INT9 instruction
Exception
N
Reserved
N
ICR00
ICR01
ICR02
ICR03
ICR04
ICR05
ICR06
ICR07
ICR08
ICR09
ICR10
ICR11
ICR12
ICR13
0000B0H
0000B1H
0000B2H
0000B3H
0000B4H
0000B5H
0000B6H
0000B7H
0000B8H
0000B9H
0000BAH
0000BBH
0000BCH
Reserved
N
CAN 1 reception
CAN 1 transmission/node status
Reserved
N
N
N
Reserved
N
Reserved
N
Reserved
N
16-bit reload timer 2
16-bit reload timer 3
Reserved
Y1
Y1
N
Reserved
N
PPG C/D
N
PPG E/F
N
Timebase timer
External interrupt 8 to 11
Watch timer
N
Y1
N
External interrupt 12 to 15
A/D converter
Y1
Y1
N
16-bit free-run timer 0
Reserved
N
Reserved
N
Input capture 0 to 3
Reserved
Y1
N
LIN-UART 0 reception
LIN-UART 0 transmission
LIN-UART 1 reception
LIN-UART 1 transmission
Y2
Y1
Y2
Y1
0000BDH
(Continued)
DS07-13746-3E
35
MB90360E Series
(Continued)
Interrupt control
register
Interrupt vector
Number Address
EI2OS
corresponding
Interrupt cause
Number
Address
Reserved
N
N
N
N
#39
#40
#41
#42
FFFF60H
FFFF5CH
FFFF58H
FFFF54H
ICR14
0000BEH
Reserved
Flash memory
ICR15
0000BFH
Delayed interrupt generation module
Y1 : Usable
Y2 : Usable, with EI2OS stop function
N : Unusable
Notes : • The peripheral resources sharing the ICR register have the same interrupt level.
• When the peripheral resources sharing the ICR register use extended intelligent I/O service, only one
can use extended intelligent I/O service at a time.
• When either of the 2 peripheral resources sharing the ICR register specifies extended intelligent I/O
service, the other one cannot use interrupts.
36
DS07-13746-3E
MB90360E Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Rating
Parameter
Symbol
Unit
Remarks
Min
Max
VCC
AVCC
AVR
VI
VSS − 0.3 VSS + 6.0
VSS − 0.3 VSS + 6.0
VSS − 0.3 VSS + 6.0
VSS − 0.3 VSS + 6.0
VSS − 0.3 VSS + 6.0
V
V
V
V
V
Power supply voltage*1
VCC = AVCC*2
AVCC ≥ AVR*2
Input voltage*1
Output voltage*1
*3
*3
VO
Maximum clamp current
Total Maximum clamp current
ICLAMP
Σ|ICLAMP|
IOL1
−2.0
⎯
+2.0
40
mA *6
mA *6
mA *4
mA *5
mA *4
mA *5
mA *4
mA *5
⎯
15
“L” level maximum output current
“L” level average output current
IOL2
⎯
40
IOLAV1
IOLAV2
ΣIOL1
⎯
4
⎯
30
⎯
125
160
“L” level maximum overall output current
ΣIOL2
⎯
ΣIOLAV1
ΣIOLAV2
ΣIOLAV1
ΣIOLAV2
IOH1
*4 +105 °C < TA ≤ +125 °C
⎯
⎯
40
40
mA
mA
*5 +105 °C < TA ≤ +125 °C
*4 −40 °C ≤ TA ≤ +105 °C
*5 −40 °C ≤ TA ≤ +105 °C
“L” level average overall output current
⎯
⎯
⎯
⎯
⎯
⎯
−15
−40
−4
mA *4
mA *5
mA *4
mA *5
mA *4
mA *5
“H” level maximum output current
“H” level average output current
IOH2
IOHAV1
IOHAV2
ΣIOH1
ΣIOH2
ΣIOHAV1
ΣIOHAV2
ΣIOHAV1
ΣIOHAV2
−30
−125
−160
“H” level maximum overall output current
*4 +105 °C < TA ≤ +125 °C
⎯
⎯
−40
−40
mA
*5 +105 °C < TA ≤ +125 °C
*4 −40 °C ≤ TA ≤ +105 °C
*5 −40 °C ≤ TA ≤ +105 °C
“H” level average overall output current
Power consumption
mA
Flash memory updata not
performed
⎯
⎯
308
390
mW
PD
Flash memory updata
performed
mW
−40
−40
−55
+105
+125
+150
°C
Operating temperature
Storage temperature
TA
°C *7
°C
TSTG
(Continued)
37
DS07-13746-3E
MB90360E Series
(Continued)
*1 : This parameter is based on VSS = AVSS = 0 V.
*2 : Set AVCC and VCC to the same voltage. Make sure that AVCC does not exceed VCC and that the voltage at the
analog inputs does not exceed AVCC when the power is switched on.
*3 : VI and VO should not exceed VCC + 0.3 V. VI should not exceed the specified ratings. However, if the maximun
current to/from an input is limited by some means with external components, the ICLAMP rating supersedes the
VI rating.
*4 : Applicable to pins : P24 to P27, P40 to P44, P50 to P57, P60 to P67, P80, P82 to P87
*5 : Applicable to pins : P20 to P23
*6 : Applicable to pins : P20 to P27, P40 to P44, P50 to P57, P60 to P67, P80, P82 to P87
• Use within recommended operating conditions.
• Use at DC voltage (current) .
• The +B signal should always be applied a connecting limit resistance between the +B signal and the
microcontroller.
• The value of the limiting resistance should be set so that when the +B signal is applied the input current to
the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.
• Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input
potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect
other devices.
• Note that if a +B signal is inputted when the microcontroller power supply is off (not fixed at 0 V) , the power
supply is provided from the pins, so that incomplete operation may result.
• Note that if the +B input is applied during power-on, the power supply is provided from the pins and the
resulting power supply voltage may not be sufficient to operate the power-on reset.
• Care must be taken not to leave the +B input pin open.
• Recommended circuit sample :
• Input/output equivalent circuits
Protective diode
VCC
Limiting
P-ch
resistance
+B input (0 V to 16 V)
N-ch
R
*7 : There is a restriction of reliability if the product is used exceeding TA = +105 °C.
Contact the sales or support representative.
It is ensured to write/erase data to the Flash memory between TA = − 40 °C and +105 °C.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
38
DS07-13746-3E
MB90360E Series
2. Recommended Conditions
(VSS = AVSS = 0 V)
Value
Typ
Parameter
Symbol
Unit
Remarks
Min
Max
4.0
5.0
5.5
V
V
V
Under normal operation
Under normal operation when not
using the A/D converter and not
Flash programming.
VCC,
AVCC
Power supply voltage
3.5
3.0
5.0
5.5
5.5
⎯
Maintains RAM data in stop mode
Use a ceramic capacitor or com-
parable capacitor of the AC char-
Smoothing capacitor
CS
TA
0.1
⎯
1.0
µF acteristics. Bypass capacitor at the
VCC pin should be greater than this
capacitor.
−40
−40
⎯
⎯
+105
+125
°C
Operating temperature
°C
*
* : There is a restriction of reliability if the product is used exceeding TA = +105 °C.
Contact the sales or support representative.
It is ensured to write/erase data to the Flash memory between TA = − 40 °C and +105 °C.
• C Pin Connection Diagram
C
CS
WARNING: The recommended operating conditions are required in order to ensure the normal operation of
the semiconductor device. All of the device's electrical characteristics are warranted when the
device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges.
Operation outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented
on the data sheet. Users considering application outside the listed conditions are advised to contact
their representatives beforehand.
DS07-13746-3E
39
MB90360E Series
3. DC Characteristics
Sym-
(TA = −40 °C to +125 °C, VCC = 5.0 V 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)
Value
Parameter
Pin
Condition
Unit
Remarks
bol
Min
Typ
Max
Pin inputs if CMOS
hysteresis input levels
are selected (except
P82, P85)
VIHS
⎯
⎯
0.8 VCC
⎯
VCC + 0.3
V
Pin inputs if
VIHA
⎯
⎯
⎯
⎯
0.8 VCC
0.7 VCC
⎯
⎯
VCC + 0.3
VCC + 0.3
V
V
Automotive input
levels are selected
Input “H”
voltage
P82, P85 inputs if
CMOS input levels are
selected
VIHS
RST input pin (CMOS
hysteresis)
VIHR
VIHM
⎯
⎯
⎯
⎯
0.8 VCC
⎯
⎯
VCC + 0.3
VCC + 0.3
V
V
VCC − 0.3
MD input pin
Pin inputs if CMOS
hysteresis input levels
are selected (except
P82, P85)
VILS
⎯
⎯
VSS − 0.3
⎯
0.2 VCC
V
Pin inputs if
VILA
⎯
⎯
⎯
⎯
VSS − 0.3
VSS − 0.3
⎯
⎯
0.5 VCC
0.3 VCC
V
V
Automotive input
levels are selected
Input “L”
voltage
P82, P85 inputs if
CMOS input levels are
selected
VILS
RST input pin (CMOS
hysteresis)
VILR
VILM
VOH
⎯
⎯
⎯
⎯
VSS − 0.3
VSS − 0.3
VCC − 0.5
⎯
⎯
⎯
0.2 VCC
VSS + 0.3
⎯
V
V
V
MD input pin
Other than VCC = 4.5 V,
P20 to P23 IOH = −4.0 mA
Output “H”
voltage
VCC = 4.5 V,
VOHI P20 to P23
VCC − 0.5
⎯
⎯
⎯
⎯
50
⎯
0.4
0.4
+ 1
100
V
V
IOH = −14.0 mA
Other than VCC = 4.5 V,
P20 to P23 IOL = 4.0 mA
VOL
⎯
⎯
−1
25
Output “L”
voltage
VCC = 4.5 V,
IOL = 20.0 mA
VOLI P20 to P23
V
Input leak
current
VCC = 5.5 V,
VSS < VI < VCC
IIL
⎯
µA
kΩ
Pull-up
resistance
P20 to P27,
RST
RUP
⎯
(Continued)
40
DS07-13746-3E
MB90360E Series
(TA = −40 °C to +125 °C, VCC = 5.0 V 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)
Value
Sym-
bol
Parameter
Pin
Condition
Unit
Remarks
Min Typ Max
MB90362E,
Pull-down
resistance
MB90362ES,
MB90362TE,
MB90362TES
RDOWN
MD2
⎯
25
50
100
kΩ
VCC = 5.0 V,
Internal frequency : 24 MHz,
At normal operation.
⎯
⎯
⎯
⎯
35
50
50
12
45
60
60
20
mA
mA
mA
mA
VCC = 5.0 V,
Internal frequency : 24 MHz,
At writing Flash memory.
Flash memory
devices
ICC
VCC = 5.0 V,
Internal frequency : 24 MHz,
At erasing Flash memory.
Flash memory
devices
VCC = 5.0 V,
Internal frequency : 24 MHz,
At sleep mode.
ICCS
Deviceswithout
T-suffix
⎯
⎯
0.3
0.4
0.8
1.0
VCC = 5.0 V,
Internal frequency : 2 MHz,
At main timer mode
ICTS
mA
mA
Devices with
T-suffix
VCC = 5.0 V,
Internal frequency : 24 MHz,
At PLL timer mode,
ICTSPLL6
⎯
4
7
External frequency = 4 MHz
Power supply
current*
VCC
MB90F362E,
MB90F367E,
MB90362E,
MB90367E
Stopping clock
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
40
60
90
110
10
30
60
80
100
150
200
250
50
supervisor
VCC = 5.0 V
Internalfrequency:
8 kHz,
At sub operation,
TA = +25°C
Operatingclock
supervisor
MB90F367E,
MB90367E
ICCL
µA
MB90F362TE,
MB90F367TE,
MB90362TE,
MB90367TE
Stopping clock
supervisor
Operatingclock
supervisor
MB90F367TE,
MB90367TE
MB90F362E,
MB90F367E,
MB90362E,
MB90367E
Stopping clock
supervisor
VCC = 5.0 V
Internalfrequency:
8 kHz,
At sub sleep,
TA = +25°C
Operatingclock
supervisor
MB90F367E,
MB90367E
100
150
200
ICCLS
µA
MB90F362TE,
MB90F367TE,
MB90362TE,
MB90367TE
Stopping clock
supervisor
Operatingclock
supervisor
MB90F367TE,
MB90367TE
(Continued)
DS07-13746-3E
41
MB90360E Series
(Continued)
(TA = −40 °C to +125 °C, VCC = 5.0 V 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)
Value
Sym-
bol
Parameter
Pin
Condition
Unit
Remarks
Min Typ Max
MB90F362E,
MB90F367E,
MB90362E,
MB90367E
Stopping clock
supervisor
⎯
⎯
⎯
8
30
70
VCC = 5.0 V
Internalfrequency:
8 kHz,
At watch mode,
TA = +25°C
Operatingclock
supervisor
MB90F367E,
MB90367E
30
60
ICCT
µA
MB90F362TE,
MB90F367TE,
MB90362TE,
MB90367TE
Stopping clock
supervisor
Power supply
current*
130
VCC
Operatingclock
supervisor
MB90F367TE,
MB90367TE
⎯
⎯
⎯
80
5
170
25
Deviceswithout
T-suffix
µA
µA
VCC = 5.0 V,
ICCH
CIN
At stop mode, TA = +25°C
Devices with
T-suffix
50
130
Other than
AVCC,
AVSS,AVR,
VCC, VSS, C
Input capacity
⎯
⎯
5
15
pF
* : The power supply current is measured with an external clock.
42
DS07-13746-3E
MB90360E Series
4. AC Characteristics
(1) Clock Timing
(TA = −40 °C to +125 °C, VCC = 5.0 V 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)
Value
Parameter
Symbol
Pin
Unit
Remarks
Min
Typ
Max
1/2 when PLL stops,
When using an oscillation circuit
3
⎯
16
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
PLL × 1,
When using an oscillation circuit
4
4
4
4
4
3
4
4
4
4
4
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
16
12
8
PLL × 2,
When using an oscillation circuit
X0, X1
PLL × 3,
When using an oscillation circuit
PLL × 4,
When using an oscillation circuit
6
PLL × 6,
When using an oscillation circuit
4
fC
Clock frequency*
1/2 when PLL stops,
When using an external clock
24
24
12
8
PLL × 1,
When using an external clock
PLL × 2,
When using an external clock
X0, X1
PLL × 3,
When using an external clock
PLL × 4,
When using an external clock
6
PLL × 6,
When using an external clock
4
MHz
kHz
fCL
X0A, X1A
X0, X1
—
32.768 100
62.5
⎯
⎯
333
333
—
ns When using an oscillation circuit
ns When using an external clock
µs
tCYL
Clock cycle time
X0, X1 41.67
X0A, X1A 10
tCYLL
30.5
⎯
PWH, PWL
PWHL, PWLL
X0
10
5
⎯
ns
Input clock pulse width
Duty ratio is about 30% to 70%.
µs
X0A
15.2
⎯
Input clock rise and fall
time
tCR, tCF
X0
⎯
⎯
5
ns When using external clock
Internal operating clock
frequency (machine
clock)
fCP
⎯
⎯
1.5
⎯
24
50
MHz When using main clock
kHz When using sub clock
fCPL
⎯
8.192
tCP
⎯
⎯
41.67
20
⎯
666
ns When using main clock
µs When using sub clock
(Continued)
Internal operating clock
cycletime (machineclock)
tCPL
122.1
⎯
DS07-13746-3E
43
MB90360E Series
(Continued)
* : When selecting the PLL clock, the range of clock frequency is limited. Use this product within range as mentioned
in “Relation among external clock frequency and internal clock frequency”.
• Clock Timing
t
CYL
0.8 VCC
0.2 VCC
X0
P
WH
PWL
t
CF
tCR
t
CYLL
0.8 VCC
0.2 VCC
X0A
P
WHL
PWLL
t
CF
tCR
44
DS07-13746-3E
MB90360E Series
• Guaranteed PLL Operation Range
Guaranteed operation range
5.5
4.0
3.5
Guaranteed A/D converter
operation range
Guaranteed PLL operation range
1.5
4
24
Internal clock fCP (MHz)
Guaranteed operation range of MB90360E series
Guaranteed oscillation frequency range
× 6 × 4
× 3
× 2
× 1
24
16
12
8
×1/2
(PLL off)
4.0
1.5
3
4
8
12
24
16
External clock f
C
(MHz) *
* : When using the oscillation circuit, the maximum oscillation clock frequency is 16 MHz.
DS07-13746-3E
45
MB90360E Series
(2) Reset Standby Input
(TA = −40 °C to +125 °C, VCC = 5.0 V 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)
Value
Parameter Symbol
Pin
Unit
Remarks
Min
Max
500
⎯
ns
Under normal operation
In stop mode, sub clock
mode, sub sleep mode,
and watch mode
Reset input
tRSTL
Oscillation time of oscillator*
RST
⎯
⎯
µs
µs
time
+ 100 µs
100
In timebase timer mode
* : Oscillation time of oscillator is the time that the amplitude reaches 90%. In the crystal oscillator, the oscillation
time is between several ms and tens of ms. In ceramic oscillators, the oscillation time is between hundreds of µs
and several ms. With an external clock, the oscillation time is 0 ms.
• Under normal operation :
t
RSTL
RST
0.2 VCC
0.2 VCC
• In stop mode, sub clock mode, sub sleep mode, and watch mode :
tRSTL
RST
0.2 VCC
0.2 VCC
90% of
amplitude
X0
Internal operation
clock
100 µs
Oscillation time
of oscillator
Oscillation stabilization
waiting time
Instruction execution
Internal reset
46
DS07-13746-3E
MB90360E Series
(3) Power-on Reset
Parameter
(TA = −40 °C to +125 °C, VCC = 5.0 V 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)
Value
Symbol
Pin
Condition
Unit
Remarks
Min
0.05
1
Max
30
Power on rise time
Power off time
tR
VCC
VCC
ms
⎯
tOFF
⎯
ms Due to repetitive operation
tR
2.7 V
V
CC
0.2 V
0.2 V
0.2 V
tOFF
Note : If you change the power supply voltage too rapidly, a power-on reset may occur. We recommend that you
start up smoothly by restraining voltages when changing the power supply voltage during operation, as
shown in the figure below. Perform while not using the PLL clock. However, if voltage drops are within
1 V/s, you can operate while using the PLL clock.
V
CC
We recommend a rise of
50 mV/ms maximum.
3 V
Holds RAM data
V
SS
DS07-13746-3E
47
MB90360E Series
(4) LIN-UART0/1
• Bit setting: ESCR:SCES = 0, ECCR:SCDE = 0
(TA = −40 °C to +125 °C, VCC = 5.0 V 10%, fCP ≤ 24 MHz, VSS = 0 V)
Value
Parameter
Symbol
Pin
Condition
Unit
Min
Max
Serial clock cycle time
tSCYC
tSLOVI
SCK0, SCK1
5 tCP
⎯
ns
ns
SCK0, SCK1,
SOT0, SOT1
SCK ↓ → SOT delay time
−50
+50
⎯
Internal shift clock
mode output pins are
CL = 80 pF + 1 TTL.
SCK0, SCK1,
SIN0, SIN1
Valid SIN → SCK ↑
tIVSHI
tCP + 80
0
ns
ns
SCK0, SCK1,
SIN0, SIN1
SCK ↑ → Valid SIN hold time
tSHIXI
⎯
Serial clock “L” pulse width
Serial clock “H” pulse width
tSHSL
tSLSH
SCK0, SCK1
SCK0, SCK1
3 tCP - tR
tCP + 10
⎯
⎯
ns
ns
SCK0, SCK1,
SOT0, SOT1
SCK ↓ → SOT delay time
Valid SIN → SCK ↑
tSLOVE
tIVSHE
tSHIXE
⎯
30
2 tCP + 60 ns
External shift clock
mode output pins are
CL = 80 pF + 1 TTL.
SCK0, SCK1,
SIN0, SIN1
⎯
⎯
ns
ns
SCK0, SCK3,
SIN0, SIN1
SCK ↑ → Valid SIN hold time
tCP + 30
SCK fall time
SCK rise time
tF
SCK0, SCK1
SCK0, SCK1
⎯
⎯
10
10
ns
ns
tR
Notes : • AC characteristic in CLK synchronized mode.
• CL is load capacity value of pins when testing.
• tCP is internal operating clock cycle time (machine clock) . Refer to “ (1) Clock Timing”.
• Internal Shift Clock Mode
tSCYC
2.4 V
SCK0, SCK1
0.8 V
0.8 V
tSLOVI
2.4 V
0.8 V
SOT0, SOT1
SIN0, SIN1
tIVSHI
tSHIXI
VIH
VIL
VIH
VIL
48
DS07-13746-3E
MB90360E Series
• External Shift Clock Mode
t
SLSH
t
SHSL
VIH
VIH
SCK0, SCK1
VIL
VIL
t
SLOVE
tF
t
R
2.4 V
0.8 V
SOT0, SOT1
SIN0, SIN1
t
IVSHE
tSHIXE
V
V
IH
IL
V
IH
IL
V
• Bit setting: ESCR:SCES = 1, ECCR:SCDE = 0
(TA = −40 °C to +125 °C, VCC = 5.0 V 10%, fCP ≤ 24 MHz, VSS = 0 V)
Value
Parameter
Symbol
Pin
Condition
Unit
Min
Max
Serial clock cycle time
tSCYC
SCK0, SCK1
5 tCP
⎯
ns
ns
SCK0, SCK1,
SOT0, SOT1
SCK ↑ → SOT delay time
tSHOVI
−50
tCP + 80
0
+50
⎯
Internal shift clock
mode output pins are
CL = 80 pF + 1 TTL.
SCK0, SCK1,
SIN0, SIN1
Valid SIN → SCK ↓
tIVSLI
tSLIXI
ns
ns
SCK0, SCK1,
SIN0, SIN1
SCK ↓ → Valid SIN hold time
⎯
Serial clock “H” pulse width
Serial clock “L” pulse width
tSHSL
tSLSH
SCK0, SCK1
SCK0, SCK1
3 tCP - tR
tCP + 10
⎯
⎯
ns
ns
SCK0, SCK1,
SOT0, SOT1
SCK ↑ → SOT delay time
Valid SIN → SCK ↓
tSHOVE
tIVSLE
tSLIXE
⎯
30
2 tCP + 60
ns
ns
ns
External shift clock
mode output pins are
CL = 80 pF + 1 TTL.
SCK0, SCK1,
SIN0, SIN1
⎯
⎯
SCK0, SCK1,
SIN0, SIN1
SCK ↓ → Valid SIN hold time
tCP + 30
SCK fall time
SCK rise time
tF
SCK0, SCK1
SCK0, SCK1
⎯
⎯
10
10
ns
ns
tR
Notes : • CL is load capacity value of pins when testing.
• tCP is internal operating clock cycle time (machine clock) . Refer to “ (1) Clock Timing”.
DS07-13746-3E
49
MB90360E Series
• Internal Shift Clock Mode
tSCYC
2.4 V
SCK0, SCK1
SOT0, SOT1
0.8 V
t
SHOVI
2.4 V
0.8 V
t
IVSLI
t
SLIXI
V
V
IH
IL
V
IH
IL
SIN0, SIN1
V
• External Shift Clock Mode
t
SHSL
t
SLSH
V
IH
V
IH
SCK0, SCK1
V
IL
VIL
tSHOVE
t
R
t
F
2.4 V
0.8 V
SOT0, SOT1
SIN0, SIN1
t
IVSLE
tSLIXE
V
V
IH
IL
V
V
IH
IL
50
DS07-13746-3E
MB90360E Series
• Bit setting: ESCR:SCES = 0, ECCR:SCDE = 1
(TA = −40 °C to +125 °C, VCC = 5.0 V 10%, fCP ≤ 24 MHz, VSS = 0 V)
Value
Parameter
Symbol
Pin
Condition
Unit
Min
Max
Serial clock cycle time
tSCYC
SCK0, SCK1
5 tCP
⎯
ns
ns
SCK0, SCK1,
SOT0, SOT1
SCK ↑ → SOT delay time
tSHOVI
−50
tCP + 80
0
+50
⎯
SCK0, SCK1, Internal clock operation
SIN0, SIN1
Valid SIN → SCK ↓
tIVSLI
tSLIXI
tSOVLI
ns
ns
ns
output pins are
= 80 pF + 1 TTL.
C
L
SCK0, SCK1,
SIN0, SIN1
SCK ↓ → Valid SIN hold time
SOT → SCK ↓ delay time
⎯
SCK0, SCK1,
SOT0, SOT1
3 tCP − 70
⎯
Notes : • CL is load capacity value of pins when testing.
• tCP is internal operating clock cycle time (machine clock) . Refer to “ (1) Clock Timing”.
tSCYC
2.4 V
SCK0, SCK1
0.8 V
0.8 V
tSHOVI
tSOVLI
2.4 V
0.8 V
2.4 V
0.8 V
SOT0, SOT1
SIN0, SIN1
tIVSLI
tSLIXI
VIH
VIL
VIH
VIL
DS07-13746-3E
51
MB90360E Series
• Bit setting: ESCR:SCES = 1, ECCR:SCDE = 1
(TA = −40 °C to +125 °C, VCC = 5.0 V 10%, fCP ≤ 24 MHz, VSS = 0 V)
Value
Parameter
Symbol
Pin
Condition
Unit
Min
Max
Serial clock cycle time
tSCYC
tSLOVI
SCK0, SCK1
5 tCP
⎯
ns
ns
SCK0, SCK1,
SOT0, SOT1
SCK ↓ → SOT delay time
−50
+50
⎯
SCK0, SCK1, Internalclockoperation
SIN0, SIN1
Valid SIN → SCK ↑
tIVSHI
tSHIXI
tSOVHI
tCP + 80
0
ns
ns
ns
output pins are
= 80 pF + 1 TTL.
C
L
SCK0, SCK1,
SIN0, SIN1
SCK ↑ → Valid SIN hold time
SOT → SCK ↑ delay time
⎯
SCK0, SCK1,
SOT0, SOT1
3 tCP − 70
⎯
Notes : • CL is load capacity value of pins when testing.
• tCP is internal operating clock cycle time (machine clock) . Refer to “ (1) Clock Timing”.
t
SCYC
2.4 V
2.4 V
SCK0, SCK1
SOT0, SOT1
0.8 V
t
SLOVI
t
SOVHI
2.4 V
2.4 V
0.8 V
0.8 V
t
IVSHI
tSHIXI
V
V
IH
IL
V
V
IH
IL
SIN0, SIN1
52
DS07-13746-3E
MB90360E Series
(5) Trigger Input Timing
Parameter
(TA = −40 °C to +125 °C, VCC = 5.0 V 10%, fCP ≤ 24 MHz, VSS = 0 V)
Value
Symbol
Pin
Condition
Unit
Min
Max
INT8, INT9R
INT10, INT11
INT12R, INT13
INT14R, INT15R
ADTG
tTRGH
tTRGL
Input pulse width
⎯
5 tCP
⎯
ns
Note : tCP is internal operating clock cycle time (machine clock) . Refer to “ (1) Clock Timing”.
V
IH
VIH
INT8, INT9R
INT10, INT11
INT12R, INT13
INT14R, INT15R
ADTG
V
IL
VIL
t
TRGH
t
TRGL
DS07-13746-3E
53
MB90360E Series
(6) Timer Related Resource Input Timing
(TA = −40 °C to +125 °C, VCC = 5.0 V 10%, fCP ≤ 24 MHz, VSS = 0 V)
Value
Parameter
Symbol
Pin
Condition
Unit
Min
Max
tTIWH
tTIWL
TIN2, TIN3
IN0 to IN3
Input pulse width
⎯
4 tCP
⎯
ns
Note : tCP is internal operating clock cycle time (machine clock) . Refer to “ (1) Clock Timing”.
VIH
VIH
VIL
VIL
TIN2, TIN3
IN0 to IN3
tTIWH
tTIWL
(7) Timer Related Resource Output Timing
(TA = –40°C to +125°C, VCC = 5.0 V 10%, fCP ≤ 24 MHz, VSS = 0 V)
Value
Parameter
Symbol
Pin
Condition
Unit
Min
Max
TOT2, TOT3
PPGC to PPGF
CLK ↑ → TOUT change time
tTO
⎯
30
⎯
ns
2.4 V
CLK
2.4 V
0.8 V
TOT2, TOT3
PPGC to PPGF
tTO
54
DS07-13746-3E
MB90360E Series
5. A/D Converter
(T
Parameter
Resolution
A
= −40 °C to +125 °C, 3.0 V ≤ AVR − AVSS, VCC = AVCC = 5.0 V 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)
Value
Symbol
Pin
Unit
Remarks
Min
⎯
Typ
⎯
Max
10
⎯
⎯
⎯
⎯
⎯
⎯
bit
Total error
⎯
⎯
3.0
2.5
LSB
LSB
Nonlinearity error
⎯
⎯
Differential
nonlinearity error
⎯
⎯
⎯
⎯
1.9
LSB
V
AVSS −
AVSS +
AVSS +
Zero reading voltage
VOT
VFST
AN0 to AN15
AN0 to AN15
1.5 × LSB 0.5 × LSB 2.5 × LSB
Full scale reading
voltage
AVR −
AVR −
AVR +
V
3.5 × LSB 1.5 × LSB 0.5 × LSB
1.0
4.5 V ≤ AVCC ≤ 5.5 V
4.0 V ≤ AVCC < 4.5 V
4.5 V ≤ AVCC ≤ 5.5 V
4.0 V ≤ AVCC < 4.5 V
Compare time
Sampling time
⎯
⎯
⎯
⎯
⎯
⎯
16500
µs
µs
2.0
0.5
1.2
∞
Analog port input
current
IAIN
VAIN
⎯
AN0 to AN15
AN0 to AN15
AVR
−0.3
AVSS
⎯
⎯
⎯
+0.3
AVR
AVCC
µA
V
Analog input
voltage range
Reference
voltage range
AVSS + 2.7
V
IA
IAH
IR
AVCC
AVCC
AVR
AVR
⎯
⎯
⎯
⎯
3.5
⎯
7.5
5
mA
µA
µA
µA
Power supply current
*
*
600
⎯
900
5
Reference
voltage supply current
IRH
Offset between
input channels
⎯
AN0 to AN15
⎯
⎯
4
LSB
* : If A/D converter is not operating, a current when CPU is stopped is applicable (VCC = AVCC = AVR = 5.0 V) .
DS07-13746-3E
55
MB90360E Series
• About the external impedance of analog input and its sampling time
A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling
time, the analog voltage changed to the internal sample and hold capacitor is insufficient, adversely affecting A/
D conversion precision. Therefore, to satisfy the A/D conversion precision standard, consider the relationship
between the external impedance and minimum sampling time and either adjust the resistor value and operating
frequency or decrease the external impedance so that the sampling time is longer than the minimum value. And,
if the sampling time cannot be sufficient, connect a capacitor of about 0.1 µF to the analog input pin.
• Analog input equivalent circuit model
R
Comparator
Analog input
C
During sampling : ON
MB90F362E/TE/ES/TES, MB90F367E/TE/ES/TES
R
C
4.5 V ≤ AVCC ≤ 5.5 V
4.0 V ≤ AVCC < 4.5 V
2.0 kΩ (Max)
8.2 kΩ (Max)
16.0 pF (Max)
16.0 pF (Max)
MB90362E/TE/ES/TES, MB90367E/TE/ES/TES,
MB90V340E-101/102/103/104
R
C
4.5 V ≤ AVCC ≤ 5.5 V
4.0 V ≤ AVCC < 4.5 V
2.0 kΩ (Max)
8.2 kΩ (Max)
14.4 pF (Max)
14.4 pF (Max)
Note : The values are reference values.
56
DS07-13746-3E
MB90360E Series
• The relationship between external impedance and minimum sampling time
• At 4.5 V ≤ AVCC ≤ 5.5 V
(External impedance = 0 kΩ to 20 kΩ)
(External impedance = 0 kΩ to 100 kΩ)
MB90362E/TE/ES/TES,
MB90367E/TE/ES/TES,
MB90V340E-101/102/103/104
MB90362E/TE/ES/TES,
MB90367E/TE/ES/TES,
MB90V340E-101/102/103/104
20
100
18
16
14
12
10
8
90
80
MB90F362E/TE/ES/TES
MB90F367E/TE/ES/TES
MB90F362E/TE/ES/TES
MB90F367E/TE/ES/TES
70
60
50
40
30
20
6
4
2
0
10
0
0
1
2
3
4
5
6
7
8
0
5
10
15
20
25
30
35
Minimum sampling time [µs]
Minimum sampling time [µs]
• At 4.0 V ≤ AVCC < 4.5 V
(External impedance = 0 kΩ to 20 kΩ)
(External impedance = 0 kΩ to 100 kΩ)
MB90362E/TE/ES/TES,
MB90367E/TE/ES/TES,
MB90V340E-101/102/103/104
MB90362E/TE/ES/TES,
MB90367E/TE/ES/TES,
MB90V340E-101/102/103/104
20
18
16
14
12
10
8
100
90
80
70
60
50
40
30
20
MB90F362E/TE/ES/TES
MB90F367E/TE/ES/TES
MB90F362E/TE/ES/TES
MB90F367E/TE/ES/TES
6
4
2
0
10
0
0
1
2
3
4
5
6
7
8
0
5
10
15
20
25
30
35
Minimum sampling time [µs]
Minimum sampling time [µs]
• About errors
As | AVR − AVSS | becomes smaller, values of relative errors grow larger.
DS07-13746-3E
57
MB90360E Series
6. Definition of A/D Converter Terms
Resolution
: Analog variation that is recognized by an A/D converter.
Non linearity
error
: Deviation between a line across zero-transition line ( “00 0000 0000B” ← → “00 0000 0001B” )
and full-scale transition line ( “11 1111 1110B” ← → “11 1111 1111B” ) and actual conversion
characteristics.
Differential
linearity error
: Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal
value.
Total error
: Difference between an actual value and an theoretical value. A total error includes zero transi-
tion error, full-scale transition error, and linear error.
Total error
3FFH
1.5 LSB
3FEH
3FDH
Actual conversion
characteristics
{1 LSB × (N − 1) + 0.5 LSB}
004H
003H
002H
001H
VNT
(Actually-measured value)
Actual conversion
characteristics
Ideal characteristics
0.5 LSB
AVSS
AVR
Analog input
VNT − {1 LSB × (N − 1) + 0.5 LSB}
[LSB]
Total error of digital output “N” =
1 LSB
AVR − AVSS
1 LSB (Ideal value) =
[V]
1024
N : A/D converter digital output value
VOT (Ideal value) = AVSS + 0.5 LSB [V]
VFST (Ideal value) = AVR − 1.5 LSB [V]
VNT : A voltage at which digital output transits from (N − 1) to N.
(Continued)
58
DS07-13746-3E
MB90360E Series
(Continued)
Non linearity error
Differential linearity error
Ideal
characteristics
3FF
3FE
3FD
H
H
H
Actual conversion
characteristics
N + 1
H
H
H
H
Actual conversion
characteristics
{1 LSB × (N − 1)
+ VOT
}
V
FST (actual
measurement
value)
N
V
NT (actual
measurement value)
004
003
002
001
H
H
H
H
V
(N + 1) T
(actual measurement
Actual conversion
characteristics
N − 1
N − 2
value)
V
NT
(actual measurement value)
Ideal characteristics
Actual conversion
characteristics
V
OT (actual measurement value)
Analog input
AVSS
AVR
AVSS
AVR
Analog input
VNT − {1 LSB × (N − 1) + VOT}
[LSB]
Non linearity error of digital output N =
1 LSB
V (N+1) T − VNT
−1 LSB [LSB]
1 LSB
Differential linearity error of digital output N =
1 LSB =
VFST − VOT
[V]
1022
N
: A/D converter digital output value
VOT : Voltage at which digital output transits from “000H” to “001H.”
VFST : Voltage at which digital output transits from “3FEH” to “3FFH.”
DS07-13746-3E
59
MB90360E Series
7. Flash Memory Program/Erase Characteristics
Value
Typ
Parameter
Conditions
Unit
Remarks
Min
Max
Excludes programming
prior to erasure
Chip erase time
⎯
1
15
s
TA = −40 °C to +105 °C
VCC = 5.0 V
Word (16-bit width)
programming time
Except for the overhead
time of the system level
⎯
10000
20
16
⎯
⎯
3600
⎯
µs
Program/Erase cycle
⎯
cycle
year
Flash memory data
retention time
Average
TA = +85 °C
⎯
*
* : Corresponding value comes from the technology reliability evaluation result (using Arrhenius equation to translate
high temperature measurements into normalized value at +85 °C) .
60
DS07-13746-3E
MB90360E Series
■ ORDERING INFORMATION
Part number
MB90F362EPMT
MB90F362TEPMT
MB90F362ESPMT
MB90F362TESPMT
MB90F367EPMT
MB90F367TEPMT
MB90F367ESPMT
MB90F367TESPMT
MB90362EPMT
Package
Remarks
48-pin plastic LQFP
(FPT-48P-M26)
MB90362TEPMT
MB90362ESPMT
MB90362TESPMT
MB90367EPMT
MB90367TEPMT
MB90367ESPMT
MB90367TESPMT
MB90V340E-101CR
MB90V340E-102CR
MB90V340E-103CR
MB90V340E-104CR
299-pin ceramic PGA
(PGA-299C-A01)
For evaluation
DS07-13746-3E
61
MB90360E Series
■ PACKAGE DIMENSION
48-pin plastic LQFP
Lead pitch
0.50 mm
7 × 7 mm
Package width ×
package length
Lead shape
Sealing method
Mounting height
Weight
Gullwing
Plastic mold
1.70 mm MAX
0.17 g
Code
(Reference)
P-LFQFP48-7×7-0.50
(FPT-48P-M26)
48-pin plastic LQFP
(FPT-48P-M26)
Note 1) * : These dimensions include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
9.00 0.20(.354 .008)SQ
+0.40
7.00 –0.10 .276 –+..000146 SQ
0.145 0.055
(.006 .002)
*
36
25
37
24
Details of "A" part
0.08(.003)
1.50 +–00..1200
(Mounting height)
.059 +–..000048
INDEX
48
13
0.10 0.10
(.004 .004)
(Stand off)
"A"
0˚~8˚
1
12
LEAD No.
0.50(.020)
0.25(.010)
0.20 0.05
M
0.08(.003)
(.008 .002)
0.60 0.15
(.024 .006)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
©2003-2008 FUJITSU MICROELECTRONICS LIMITED F48040S-c-2-3
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/package/en-search/
62
DS07-13746-3E
MB90360E Series
■ MAIN CHANGES IN THIS EDITION
Page
Section
Change Results
Changed are following names.
⎯
⎯
UART → LIN-UART
16-bit I/O timer → 16-bit free-run timer
4, 5
15
■ PRODUCT LINEUP
Added the row of LIN-UART.
■ HANDLING DEVICES
Added the item “17.Serial communication”.
■ ELECTRICAL CHARACTERISTICS Changed the maximum rating values and Remarks on
1. Absolute Maximum Ratings
Ratings of Power consumption.
37
300 → 308 Flash memory updata not performed
390 Flash memory updata performed
4. AC Characteristics
5. A/D Converter
Changed the characteristics of (4)LIN-UART0/1.
(4) UART0/UART1 → (4)LIN-UART0/1
48 to 52
55
Changed the items of “Zero reading voltage” and “Full
scale reading voltage”.
■ ORDERING INFORMATION
Changed the part numbers;
MB90V340E-101 → MB90V340E-101CR
MB90V340E-102 → MB90V340E-102CR
MB90V340E-103 → MB90V340E-103CR
MB90V340E-104 → MB90V340E-104CR
61
The vertical lines marked in the left side of the page show the changes.
DS07-13746-3E
63
MB90360E Series
FUJITSU MICROELECTRONICS LIMITED
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Korea
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Korea
Hong Kong
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Tel: +82-2-3484-7100 Fax: +82-2-3484-7111
http://www.fmk.fujitsu.com/
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